1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */ 2 /* 3 * Copyright 1996-1999 Thomas Bogendoerfer 4 * 5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker. 6 * 7 * Copyright 1993 United States Government as represented by the 8 * Director, National Security Agency. 9 * 10 * This software may be used and distributed according to the terms 11 * of the GNU General Public License, incorporated herein by reference. 12 * 13 * This driver is for PCnet32 and PCnetPCI based ethercards 14 */ 15 /************************************************************************** 16 * 23 Oct, 2000. 17 * Fixed a few bugs, related to running the controller in 32bit mode. 18 * 19 * Carsten Langgaard, carstenl@mips.com 20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 21 * 22 *************************************************************************/ 23 24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26 #define DRV_NAME "pcnet32" 27 #define DRV_VERSION "1.35" 28 #define DRV_RELDATE "21.Apr.2008" 29 #define PFX DRV_NAME ": " 30 31 static const char *const version = 32 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n"; 33 34 #include <linux/module.h> 35 #include <linux/kernel.h> 36 #include <linux/sched.h> 37 #include <linux/string.h> 38 #include <linux/errno.h> 39 #include <linux/ioport.h> 40 #include <linux/slab.h> 41 #include <linux/interrupt.h> 42 #include <linux/pci.h> 43 #include <linux/delay.h> 44 #include <linux/init.h> 45 #include <linux/ethtool.h> 46 #include <linux/mii.h> 47 #include <linux/crc32.h> 48 #include <linux/netdevice.h> 49 #include <linux/etherdevice.h> 50 #include <linux/if_ether.h> 51 #include <linux/skbuff.h> 52 #include <linux/spinlock.h> 53 #include <linux/moduleparam.h> 54 #include <linux/bitops.h> 55 #include <linux/io.h> 56 #include <linux/uaccess.h> 57 58 #include <asm/dma.h> 59 #include <asm/irq.h> 60 61 /* 62 * PCI device identifiers for "new style" Linux PCI Device Drivers 63 */ 64 static DEFINE_PCI_DEVICE_TABLE(pcnet32_pci_tbl) = { 65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), }, 66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), }, 67 68 /* 69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have 70 * the incorrect vendor id. 71 */ 72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE), 73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, }, 74 75 { } /* terminate list */ 76 }; 77 78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl); 79 80 static int cards_found; 81 82 /* 83 * VLB I/O addresses 84 */ 85 static unsigned int pcnet32_portlist[] = 86 { 0x300, 0x320, 0x340, 0x360, 0 }; 87 88 static int pcnet32_debug; 89 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */ 90 static int pcnet32vlb; /* check for VLB cards ? */ 91 92 static struct net_device *pcnet32_dev; 93 94 static int max_interrupt_work = 2; 95 static int rx_copybreak = 200; 96 97 #define PCNET32_PORT_AUI 0x00 98 #define PCNET32_PORT_10BT 0x01 99 #define PCNET32_PORT_GPSI 0x02 100 #define PCNET32_PORT_MII 0x03 101 102 #define PCNET32_PORT_PORTSEL 0x03 103 #define PCNET32_PORT_ASEL 0x04 104 #define PCNET32_PORT_100 0x40 105 #define PCNET32_PORT_FD 0x80 106 107 #define PCNET32_DMA_MASK 0xffffffff 108 109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ)) 110 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4)) 111 112 /* 113 * table to translate option values from tulip 114 * to internal options 115 */ 116 static const unsigned char options_mapping[] = { 117 PCNET32_PORT_ASEL, /* 0 Auto-select */ 118 PCNET32_PORT_AUI, /* 1 BNC/AUI */ 119 PCNET32_PORT_AUI, /* 2 AUI/BNC */ 120 PCNET32_PORT_ASEL, /* 3 not supported */ 121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */ 122 PCNET32_PORT_ASEL, /* 5 not supported */ 123 PCNET32_PORT_ASEL, /* 6 not supported */ 124 PCNET32_PORT_ASEL, /* 7 not supported */ 125 PCNET32_PORT_ASEL, /* 8 not supported */ 126 PCNET32_PORT_MII, /* 9 MII 10baseT */ 127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */ 128 PCNET32_PORT_MII, /* 11 MII (autosel) */ 129 PCNET32_PORT_10BT, /* 12 10BaseT */ 130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */ 131 /* 14 MII 100BaseTx-FD */ 132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, 133 PCNET32_PORT_ASEL /* 15 not supported */ 134 }; 135 136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = { 137 "Loopback test (offline)" 138 }; 139 140 #define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test) 141 142 #define PCNET32_NUM_REGS 136 143 144 #define MAX_UNITS 8 /* More are supported, limit only on options */ 145 static int options[MAX_UNITS]; 146 static int full_duplex[MAX_UNITS]; 147 static int homepna[MAX_UNITS]; 148 149 /* 150 * Theory of Operation 151 * 152 * This driver uses the same software structure as the normal lance 153 * driver. So look for a verbose description in lance.c. The differences 154 * to the normal lance driver is the use of the 32bit mode of PCnet32 155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no 156 * 16MB limitation and we don't need bounce buffers. 157 */ 158 159 /* 160 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 163 */ 164 #ifndef PCNET32_LOG_TX_BUFFERS 165 #define PCNET32_LOG_TX_BUFFERS 4 166 #define PCNET32_LOG_RX_BUFFERS 5 167 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */ 168 #define PCNET32_LOG_MAX_RX_BUFFERS 9 169 #endif 170 171 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS)) 172 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS)) 173 174 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS)) 175 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS)) 176 177 #define PKT_BUF_SKB 1544 178 /* actual buffer length after being aligned */ 179 #define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN) 180 /* chip wants twos complement of the (aligned) buffer length */ 181 #define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB) 182 183 /* Offsets from base I/O address. */ 184 #define PCNET32_WIO_RDP 0x10 185 #define PCNET32_WIO_RAP 0x12 186 #define PCNET32_WIO_RESET 0x14 187 #define PCNET32_WIO_BDP 0x16 188 189 #define PCNET32_DWIO_RDP 0x10 190 #define PCNET32_DWIO_RAP 0x14 191 #define PCNET32_DWIO_RESET 0x18 192 #define PCNET32_DWIO_BDP 0x1C 193 194 #define PCNET32_TOTAL_SIZE 0x20 195 196 #define CSR0 0 197 #define CSR0_INIT 0x1 198 #define CSR0_START 0x2 199 #define CSR0_STOP 0x4 200 #define CSR0_TXPOLL 0x8 201 #define CSR0_INTEN 0x40 202 #define CSR0_IDON 0x0100 203 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN) 204 #define PCNET32_INIT_LOW 1 205 #define PCNET32_INIT_HIGH 2 206 #define CSR3 3 207 #define CSR4 4 208 #define CSR5 5 209 #define CSR5_SUSPEND 0x0001 210 #define CSR15 15 211 #define PCNET32_MC_FILTER 8 212 213 #define PCNET32_79C970A 0x2621 214 215 /* The PCNET32 Rx and Tx ring descriptors. */ 216 struct pcnet32_rx_head { 217 __le32 base; 218 __le16 buf_length; /* two`s complement of length */ 219 __le16 status; 220 __le32 msg_length; 221 __le32 reserved; 222 }; 223 224 struct pcnet32_tx_head { 225 __le32 base; 226 __le16 length; /* two`s complement of length */ 227 __le16 status; 228 __le32 misc; 229 __le32 reserved; 230 }; 231 232 /* The PCNET32 32-Bit initialization block, described in databook. */ 233 struct pcnet32_init_block { 234 __le16 mode; 235 __le16 tlen_rlen; 236 u8 phys_addr[6]; 237 __le16 reserved; 238 __le32 filter[2]; 239 /* Receive and transmit ring base, along with extra bits. */ 240 __le32 rx_ring; 241 __le32 tx_ring; 242 }; 243 244 /* PCnet32 access functions */ 245 struct pcnet32_access { 246 u16 (*read_csr) (unsigned long, int); 247 void (*write_csr) (unsigned long, int, u16); 248 u16 (*read_bcr) (unsigned long, int); 249 void (*write_bcr) (unsigned long, int, u16); 250 u16 (*read_rap) (unsigned long); 251 void (*write_rap) (unsigned long, u16); 252 void (*reset) (unsigned long); 253 }; 254 255 /* 256 * The first field of pcnet32_private is read by the ethernet device 257 * so the structure should be allocated using pci_alloc_consistent(). 258 */ 259 struct pcnet32_private { 260 struct pcnet32_init_block *init_block; 261 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */ 262 struct pcnet32_rx_head *rx_ring; 263 struct pcnet32_tx_head *tx_ring; 264 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block, 265 returned by pci_alloc_consistent */ 266 struct pci_dev *pci_dev; 267 const char *name; 268 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 269 struct sk_buff **tx_skbuff; 270 struct sk_buff **rx_skbuff; 271 dma_addr_t *tx_dma_addr; 272 dma_addr_t *rx_dma_addr; 273 const struct pcnet32_access *a; 274 spinlock_t lock; /* Guard lock */ 275 unsigned int cur_rx, cur_tx; /* The next free ring entry */ 276 unsigned int rx_ring_size; /* current rx ring size */ 277 unsigned int tx_ring_size; /* current tx ring size */ 278 unsigned int rx_mod_mask; /* rx ring modular mask */ 279 unsigned int tx_mod_mask; /* tx ring modular mask */ 280 unsigned short rx_len_bits; 281 unsigned short tx_len_bits; 282 dma_addr_t rx_ring_dma_addr; 283 dma_addr_t tx_ring_dma_addr; 284 unsigned int dirty_rx, /* ring entries to be freed. */ 285 dirty_tx; 286 287 struct net_device *dev; 288 struct napi_struct napi; 289 char tx_full; 290 char phycount; /* number of phys found */ 291 int options; 292 unsigned int shared_irq:1, /* shared irq possible */ 293 dxsuflo:1, /* disable transmit stop on uflo */ 294 mii:1; /* mii port available */ 295 struct net_device *next; 296 struct mii_if_info mii_if; 297 struct timer_list watchdog_timer; 298 u32 msg_enable; /* debug message level */ 299 300 /* each bit indicates an available PHY */ 301 u32 phymask; 302 unsigned short chip_version; /* which variant this is */ 303 304 /* saved registers during ethtool blink */ 305 u16 save_regs[4]; 306 }; 307 308 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *); 309 static int pcnet32_probe1(unsigned long, int, struct pci_dev *); 310 static int pcnet32_open(struct net_device *); 311 static int pcnet32_init_ring(struct net_device *); 312 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *, 313 struct net_device *); 314 static void pcnet32_tx_timeout(struct net_device *dev); 315 static irqreturn_t pcnet32_interrupt(int, void *); 316 static int pcnet32_close(struct net_device *); 317 static struct net_device_stats *pcnet32_get_stats(struct net_device *); 318 static void pcnet32_load_multicast(struct net_device *dev); 319 static void pcnet32_set_multicast_list(struct net_device *); 320 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int); 321 static void pcnet32_watchdog(struct net_device *); 322 static int mdio_read(struct net_device *dev, int phy_id, int reg_num); 323 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, 324 int val); 325 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits); 326 static void pcnet32_ethtool_test(struct net_device *dev, 327 struct ethtool_test *eth_test, u64 * data); 328 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1); 329 static int pcnet32_get_regs_len(struct net_device *dev); 330 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 331 void *ptr); 332 static void pcnet32_purge_tx_ring(struct net_device *dev); 333 static int pcnet32_alloc_ring(struct net_device *dev, const char *name); 334 static void pcnet32_free_ring(struct net_device *dev); 335 static void pcnet32_check_media(struct net_device *dev, int verbose); 336 337 static u16 pcnet32_wio_read_csr(unsigned long addr, int index) 338 { 339 outw(index, addr + PCNET32_WIO_RAP); 340 return inw(addr + PCNET32_WIO_RDP); 341 } 342 343 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val) 344 { 345 outw(index, addr + PCNET32_WIO_RAP); 346 outw(val, addr + PCNET32_WIO_RDP); 347 } 348 349 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index) 350 { 351 outw(index, addr + PCNET32_WIO_RAP); 352 return inw(addr + PCNET32_WIO_BDP); 353 } 354 355 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val) 356 { 357 outw(index, addr + PCNET32_WIO_RAP); 358 outw(val, addr + PCNET32_WIO_BDP); 359 } 360 361 static u16 pcnet32_wio_read_rap(unsigned long addr) 362 { 363 return inw(addr + PCNET32_WIO_RAP); 364 } 365 366 static void pcnet32_wio_write_rap(unsigned long addr, u16 val) 367 { 368 outw(val, addr + PCNET32_WIO_RAP); 369 } 370 371 static void pcnet32_wio_reset(unsigned long addr) 372 { 373 inw(addr + PCNET32_WIO_RESET); 374 } 375 376 static int pcnet32_wio_check(unsigned long addr) 377 { 378 outw(88, addr + PCNET32_WIO_RAP); 379 return inw(addr + PCNET32_WIO_RAP) == 88; 380 } 381 382 static const struct pcnet32_access pcnet32_wio = { 383 .read_csr = pcnet32_wio_read_csr, 384 .write_csr = pcnet32_wio_write_csr, 385 .read_bcr = pcnet32_wio_read_bcr, 386 .write_bcr = pcnet32_wio_write_bcr, 387 .read_rap = pcnet32_wio_read_rap, 388 .write_rap = pcnet32_wio_write_rap, 389 .reset = pcnet32_wio_reset 390 }; 391 392 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index) 393 { 394 outl(index, addr + PCNET32_DWIO_RAP); 395 return inl(addr + PCNET32_DWIO_RDP) & 0xffff; 396 } 397 398 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val) 399 { 400 outl(index, addr + PCNET32_DWIO_RAP); 401 outl(val, addr + PCNET32_DWIO_RDP); 402 } 403 404 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index) 405 { 406 outl(index, addr + PCNET32_DWIO_RAP); 407 return inl(addr + PCNET32_DWIO_BDP) & 0xffff; 408 } 409 410 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val) 411 { 412 outl(index, addr + PCNET32_DWIO_RAP); 413 outl(val, addr + PCNET32_DWIO_BDP); 414 } 415 416 static u16 pcnet32_dwio_read_rap(unsigned long addr) 417 { 418 return inl(addr + PCNET32_DWIO_RAP) & 0xffff; 419 } 420 421 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val) 422 { 423 outl(val, addr + PCNET32_DWIO_RAP); 424 } 425 426 static void pcnet32_dwio_reset(unsigned long addr) 427 { 428 inl(addr + PCNET32_DWIO_RESET); 429 } 430 431 static int pcnet32_dwio_check(unsigned long addr) 432 { 433 outl(88, addr + PCNET32_DWIO_RAP); 434 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88; 435 } 436 437 static const struct pcnet32_access pcnet32_dwio = { 438 .read_csr = pcnet32_dwio_read_csr, 439 .write_csr = pcnet32_dwio_write_csr, 440 .read_bcr = pcnet32_dwio_read_bcr, 441 .write_bcr = pcnet32_dwio_write_bcr, 442 .read_rap = pcnet32_dwio_read_rap, 443 .write_rap = pcnet32_dwio_write_rap, 444 .reset = pcnet32_dwio_reset 445 }; 446 447 static void pcnet32_netif_stop(struct net_device *dev) 448 { 449 struct pcnet32_private *lp = netdev_priv(dev); 450 451 dev->trans_start = jiffies; /* prevent tx timeout */ 452 napi_disable(&lp->napi); 453 netif_tx_disable(dev); 454 } 455 456 static void pcnet32_netif_start(struct net_device *dev) 457 { 458 struct pcnet32_private *lp = netdev_priv(dev); 459 ulong ioaddr = dev->base_addr; 460 u16 val; 461 462 netif_wake_queue(dev); 463 val = lp->a->read_csr(ioaddr, CSR3); 464 val &= 0x00ff; 465 lp->a->write_csr(ioaddr, CSR3, val); 466 napi_enable(&lp->napi); 467 } 468 469 /* 470 * Allocate space for the new sized tx ring. 471 * Free old resources 472 * Save new resources. 473 * Any failure keeps old resources. 474 * Must be called with lp->lock held. 475 */ 476 static void pcnet32_realloc_tx_ring(struct net_device *dev, 477 struct pcnet32_private *lp, 478 unsigned int size) 479 { 480 dma_addr_t new_ring_dma_addr; 481 dma_addr_t *new_dma_addr_list; 482 struct pcnet32_tx_head *new_tx_ring; 483 struct sk_buff **new_skb_list; 484 485 pcnet32_purge_tx_ring(dev); 486 487 new_tx_ring = pci_alloc_consistent(lp->pci_dev, 488 sizeof(struct pcnet32_tx_head) * 489 (1 << size), 490 &new_ring_dma_addr); 491 if (new_tx_ring == NULL) { 492 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 493 return; 494 } 495 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size)); 496 497 new_dma_addr_list = kcalloc(1 << size, sizeof(dma_addr_t), 498 GFP_ATOMIC); 499 if (!new_dma_addr_list) 500 goto free_new_tx_ring; 501 502 new_skb_list = kcalloc(1 << size, sizeof(struct sk_buff *), 503 GFP_ATOMIC); 504 if (!new_skb_list) 505 goto free_new_lists; 506 507 kfree(lp->tx_skbuff); 508 kfree(lp->tx_dma_addr); 509 pci_free_consistent(lp->pci_dev, 510 sizeof(struct pcnet32_tx_head) * 511 lp->tx_ring_size, lp->tx_ring, 512 lp->tx_ring_dma_addr); 513 514 lp->tx_ring_size = (1 << size); 515 lp->tx_mod_mask = lp->tx_ring_size - 1; 516 lp->tx_len_bits = (size << 12); 517 lp->tx_ring = new_tx_ring; 518 lp->tx_ring_dma_addr = new_ring_dma_addr; 519 lp->tx_dma_addr = new_dma_addr_list; 520 lp->tx_skbuff = new_skb_list; 521 return; 522 523 free_new_lists: 524 kfree(new_dma_addr_list); 525 free_new_tx_ring: 526 pci_free_consistent(lp->pci_dev, 527 sizeof(struct pcnet32_tx_head) * 528 (1 << size), 529 new_tx_ring, 530 new_ring_dma_addr); 531 } 532 533 /* 534 * Allocate space for the new sized rx ring. 535 * Re-use old receive buffers. 536 * alloc extra buffers 537 * free unneeded buffers 538 * free unneeded buffers 539 * Save new resources. 540 * Any failure keeps old resources. 541 * Must be called with lp->lock held. 542 */ 543 static void pcnet32_realloc_rx_ring(struct net_device *dev, 544 struct pcnet32_private *lp, 545 unsigned int size) 546 { 547 dma_addr_t new_ring_dma_addr; 548 dma_addr_t *new_dma_addr_list; 549 struct pcnet32_rx_head *new_rx_ring; 550 struct sk_buff **new_skb_list; 551 int new, overlap; 552 553 new_rx_ring = pci_alloc_consistent(lp->pci_dev, 554 sizeof(struct pcnet32_rx_head) * 555 (1 << size), 556 &new_ring_dma_addr); 557 if (new_rx_ring == NULL) { 558 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 559 return; 560 } 561 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size)); 562 563 new_dma_addr_list = kcalloc(1 << size, sizeof(dma_addr_t), GFP_ATOMIC); 564 if (!new_dma_addr_list) 565 goto free_new_rx_ring; 566 567 new_skb_list = kcalloc(1 << size, sizeof(struct sk_buff *), 568 GFP_ATOMIC); 569 if (!new_skb_list) 570 goto free_new_lists; 571 572 /* first copy the current receive buffers */ 573 overlap = min(size, lp->rx_ring_size); 574 for (new = 0; new < overlap; new++) { 575 new_rx_ring[new] = lp->rx_ring[new]; 576 new_dma_addr_list[new] = lp->rx_dma_addr[new]; 577 new_skb_list[new] = lp->rx_skbuff[new]; 578 } 579 /* now allocate any new buffers needed */ 580 for (; new < size; new++) { 581 struct sk_buff *rx_skbuff; 582 new_skb_list[new] = netdev_alloc_skb(dev, PKT_BUF_SKB); 583 rx_skbuff = new_skb_list[new]; 584 if (!rx_skbuff) { 585 /* keep the original lists and buffers */ 586 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n", 587 __func__); 588 goto free_all_new; 589 } 590 skb_reserve(rx_skbuff, NET_IP_ALIGN); 591 592 new_dma_addr_list[new] = 593 pci_map_single(lp->pci_dev, rx_skbuff->data, 594 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 595 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]); 596 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE); 597 new_rx_ring[new].status = cpu_to_le16(0x8000); 598 } 599 /* and free any unneeded buffers */ 600 for (; new < lp->rx_ring_size; new++) { 601 if (lp->rx_skbuff[new]) { 602 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new], 603 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 604 dev_kfree_skb(lp->rx_skbuff[new]); 605 } 606 } 607 608 kfree(lp->rx_skbuff); 609 kfree(lp->rx_dma_addr); 610 pci_free_consistent(lp->pci_dev, 611 sizeof(struct pcnet32_rx_head) * 612 lp->rx_ring_size, lp->rx_ring, 613 lp->rx_ring_dma_addr); 614 615 lp->rx_ring_size = (1 << size); 616 lp->rx_mod_mask = lp->rx_ring_size - 1; 617 lp->rx_len_bits = (size << 4); 618 lp->rx_ring = new_rx_ring; 619 lp->rx_ring_dma_addr = new_ring_dma_addr; 620 lp->rx_dma_addr = new_dma_addr_list; 621 lp->rx_skbuff = new_skb_list; 622 return; 623 624 free_all_new: 625 while (--new >= lp->rx_ring_size) { 626 if (new_skb_list[new]) { 627 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new], 628 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 629 dev_kfree_skb(new_skb_list[new]); 630 } 631 } 632 kfree(new_skb_list); 633 free_new_lists: 634 kfree(new_dma_addr_list); 635 free_new_rx_ring: 636 pci_free_consistent(lp->pci_dev, 637 sizeof(struct pcnet32_rx_head) * 638 (1 << size), 639 new_rx_ring, 640 new_ring_dma_addr); 641 } 642 643 static void pcnet32_purge_rx_ring(struct net_device *dev) 644 { 645 struct pcnet32_private *lp = netdev_priv(dev); 646 int i; 647 648 /* free all allocated skbuffs */ 649 for (i = 0; i < lp->rx_ring_size; i++) { 650 lp->rx_ring[i].status = 0; /* CPU owns buffer */ 651 wmb(); /* Make sure adapter sees owner change */ 652 if (lp->rx_skbuff[i]) { 653 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], 654 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 655 dev_kfree_skb_any(lp->rx_skbuff[i]); 656 } 657 lp->rx_skbuff[i] = NULL; 658 lp->rx_dma_addr[i] = 0; 659 } 660 } 661 662 #ifdef CONFIG_NET_POLL_CONTROLLER 663 static void pcnet32_poll_controller(struct net_device *dev) 664 { 665 disable_irq(dev->irq); 666 pcnet32_interrupt(0, dev); 667 enable_irq(dev->irq); 668 } 669 #endif 670 671 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 672 { 673 struct pcnet32_private *lp = netdev_priv(dev); 674 unsigned long flags; 675 int r = -EOPNOTSUPP; 676 677 if (lp->mii) { 678 spin_lock_irqsave(&lp->lock, flags); 679 mii_ethtool_gset(&lp->mii_if, cmd); 680 spin_unlock_irqrestore(&lp->lock, flags); 681 r = 0; 682 } 683 return r; 684 } 685 686 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 687 { 688 struct pcnet32_private *lp = netdev_priv(dev); 689 unsigned long flags; 690 int r = -EOPNOTSUPP; 691 692 if (lp->mii) { 693 spin_lock_irqsave(&lp->lock, flags); 694 r = mii_ethtool_sset(&lp->mii_if, cmd); 695 spin_unlock_irqrestore(&lp->lock, flags); 696 } 697 return r; 698 } 699 700 static void pcnet32_get_drvinfo(struct net_device *dev, 701 struct ethtool_drvinfo *info) 702 { 703 struct pcnet32_private *lp = netdev_priv(dev); 704 705 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 706 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 707 if (lp->pci_dev) 708 strlcpy(info->bus_info, pci_name(lp->pci_dev), 709 sizeof(info->bus_info)); 710 else 711 snprintf(info->bus_info, sizeof(info->bus_info), 712 "VLB 0x%lx", dev->base_addr); 713 } 714 715 static u32 pcnet32_get_link(struct net_device *dev) 716 { 717 struct pcnet32_private *lp = netdev_priv(dev); 718 unsigned long flags; 719 int r; 720 721 spin_lock_irqsave(&lp->lock, flags); 722 if (lp->mii) { 723 r = mii_link_ok(&lp->mii_if); 724 } else if (lp->chip_version >= PCNET32_79C970A) { 725 ulong ioaddr = dev->base_addr; /* card base I/O address */ 726 r = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 727 } else { /* can not detect link on really old chips */ 728 r = 1; 729 } 730 spin_unlock_irqrestore(&lp->lock, flags); 731 732 return r; 733 } 734 735 static u32 pcnet32_get_msglevel(struct net_device *dev) 736 { 737 struct pcnet32_private *lp = netdev_priv(dev); 738 return lp->msg_enable; 739 } 740 741 static void pcnet32_set_msglevel(struct net_device *dev, u32 value) 742 { 743 struct pcnet32_private *lp = netdev_priv(dev); 744 lp->msg_enable = value; 745 } 746 747 static int pcnet32_nway_reset(struct net_device *dev) 748 { 749 struct pcnet32_private *lp = netdev_priv(dev); 750 unsigned long flags; 751 int r = -EOPNOTSUPP; 752 753 if (lp->mii) { 754 spin_lock_irqsave(&lp->lock, flags); 755 r = mii_nway_restart(&lp->mii_if); 756 spin_unlock_irqrestore(&lp->lock, flags); 757 } 758 return r; 759 } 760 761 static void pcnet32_get_ringparam(struct net_device *dev, 762 struct ethtool_ringparam *ering) 763 { 764 struct pcnet32_private *lp = netdev_priv(dev); 765 766 ering->tx_max_pending = TX_MAX_RING_SIZE; 767 ering->tx_pending = lp->tx_ring_size; 768 ering->rx_max_pending = RX_MAX_RING_SIZE; 769 ering->rx_pending = lp->rx_ring_size; 770 } 771 772 static int pcnet32_set_ringparam(struct net_device *dev, 773 struct ethtool_ringparam *ering) 774 { 775 struct pcnet32_private *lp = netdev_priv(dev); 776 unsigned long flags; 777 unsigned int size; 778 ulong ioaddr = dev->base_addr; 779 int i; 780 781 if (ering->rx_mini_pending || ering->rx_jumbo_pending) 782 return -EINVAL; 783 784 if (netif_running(dev)) 785 pcnet32_netif_stop(dev); 786 787 spin_lock_irqsave(&lp->lock, flags); 788 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 789 790 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE); 791 792 /* set the minimum ring size to 4, to allow the loopback test to work 793 * unchanged. 794 */ 795 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) { 796 if (size <= (1 << i)) 797 break; 798 } 799 if ((1 << i) != lp->tx_ring_size) 800 pcnet32_realloc_tx_ring(dev, lp, i); 801 802 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE); 803 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) { 804 if (size <= (1 << i)) 805 break; 806 } 807 if ((1 << i) != lp->rx_ring_size) 808 pcnet32_realloc_rx_ring(dev, lp, i); 809 810 lp->napi.weight = lp->rx_ring_size / 2; 811 812 if (netif_running(dev)) { 813 pcnet32_netif_start(dev); 814 pcnet32_restart(dev, CSR0_NORMAL); 815 } 816 817 spin_unlock_irqrestore(&lp->lock, flags); 818 819 netif_info(lp, drv, dev, "Ring Param Settings: RX: %d, TX: %d\n", 820 lp->rx_ring_size, lp->tx_ring_size); 821 822 return 0; 823 } 824 825 static void pcnet32_get_strings(struct net_device *dev, u32 stringset, 826 u8 *data) 827 { 828 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test)); 829 } 830 831 static int pcnet32_get_sset_count(struct net_device *dev, int sset) 832 { 833 switch (sset) { 834 case ETH_SS_TEST: 835 return PCNET32_TEST_LEN; 836 default: 837 return -EOPNOTSUPP; 838 } 839 } 840 841 static void pcnet32_ethtool_test(struct net_device *dev, 842 struct ethtool_test *test, u64 * data) 843 { 844 struct pcnet32_private *lp = netdev_priv(dev); 845 int rc; 846 847 if (test->flags == ETH_TEST_FL_OFFLINE) { 848 rc = pcnet32_loopback_test(dev, data); 849 if (rc) { 850 netif_printk(lp, hw, KERN_DEBUG, dev, 851 "Loopback test failed\n"); 852 test->flags |= ETH_TEST_FL_FAILED; 853 } else 854 netif_printk(lp, hw, KERN_DEBUG, dev, 855 "Loopback test passed\n"); 856 } else 857 netif_printk(lp, hw, KERN_DEBUG, dev, 858 "No tests to run (specify 'Offline' on ethtool)\n"); 859 } /* end pcnet32_ethtool_test */ 860 861 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1) 862 { 863 struct pcnet32_private *lp = netdev_priv(dev); 864 const struct pcnet32_access *a = lp->a; /* access to registers */ 865 ulong ioaddr = dev->base_addr; /* card base I/O address */ 866 struct sk_buff *skb; /* sk buff */ 867 int x, i; /* counters */ 868 int numbuffs = 4; /* number of TX/RX buffers and descs */ 869 u16 status = 0x8300; /* TX ring status */ 870 __le16 teststatus; /* test of ring status */ 871 int rc; /* return code */ 872 int size; /* size of packets */ 873 unsigned char *packet; /* source packet data */ 874 static const int data_len = 60; /* length of source packets */ 875 unsigned long flags; 876 unsigned long ticks; 877 878 rc = 1; /* default to fail */ 879 880 if (netif_running(dev)) 881 pcnet32_netif_stop(dev); 882 883 spin_lock_irqsave(&lp->lock, flags); 884 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ 885 886 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size)); 887 888 /* Reset the PCNET32 */ 889 lp->a->reset(ioaddr); 890 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 891 892 /* switch pcnet32 to 32bit mode */ 893 lp->a->write_bcr(ioaddr, 20, 2); 894 895 /* purge & init rings but don't actually restart */ 896 pcnet32_restart(dev, 0x0000); 897 898 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 899 900 /* Initialize Transmit buffers. */ 901 size = data_len + 15; 902 for (x = 0; x < numbuffs; x++) { 903 skb = netdev_alloc_skb(dev, size); 904 if (!skb) { 905 netif_printk(lp, hw, KERN_DEBUG, dev, 906 "Cannot allocate skb at line: %d!\n", 907 __LINE__); 908 goto clean_up; 909 } 910 packet = skb->data; 911 skb_put(skb, size); /* create space for data */ 912 lp->tx_skbuff[x] = skb; 913 lp->tx_ring[x].length = cpu_to_le16(-skb->len); 914 lp->tx_ring[x].misc = 0; 915 916 /* put DA and SA into the skb */ 917 for (i = 0; i < 6; i++) 918 *packet++ = dev->dev_addr[i]; 919 for (i = 0; i < 6; i++) 920 *packet++ = dev->dev_addr[i]; 921 /* type */ 922 *packet++ = 0x08; 923 *packet++ = 0x06; 924 /* packet number */ 925 *packet++ = x; 926 /* fill packet with data */ 927 for (i = 0; i < data_len; i++) 928 *packet++ = i; 929 930 lp->tx_dma_addr[x] = 931 pci_map_single(lp->pci_dev, skb->data, skb->len, 932 PCI_DMA_TODEVICE); 933 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]); 934 wmb(); /* Make sure owner changes after all others are visible */ 935 lp->tx_ring[x].status = cpu_to_le16(status); 936 } 937 938 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */ 939 a->write_bcr(ioaddr, 32, x | 0x0002); 940 941 /* set int loopback in CSR15 */ 942 x = a->read_csr(ioaddr, CSR15) & 0xfffc; 943 lp->a->write_csr(ioaddr, CSR15, x | 0x0044); 944 945 teststatus = cpu_to_le16(0x8000); 946 lp->a->write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */ 947 948 /* Check status of descriptors */ 949 for (x = 0; x < numbuffs; x++) { 950 ticks = 0; 951 rmb(); 952 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) { 953 spin_unlock_irqrestore(&lp->lock, flags); 954 msleep(1); 955 spin_lock_irqsave(&lp->lock, flags); 956 rmb(); 957 ticks++; 958 } 959 if (ticks == 200) { 960 netif_err(lp, hw, dev, "Desc %d failed to reset!\n", x); 961 break; 962 } 963 } 964 965 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */ 966 wmb(); 967 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) { 968 netdev_printk(KERN_DEBUG, dev, "RX loopback packets:\n"); 969 970 for (x = 0; x < numbuffs; x++) { 971 netdev_printk(KERN_DEBUG, dev, "Packet %d: ", x); 972 skb = lp->rx_skbuff[x]; 973 for (i = 0; i < size; i++) 974 pr_cont(" %02x", *(skb->data + i)); 975 pr_cont("\n"); 976 } 977 } 978 979 x = 0; 980 rc = 0; 981 while (x < numbuffs && !rc) { 982 skb = lp->rx_skbuff[x]; 983 packet = lp->tx_skbuff[x]->data; 984 for (i = 0; i < size; i++) { 985 if (*(skb->data + i) != packet[i]) { 986 netif_printk(lp, hw, KERN_DEBUG, dev, 987 "Error in compare! %2x - %02x %02x\n", 988 i, *(skb->data + i), packet[i]); 989 rc = 1; 990 break; 991 } 992 } 993 x++; 994 } 995 996 clean_up: 997 *data1 = rc; 998 pcnet32_purge_tx_ring(dev); 999 1000 x = a->read_csr(ioaddr, CSR15); 1001 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */ 1002 1003 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */ 1004 a->write_bcr(ioaddr, 32, (x & ~0x0002)); 1005 1006 if (netif_running(dev)) { 1007 pcnet32_netif_start(dev); 1008 pcnet32_restart(dev, CSR0_NORMAL); 1009 } else { 1010 pcnet32_purge_rx_ring(dev); 1011 lp->a->write_bcr(ioaddr, 20, 4); /* return to 16bit mode */ 1012 } 1013 spin_unlock_irqrestore(&lp->lock, flags); 1014 1015 return rc; 1016 } /* end pcnet32_loopback_test */ 1017 1018 static int pcnet32_set_phys_id(struct net_device *dev, 1019 enum ethtool_phys_id_state state) 1020 { 1021 struct pcnet32_private *lp = netdev_priv(dev); 1022 const struct pcnet32_access *a = lp->a; 1023 ulong ioaddr = dev->base_addr; 1024 unsigned long flags; 1025 int i; 1026 1027 switch (state) { 1028 case ETHTOOL_ID_ACTIVE: 1029 /* Save the current value of the bcrs */ 1030 spin_lock_irqsave(&lp->lock, flags); 1031 for (i = 4; i < 8; i++) 1032 lp->save_regs[i - 4] = a->read_bcr(ioaddr, i); 1033 spin_unlock_irqrestore(&lp->lock, flags); 1034 return 2; /* cycle on/off twice per second */ 1035 1036 case ETHTOOL_ID_ON: 1037 case ETHTOOL_ID_OFF: 1038 /* Blink the led */ 1039 spin_lock_irqsave(&lp->lock, flags); 1040 for (i = 4; i < 8; i++) 1041 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000); 1042 spin_unlock_irqrestore(&lp->lock, flags); 1043 break; 1044 1045 case ETHTOOL_ID_INACTIVE: 1046 /* Restore the original value of the bcrs */ 1047 spin_lock_irqsave(&lp->lock, flags); 1048 for (i = 4; i < 8; i++) 1049 a->write_bcr(ioaddr, i, lp->save_regs[i - 4]); 1050 spin_unlock_irqrestore(&lp->lock, flags); 1051 } 1052 return 0; 1053 } 1054 1055 /* 1056 * lp->lock must be held. 1057 */ 1058 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags, 1059 int can_sleep) 1060 { 1061 int csr5; 1062 struct pcnet32_private *lp = netdev_priv(dev); 1063 const struct pcnet32_access *a = lp->a; 1064 ulong ioaddr = dev->base_addr; 1065 int ticks; 1066 1067 /* really old chips have to be stopped. */ 1068 if (lp->chip_version < PCNET32_79C970A) 1069 return 0; 1070 1071 /* set SUSPEND (SPND) - CSR5 bit 0 */ 1072 csr5 = a->read_csr(ioaddr, CSR5); 1073 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); 1074 1075 /* poll waiting for bit to be set */ 1076 ticks = 0; 1077 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { 1078 spin_unlock_irqrestore(&lp->lock, *flags); 1079 if (can_sleep) 1080 msleep(1); 1081 else 1082 mdelay(1); 1083 spin_lock_irqsave(&lp->lock, *flags); 1084 ticks++; 1085 if (ticks > 200) { 1086 netif_printk(lp, hw, KERN_DEBUG, dev, 1087 "Error getting into suspend!\n"); 1088 return 0; 1089 } 1090 } 1091 return 1; 1092 } 1093 1094 /* 1095 * process one receive descriptor entry 1096 */ 1097 1098 static void pcnet32_rx_entry(struct net_device *dev, 1099 struct pcnet32_private *lp, 1100 struct pcnet32_rx_head *rxp, 1101 int entry) 1102 { 1103 int status = (short)le16_to_cpu(rxp->status) >> 8; 1104 int rx_in_place = 0; 1105 struct sk_buff *skb; 1106 short pkt_len; 1107 1108 if (status != 0x03) { /* There was an error. */ 1109 /* 1110 * There is a tricky error noted by John Murphy, 1111 * <murf@perftech.com> to Russ Nelson: Even with full-sized 1112 * buffers it's possible for a jabber packet to use two 1113 * buffers, with only the last correctly noting the error. 1114 */ 1115 if (status & 0x01) /* Only count a general error at the */ 1116 dev->stats.rx_errors++; /* end of a packet. */ 1117 if (status & 0x20) 1118 dev->stats.rx_frame_errors++; 1119 if (status & 0x10) 1120 dev->stats.rx_over_errors++; 1121 if (status & 0x08) 1122 dev->stats.rx_crc_errors++; 1123 if (status & 0x04) 1124 dev->stats.rx_fifo_errors++; 1125 return; 1126 } 1127 1128 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4; 1129 1130 /* Discard oversize frames. */ 1131 if (unlikely(pkt_len > PKT_BUF_SIZE)) { 1132 netif_err(lp, drv, dev, "Impossible packet size %d!\n", 1133 pkt_len); 1134 dev->stats.rx_errors++; 1135 return; 1136 } 1137 if (pkt_len < 60) { 1138 netif_err(lp, rx_err, dev, "Runt packet!\n"); 1139 dev->stats.rx_errors++; 1140 return; 1141 } 1142 1143 if (pkt_len > rx_copybreak) { 1144 struct sk_buff *newskb; 1145 1146 newskb = netdev_alloc_skb(dev, PKT_BUF_SKB); 1147 if (newskb) { 1148 skb_reserve(newskb, NET_IP_ALIGN); 1149 skb = lp->rx_skbuff[entry]; 1150 pci_unmap_single(lp->pci_dev, 1151 lp->rx_dma_addr[entry], 1152 PKT_BUF_SIZE, 1153 PCI_DMA_FROMDEVICE); 1154 skb_put(skb, pkt_len); 1155 lp->rx_skbuff[entry] = newskb; 1156 lp->rx_dma_addr[entry] = 1157 pci_map_single(lp->pci_dev, 1158 newskb->data, 1159 PKT_BUF_SIZE, 1160 PCI_DMA_FROMDEVICE); 1161 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]); 1162 rx_in_place = 1; 1163 } else 1164 skb = NULL; 1165 } else 1166 skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN); 1167 1168 if (skb == NULL) { 1169 netif_err(lp, drv, dev, "Memory squeeze, dropping packet\n"); 1170 dev->stats.rx_dropped++; 1171 return; 1172 } 1173 if (!rx_in_place) { 1174 skb_reserve(skb, NET_IP_ALIGN); 1175 skb_put(skb, pkt_len); /* Make room */ 1176 pci_dma_sync_single_for_cpu(lp->pci_dev, 1177 lp->rx_dma_addr[entry], 1178 pkt_len, 1179 PCI_DMA_FROMDEVICE); 1180 skb_copy_to_linear_data(skb, 1181 (unsigned char *)(lp->rx_skbuff[entry]->data), 1182 pkt_len); 1183 pci_dma_sync_single_for_device(lp->pci_dev, 1184 lp->rx_dma_addr[entry], 1185 pkt_len, 1186 PCI_DMA_FROMDEVICE); 1187 } 1188 dev->stats.rx_bytes += skb->len; 1189 skb->protocol = eth_type_trans(skb, dev); 1190 netif_receive_skb(skb); 1191 dev->stats.rx_packets++; 1192 } 1193 1194 static int pcnet32_rx(struct net_device *dev, int budget) 1195 { 1196 struct pcnet32_private *lp = netdev_priv(dev); 1197 int entry = lp->cur_rx & lp->rx_mod_mask; 1198 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry]; 1199 int npackets = 0; 1200 1201 /* If we own the next entry, it's a new packet. Send it up. */ 1202 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) { 1203 pcnet32_rx_entry(dev, lp, rxp, entry); 1204 npackets += 1; 1205 /* 1206 * The docs say that the buffer length isn't touched, but Andrew 1207 * Boyd of QNX reports that some revs of the 79C965 clear it. 1208 */ 1209 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE); 1210 wmb(); /* Make sure owner changes after others are visible */ 1211 rxp->status = cpu_to_le16(0x8000); 1212 entry = (++lp->cur_rx) & lp->rx_mod_mask; 1213 rxp = &lp->rx_ring[entry]; 1214 } 1215 1216 return npackets; 1217 } 1218 1219 static int pcnet32_tx(struct net_device *dev) 1220 { 1221 struct pcnet32_private *lp = netdev_priv(dev); 1222 unsigned int dirty_tx = lp->dirty_tx; 1223 int delta; 1224 int must_restart = 0; 1225 1226 while (dirty_tx != lp->cur_tx) { 1227 int entry = dirty_tx & lp->tx_mod_mask; 1228 int status = (short)le16_to_cpu(lp->tx_ring[entry].status); 1229 1230 if (status < 0) 1231 break; /* It still hasn't been Txed */ 1232 1233 lp->tx_ring[entry].base = 0; 1234 1235 if (status & 0x4000) { 1236 /* There was a major error, log it. */ 1237 int err_status = le32_to_cpu(lp->tx_ring[entry].misc); 1238 dev->stats.tx_errors++; 1239 netif_err(lp, tx_err, dev, 1240 "Tx error status=%04x err_status=%08x\n", 1241 status, err_status); 1242 if (err_status & 0x04000000) 1243 dev->stats.tx_aborted_errors++; 1244 if (err_status & 0x08000000) 1245 dev->stats.tx_carrier_errors++; 1246 if (err_status & 0x10000000) 1247 dev->stats.tx_window_errors++; 1248 #ifndef DO_DXSUFLO 1249 if (err_status & 0x40000000) { 1250 dev->stats.tx_fifo_errors++; 1251 /* Ackk! On FIFO errors the Tx unit is turned off! */ 1252 /* Remove this verbosity later! */ 1253 netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); 1254 must_restart = 1; 1255 } 1256 #else 1257 if (err_status & 0x40000000) { 1258 dev->stats.tx_fifo_errors++; 1259 if (!lp->dxsuflo) { /* If controller doesn't recover ... */ 1260 /* Ackk! On FIFO errors the Tx unit is turned off! */ 1261 /* Remove this verbosity later! */ 1262 netif_err(lp, tx_err, dev, "Tx FIFO error!\n"); 1263 must_restart = 1; 1264 } 1265 } 1266 #endif 1267 } else { 1268 if (status & 0x1800) 1269 dev->stats.collisions++; 1270 dev->stats.tx_packets++; 1271 } 1272 1273 /* We must free the original skb */ 1274 if (lp->tx_skbuff[entry]) { 1275 pci_unmap_single(lp->pci_dev, 1276 lp->tx_dma_addr[entry], 1277 lp->tx_skbuff[entry]-> 1278 len, PCI_DMA_TODEVICE); 1279 dev_kfree_skb_any(lp->tx_skbuff[entry]); 1280 lp->tx_skbuff[entry] = NULL; 1281 lp->tx_dma_addr[entry] = 0; 1282 } 1283 dirty_tx++; 1284 } 1285 1286 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size); 1287 if (delta > lp->tx_ring_size) { 1288 netif_err(lp, drv, dev, "out-of-sync dirty pointer, %d vs. %d, full=%d\n", 1289 dirty_tx, lp->cur_tx, lp->tx_full); 1290 dirty_tx += lp->tx_ring_size; 1291 delta -= lp->tx_ring_size; 1292 } 1293 1294 if (lp->tx_full && 1295 netif_queue_stopped(dev) && 1296 delta < lp->tx_ring_size - 2) { 1297 /* The ring is no longer full, clear tbusy. */ 1298 lp->tx_full = 0; 1299 netif_wake_queue(dev); 1300 } 1301 lp->dirty_tx = dirty_tx; 1302 1303 return must_restart; 1304 } 1305 1306 static int pcnet32_poll(struct napi_struct *napi, int budget) 1307 { 1308 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi); 1309 struct net_device *dev = lp->dev; 1310 unsigned long ioaddr = dev->base_addr; 1311 unsigned long flags; 1312 int work_done; 1313 u16 val; 1314 1315 work_done = pcnet32_rx(dev, budget); 1316 1317 spin_lock_irqsave(&lp->lock, flags); 1318 if (pcnet32_tx(dev)) { 1319 /* reset the chip to clear the error condition, then restart */ 1320 lp->a->reset(ioaddr); 1321 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 1322 pcnet32_restart(dev, CSR0_START); 1323 netif_wake_queue(dev); 1324 } 1325 spin_unlock_irqrestore(&lp->lock, flags); 1326 1327 if (work_done < budget) { 1328 spin_lock_irqsave(&lp->lock, flags); 1329 1330 __napi_complete(napi); 1331 1332 /* clear interrupt masks */ 1333 val = lp->a->read_csr(ioaddr, CSR3); 1334 val &= 0x00ff; 1335 lp->a->write_csr(ioaddr, CSR3, val); 1336 1337 /* Set interrupt enable. */ 1338 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN); 1339 1340 spin_unlock_irqrestore(&lp->lock, flags); 1341 } 1342 return work_done; 1343 } 1344 1345 #define PCNET32_REGS_PER_PHY 32 1346 #define PCNET32_MAX_PHYS 32 1347 static int pcnet32_get_regs_len(struct net_device *dev) 1348 { 1349 struct pcnet32_private *lp = netdev_priv(dev); 1350 int j = lp->phycount * PCNET32_REGS_PER_PHY; 1351 1352 return (PCNET32_NUM_REGS + j) * sizeof(u16); 1353 } 1354 1355 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1356 void *ptr) 1357 { 1358 int i, csr0; 1359 u16 *buff = ptr; 1360 struct pcnet32_private *lp = netdev_priv(dev); 1361 const struct pcnet32_access *a = lp->a; 1362 ulong ioaddr = dev->base_addr; 1363 unsigned long flags; 1364 1365 spin_lock_irqsave(&lp->lock, flags); 1366 1367 csr0 = a->read_csr(ioaddr, CSR0); 1368 if (!(csr0 & CSR0_STOP)) /* If not stopped */ 1369 pcnet32_suspend(dev, &flags, 1); 1370 1371 /* read address PROM */ 1372 for (i = 0; i < 16; i += 2) 1373 *buff++ = inw(ioaddr + i); 1374 1375 /* read control and status registers */ 1376 for (i = 0; i < 90; i++) 1377 *buff++ = a->read_csr(ioaddr, i); 1378 1379 *buff++ = a->read_csr(ioaddr, 112); 1380 *buff++ = a->read_csr(ioaddr, 114); 1381 1382 /* read bus configuration registers */ 1383 for (i = 0; i < 30; i++) 1384 *buff++ = a->read_bcr(ioaddr, i); 1385 1386 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */ 1387 1388 for (i = 31; i < 36; i++) 1389 *buff++ = a->read_bcr(ioaddr, i); 1390 1391 /* read mii phy registers */ 1392 if (lp->mii) { 1393 int j; 1394 for (j = 0; j < PCNET32_MAX_PHYS; j++) { 1395 if (lp->phymask & (1 << j)) { 1396 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) { 1397 lp->a->write_bcr(ioaddr, 33, 1398 (j << 5) | i); 1399 *buff++ = lp->a->read_bcr(ioaddr, 34); 1400 } 1401 } 1402 } 1403 } 1404 1405 if (!(csr0 & CSR0_STOP)) { /* If not stopped */ 1406 int csr5; 1407 1408 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 1409 csr5 = a->read_csr(ioaddr, CSR5); 1410 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); 1411 } 1412 1413 spin_unlock_irqrestore(&lp->lock, flags); 1414 } 1415 1416 static const struct ethtool_ops pcnet32_ethtool_ops = { 1417 .get_settings = pcnet32_get_settings, 1418 .set_settings = pcnet32_set_settings, 1419 .get_drvinfo = pcnet32_get_drvinfo, 1420 .get_msglevel = pcnet32_get_msglevel, 1421 .set_msglevel = pcnet32_set_msglevel, 1422 .nway_reset = pcnet32_nway_reset, 1423 .get_link = pcnet32_get_link, 1424 .get_ringparam = pcnet32_get_ringparam, 1425 .set_ringparam = pcnet32_set_ringparam, 1426 .get_strings = pcnet32_get_strings, 1427 .self_test = pcnet32_ethtool_test, 1428 .set_phys_id = pcnet32_set_phys_id, 1429 .get_regs_len = pcnet32_get_regs_len, 1430 .get_regs = pcnet32_get_regs, 1431 .get_sset_count = pcnet32_get_sset_count, 1432 }; 1433 1434 /* only probes for non-PCI devices, the rest are handled by 1435 * pci_register_driver via pcnet32_probe_pci */ 1436 1437 static void pcnet32_probe_vlbus(unsigned int *pcnet32_portlist) 1438 { 1439 unsigned int *port, ioaddr; 1440 1441 /* search for PCnet32 VLB cards at known addresses */ 1442 for (port = pcnet32_portlist; (ioaddr = *port); port++) { 1443 if (request_region 1444 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) { 1445 /* check if there is really a pcnet chip on that ioaddr */ 1446 if ((inb(ioaddr + 14) == 0x57) && 1447 (inb(ioaddr + 15) == 0x57)) { 1448 pcnet32_probe1(ioaddr, 0, NULL); 1449 } else { 1450 release_region(ioaddr, PCNET32_TOTAL_SIZE); 1451 } 1452 } 1453 } 1454 } 1455 1456 static int 1457 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent) 1458 { 1459 unsigned long ioaddr; 1460 int err; 1461 1462 err = pci_enable_device(pdev); 1463 if (err < 0) { 1464 if (pcnet32_debug & NETIF_MSG_PROBE) 1465 pr_err("failed to enable device -- err=%d\n", err); 1466 return err; 1467 } 1468 pci_set_master(pdev); 1469 1470 ioaddr = pci_resource_start(pdev, 0); 1471 if (!ioaddr) { 1472 if (pcnet32_debug & NETIF_MSG_PROBE) 1473 pr_err("card has no PCI IO resources, aborting\n"); 1474 return -ENODEV; 1475 } 1476 1477 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) { 1478 if (pcnet32_debug & NETIF_MSG_PROBE) 1479 pr_err("architecture does not support 32bit PCI busmaster DMA\n"); 1480 return -ENODEV; 1481 } 1482 if (!request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci")) { 1483 if (pcnet32_debug & NETIF_MSG_PROBE) 1484 pr_err("io address range already allocated\n"); 1485 return -EBUSY; 1486 } 1487 1488 err = pcnet32_probe1(ioaddr, 1, pdev); 1489 if (err < 0) 1490 pci_disable_device(pdev); 1491 1492 return err; 1493 } 1494 1495 static const struct net_device_ops pcnet32_netdev_ops = { 1496 .ndo_open = pcnet32_open, 1497 .ndo_stop = pcnet32_close, 1498 .ndo_start_xmit = pcnet32_start_xmit, 1499 .ndo_tx_timeout = pcnet32_tx_timeout, 1500 .ndo_get_stats = pcnet32_get_stats, 1501 .ndo_set_rx_mode = pcnet32_set_multicast_list, 1502 .ndo_do_ioctl = pcnet32_ioctl, 1503 .ndo_change_mtu = eth_change_mtu, 1504 .ndo_set_mac_address = eth_mac_addr, 1505 .ndo_validate_addr = eth_validate_addr, 1506 #ifdef CONFIG_NET_POLL_CONTROLLER 1507 .ndo_poll_controller = pcnet32_poll_controller, 1508 #endif 1509 }; 1510 1511 /* pcnet32_probe1 1512 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci. 1513 * pdev will be NULL when called from pcnet32_probe_vlbus. 1514 */ 1515 static int 1516 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev) 1517 { 1518 struct pcnet32_private *lp; 1519 int i, media; 1520 int fdx, mii, fset, dxsuflo; 1521 int chip_version; 1522 char *chipname; 1523 struct net_device *dev; 1524 const struct pcnet32_access *a = NULL; 1525 u8 promaddr[6]; 1526 int ret = -ENODEV; 1527 1528 /* reset the chip */ 1529 pcnet32_wio_reset(ioaddr); 1530 1531 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */ 1532 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) { 1533 a = &pcnet32_wio; 1534 } else { 1535 pcnet32_dwio_reset(ioaddr); 1536 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && 1537 pcnet32_dwio_check(ioaddr)) { 1538 a = &pcnet32_dwio; 1539 } else { 1540 if (pcnet32_debug & NETIF_MSG_PROBE) 1541 pr_err("No access methods\n"); 1542 goto err_release_region; 1543 } 1544 } 1545 1546 chip_version = 1547 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); 1548 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW)) 1549 pr_info(" PCnet chip version is %#x\n", chip_version); 1550 if ((chip_version & 0xfff) != 0x003) { 1551 if (pcnet32_debug & NETIF_MSG_PROBE) 1552 pr_info("Unsupported chip version\n"); 1553 goto err_release_region; 1554 } 1555 1556 /* initialize variables */ 1557 fdx = mii = fset = dxsuflo = 0; 1558 chip_version = (chip_version >> 12) & 0xffff; 1559 1560 switch (chip_version) { 1561 case 0x2420: 1562 chipname = "PCnet/PCI 79C970"; /* PCI */ 1563 break; 1564 case 0x2430: 1565 if (shared) 1566 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */ 1567 else 1568 chipname = "PCnet/32 79C965"; /* 486/VL bus */ 1569 break; 1570 case 0x2621: 1571 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 1572 fdx = 1; 1573 break; 1574 case 0x2623: 1575 chipname = "PCnet/FAST 79C971"; /* PCI */ 1576 fdx = 1; 1577 mii = 1; 1578 fset = 1; 1579 break; 1580 case 0x2624: 1581 chipname = "PCnet/FAST+ 79C972"; /* PCI */ 1582 fdx = 1; 1583 mii = 1; 1584 fset = 1; 1585 break; 1586 case 0x2625: 1587 chipname = "PCnet/FAST III 79C973"; /* PCI */ 1588 fdx = 1; 1589 mii = 1; 1590 break; 1591 case 0x2626: 1592 chipname = "PCnet/Home 79C978"; /* PCI */ 1593 fdx = 1; 1594 /* 1595 * This is based on specs published at www.amd.com. This section 1596 * assumes that a card with a 79C978 wants to go into standard 1597 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode, 1598 * and the module option homepna=1 can select this instead. 1599 */ 1600 media = a->read_bcr(ioaddr, 49); 1601 media &= ~3; /* default to 10Mb ethernet */ 1602 if (cards_found < MAX_UNITS && homepna[cards_found]) 1603 media |= 1; /* switch to home wiring mode */ 1604 if (pcnet32_debug & NETIF_MSG_PROBE) 1605 printk(KERN_DEBUG PFX "media set to %sMbit mode\n", 1606 (media & 1) ? "1" : "10"); 1607 a->write_bcr(ioaddr, 49, media); 1608 break; 1609 case 0x2627: 1610 chipname = "PCnet/FAST III 79C975"; /* PCI */ 1611 fdx = 1; 1612 mii = 1; 1613 break; 1614 case 0x2628: 1615 chipname = "PCnet/PRO 79C976"; 1616 fdx = 1; 1617 mii = 1; 1618 break; 1619 default: 1620 if (pcnet32_debug & NETIF_MSG_PROBE) 1621 pr_info("PCnet version %#x, no PCnet32 chip\n", 1622 chip_version); 1623 goto err_release_region; 1624 } 1625 1626 /* 1627 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit 1628 * starting until the packet is loaded. Strike one for reliability, lose 1629 * one for latency - although on PCI this isn't a big loss. Older chips 1630 * have FIFO's smaller than a packet, so you can't do this. 1631 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn. 1632 */ 1633 1634 if (fset) { 1635 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860)); 1636 a->write_csr(ioaddr, 80, 1637 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); 1638 dxsuflo = 1; 1639 } 1640 1641 dev = alloc_etherdev(sizeof(*lp)); 1642 if (!dev) { 1643 ret = -ENOMEM; 1644 goto err_release_region; 1645 } 1646 1647 if (pdev) 1648 SET_NETDEV_DEV(dev, &pdev->dev); 1649 1650 if (pcnet32_debug & NETIF_MSG_PROBE) 1651 pr_info("%s at %#3lx,", chipname, ioaddr); 1652 1653 /* In most chips, after a chip reset, the ethernet address is read from the 1654 * station address PROM at the base address and programmed into the 1655 * "Physical Address Registers" CSR12-14. 1656 * As a precautionary measure, we read the PROM values and complain if 1657 * they disagree with the CSRs. If they miscompare, and the PROM addr 1658 * is valid, then the PROM addr is used. 1659 */ 1660 for (i = 0; i < 3; i++) { 1661 unsigned int val; 1662 val = a->read_csr(ioaddr, i + 12) & 0x0ffff; 1663 /* There may be endianness issues here. */ 1664 dev->dev_addr[2 * i] = val & 0x0ff; 1665 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff; 1666 } 1667 1668 /* read PROM address and compare with CSR address */ 1669 for (i = 0; i < 6; i++) 1670 promaddr[i] = inb(ioaddr + i); 1671 1672 if (memcmp(promaddr, dev->dev_addr, 6) || 1673 !is_valid_ether_addr(dev->dev_addr)) { 1674 if (is_valid_ether_addr(promaddr)) { 1675 if (pcnet32_debug & NETIF_MSG_PROBE) { 1676 pr_cont(" warning: CSR address invalid,\n"); 1677 pr_info(" using instead PROM address of"); 1678 } 1679 memcpy(dev->dev_addr, promaddr, 6); 1680 } 1681 } 1682 1683 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */ 1684 if (!is_valid_ether_addr(dev->dev_addr)) 1685 memset(dev->dev_addr, 0, ETH_ALEN); 1686 1687 if (pcnet32_debug & NETIF_MSG_PROBE) { 1688 pr_cont(" %pM", dev->dev_addr); 1689 1690 /* Version 0x2623 and 0x2624 */ 1691 if (((chip_version + 1) & 0xfffe) == 0x2624) { 1692 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ 1693 pr_info(" tx_start_pt(0x%04x):", i); 1694 switch (i >> 10) { 1695 case 0: 1696 pr_cont(" 20 bytes,"); 1697 break; 1698 case 1: 1699 pr_cont(" 64 bytes,"); 1700 break; 1701 case 2: 1702 pr_cont(" 128 bytes,"); 1703 break; 1704 case 3: 1705 pr_cont("~220 bytes,"); 1706 break; 1707 } 1708 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */ 1709 pr_cont(" BCR18(%x):", i & 0xffff); 1710 if (i & (1 << 5)) 1711 pr_cont("BurstWrEn "); 1712 if (i & (1 << 6)) 1713 pr_cont("BurstRdEn "); 1714 if (i & (1 << 7)) 1715 pr_cont("DWordIO "); 1716 if (i & (1 << 11)) 1717 pr_cont("NoUFlow "); 1718 i = a->read_bcr(ioaddr, 25); 1719 pr_info(" SRAMSIZE=0x%04x,", i << 8); 1720 i = a->read_bcr(ioaddr, 26); 1721 pr_cont(" SRAM_BND=0x%04x,", i << 8); 1722 i = a->read_bcr(ioaddr, 27); 1723 if (i & (1 << 14)) 1724 pr_cont("LowLatRx"); 1725 } 1726 } 1727 1728 dev->base_addr = ioaddr; 1729 lp = netdev_priv(dev); 1730 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */ 1731 lp->init_block = pci_alloc_consistent(pdev, sizeof(*lp->init_block), 1732 &lp->init_dma_addr); 1733 if (!lp->init_block) { 1734 if (pcnet32_debug & NETIF_MSG_PROBE) 1735 pr_err("Consistent memory allocation failed\n"); 1736 ret = -ENOMEM; 1737 goto err_free_netdev; 1738 } 1739 lp->pci_dev = pdev; 1740 1741 lp->dev = dev; 1742 1743 spin_lock_init(&lp->lock); 1744 1745 lp->name = chipname; 1746 lp->shared_irq = shared; 1747 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */ 1748 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */ 1749 lp->tx_mod_mask = lp->tx_ring_size - 1; 1750 lp->rx_mod_mask = lp->rx_ring_size - 1; 1751 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12); 1752 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4); 1753 lp->mii_if.full_duplex = fdx; 1754 lp->mii_if.phy_id_mask = 0x1f; 1755 lp->mii_if.reg_num_mask = 0x1f; 1756 lp->dxsuflo = dxsuflo; 1757 lp->mii = mii; 1758 lp->chip_version = chip_version; 1759 lp->msg_enable = pcnet32_debug; 1760 if ((cards_found >= MAX_UNITS) || 1761 (options[cards_found] >= sizeof(options_mapping))) 1762 lp->options = PCNET32_PORT_ASEL; 1763 else 1764 lp->options = options_mapping[options[cards_found]]; 1765 lp->mii_if.dev = dev; 1766 lp->mii_if.mdio_read = mdio_read; 1767 lp->mii_if.mdio_write = mdio_write; 1768 1769 /* napi.weight is used in both the napi and non-napi cases */ 1770 lp->napi.weight = lp->rx_ring_size / 2; 1771 1772 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2); 1773 1774 if (fdx && !(lp->options & PCNET32_PORT_ASEL) && 1775 ((cards_found >= MAX_UNITS) || full_duplex[cards_found])) 1776 lp->options |= PCNET32_PORT_FD; 1777 1778 lp->a = a; 1779 1780 /* prior to register_netdev, dev->name is not yet correct */ 1781 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) { 1782 ret = -ENOMEM; 1783 goto err_free_ring; 1784 } 1785 /* detect special T1/E1 WAN card by checking for MAC address */ 1786 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 && 1787 dev->dev_addr[2] == 0x75) 1788 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI; 1789 1790 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */ 1791 lp->init_block->tlen_rlen = 1792 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); 1793 for (i = 0; i < 6; i++) 1794 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 1795 lp->init_block->filter[0] = 0x00000000; 1796 lp->init_block->filter[1] = 0x00000000; 1797 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); 1798 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); 1799 1800 /* switch pcnet32 to 32bit mode */ 1801 a->write_bcr(ioaddr, 20, 2); 1802 1803 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 1804 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); 1805 1806 if (pdev) { /* use the IRQ provided by PCI */ 1807 dev->irq = pdev->irq; 1808 if (pcnet32_debug & NETIF_MSG_PROBE) 1809 pr_cont(" assigned IRQ %d\n", dev->irq); 1810 } else { 1811 unsigned long irq_mask = probe_irq_on(); 1812 1813 /* 1814 * To auto-IRQ we enable the initialization-done and DMA error 1815 * interrupts. For ISA boards we get a DMA error, but VLB and PCI 1816 * boards will work. 1817 */ 1818 /* Trigger an initialization just for the interrupt. */ 1819 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT); 1820 mdelay(1); 1821 1822 dev->irq = probe_irq_off(irq_mask); 1823 if (!dev->irq) { 1824 if (pcnet32_debug & NETIF_MSG_PROBE) 1825 pr_cont(", failed to detect IRQ line\n"); 1826 ret = -ENODEV; 1827 goto err_free_ring; 1828 } 1829 if (pcnet32_debug & NETIF_MSG_PROBE) 1830 pr_cont(", probed IRQ %d\n", dev->irq); 1831 } 1832 1833 /* Set the mii phy_id so that we can query the link state */ 1834 if (lp->mii) { 1835 /* lp->phycount and lp->phymask are set to 0 by memset above */ 1836 1837 lp->mii_if.phy_id = ((lp->a->read_bcr(ioaddr, 33)) >> 5) & 0x1f; 1838 /* scan for PHYs */ 1839 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 1840 unsigned short id1, id2; 1841 1842 id1 = mdio_read(dev, i, MII_PHYSID1); 1843 if (id1 == 0xffff) 1844 continue; 1845 id2 = mdio_read(dev, i, MII_PHYSID2); 1846 if (id2 == 0xffff) 1847 continue; 1848 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624) 1849 continue; /* 79C971 & 79C972 have phantom phy at id 31 */ 1850 lp->phycount++; 1851 lp->phymask |= (1 << i); 1852 lp->mii_if.phy_id = i; 1853 if (pcnet32_debug & NETIF_MSG_PROBE) 1854 pr_info("Found PHY %04x:%04x at address %d\n", 1855 id1, id2, i); 1856 } 1857 lp->a->write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5); 1858 if (lp->phycount > 1) 1859 lp->options |= PCNET32_PORT_MII; 1860 } 1861 1862 init_timer(&lp->watchdog_timer); 1863 lp->watchdog_timer.data = (unsigned long)dev; 1864 lp->watchdog_timer.function = (void *)&pcnet32_watchdog; 1865 1866 /* The PCNET32-specific entries in the device structure. */ 1867 dev->netdev_ops = &pcnet32_netdev_ops; 1868 dev->ethtool_ops = &pcnet32_ethtool_ops; 1869 dev->watchdog_timeo = (5 * HZ); 1870 1871 /* Fill in the generic fields of the device structure. */ 1872 if (register_netdev(dev)) 1873 goto err_free_ring; 1874 1875 if (pdev) { 1876 pci_set_drvdata(pdev, dev); 1877 } else { 1878 lp->next = pcnet32_dev; 1879 pcnet32_dev = dev; 1880 } 1881 1882 if (pcnet32_debug & NETIF_MSG_PROBE) 1883 pr_info("%s: registered as %s\n", dev->name, lp->name); 1884 cards_found++; 1885 1886 /* enable LED writes */ 1887 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000); 1888 1889 return 0; 1890 1891 err_free_ring: 1892 pcnet32_free_ring(dev); 1893 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 1894 lp->init_block, lp->init_dma_addr); 1895 err_free_netdev: 1896 free_netdev(dev); 1897 err_release_region: 1898 release_region(ioaddr, PCNET32_TOTAL_SIZE); 1899 return ret; 1900 } 1901 1902 /* if any allocation fails, caller must also call pcnet32_free_ring */ 1903 static int pcnet32_alloc_ring(struct net_device *dev, const char *name) 1904 { 1905 struct pcnet32_private *lp = netdev_priv(dev); 1906 1907 lp->tx_ring = pci_alloc_consistent(lp->pci_dev, 1908 sizeof(struct pcnet32_tx_head) * 1909 lp->tx_ring_size, 1910 &lp->tx_ring_dma_addr); 1911 if (lp->tx_ring == NULL) { 1912 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 1913 return -ENOMEM; 1914 } 1915 1916 lp->rx_ring = pci_alloc_consistent(lp->pci_dev, 1917 sizeof(struct pcnet32_rx_head) * 1918 lp->rx_ring_size, 1919 &lp->rx_ring_dma_addr); 1920 if (lp->rx_ring == NULL) { 1921 netif_err(lp, drv, dev, "Consistent memory allocation failed\n"); 1922 return -ENOMEM; 1923 } 1924 1925 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t), 1926 GFP_ATOMIC); 1927 if (!lp->tx_dma_addr) 1928 return -ENOMEM; 1929 1930 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t), 1931 GFP_ATOMIC); 1932 if (!lp->rx_dma_addr) 1933 return -ENOMEM; 1934 1935 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *), 1936 GFP_ATOMIC); 1937 if (!lp->tx_skbuff) 1938 return -ENOMEM; 1939 1940 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *), 1941 GFP_ATOMIC); 1942 if (!lp->rx_skbuff) 1943 return -ENOMEM; 1944 1945 return 0; 1946 } 1947 1948 static void pcnet32_free_ring(struct net_device *dev) 1949 { 1950 struct pcnet32_private *lp = netdev_priv(dev); 1951 1952 kfree(lp->tx_skbuff); 1953 lp->tx_skbuff = NULL; 1954 1955 kfree(lp->rx_skbuff); 1956 lp->rx_skbuff = NULL; 1957 1958 kfree(lp->tx_dma_addr); 1959 lp->tx_dma_addr = NULL; 1960 1961 kfree(lp->rx_dma_addr); 1962 lp->rx_dma_addr = NULL; 1963 1964 if (lp->tx_ring) { 1965 pci_free_consistent(lp->pci_dev, 1966 sizeof(struct pcnet32_tx_head) * 1967 lp->tx_ring_size, lp->tx_ring, 1968 lp->tx_ring_dma_addr); 1969 lp->tx_ring = NULL; 1970 } 1971 1972 if (lp->rx_ring) { 1973 pci_free_consistent(lp->pci_dev, 1974 sizeof(struct pcnet32_rx_head) * 1975 lp->rx_ring_size, lp->rx_ring, 1976 lp->rx_ring_dma_addr); 1977 lp->rx_ring = NULL; 1978 } 1979 } 1980 1981 static int pcnet32_open(struct net_device *dev) 1982 { 1983 struct pcnet32_private *lp = netdev_priv(dev); 1984 struct pci_dev *pdev = lp->pci_dev; 1985 unsigned long ioaddr = dev->base_addr; 1986 u16 val; 1987 int i; 1988 int rc; 1989 unsigned long flags; 1990 1991 if (request_irq(dev->irq, pcnet32_interrupt, 1992 lp->shared_irq ? IRQF_SHARED : 0, dev->name, 1993 (void *)dev)) { 1994 return -EAGAIN; 1995 } 1996 1997 spin_lock_irqsave(&lp->lock, flags); 1998 /* Check for a valid station address */ 1999 if (!is_valid_ether_addr(dev->dev_addr)) { 2000 rc = -EINVAL; 2001 goto err_free_irq; 2002 } 2003 2004 /* Reset the PCNET32 */ 2005 lp->a->reset(ioaddr); 2006 2007 /* switch pcnet32 to 32bit mode */ 2008 lp->a->write_bcr(ioaddr, 20, 2); 2009 2010 netif_printk(lp, ifup, KERN_DEBUG, dev, 2011 "%s() irq %d tx/rx rings %#x/%#x init %#x\n", 2012 __func__, dev->irq, (u32) (lp->tx_ring_dma_addr), 2013 (u32) (lp->rx_ring_dma_addr), 2014 (u32) (lp->init_dma_addr)); 2015 2016 /* set/reset autoselect bit */ 2017 val = lp->a->read_bcr(ioaddr, 2) & ~2; 2018 if (lp->options & PCNET32_PORT_ASEL) 2019 val |= 2; 2020 lp->a->write_bcr(ioaddr, 2, val); 2021 2022 /* handle full duplex setting */ 2023 if (lp->mii_if.full_duplex) { 2024 val = lp->a->read_bcr(ioaddr, 9) & ~3; 2025 if (lp->options & PCNET32_PORT_FD) { 2026 val |= 1; 2027 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI)) 2028 val |= 2; 2029 } else if (lp->options & PCNET32_PORT_ASEL) { 2030 /* workaround of xSeries250, turn on for 79C975 only */ 2031 if (lp->chip_version == 0x2627) 2032 val |= 3; 2033 } 2034 lp->a->write_bcr(ioaddr, 9, val); 2035 } 2036 2037 /* set/reset GPSI bit in test register */ 2038 val = lp->a->read_csr(ioaddr, 124) & ~0x10; 2039 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI) 2040 val |= 0x10; 2041 lp->a->write_csr(ioaddr, 124, val); 2042 2043 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */ 2044 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT && 2045 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX || 2046 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) { 2047 if (lp->options & PCNET32_PORT_ASEL) { 2048 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100; 2049 netif_printk(lp, link, KERN_DEBUG, dev, 2050 "Setting 100Mb-Full Duplex\n"); 2051 } 2052 } 2053 if (lp->phycount < 2) { 2054 /* 2055 * 24 Jun 2004 according AMD, in order to change the PHY, 2056 * DANAS (or DISPM for 79C976) must be set; then select the speed, 2057 * duplex, and/or enable auto negotiation, and clear DANAS 2058 */ 2059 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) { 2060 lp->a->write_bcr(ioaddr, 32, 2061 lp->a->read_bcr(ioaddr, 32) | 0x0080); 2062 /* disable Auto Negotiation, set 10Mpbs, HD */ 2063 val = lp->a->read_bcr(ioaddr, 32) & ~0xb8; 2064 if (lp->options & PCNET32_PORT_FD) 2065 val |= 0x10; 2066 if (lp->options & PCNET32_PORT_100) 2067 val |= 0x08; 2068 lp->a->write_bcr(ioaddr, 32, val); 2069 } else { 2070 if (lp->options & PCNET32_PORT_ASEL) { 2071 lp->a->write_bcr(ioaddr, 32, 2072 lp->a->read_bcr(ioaddr, 2073 32) | 0x0080); 2074 /* enable auto negotiate, setup, disable fd */ 2075 val = lp->a->read_bcr(ioaddr, 32) & ~0x98; 2076 val |= 0x20; 2077 lp->a->write_bcr(ioaddr, 32, val); 2078 } 2079 } 2080 } else { 2081 int first_phy = -1; 2082 u16 bmcr; 2083 u32 bcr9; 2084 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 2085 2086 /* 2087 * There is really no good other way to handle multiple PHYs 2088 * other than turning off all automatics 2089 */ 2090 val = lp->a->read_bcr(ioaddr, 2); 2091 lp->a->write_bcr(ioaddr, 2, val & ~2); 2092 val = lp->a->read_bcr(ioaddr, 32); 2093 lp->a->write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */ 2094 2095 if (!(lp->options & PCNET32_PORT_ASEL)) { 2096 /* setup ecmd */ 2097 ecmd.port = PORT_MII; 2098 ecmd.transceiver = XCVR_INTERNAL; 2099 ecmd.autoneg = AUTONEG_DISABLE; 2100 ethtool_cmd_speed_set(&ecmd, 2101 (lp->options & PCNET32_PORT_100) ? 2102 SPEED_100 : SPEED_10); 2103 bcr9 = lp->a->read_bcr(ioaddr, 9); 2104 2105 if (lp->options & PCNET32_PORT_FD) { 2106 ecmd.duplex = DUPLEX_FULL; 2107 bcr9 |= (1 << 0); 2108 } else { 2109 ecmd.duplex = DUPLEX_HALF; 2110 bcr9 |= ~(1 << 0); 2111 } 2112 lp->a->write_bcr(ioaddr, 9, bcr9); 2113 } 2114 2115 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 2116 if (lp->phymask & (1 << i)) { 2117 /* isolate all but the first PHY */ 2118 bmcr = mdio_read(dev, i, MII_BMCR); 2119 if (first_phy == -1) { 2120 first_phy = i; 2121 mdio_write(dev, i, MII_BMCR, 2122 bmcr & ~BMCR_ISOLATE); 2123 } else { 2124 mdio_write(dev, i, MII_BMCR, 2125 bmcr | BMCR_ISOLATE); 2126 } 2127 /* use mii_ethtool_sset to setup PHY */ 2128 lp->mii_if.phy_id = i; 2129 ecmd.phy_address = i; 2130 if (lp->options & PCNET32_PORT_ASEL) { 2131 mii_ethtool_gset(&lp->mii_if, &ecmd); 2132 ecmd.autoneg = AUTONEG_ENABLE; 2133 } 2134 mii_ethtool_sset(&lp->mii_if, &ecmd); 2135 } 2136 } 2137 lp->mii_if.phy_id = first_phy; 2138 netif_info(lp, link, dev, "Using PHY number %d\n", first_phy); 2139 } 2140 2141 #ifdef DO_DXSUFLO 2142 if (lp->dxsuflo) { /* Disable transmit stop on underflow */ 2143 val = lp->a->read_csr(ioaddr, CSR3); 2144 val |= 0x40; 2145 lp->a->write_csr(ioaddr, CSR3, val); 2146 } 2147 #endif 2148 2149 lp->init_block->mode = 2150 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); 2151 pcnet32_load_multicast(dev); 2152 2153 if (pcnet32_init_ring(dev)) { 2154 rc = -ENOMEM; 2155 goto err_free_ring; 2156 } 2157 2158 napi_enable(&lp->napi); 2159 2160 /* Re-initialize the PCNET32, and start it when done. */ 2161 lp->a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff)); 2162 lp->a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16)); 2163 2164 lp->a->write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */ 2165 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); 2166 2167 netif_start_queue(dev); 2168 2169 if (lp->chip_version >= PCNET32_79C970A) { 2170 /* Print the link status and start the watchdog */ 2171 pcnet32_check_media(dev, 1); 2172 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT); 2173 } 2174 2175 i = 0; 2176 while (i++ < 100) 2177 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) 2178 break; 2179 /* 2180 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton 2181 * reports that doing so triggers a bug in the '974. 2182 */ 2183 lp->a->write_csr(ioaddr, CSR0, CSR0_NORMAL); 2184 2185 netif_printk(lp, ifup, KERN_DEBUG, dev, 2186 "pcnet32 open after %d ticks, init block %#x csr0 %4.4x\n", 2187 i, 2188 (u32) (lp->init_dma_addr), 2189 lp->a->read_csr(ioaddr, CSR0)); 2190 2191 spin_unlock_irqrestore(&lp->lock, flags); 2192 2193 return 0; /* Always succeed */ 2194 2195 err_free_ring: 2196 /* free any allocated skbuffs */ 2197 pcnet32_purge_rx_ring(dev); 2198 2199 /* 2200 * Switch back to 16bit mode to avoid problems with dumb 2201 * DOS packet driver after a warm reboot 2202 */ 2203 lp->a->write_bcr(ioaddr, 20, 4); 2204 2205 err_free_irq: 2206 spin_unlock_irqrestore(&lp->lock, flags); 2207 free_irq(dev->irq, dev); 2208 return rc; 2209 } 2210 2211 /* 2212 * The LANCE has been halted for one reason or another (busmaster memory 2213 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure, 2214 * etc.). Modern LANCE variants always reload their ring-buffer 2215 * configuration when restarted, so we must reinitialize our ring 2216 * context before restarting. As part of this reinitialization, 2217 * find all packets still on the Tx ring and pretend that they had been 2218 * sent (in effect, drop the packets on the floor) - the higher-level 2219 * protocols will time out and retransmit. It'd be better to shuffle 2220 * these skbs to a temp list and then actually re-Tx them after 2221 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com 2222 */ 2223 2224 static void pcnet32_purge_tx_ring(struct net_device *dev) 2225 { 2226 struct pcnet32_private *lp = netdev_priv(dev); 2227 int i; 2228 2229 for (i = 0; i < lp->tx_ring_size; i++) { 2230 lp->tx_ring[i].status = 0; /* CPU owns buffer */ 2231 wmb(); /* Make sure adapter sees owner change */ 2232 if (lp->tx_skbuff[i]) { 2233 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], 2234 lp->tx_skbuff[i]->len, 2235 PCI_DMA_TODEVICE); 2236 dev_kfree_skb_any(lp->tx_skbuff[i]); 2237 } 2238 lp->tx_skbuff[i] = NULL; 2239 lp->tx_dma_addr[i] = 0; 2240 } 2241 } 2242 2243 /* Initialize the PCNET32 Rx and Tx rings. */ 2244 static int pcnet32_init_ring(struct net_device *dev) 2245 { 2246 struct pcnet32_private *lp = netdev_priv(dev); 2247 int i; 2248 2249 lp->tx_full = 0; 2250 lp->cur_rx = lp->cur_tx = 0; 2251 lp->dirty_rx = lp->dirty_tx = 0; 2252 2253 for (i = 0; i < lp->rx_ring_size; i++) { 2254 struct sk_buff *rx_skbuff = lp->rx_skbuff[i]; 2255 if (rx_skbuff == NULL) { 2256 lp->rx_skbuff[i] = netdev_alloc_skb(dev, PKT_BUF_SKB); 2257 rx_skbuff = lp->rx_skbuff[i]; 2258 if (!rx_skbuff) { 2259 /* there is not much we can do at this point */ 2260 netif_err(lp, drv, dev, "%s netdev_alloc_skb failed\n", 2261 __func__); 2262 return -1; 2263 } 2264 skb_reserve(rx_skbuff, NET_IP_ALIGN); 2265 } 2266 2267 rmb(); 2268 if (lp->rx_dma_addr[i] == 0) 2269 lp->rx_dma_addr[i] = 2270 pci_map_single(lp->pci_dev, rx_skbuff->data, 2271 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE); 2272 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]); 2273 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE); 2274 wmb(); /* Make sure owner changes after all others are visible */ 2275 lp->rx_ring[i].status = cpu_to_le16(0x8000); 2276 } 2277 /* The Tx buffer address is filled in as needed, but we do need to clear 2278 * the upper ownership bit. */ 2279 for (i = 0; i < lp->tx_ring_size; i++) { 2280 lp->tx_ring[i].status = 0; /* CPU owns buffer */ 2281 wmb(); /* Make sure adapter sees owner change */ 2282 lp->tx_ring[i].base = 0; 2283 lp->tx_dma_addr[i] = 0; 2284 } 2285 2286 lp->init_block->tlen_rlen = 2287 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits); 2288 for (i = 0; i < 6; i++) 2289 lp->init_block->phys_addr[i] = dev->dev_addr[i]; 2290 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr); 2291 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr); 2292 wmb(); /* Make sure all changes are visible */ 2293 return 0; 2294 } 2295 2296 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit 2297 * then flush the pending transmit operations, re-initialize the ring, 2298 * and tell the chip to initialize. 2299 */ 2300 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits) 2301 { 2302 struct pcnet32_private *lp = netdev_priv(dev); 2303 unsigned long ioaddr = dev->base_addr; 2304 int i; 2305 2306 /* wait for stop */ 2307 for (i = 0; i < 100; i++) 2308 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP) 2309 break; 2310 2311 if (i >= 100) 2312 netif_err(lp, drv, dev, "%s timed out waiting for stop\n", 2313 __func__); 2314 2315 pcnet32_purge_tx_ring(dev); 2316 if (pcnet32_init_ring(dev)) 2317 return; 2318 2319 /* ReInit Ring */ 2320 lp->a->write_csr(ioaddr, CSR0, CSR0_INIT); 2321 i = 0; 2322 while (i++ < 1000) 2323 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) 2324 break; 2325 2326 lp->a->write_csr(ioaddr, CSR0, csr0_bits); 2327 } 2328 2329 static void pcnet32_tx_timeout(struct net_device *dev) 2330 { 2331 struct pcnet32_private *lp = netdev_priv(dev); 2332 unsigned long ioaddr = dev->base_addr, flags; 2333 2334 spin_lock_irqsave(&lp->lock, flags); 2335 /* Transmitter timeout, serious problems. */ 2336 if (pcnet32_debug & NETIF_MSG_DRV) 2337 pr_err("%s: transmit timed out, status %4.4x, resetting\n", 2338 dev->name, lp->a->read_csr(ioaddr, CSR0)); 2339 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2340 dev->stats.tx_errors++; 2341 if (netif_msg_tx_err(lp)) { 2342 int i; 2343 printk(KERN_DEBUG 2344 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.", 2345 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "", 2346 lp->cur_rx); 2347 for (i = 0; i < lp->rx_ring_size; i++) 2348 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", 2349 le32_to_cpu(lp->rx_ring[i].base), 2350 (-le16_to_cpu(lp->rx_ring[i].buf_length)) & 2351 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length), 2352 le16_to_cpu(lp->rx_ring[i].status)); 2353 for (i = 0; i < lp->tx_ring_size; i++) 2354 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ", 2355 le32_to_cpu(lp->tx_ring[i].base), 2356 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff, 2357 le32_to_cpu(lp->tx_ring[i].misc), 2358 le16_to_cpu(lp->tx_ring[i].status)); 2359 printk("\n"); 2360 } 2361 pcnet32_restart(dev, CSR0_NORMAL); 2362 2363 dev->trans_start = jiffies; /* prevent tx timeout */ 2364 netif_wake_queue(dev); 2365 2366 spin_unlock_irqrestore(&lp->lock, flags); 2367 } 2368 2369 static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb, 2370 struct net_device *dev) 2371 { 2372 struct pcnet32_private *lp = netdev_priv(dev); 2373 unsigned long ioaddr = dev->base_addr; 2374 u16 status; 2375 int entry; 2376 unsigned long flags; 2377 2378 spin_lock_irqsave(&lp->lock, flags); 2379 2380 netif_printk(lp, tx_queued, KERN_DEBUG, dev, 2381 "%s() called, csr0 %4.4x\n", 2382 __func__, lp->a->read_csr(ioaddr, CSR0)); 2383 2384 /* Default status -- will not enable Successful-TxDone 2385 * interrupt when that option is available to us. 2386 */ 2387 status = 0x8300; 2388 2389 /* Fill in a Tx ring entry */ 2390 2391 /* Mask to ring buffer boundary. */ 2392 entry = lp->cur_tx & lp->tx_mod_mask; 2393 2394 /* Caution: the write order is important here, set the status 2395 * with the "ownership" bits last. */ 2396 2397 lp->tx_ring[entry].length = cpu_to_le16(-skb->len); 2398 2399 lp->tx_ring[entry].misc = 0x00000000; 2400 2401 lp->tx_skbuff[entry] = skb; 2402 lp->tx_dma_addr[entry] = 2403 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); 2404 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]); 2405 wmb(); /* Make sure owner changes after all others are visible */ 2406 lp->tx_ring[entry].status = cpu_to_le16(status); 2407 2408 lp->cur_tx++; 2409 dev->stats.tx_bytes += skb->len; 2410 2411 /* Trigger an immediate send poll. */ 2412 lp->a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL); 2413 2414 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) { 2415 lp->tx_full = 1; 2416 netif_stop_queue(dev); 2417 } 2418 spin_unlock_irqrestore(&lp->lock, flags); 2419 return NETDEV_TX_OK; 2420 } 2421 2422 /* The PCNET32 interrupt handler. */ 2423 static irqreturn_t 2424 pcnet32_interrupt(int irq, void *dev_id) 2425 { 2426 struct net_device *dev = dev_id; 2427 struct pcnet32_private *lp; 2428 unsigned long ioaddr; 2429 u16 csr0; 2430 int boguscnt = max_interrupt_work; 2431 2432 ioaddr = dev->base_addr; 2433 lp = netdev_priv(dev); 2434 2435 spin_lock(&lp->lock); 2436 2437 csr0 = lp->a->read_csr(ioaddr, CSR0); 2438 while ((csr0 & 0x8f00) && --boguscnt >= 0) { 2439 if (csr0 == 0xffff) 2440 break; /* PCMCIA remove happened */ 2441 /* Acknowledge all of the current interrupt sources ASAP. */ 2442 lp->a->write_csr(ioaddr, CSR0, csr0 & ~0x004f); 2443 2444 netif_printk(lp, intr, KERN_DEBUG, dev, 2445 "interrupt csr0=%#2.2x new csr=%#2.2x\n", 2446 csr0, lp->a->read_csr(ioaddr, CSR0)); 2447 2448 /* Log misc errors. */ 2449 if (csr0 & 0x4000) 2450 dev->stats.tx_errors++; /* Tx babble. */ 2451 if (csr0 & 0x1000) { 2452 /* 2453 * This happens when our receive ring is full. This 2454 * shouldn't be a problem as we will see normal rx 2455 * interrupts for the frames in the receive ring. But 2456 * there are some PCI chipsets (I can reproduce this 2457 * on SP3G with Intel saturn chipset) which have 2458 * sometimes problems and will fill up the receive 2459 * ring with error descriptors. In this situation we 2460 * don't get a rx interrupt, but a missed frame 2461 * interrupt sooner or later. 2462 */ 2463 dev->stats.rx_errors++; /* Missed a Rx frame. */ 2464 } 2465 if (csr0 & 0x0800) { 2466 netif_err(lp, drv, dev, "Bus master arbitration failure, status %4.4x\n", 2467 csr0); 2468 /* unlike for the lance, there is no restart needed */ 2469 } 2470 if (napi_schedule_prep(&lp->napi)) { 2471 u16 val; 2472 /* set interrupt masks */ 2473 val = lp->a->read_csr(ioaddr, CSR3); 2474 val |= 0x5f00; 2475 lp->a->write_csr(ioaddr, CSR3, val); 2476 2477 __napi_schedule(&lp->napi); 2478 break; 2479 } 2480 csr0 = lp->a->read_csr(ioaddr, CSR0); 2481 } 2482 2483 netif_printk(lp, intr, KERN_DEBUG, dev, 2484 "exiting interrupt, csr0=%#4.4x\n", 2485 lp->a->read_csr(ioaddr, CSR0)); 2486 2487 spin_unlock(&lp->lock); 2488 2489 return IRQ_HANDLED; 2490 } 2491 2492 static int pcnet32_close(struct net_device *dev) 2493 { 2494 unsigned long ioaddr = dev->base_addr; 2495 struct pcnet32_private *lp = netdev_priv(dev); 2496 unsigned long flags; 2497 2498 del_timer_sync(&lp->watchdog_timer); 2499 2500 netif_stop_queue(dev); 2501 napi_disable(&lp->napi); 2502 2503 spin_lock_irqsave(&lp->lock, flags); 2504 2505 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); 2506 2507 netif_printk(lp, ifdown, KERN_DEBUG, dev, 2508 "Shutting down ethercard, status was %2.2x\n", 2509 lp->a->read_csr(ioaddr, CSR0)); 2510 2511 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */ 2512 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2513 2514 /* 2515 * Switch back to 16bit mode to avoid problems with dumb 2516 * DOS packet driver after a warm reboot 2517 */ 2518 lp->a->write_bcr(ioaddr, 20, 4); 2519 2520 spin_unlock_irqrestore(&lp->lock, flags); 2521 2522 free_irq(dev->irq, dev); 2523 2524 spin_lock_irqsave(&lp->lock, flags); 2525 2526 pcnet32_purge_rx_ring(dev); 2527 pcnet32_purge_tx_ring(dev); 2528 2529 spin_unlock_irqrestore(&lp->lock, flags); 2530 2531 return 0; 2532 } 2533 2534 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev) 2535 { 2536 struct pcnet32_private *lp = netdev_priv(dev); 2537 unsigned long ioaddr = dev->base_addr; 2538 unsigned long flags; 2539 2540 spin_lock_irqsave(&lp->lock, flags); 2541 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); 2542 spin_unlock_irqrestore(&lp->lock, flags); 2543 2544 return &dev->stats; 2545 } 2546 2547 /* taken from the sunlance driver, which it took from the depca driver */ 2548 static void pcnet32_load_multicast(struct net_device *dev) 2549 { 2550 struct pcnet32_private *lp = netdev_priv(dev); 2551 volatile struct pcnet32_init_block *ib = lp->init_block; 2552 volatile __le16 *mcast_table = (__le16 *)ib->filter; 2553 struct netdev_hw_addr *ha; 2554 unsigned long ioaddr = dev->base_addr; 2555 int i; 2556 u32 crc; 2557 2558 /* set all multicast bits */ 2559 if (dev->flags & IFF_ALLMULTI) { 2560 ib->filter[0] = cpu_to_le32(~0U); 2561 ib->filter[1] = cpu_to_le32(~0U); 2562 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff); 2563 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff); 2564 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff); 2565 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff); 2566 return; 2567 } 2568 /* clear the multicast filter */ 2569 ib->filter[0] = 0; 2570 ib->filter[1] = 0; 2571 2572 /* Add addresses */ 2573 netdev_for_each_mc_addr(ha, dev) { 2574 crc = ether_crc_le(6, ha->addr); 2575 crc = crc >> 26; 2576 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf)); 2577 } 2578 for (i = 0; i < 4; i++) 2579 lp->a->write_csr(ioaddr, PCNET32_MC_FILTER + i, 2580 le16_to_cpu(mcast_table[i])); 2581 } 2582 2583 /* 2584 * Set or clear the multicast filter for this adaptor. 2585 */ 2586 static void pcnet32_set_multicast_list(struct net_device *dev) 2587 { 2588 unsigned long ioaddr = dev->base_addr, flags; 2589 struct pcnet32_private *lp = netdev_priv(dev); 2590 int csr15, suspended; 2591 2592 spin_lock_irqsave(&lp->lock, flags); 2593 suspended = pcnet32_suspend(dev, &flags, 0); 2594 csr15 = lp->a->read_csr(ioaddr, CSR15); 2595 if (dev->flags & IFF_PROMISC) { 2596 /* Log any net taps. */ 2597 netif_info(lp, hw, dev, "Promiscuous mode enabled\n"); 2598 lp->init_block->mode = 2599 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 2600 7); 2601 lp->a->write_csr(ioaddr, CSR15, csr15 | 0x8000); 2602 } else { 2603 lp->init_block->mode = 2604 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7); 2605 lp->a->write_csr(ioaddr, CSR15, csr15 & 0x7fff); 2606 pcnet32_load_multicast(dev); 2607 } 2608 2609 if (suspended) { 2610 int csr5; 2611 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 2612 csr5 = lp->a->read_csr(ioaddr, CSR5); 2613 lp->a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); 2614 } else { 2615 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); 2616 pcnet32_restart(dev, CSR0_NORMAL); 2617 netif_wake_queue(dev); 2618 } 2619 2620 spin_unlock_irqrestore(&lp->lock, flags); 2621 } 2622 2623 /* This routine assumes that the lp->lock is held */ 2624 static int mdio_read(struct net_device *dev, int phy_id, int reg_num) 2625 { 2626 struct pcnet32_private *lp = netdev_priv(dev); 2627 unsigned long ioaddr = dev->base_addr; 2628 u16 val_out; 2629 2630 if (!lp->mii) 2631 return 0; 2632 2633 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); 2634 val_out = lp->a->read_bcr(ioaddr, 34); 2635 2636 return val_out; 2637 } 2638 2639 /* This routine assumes that the lp->lock is held */ 2640 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val) 2641 { 2642 struct pcnet32_private *lp = netdev_priv(dev); 2643 unsigned long ioaddr = dev->base_addr; 2644 2645 if (!lp->mii) 2646 return; 2647 2648 lp->a->write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f)); 2649 lp->a->write_bcr(ioaddr, 34, val); 2650 } 2651 2652 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2653 { 2654 struct pcnet32_private *lp = netdev_priv(dev); 2655 int rc; 2656 unsigned long flags; 2657 2658 /* SIOC[GS]MIIxxx ioctls */ 2659 if (lp->mii) { 2660 spin_lock_irqsave(&lp->lock, flags); 2661 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL); 2662 spin_unlock_irqrestore(&lp->lock, flags); 2663 } else { 2664 rc = -EOPNOTSUPP; 2665 } 2666 2667 return rc; 2668 } 2669 2670 static int pcnet32_check_otherphy(struct net_device *dev) 2671 { 2672 struct pcnet32_private *lp = netdev_priv(dev); 2673 struct mii_if_info mii = lp->mii_if; 2674 u16 bmcr; 2675 int i; 2676 2677 for (i = 0; i < PCNET32_MAX_PHYS; i++) { 2678 if (i == lp->mii_if.phy_id) 2679 continue; /* skip active phy */ 2680 if (lp->phymask & (1 << i)) { 2681 mii.phy_id = i; 2682 if (mii_link_ok(&mii)) { 2683 /* found PHY with active link */ 2684 netif_info(lp, link, dev, "Using PHY number %d\n", 2685 i); 2686 2687 /* isolate inactive phy */ 2688 bmcr = 2689 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR); 2690 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR, 2691 bmcr | BMCR_ISOLATE); 2692 2693 /* de-isolate new phy */ 2694 bmcr = mdio_read(dev, i, MII_BMCR); 2695 mdio_write(dev, i, MII_BMCR, 2696 bmcr & ~BMCR_ISOLATE); 2697 2698 /* set new phy address */ 2699 lp->mii_if.phy_id = i; 2700 return 1; 2701 } 2702 } 2703 } 2704 return 0; 2705 } 2706 2707 /* 2708 * Show the status of the media. Similar to mii_check_media however it 2709 * correctly shows the link speed for all (tested) pcnet32 variants. 2710 * Devices with no mii just report link state without speed. 2711 * 2712 * Caller is assumed to hold and release the lp->lock. 2713 */ 2714 2715 static void pcnet32_check_media(struct net_device *dev, int verbose) 2716 { 2717 struct pcnet32_private *lp = netdev_priv(dev); 2718 int curr_link; 2719 int prev_link = netif_carrier_ok(dev) ? 1 : 0; 2720 u32 bcr9; 2721 2722 if (lp->mii) { 2723 curr_link = mii_link_ok(&lp->mii_if); 2724 } else { 2725 ulong ioaddr = dev->base_addr; /* card base I/O address */ 2726 curr_link = (lp->a->read_bcr(ioaddr, 4) != 0xc0); 2727 } 2728 if (!curr_link) { 2729 if (prev_link || verbose) { 2730 netif_carrier_off(dev); 2731 netif_info(lp, link, dev, "link down\n"); 2732 } 2733 if (lp->phycount > 1) { 2734 curr_link = pcnet32_check_otherphy(dev); 2735 prev_link = 0; 2736 } 2737 } else if (verbose || !prev_link) { 2738 netif_carrier_on(dev); 2739 if (lp->mii) { 2740 if (netif_msg_link(lp)) { 2741 struct ethtool_cmd ecmd = { 2742 .cmd = ETHTOOL_GSET }; 2743 mii_ethtool_gset(&lp->mii_if, &ecmd); 2744 netdev_info(dev, "link up, %uMbps, %s-duplex\n", 2745 ethtool_cmd_speed(&ecmd), 2746 (ecmd.duplex == DUPLEX_FULL) 2747 ? "full" : "half"); 2748 } 2749 bcr9 = lp->a->read_bcr(dev->base_addr, 9); 2750 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) { 2751 if (lp->mii_if.full_duplex) 2752 bcr9 |= (1 << 0); 2753 else 2754 bcr9 &= ~(1 << 0); 2755 lp->a->write_bcr(dev->base_addr, 9, bcr9); 2756 } 2757 } else { 2758 netif_info(lp, link, dev, "link up\n"); 2759 } 2760 } 2761 } 2762 2763 /* 2764 * Check for loss of link and link establishment. 2765 * Can not use mii_check_media because it does nothing if mode is forced. 2766 */ 2767 2768 static void pcnet32_watchdog(struct net_device *dev) 2769 { 2770 struct pcnet32_private *lp = netdev_priv(dev); 2771 unsigned long flags; 2772 2773 /* Print the link status if it has changed */ 2774 spin_lock_irqsave(&lp->lock, flags); 2775 pcnet32_check_media(dev, 0); 2776 spin_unlock_irqrestore(&lp->lock, flags); 2777 2778 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT)); 2779 } 2780 2781 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state) 2782 { 2783 struct net_device *dev = pci_get_drvdata(pdev); 2784 2785 if (netif_running(dev)) { 2786 netif_device_detach(dev); 2787 pcnet32_close(dev); 2788 } 2789 pci_save_state(pdev); 2790 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 2791 return 0; 2792 } 2793 2794 static int pcnet32_pm_resume(struct pci_dev *pdev) 2795 { 2796 struct net_device *dev = pci_get_drvdata(pdev); 2797 2798 pci_set_power_state(pdev, PCI_D0); 2799 pci_restore_state(pdev); 2800 2801 if (netif_running(dev)) { 2802 pcnet32_open(dev); 2803 netif_device_attach(dev); 2804 } 2805 return 0; 2806 } 2807 2808 static void pcnet32_remove_one(struct pci_dev *pdev) 2809 { 2810 struct net_device *dev = pci_get_drvdata(pdev); 2811 2812 if (dev) { 2813 struct pcnet32_private *lp = netdev_priv(dev); 2814 2815 unregister_netdev(dev); 2816 pcnet32_free_ring(dev); 2817 release_region(dev->base_addr, PCNET32_TOTAL_SIZE); 2818 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 2819 lp->init_block, lp->init_dma_addr); 2820 free_netdev(dev); 2821 pci_disable_device(pdev); 2822 pci_set_drvdata(pdev, NULL); 2823 } 2824 } 2825 2826 static struct pci_driver pcnet32_driver = { 2827 .name = DRV_NAME, 2828 .probe = pcnet32_probe_pci, 2829 .remove = pcnet32_remove_one, 2830 .id_table = pcnet32_pci_tbl, 2831 .suspend = pcnet32_pm_suspend, 2832 .resume = pcnet32_pm_resume, 2833 }; 2834 2835 /* An additional parameter that may be passed in... */ 2836 static int debug = -1; 2837 static int tx_start_pt = -1; 2838 static int pcnet32_have_pci; 2839 2840 module_param(debug, int, 0); 2841 MODULE_PARM_DESC(debug, DRV_NAME " debug level"); 2842 module_param(max_interrupt_work, int, 0); 2843 MODULE_PARM_DESC(max_interrupt_work, 2844 DRV_NAME " maximum events handled per interrupt"); 2845 module_param(rx_copybreak, int, 0); 2846 MODULE_PARM_DESC(rx_copybreak, 2847 DRV_NAME " copy breakpoint for copy-only-tiny-frames"); 2848 module_param(tx_start_pt, int, 0); 2849 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)"); 2850 module_param(pcnet32vlb, int, 0); 2851 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)"); 2852 module_param_array(options, int, NULL, 0); 2853 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)"); 2854 module_param_array(full_duplex, int, NULL, 0); 2855 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)"); 2856 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */ 2857 module_param_array(homepna, int, NULL, 0); 2858 MODULE_PARM_DESC(homepna, 2859 DRV_NAME 2860 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet"); 2861 2862 MODULE_AUTHOR("Thomas Bogendoerfer"); 2863 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards"); 2864 MODULE_LICENSE("GPL"); 2865 2866 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 2867 2868 static int __init pcnet32_init_module(void) 2869 { 2870 pr_info("%s", version); 2871 2872 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT); 2873 2874 if ((tx_start_pt >= 0) && (tx_start_pt <= 3)) 2875 tx_start = tx_start_pt; 2876 2877 /* find the PCI devices */ 2878 if (!pci_register_driver(&pcnet32_driver)) 2879 pcnet32_have_pci = 1; 2880 2881 /* should we find any remaining VLbus devices ? */ 2882 if (pcnet32vlb) 2883 pcnet32_probe_vlbus(pcnet32_portlist); 2884 2885 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE)) 2886 pr_info("%d cards_found\n", cards_found); 2887 2888 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV; 2889 } 2890 2891 static void __exit pcnet32_cleanup_module(void) 2892 { 2893 struct net_device *next_dev; 2894 2895 while (pcnet32_dev) { 2896 struct pcnet32_private *lp = netdev_priv(pcnet32_dev); 2897 next_dev = lp->next; 2898 unregister_netdev(pcnet32_dev); 2899 pcnet32_free_ring(pcnet32_dev); 2900 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE); 2901 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 2902 lp->init_block, lp->init_dma_addr); 2903 free_netdev(pcnet32_dev); 2904 pcnet32_dev = next_dev; 2905 } 2906 2907 if (pcnet32_have_pci) 2908 pci_unregister_driver(&pcnet32_driver); 2909 } 2910 2911 module_init(pcnet32_init_module); 2912 module_exit(pcnet32_cleanup_module); 2913 2914 /* 2915 * Local variables: 2916 * c-indent-level: 4 2917 * tab-width: 8 2918 * End: 2919 */ 2920