1 /* ---------------------------------------------------------------------------- 2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN. 3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao 4 5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media 6 Access Controller for Ethernet (MACE). It is essentially the Am2150 7 PCMCIA Ethernet card contained in the Am2150 Demo Kit. 8 9 Written by Roger C. Pao <rpao@paonet.org> 10 Copyright 1995 Roger C. Pao 11 Linux 2.5 cleanups Copyright Red Hat 2003 12 13 This software may be used and distributed according to the terms of 14 the GNU General Public License. 15 16 Ported to Linux 1.3.* network driver environment by 17 Matti Aarnio <mea@utu.fi> 18 19 References 20 21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993 22 Am79C940 (MACE) Data Sheet, 1994 23 Am79C90 (C-LANCE) Data Sheet, 1994 24 Linux PCMCIA Programmer's Guide v1.17 25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8 26 27 Eric Mears, New Media Corporation 28 Tom Pollard, New Media Corporation 29 Dean Siasoyco, New Media Corporation 30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com> 31 Donald Becker <becker@scyld.com> 32 David Hinds <dahinds@users.sourceforge.net> 33 34 The Linux client driver is based on the 3c589_cs.c client driver by 35 David Hinds. 36 37 The Linux network driver outline is based on the 3c589_cs.c driver, 38 the 8390.c driver, and the example skeleton.c kernel code, which are 39 by Donald Becker. 40 41 The Am2150 network driver hardware interface code is based on the 42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears. 43 44 Special thanks for testing and help in debugging this driver goes 45 to Ken Lesniak. 46 47 ------------------------------------------------------------------------------- 48 Driver Notes and Issues 49 ------------------------------------------------------------------------------- 50 51 1. Developed on a Dell 320SLi 52 PCMCIA Card Services 2.6.2 53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386 54 55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300: 56 'insmod pcmcia_core.o io_speed=300'. 57 This will avoid problems with fast systems which causes rx_framecnt 58 to return random values. 59 60 3. If hot extraction does not work for you, use 'ifconfig eth0 down' 61 before extraction. 62 63 4. There is a bad slow-down problem in this driver. 64 65 5. Future: Multicast processing. In the meantime, do _not_ compile your 66 kernel with multicast ip enabled. 67 68 ------------------------------------------------------------------------------- 69 History 70 ------------------------------------------------------------------------------- 71 Log: nmclan_cs.c,v 72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk> 73 * Fixed hang on card eject as we probe it 74 * Cleaned up to use new style locking. 75 * 76 * Revision 0.16 1995/07/01 06:42:17 rpao 77 * Bug fix: nmclan_reset() called CardServices incorrectly. 78 * 79 * Revision 0.15 1995/05/24 08:09:47 rpao 80 * Re-implement MULTI_TX dev->tbusy handling. 81 * 82 * Revision 0.14 1995/05/23 03:19:30 rpao 83 * Added, in nmclan_config(), "tuple.Attributes = 0;". 84 * Modified MACE ID check to ignore chip revision level. 85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt. 86 * 87 * Revision 0.13 1995/05/18 05:56:34 rpao 88 * Statistics changes. 89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list. 90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup. 91 * 92 * Revision 0.12 1995/05/14 00:12:23 rpao 93 * Statistics overhaul. 94 * 95 96 95/05/13 rpao V0.10a 97 Bug fix: MACE statistics counters used wrong I/O ports. 98 Bug fix: mace_interrupt() needed to allow statistics to be 99 processed without RX or TX interrupts pending. 100 95/05/11 rpao V0.10 101 Multiple transmit request processing. 102 Modified statistics to use MACE counters where possible. 103 95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO. 104 *Released 105 95/05/10 rpao V0.08 106 Bug fix: Make all non-exported functions private by using 107 static keyword. 108 Bug fix: Test IntrCnt _before_ reading MACE_IR. 109 95/05/10 rpao V0.07 Statistics. 110 95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states. 111 112 ---------------------------------------------------------------------------- */ 113 114 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 115 116 #define DRV_NAME "nmclan_cs" 117 #define DRV_VERSION "0.16" 118 119 120 /* ---------------------------------------------------------------------------- 121 Conditional Compilation Options 122 ---------------------------------------------------------------------------- */ 123 124 #define MULTI_TX 0 125 #define RESET_ON_TIMEOUT 1 126 #define TX_INTERRUPTABLE 1 127 #define RESET_XILINX 0 128 129 /* ---------------------------------------------------------------------------- 130 Include Files 131 ---------------------------------------------------------------------------- */ 132 133 #include <linux/module.h> 134 #include <linux/kernel.h> 135 #include <linux/init.h> 136 #include <linux/ptrace.h> 137 #include <linux/slab.h> 138 #include <linux/string.h> 139 #include <linux/timer.h> 140 #include <linux/interrupt.h> 141 #include <linux/in.h> 142 #include <linux/delay.h> 143 #include <linux/ethtool.h> 144 #include <linux/netdevice.h> 145 #include <linux/etherdevice.h> 146 #include <linux/skbuff.h> 147 #include <linux/if_arp.h> 148 #include <linux/ioport.h> 149 #include <linux/bitops.h> 150 151 #include <pcmcia/cisreg.h> 152 #include <pcmcia/cistpl.h> 153 #include <pcmcia/ds.h> 154 155 #include <asm/uaccess.h> 156 #include <asm/io.h> 157 158 /* ---------------------------------------------------------------------------- 159 Defines 160 ---------------------------------------------------------------------------- */ 161 162 #define MACE_LADRF_LEN 8 163 /* 8 bytes in Logical Address Filter */ 164 165 /* Loop Control Defines */ 166 #define MACE_MAX_IR_ITERATIONS 10 167 #define MACE_MAX_RX_ITERATIONS 12 168 /* 169 TBD: Dean brought this up, and I assumed the hardware would 170 handle it: 171 172 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be 173 non-zero when the isr exits. We may not get another interrupt 174 to process the remaining packets for some time. 175 */ 176 177 /* 178 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA) 179 which manages the interface between the MACE and the PCMCIA bus. It 180 also includes buffer management for the 32K x 8 SRAM to control up to 181 four transmit and 12 receive frames at a time. 182 */ 183 #define AM2150_MAX_TX_FRAMES 4 184 #define AM2150_MAX_RX_FRAMES 12 185 186 /* Am2150 Ethernet Card I/O Mapping */ 187 #define AM2150_RCV 0x00 188 #define AM2150_XMT 0x04 189 #define AM2150_XMT_SKIP 0x09 190 #define AM2150_RCV_NEXT 0x0A 191 #define AM2150_RCV_FRAME_COUNT 0x0B 192 #define AM2150_MACE_BANK 0x0C 193 #define AM2150_MACE_BASE 0x10 194 195 /* MACE Registers */ 196 #define MACE_RCVFIFO 0 197 #define MACE_XMTFIFO 1 198 #define MACE_XMTFC 2 199 #define MACE_XMTFS 3 200 #define MACE_XMTRC 4 201 #define MACE_RCVFC 5 202 #define MACE_RCVFS 6 203 #define MACE_FIFOFC 7 204 #define MACE_IR 8 205 #define MACE_IMR 9 206 #define MACE_PR 10 207 #define MACE_BIUCC 11 208 #define MACE_FIFOCC 12 209 #define MACE_MACCC 13 210 #define MACE_PLSCC 14 211 #define MACE_PHYCC 15 212 #define MACE_CHIPIDL 16 213 #define MACE_CHIPIDH 17 214 #define MACE_IAC 18 215 /* Reserved */ 216 #define MACE_LADRF 20 217 #define MACE_PADR 21 218 /* Reserved */ 219 /* Reserved */ 220 #define MACE_MPC 24 221 /* Reserved */ 222 #define MACE_RNTPC 26 223 #define MACE_RCVCC 27 224 /* Reserved */ 225 #define MACE_UTR 29 226 #define MACE_RTR1 30 227 #define MACE_RTR2 31 228 229 /* MACE Bit Masks */ 230 #define MACE_XMTRC_EXDEF 0x80 231 #define MACE_XMTRC_XMTRC 0x0F 232 233 #define MACE_XMTFS_XMTSV 0x80 234 #define MACE_XMTFS_UFLO 0x40 235 #define MACE_XMTFS_LCOL 0x20 236 #define MACE_XMTFS_MORE 0x10 237 #define MACE_XMTFS_ONE 0x08 238 #define MACE_XMTFS_DEFER 0x04 239 #define MACE_XMTFS_LCAR 0x02 240 #define MACE_XMTFS_RTRY 0x01 241 242 #define MACE_RCVFS_RCVSTS 0xF000 243 #define MACE_RCVFS_OFLO 0x8000 244 #define MACE_RCVFS_CLSN 0x4000 245 #define MACE_RCVFS_FRAM 0x2000 246 #define MACE_RCVFS_FCS 0x1000 247 248 #define MACE_FIFOFC_RCVFC 0xF0 249 #define MACE_FIFOFC_XMTFC 0x0F 250 251 #define MACE_IR_JAB 0x80 252 #define MACE_IR_BABL 0x40 253 #define MACE_IR_CERR 0x20 254 #define MACE_IR_RCVCCO 0x10 255 #define MACE_IR_RNTPCO 0x08 256 #define MACE_IR_MPCO 0x04 257 #define MACE_IR_RCVINT 0x02 258 #define MACE_IR_XMTINT 0x01 259 260 #define MACE_MACCC_PROM 0x80 261 #define MACE_MACCC_DXMT2PD 0x40 262 #define MACE_MACCC_EMBA 0x20 263 #define MACE_MACCC_RESERVED 0x10 264 #define MACE_MACCC_DRCVPA 0x08 265 #define MACE_MACCC_DRCVBC 0x04 266 #define MACE_MACCC_ENXMT 0x02 267 #define MACE_MACCC_ENRCV 0x01 268 269 #define MACE_PHYCC_LNKFL 0x80 270 #define MACE_PHYCC_DLNKTST 0x40 271 #define MACE_PHYCC_REVPOL 0x20 272 #define MACE_PHYCC_DAPC 0x10 273 #define MACE_PHYCC_LRT 0x08 274 #define MACE_PHYCC_ASEL 0x04 275 #define MACE_PHYCC_RWAKE 0x02 276 #define MACE_PHYCC_AWAKE 0x01 277 278 #define MACE_IAC_ADDRCHG 0x80 279 #define MACE_IAC_PHYADDR 0x04 280 #define MACE_IAC_LOGADDR 0x02 281 282 #define MACE_UTR_RTRE 0x80 283 #define MACE_UTR_RTRD 0x40 284 #define MACE_UTR_RPA 0x20 285 #define MACE_UTR_FCOLL 0x10 286 #define MACE_UTR_RCVFCSE 0x08 287 #define MACE_UTR_LOOP_INCL_MENDEC 0x06 288 #define MACE_UTR_LOOP_NO_MENDEC 0x04 289 #define MACE_UTR_LOOP_EXTERNAL 0x02 290 #define MACE_UTR_LOOP_NONE 0x00 291 #define MACE_UTR_RESERVED 0x01 292 293 /* Switch MACE register bank (only 0 and 1 are valid) */ 294 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK) 295 296 #define MACE_IMR_DEFAULT \ 297 (0xFF - \ 298 ( \ 299 MACE_IR_CERR | \ 300 MACE_IR_RCVCCO | \ 301 MACE_IR_RNTPCO | \ 302 MACE_IR_MPCO | \ 303 MACE_IR_RCVINT | \ 304 MACE_IR_XMTINT \ 305 ) \ 306 ) 307 #undef MACE_IMR_DEFAULT 308 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */ 309 310 #define TX_TIMEOUT ((400*HZ)/1000) 311 312 /* ---------------------------------------------------------------------------- 313 Type Definitions 314 ---------------------------------------------------------------------------- */ 315 316 typedef struct _mace_statistics { 317 /* MACE_XMTFS */ 318 int xmtsv; 319 int uflo; 320 int lcol; 321 int more; 322 int one; 323 int defer; 324 int lcar; 325 int rtry; 326 327 /* MACE_XMTRC */ 328 int exdef; 329 int xmtrc; 330 331 /* RFS1--Receive Status (RCVSTS) */ 332 int oflo; 333 int clsn; 334 int fram; 335 int fcs; 336 337 /* RFS2--Runt Packet Count (RNTPC) */ 338 int rfs_rntpc; 339 340 /* RFS3--Receive Collision Count (RCVCC) */ 341 int rfs_rcvcc; 342 343 /* MACE_IR */ 344 int jab; 345 int babl; 346 int cerr; 347 int rcvcco; 348 int rntpco; 349 int mpco; 350 351 /* MACE_MPC */ 352 int mpc; 353 354 /* MACE_RNTPC */ 355 int rntpc; 356 357 /* MACE_RCVCC */ 358 int rcvcc; 359 } mace_statistics; 360 361 typedef struct _mace_private { 362 struct pcmcia_device *p_dev; 363 struct net_device_stats linux_stats; /* Linux statistics counters */ 364 mace_statistics mace_stats; /* MACE chip statistics counters */ 365 366 /* restore_multicast_list() state variables */ 367 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */ 368 int multicast_num_addrs; 369 370 char tx_free_frames; /* Number of free transmit frame buffers */ 371 char tx_irq_disabled; /* MACE TX interrupt disabled */ 372 373 spinlock_t bank_lock; /* Must be held if you step off bank 0 */ 374 } mace_private; 375 376 /* ---------------------------------------------------------------------------- 377 Private Global Variables 378 ---------------------------------------------------------------------------- */ 379 380 static const char *if_names[]={ 381 "Auto", "10baseT", "BNC", 382 }; 383 384 /* ---------------------------------------------------------------------------- 385 Parameters 386 These are the parameters that can be set during loading with 387 'insmod'. 388 ---------------------------------------------------------------------------- */ 389 390 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver"); 391 MODULE_LICENSE("GPL"); 392 393 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0) 394 395 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */ 396 INT_MODULE_PARM(if_port, 0); 397 398 399 /* ---------------------------------------------------------------------------- 400 Function Prototypes 401 ---------------------------------------------------------------------------- */ 402 403 static int nmclan_config(struct pcmcia_device *link); 404 static void nmclan_release(struct pcmcia_device *link); 405 406 static void nmclan_reset(struct net_device *dev); 407 static int mace_config(struct net_device *dev, struct ifmap *map); 408 static int mace_open(struct net_device *dev); 409 static int mace_close(struct net_device *dev); 410 static netdev_tx_t mace_start_xmit(struct sk_buff *skb, 411 struct net_device *dev); 412 static void mace_tx_timeout(struct net_device *dev); 413 static irqreturn_t mace_interrupt(int irq, void *dev_id); 414 static struct net_device_stats *mace_get_stats(struct net_device *dev); 415 static int mace_rx(struct net_device *dev, unsigned char RxCnt); 416 static void restore_multicast_list(struct net_device *dev); 417 static void set_multicast_list(struct net_device *dev); 418 static const struct ethtool_ops netdev_ethtool_ops; 419 420 421 static void nmclan_detach(struct pcmcia_device *p_dev); 422 423 static const struct net_device_ops mace_netdev_ops = { 424 .ndo_open = mace_open, 425 .ndo_stop = mace_close, 426 .ndo_start_xmit = mace_start_xmit, 427 .ndo_tx_timeout = mace_tx_timeout, 428 .ndo_set_config = mace_config, 429 .ndo_get_stats = mace_get_stats, 430 .ndo_set_rx_mode = set_multicast_list, 431 .ndo_change_mtu = eth_change_mtu, 432 .ndo_set_mac_address = eth_mac_addr, 433 .ndo_validate_addr = eth_validate_addr, 434 }; 435 436 static int nmclan_probe(struct pcmcia_device *link) 437 { 438 mace_private *lp; 439 struct net_device *dev; 440 441 dev_dbg(&link->dev, "nmclan_attach()\n"); 442 443 /* Create new ethernet device */ 444 dev = alloc_etherdev(sizeof(mace_private)); 445 if (!dev) 446 return -ENOMEM; 447 lp = netdev_priv(dev); 448 lp->p_dev = link; 449 link->priv = dev; 450 451 spin_lock_init(&lp->bank_lock); 452 link->resource[0]->end = 32; 453 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO; 454 link->config_flags |= CONF_ENABLE_IRQ; 455 link->config_index = 1; 456 link->config_regs = PRESENT_OPTION; 457 458 lp->tx_free_frames=AM2150_MAX_TX_FRAMES; 459 460 dev->netdev_ops = &mace_netdev_ops; 461 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops); 462 dev->watchdog_timeo = TX_TIMEOUT; 463 464 return nmclan_config(link); 465 } /* nmclan_attach */ 466 467 static void nmclan_detach(struct pcmcia_device *link) 468 { 469 struct net_device *dev = link->priv; 470 471 dev_dbg(&link->dev, "nmclan_detach\n"); 472 473 unregister_netdev(dev); 474 475 nmclan_release(link); 476 477 free_netdev(dev); 478 } /* nmclan_detach */ 479 480 /* ---------------------------------------------------------------------------- 481 mace_read 482 Reads a MACE register. This is bank independent; however, the 483 caller must ensure that this call is not interruptable. We are 484 assuming that during normal operation, the MACE is always in 485 bank 0. 486 ---------------------------------------------------------------------------- */ 487 static int mace_read(mace_private *lp, unsigned int ioaddr, int reg) 488 { 489 int data = 0xFF; 490 unsigned long flags; 491 492 switch (reg >> 4) { 493 case 0: /* register 0-15 */ 494 data = inb(ioaddr + AM2150_MACE_BASE + reg); 495 break; 496 case 1: /* register 16-31 */ 497 spin_lock_irqsave(&lp->bank_lock, flags); 498 MACEBANK(1); 499 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); 500 MACEBANK(0); 501 spin_unlock_irqrestore(&lp->bank_lock, flags); 502 break; 503 } 504 return data & 0xFF; 505 } /* mace_read */ 506 507 /* ---------------------------------------------------------------------------- 508 mace_write 509 Writes to a MACE register. This is bank independent; however, 510 the caller must ensure that this call is not interruptable. We 511 are assuming that during normal operation, the MACE is always in 512 bank 0. 513 ---------------------------------------------------------------------------- */ 514 static void mace_write(mace_private *lp, unsigned int ioaddr, int reg, 515 int data) 516 { 517 unsigned long flags; 518 519 switch (reg >> 4) { 520 case 0: /* register 0-15 */ 521 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg); 522 break; 523 case 1: /* register 16-31 */ 524 spin_lock_irqsave(&lp->bank_lock, flags); 525 MACEBANK(1); 526 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F)); 527 MACEBANK(0); 528 spin_unlock_irqrestore(&lp->bank_lock, flags); 529 break; 530 } 531 } /* mace_write */ 532 533 /* ---------------------------------------------------------------------------- 534 mace_init 535 Resets the MACE chip. 536 ---------------------------------------------------------------------------- */ 537 static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr) 538 { 539 int i; 540 int ct = 0; 541 542 /* MACE Software reset */ 543 mace_write(lp, ioaddr, MACE_BIUCC, 1); 544 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) { 545 /* Wait for reset bit to be cleared automatically after <= 200ns */; 546 if(++ct > 500) 547 { 548 pr_err("reset failed, card removed?\n"); 549 return -1; 550 } 551 udelay(1); 552 } 553 mace_write(lp, ioaddr, MACE_BIUCC, 0); 554 555 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */ 556 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F); 557 558 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */ 559 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */ 560 561 /* 562 * Bit 2-1 PORTSEL[1-0] Port Select. 563 * 00 AUI/10Base-2 564 * 01 10Base-T 565 * 10 DAI Port (reserved in Am2150) 566 * 11 GPSI 567 * For this card, only the first two are valid. 568 * So, PLSCC should be set to 569 * 0x00 for 10Base-2 570 * 0x02 for 10Base-T 571 * Or just set ASEL in PHYCC below! 572 */ 573 switch (if_port) { 574 case 1: 575 mace_write(lp, ioaddr, MACE_PLSCC, 0x02); 576 break; 577 case 2: 578 mace_write(lp, ioaddr, MACE_PLSCC, 0x00); 579 break; 580 default: 581 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4); 582 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden, 583 and the MACE device will automatically select the operating media 584 interface port. */ 585 break; 586 } 587 588 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR); 589 /* Poll ADDRCHG bit */ 590 ct = 0; 591 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG) 592 { 593 if(++ ct > 500) 594 { 595 pr_err("ADDRCHG timeout, card removed?\n"); 596 return -1; 597 } 598 } 599 /* Set PADR register */ 600 for (i = 0; i < ETH_ALEN; i++) 601 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]); 602 603 /* MAC Configuration Control Register should be written last */ 604 /* Let set_multicast_list set this. */ 605 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */ 606 mace_write(lp, ioaddr, MACE_MACCC, 0x00); 607 return 0; 608 } /* mace_init */ 609 610 static int nmclan_config(struct pcmcia_device *link) 611 { 612 struct net_device *dev = link->priv; 613 mace_private *lp = netdev_priv(dev); 614 u8 *buf; 615 size_t len; 616 int i, ret; 617 unsigned int ioaddr; 618 619 dev_dbg(&link->dev, "nmclan_config\n"); 620 621 link->io_lines = 5; 622 ret = pcmcia_request_io(link); 623 if (ret) 624 goto failed; 625 ret = pcmcia_request_exclusive_irq(link, mace_interrupt); 626 if (ret) 627 goto failed; 628 ret = pcmcia_enable_device(link); 629 if (ret) 630 goto failed; 631 632 dev->irq = link->irq; 633 dev->base_addr = link->resource[0]->start; 634 635 ioaddr = dev->base_addr; 636 637 /* Read the ethernet address from the CIS. */ 638 len = pcmcia_get_tuple(link, 0x80, &buf); 639 if (!buf || len < ETH_ALEN) { 640 kfree(buf); 641 goto failed; 642 } 643 memcpy(dev->dev_addr, buf, ETH_ALEN); 644 kfree(buf); 645 646 /* Verify configuration by reading the MACE ID. */ 647 { 648 char sig[2]; 649 650 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL); 651 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH); 652 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) { 653 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n", 654 sig[0], sig[1]); 655 } else { 656 pr_notice("mace id not found: %x %x should be 0x40 0x?9\n", 657 sig[0], sig[1]); 658 return -ENODEV; 659 } 660 } 661 662 if(mace_init(lp, ioaddr, dev->dev_addr) == -1) 663 goto failed; 664 665 /* The if_port symbol can be set when the module is loaded */ 666 if (if_port <= 2) 667 dev->if_port = if_port; 668 else 669 pr_notice("invalid if_port requested\n"); 670 671 SET_NETDEV_DEV(dev, &link->dev); 672 673 i = register_netdev(dev); 674 if (i != 0) { 675 pr_notice("register_netdev() failed\n"); 676 goto failed; 677 } 678 679 netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n", 680 dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr); 681 return 0; 682 683 failed: 684 nmclan_release(link); 685 return -ENODEV; 686 } /* nmclan_config */ 687 688 static void nmclan_release(struct pcmcia_device *link) 689 { 690 dev_dbg(&link->dev, "nmclan_release\n"); 691 pcmcia_disable_device(link); 692 } 693 694 static int nmclan_suspend(struct pcmcia_device *link) 695 { 696 struct net_device *dev = link->priv; 697 698 if (link->open) 699 netif_device_detach(dev); 700 701 return 0; 702 } 703 704 static int nmclan_resume(struct pcmcia_device *link) 705 { 706 struct net_device *dev = link->priv; 707 708 if (link->open) { 709 nmclan_reset(dev); 710 netif_device_attach(dev); 711 } 712 713 return 0; 714 } 715 716 717 /* ---------------------------------------------------------------------------- 718 nmclan_reset 719 Reset and restore all of the Xilinx and MACE registers. 720 ---------------------------------------------------------------------------- */ 721 static void nmclan_reset(struct net_device *dev) 722 { 723 mace_private *lp = netdev_priv(dev); 724 725 #if RESET_XILINX 726 struct pcmcia_device *link = &lp->link; 727 u8 OrigCorValue; 728 729 /* Save original COR value */ 730 pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue); 731 732 /* Reset Xilinx */ 733 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n", 734 OrigCorValue); 735 pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET); 736 /* Need to wait for 20 ms for PCMCIA to finish reset. */ 737 738 /* Restore original COR configuration index */ 739 pcmcia_write_config_byte(link, CISREG_COR, 740 (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK))); 741 /* Xilinx is now completely reset along with the MACE chip. */ 742 lp->tx_free_frames=AM2150_MAX_TX_FRAMES; 743 744 #endif /* #if RESET_XILINX */ 745 746 /* Xilinx is now completely reset along with the MACE chip. */ 747 lp->tx_free_frames=AM2150_MAX_TX_FRAMES; 748 749 /* Reinitialize the MACE chip for operation. */ 750 mace_init(lp, dev->base_addr, dev->dev_addr); 751 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT); 752 753 /* Restore the multicast list and enable TX and RX. */ 754 restore_multicast_list(dev); 755 } /* nmclan_reset */ 756 757 /* ---------------------------------------------------------------------------- 758 mace_config 759 [Someone tell me what this is supposed to do? Is if_port a defined 760 standard? If so, there should be defines to indicate 1=10Base-T, 761 2=10Base-2, etc. including limited automatic detection.] 762 ---------------------------------------------------------------------------- */ 763 static int mace_config(struct net_device *dev, struct ifmap *map) 764 { 765 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) { 766 if (map->port <= 2) { 767 dev->if_port = map->port; 768 netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]); 769 } else 770 return -EINVAL; 771 } 772 return 0; 773 } /* mace_config */ 774 775 /* ---------------------------------------------------------------------------- 776 mace_open 777 Open device driver. 778 ---------------------------------------------------------------------------- */ 779 static int mace_open(struct net_device *dev) 780 { 781 unsigned int ioaddr = dev->base_addr; 782 mace_private *lp = netdev_priv(dev); 783 struct pcmcia_device *link = lp->p_dev; 784 785 if (!pcmcia_dev_present(link)) 786 return -ENODEV; 787 788 link->open++; 789 790 MACEBANK(0); 791 792 netif_start_queue(dev); 793 nmclan_reset(dev); 794 795 return 0; /* Always succeed */ 796 } /* mace_open */ 797 798 /* ---------------------------------------------------------------------------- 799 mace_close 800 Closes device driver. 801 ---------------------------------------------------------------------------- */ 802 static int mace_close(struct net_device *dev) 803 { 804 unsigned int ioaddr = dev->base_addr; 805 mace_private *lp = netdev_priv(dev); 806 struct pcmcia_device *link = lp->p_dev; 807 808 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name); 809 810 /* Mask off all interrupts from the MACE chip. */ 811 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR); 812 813 link->open--; 814 netif_stop_queue(dev); 815 816 return 0; 817 } /* mace_close */ 818 819 static void netdev_get_drvinfo(struct net_device *dev, 820 struct ethtool_drvinfo *info) 821 { 822 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 823 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 824 snprintf(info->bus_info, sizeof(info->bus_info), 825 "PCMCIA 0x%lx", dev->base_addr); 826 } 827 828 static const struct ethtool_ops netdev_ethtool_ops = { 829 .get_drvinfo = netdev_get_drvinfo, 830 }; 831 832 /* ---------------------------------------------------------------------------- 833 mace_start_xmit 834 This routine begins the packet transmit function. When completed, 835 it will generate a transmit interrupt. 836 837 According to /usr/src/linux/net/inet/dev.c, if _start_xmit 838 returns 0, the "packet is now solely the responsibility of the 839 driver." If _start_xmit returns non-zero, the "transmission 840 failed, put skb back into a list." 841 ---------------------------------------------------------------------------- */ 842 843 static void mace_tx_timeout(struct net_device *dev) 844 { 845 mace_private *lp = netdev_priv(dev); 846 struct pcmcia_device *link = lp->p_dev; 847 848 netdev_notice(dev, "transmit timed out -- "); 849 #if RESET_ON_TIMEOUT 850 pr_cont("resetting card\n"); 851 pcmcia_reset_card(link->socket); 852 #else /* #if RESET_ON_TIMEOUT */ 853 pr_cont("NOT resetting card\n"); 854 #endif /* #if RESET_ON_TIMEOUT */ 855 dev->trans_start = jiffies; /* prevent tx timeout */ 856 netif_wake_queue(dev); 857 } 858 859 static netdev_tx_t mace_start_xmit(struct sk_buff *skb, 860 struct net_device *dev) 861 { 862 mace_private *lp = netdev_priv(dev); 863 unsigned int ioaddr = dev->base_addr; 864 865 netif_stop_queue(dev); 866 867 pr_debug("%s: mace_start_xmit(length = %ld) called.\n", 868 dev->name, (long)skb->len); 869 870 #if (!TX_INTERRUPTABLE) 871 /* Disable MACE TX interrupts. */ 872 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT, 873 ioaddr + AM2150_MACE_BASE + MACE_IMR); 874 lp->tx_irq_disabled=1; 875 #endif /* #if (!TX_INTERRUPTABLE) */ 876 877 { 878 /* This block must not be interrupted by another transmit request! 879 mace_tx_timeout will take care of timer-based retransmissions from 880 the upper layers. The interrupt handler is guaranteed never to 881 service a transmit interrupt while we are in here. 882 */ 883 884 lp->linux_stats.tx_bytes += skb->len; 885 lp->tx_free_frames--; 886 887 /* WARNING: Write the _exact_ number of bytes written in the header! */ 888 /* Put out the word header [must be an outw()] . . . */ 889 outw(skb->len, ioaddr + AM2150_XMT); 890 /* . . . and the packet [may be any combination of outw() and outb()] */ 891 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1); 892 if (skb->len & 1) { 893 /* Odd byte transfer */ 894 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT); 895 } 896 897 #if MULTI_TX 898 if (lp->tx_free_frames > 0) 899 netif_start_queue(dev); 900 #endif /* #if MULTI_TX */ 901 } 902 903 #if (!TX_INTERRUPTABLE) 904 /* Re-enable MACE TX interrupts. */ 905 lp->tx_irq_disabled=0; 906 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR); 907 #endif /* #if (!TX_INTERRUPTABLE) */ 908 909 dev_kfree_skb(skb); 910 911 return NETDEV_TX_OK; 912 } /* mace_start_xmit */ 913 914 /* ---------------------------------------------------------------------------- 915 mace_interrupt 916 The interrupt handler. 917 ---------------------------------------------------------------------------- */ 918 static irqreturn_t mace_interrupt(int irq, void *dev_id) 919 { 920 struct net_device *dev = (struct net_device *) dev_id; 921 mace_private *lp = netdev_priv(dev); 922 unsigned int ioaddr; 923 int status; 924 int IntrCnt = MACE_MAX_IR_ITERATIONS; 925 926 if (dev == NULL) { 927 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n", 928 irq); 929 return IRQ_NONE; 930 } 931 932 ioaddr = dev->base_addr; 933 934 if (lp->tx_irq_disabled) { 935 const char *msg; 936 if (lp->tx_irq_disabled) 937 msg = "Interrupt with tx_irq_disabled"; 938 else 939 msg = "Re-entering the interrupt handler"; 940 netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n", 941 msg, 942 inb(ioaddr + AM2150_MACE_BASE + MACE_IR), 943 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)); 944 /* WARNING: MACE_IR has been read! */ 945 return IRQ_NONE; 946 } 947 948 if (!netif_device_present(dev)) { 949 netdev_dbg(dev, "interrupt from dead card\n"); 950 return IRQ_NONE; 951 } 952 953 do { 954 /* WARNING: MACE_IR is a READ/CLEAR port! */ 955 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR); 956 957 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status); 958 959 if (status & MACE_IR_RCVINT) { 960 mace_rx(dev, MACE_MAX_RX_ITERATIONS); 961 } 962 963 if (status & MACE_IR_XMTINT) { 964 unsigned char fifofc; 965 unsigned char xmtrc; 966 unsigned char xmtfs; 967 968 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC); 969 if ((fifofc & MACE_FIFOFC_XMTFC)==0) { 970 lp->linux_stats.tx_errors++; 971 outb(0xFF, ioaddr + AM2150_XMT_SKIP); 972 } 973 974 /* Transmit Retry Count (XMTRC, reg 4) */ 975 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC); 976 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++; 977 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC); 978 979 if ( 980 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) & 981 MACE_XMTFS_XMTSV /* Transmit Status Valid */ 982 ) { 983 lp->mace_stats.xmtsv++; 984 985 if (xmtfs & ~MACE_XMTFS_XMTSV) { 986 if (xmtfs & MACE_XMTFS_UFLO) { 987 /* Underflow. Indicates that the Transmit FIFO emptied before 988 the end of frame was reached. */ 989 lp->mace_stats.uflo++; 990 } 991 if (xmtfs & MACE_XMTFS_LCOL) { 992 /* Late Collision */ 993 lp->mace_stats.lcol++; 994 } 995 if (xmtfs & MACE_XMTFS_MORE) { 996 /* MORE than one retry was needed */ 997 lp->mace_stats.more++; 998 } 999 if (xmtfs & MACE_XMTFS_ONE) { 1000 /* Exactly ONE retry occurred */ 1001 lp->mace_stats.one++; 1002 } 1003 if (xmtfs & MACE_XMTFS_DEFER) { 1004 /* Transmission was defered */ 1005 lp->mace_stats.defer++; 1006 } 1007 if (xmtfs & MACE_XMTFS_LCAR) { 1008 /* Loss of carrier */ 1009 lp->mace_stats.lcar++; 1010 } 1011 if (xmtfs & MACE_XMTFS_RTRY) { 1012 /* Retry error: transmit aborted after 16 attempts */ 1013 lp->mace_stats.rtry++; 1014 } 1015 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */ 1016 1017 } /* if (xmtfs & MACE_XMTFS_XMTSV) */ 1018 1019 lp->linux_stats.tx_packets++; 1020 lp->tx_free_frames++; 1021 netif_wake_queue(dev); 1022 } /* if (status & MACE_IR_XMTINT) */ 1023 1024 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) { 1025 if (status & MACE_IR_JAB) { 1026 /* Jabber Error. Excessive transmit duration (20-150ms). */ 1027 lp->mace_stats.jab++; 1028 } 1029 if (status & MACE_IR_BABL) { 1030 /* Babble Error. >1518 bytes transmitted. */ 1031 lp->mace_stats.babl++; 1032 } 1033 if (status & MACE_IR_CERR) { 1034 /* Collision Error. CERR indicates the absence of the 1035 Signal Quality Error Test message after a packet 1036 transmission. */ 1037 lp->mace_stats.cerr++; 1038 } 1039 if (status & MACE_IR_RCVCCO) { 1040 /* Receive Collision Count Overflow; */ 1041 lp->mace_stats.rcvcco++; 1042 } 1043 if (status & MACE_IR_RNTPCO) { 1044 /* Runt Packet Count Overflow */ 1045 lp->mace_stats.rntpco++; 1046 } 1047 if (status & MACE_IR_MPCO) { 1048 /* Missed Packet Count Overflow */ 1049 lp->mace_stats.mpco++; 1050 } 1051 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */ 1052 1053 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt)); 1054 1055 return IRQ_HANDLED; 1056 } /* mace_interrupt */ 1057 1058 /* ---------------------------------------------------------------------------- 1059 mace_rx 1060 Receives packets. 1061 ---------------------------------------------------------------------------- */ 1062 static int mace_rx(struct net_device *dev, unsigned char RxCnt) 1063 { 1064 mace_private *lp = netdev_priv(dev); 1065 unsigned int ioaddr = dev->base_addr; 1066 unsigned char rx_framecnt; 1067 unsigned short rx_status; 1068 1069 while ( 1070 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) && 1071 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */ 1072 (RxCnt--) 1073 ) { 1074 rx_status = inw(ioaddr + AM2150_RCV); 1075 1076 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status" 1077 " 0x%X.\n", dev->name, rx_framecnt, rx_status); 1078 1079 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */ 1080 lp->linux_stats.rx_errors++; 1081 if (rx_status & MACE_RCVFS_OFLO) { 1082 lp->mace_stats.oflo++; 1083 } 1084 if (rx_status & MACE_RCVFS_CLSN) { 1085 lp->mace_stats.clsn++; 1086 } 1087 if (rx_status & MACE_RCVFS_FRAM) { 1088 lp->mace_stats.fram++; 1089 } 1090 if (rx_status & MACE_RCVFS_FCS) { 1091 lp->mace_stats.fcs++; 1092 } 1093 } else { 1094 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4; 1095 /* Auto Strip is off, always subtract 4 */ 1096 struct sk_buff *skb; 1097 1098 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV); 1099 /* runt packet count */ 1100 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV); 1101 /* rcv collision count */ 1102 1103 pr_debug(" receiving packet size 0x%X rx_status" 1104 " 0x%X.\n", pkt_len, rx_status); 1105 1106 skb = netdev_alloc_skb(dev, pkt_len + 2); 1107 1108 if (skb != NULL) { 1109 skb_reserve(skb, 2); 1110 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1); 1111 if (pkt_len & 1) 1112 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV); 1113 skb->protocol = eth_type_trans(skb, dev); 1114 1115 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */ 1116 1117 lp->linux_stats.rx_packets++; 1118 lp->linux_stats.rx_bytes += pkt_len; 1119 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */ 1120 continue; 1121 } else { 1122 pr_debug("%s: couldn't allocate a sk_buff of size" 1123 " %d.\n", dev->name, pkt_len); 1124 lp->linux_stats.rx_dropped++; 1125 } 1126 } 1127 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */ 1128 } /* while */ 1129 1130 return 0; 1131 } /* mace_rx */ 1132 1133 /* ---------------------------------------------------------------------------- 1134 pr_linux_stats 1135 ---------------------------------------------------------------------------- */ 1136 static void pr_linux_stats(struct net_device_stats *pstats) 1137 { 1138 pr_debug("pr_linux_stats\n"); 1139 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n", 1140 (long)pstats->rx_packets, (long)pstats->tx_packets); 1141 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n", 1142 (long)pstats->rx_errors, (long)pstats->tx_errors); 1143 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n", 1144 (long)pstats->rx_dropped, (long)pstats->tx_dropped); 1145 pr_debug(" multicast=%-7ld collisions=%ld\n", 1146 (long)pstats->multicast, (long)pstats->collisions); 1147 1148 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n", 1149 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors); 1150 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n", 1151 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors); 1152 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n", 1153 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors); 1154 1155 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n", 1156 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors); 1157 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n", 1158 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors); 1159 pr_debug(" tx_window_errors=%ld\n", 1160 (long)pstats->tx_window_errors); 1161 } /* pr_linux_stats */ 1162 1163 /* ---------------------------------------------------------------------------- 1164 pr_mace_stats 1165 ---------------------------------------------------------------------------- */ 1166 static void pr_mace_stats(mace_statistics *pstats) 1167 { 1168 pr_debug("pr_mace_stats\n"); 1169 1170 pr_debug(" xmtsv=%-7d uflo=%d\n", 1171 pstats->xmtsv, pstats->uflo); 1172 pr_debug(" lcol=%-7d more=%d\n", 1173 pstats->lcol, pstats->more); 1174 pr_debug(" one=%-7d defer=%d\n", 1175 pstats->one, pstats->defer); 1176 pr_debug(" lcar=%-7d rtry=%d\n", 1177 pstats->lcar, pstats->rtry); 1178 1179 /* MACE_XMTRC */ 1180 pr_debug(" exdef=%-7d xmtrc=%d\n", 1181 pstats->exdef, pstats->xmtrc); 1182 1183 /* RFS1--Receive Status (RCVSTS) */ 1184 pr_debug(" oflo=%-7d clsn=%d\n", 1185 pstats->oflo, pstats->clsn); 1186 pr_debug(" fram=%-7d fcs=%d\n", 1187 pstats->fram, pstats->fcs); 1188 1189 /* RFS2--Runt Packet Count (RNTPC) */ 1190 /* RFS3--Receive Collision Count (RCVCC) */ 1191 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n", 1192 pstats->rfs_rntpc, pstats->rfs_rcvcc); 1193 1194 /* MACE_IR */ 1195 pr_debug(" jab=%-7d babl=%d\n", 1196 pstats->jab, pstats->babl); 1197 pr_debug(" cerr=%-7d rcvcco=%d\n", 1198 pstats->cerr, pstats->rcvcco); 1199 pr_debug(" rntpco=%-7d mpco=%d\n", 1200 pstats->rntpco, pstats->mpco); 1201 1202 /* MACE_MPC */ 1203 pr_debug(" mpc=%d\n", pstats->mpc); 1204 1205 /* MACE_RNTPC */ 1206 pr_debug(" rntpc=%d\n", pstats->rntpc); 1207 1208 /* MACE_RCVCC */ 1209 pr_debug(" rcvcc=%d\n", pstats->rcvcc); 1210 1211 } /* pr_mace_stats */ 1212 1213 /* ---------------------------------------------------------------------------- 1214 update_stats 1215 Update statistics. We change to register window 1, so this 1216 should be run single-threaded if the device is active. This is 1217 expected to be a rare operation, and it's simpler for the rest 1218 of the driver to assume that window 0 is always valid rather 1219 than use a special window-state variable. 1220 1221 oflo & uflo should _never_ occur since it would mean the Xilinx 1222 was not able to transfer data between the MACE FIFO and the 1223 card's SRAM fast enough. If this happens, something is 1224 seriously wrong with the hardware. 1225 ---------------------------------------------------------------------------- */ 1226 static void update_stats(unsigned int ioaddr, struct net_device *dev) 1227 { 1228 mace_private *lp = netdev_priv(dev); 1229 1230 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC); 1231 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC); 1232 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC); 1233 /* At this point, mace_stats is fully updated for this call. 1234 We may now update the linux_stats. */ 1235 1236 /* The MACE has no equivalent for linux_stats field which are commented 1237 out. */ 1238 1239 /* lp->linux_stats.multicast; */ 1240 lp->linux_stats.collisions = 1241 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc; 1242 /* Collision: The MACE may retry sending a packet 15 times 1243 before giving up. The retry count is in XMTRC. 1244 Does each retry constitute a collision? 1245 If so, why doesn't the RCVCC record these collisions? */ 1246 1247 /* detailed rx_errors: */ 1248 lp->linux_stats.rx_length_errors = 1249 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc; 1250 /* lp->linux_stats.rx_over_errors */ 1251 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs; 1252 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram; 1253 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo; 1254 lp->linux_stats.rx_missed_errors = 1255 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc; 1256 1257 /* detailed tx_errors */ 1258 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry; 1259 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar; 1260 /* LCAR usually results from bad cabling. */ 1261 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo; 1262 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr; 1263 /* lp->linux_stats.tx_window_errors; */ 1264 } /* update_stats */ 1265 1266 /* ---------------------------------------------------------------------------- 1267 mace_get_stats 1268 Gathers ethernet statistics from the MACE chip. 1269 ---------------------------------------------------------------------------- */ 1270 static struct net_device_stats *mace_get_stats(struct net_device *dev) 1271 { 1272 mace_private *lp = netdev_priv(dev); 1273 1274 update_stats(dev->base_addr, dev); 1275 1276 pr_debug("%s: updating the statistics.\n", dev->name); 1277 pr_linux_stats(&lp->linux_stats); 1278 pr_mace_stats(&lp->mace_stats); 1279 1280 return &lp->linux_stats; 1281 } /* net_device_stats */ 1282 1283 /* ---------------------------------------------------------------------------- 1284 updateCRC 1285 Modified from Am79C90 data sheet. 1286 ---------------------------------------------------------------------------- */ 1287 1288 #ifdef BROKEN_MULTICAST 1289 1290 static void updateCRC(int *CRC, int bit) 1291 { 1292 static const int poly[]={ 1293 1,1,1,0, 1,1,0,1, 1294 1,0,1,1, 1,0,0,0, 1295 1,0,0,0, 0,0,1,1, 1296 0,0,1,0, 0,0,0,0 1297 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the 1298 CRC generator polynomial. */ 1299 1300 int j; 1301 1302 /* shift CRC and control bit (CRC[32]) */ 1303 for (j = 32; j > 0; j--) 1304 CRC[j] = CRC[j-1]; 1305 CRC[0] = 0; 1306 1307 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */ 1308 if (bit ^ CRC[32]) 1309 for (j = 0; j < 32; j++) 1310 CRC[j] ^= poly[j]; 1311 } /* updateCRC */ 1312 1313 /* ---------------------------------------------------------------------------- 1314 BuildLAF 1315 Build logical address filter. 1316 Modified from Am79C90 data sheet. 1317 1318 Input 1319 ladrf: logical address filter (contents initialized to 0) 1320 adr: ethernet address 1321 ---------------------------------------------------------------------------- */ 1322 static void BuildLAF(int *ladrf, int *adr) 1323 { 1324 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */ 1325 1326 int i, byte; /* temporary array indices */ 1327 int hashcode; /* the output object */ 1328 1329 CRC[32]=0; 1330 1331 for (byte = 0; byte < 6; byte++) 1332 for (i = 0; i < 8; i++) 1333 updateCRC(CRC, (adr[byte] >> i) & 1); 1334 1335 hashcode = 0; 1336 for (i = 0; i < 6; i++) 1337 hashcode = (hashcode << 1) + CRC[i]; 1338 1339 byte = hashcode >> 3; 1340 ladrf[byte] |= (1 << (hashcode & 7)); 1341 1342 #ifdef PCMCIA_DEBUG 1343 if (0) 1344 printk(KERN_DEBUG " adr =%pM\n", adr); 1345 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode); 1346 for (i = 0; i < 8; i++) 1347 pr_cont(" %02X", ladrf[i]); 1348 pr_cont("\n"); 1349 #endif 1350 } /* BuildLAF */ 1351 1352 /* ---------------------------------------------------------------------------- 1353 restore_multicast_list 1354 Restores the multicast filter for MACE chip to the last 1355 set_multicast_list() call. 1356 1357 Input 1358 multicast_num_addrs 1359 multicast_ladrf[] 1360 ---------------------------------------------------------------------------- */ 1361 static void restore_multicast_list(struct net_device *dev) 1362 { 1363 mace_private *lp = netdev_priv(dev); 1364 int num_addrs = lp->multicast_num_addrs; 1365 int *ladrf = lp->multicast_ladrf; 1366 unsigned int ioaddr = dev->base_addr; 1367 int i; 1368 1369 pr_debug("%s: restoring Rx mode to %d addresses.\n", 1370 dev->name, num_addrs); 1371 1372 if (num_addrs > 0) { 1373 1374 pr_debug("Attempt to restore multicast list detected.\n"); 1375 1376 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR); 1377 /* Poll ADDRCHG bit */ 1378 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG) 1379 ; 1380 /* Set LADRF register */ 1381 for (i = 0; i < MACE_LADRF_LEN; i++) 1382 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]); 1383 1384 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL); 1385 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); 1386 1387 } else if (num_addrs < 0) { 1388 1389 /* Promiscuous mode: receive all packets */ 1390 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1391 mace_write(lp, ioaddr, MACE_MACCC, 1392 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV 1393 ); 1394 1395 } else { 1396 1397 /* Normal mode */ 1398 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1399 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); 1400 1401 } 1402 } /* restore_multicast_list */ 1403 1404 /* ---------------------------------------------------------------------------- 1405 set_multicast_list 1406 Set or clear the multicast filter for this adaptor. 1407 1408 Input 1409 num_addrs == -1 Promiscuous mode, receive all packets 1410 num_addrs == 0 Normal mode, clear multicast list 1411 num_addrs > 0 Multicast mode, receive normal and MC packets, and do 1412 best-effort filtering. 1413 Output 1414 multicast_num_addrs 1415 multicast_ladrf[] 1416 ---------------------------------------------------------------------------- */ 1417 1418 static void set_multicast_list(struct net_device *dev) 1419 { 1420 mace_private *lp = netdev_priv(dev); 1421 int adr[ETH_ALEN] = {0}; /* Ethernet address */ 1422 struct netdev_hw_addr *ha; 1423 1424 #ifdef PCMCIA_DEBUG 1425 { 1426 static int old; 1427 if (netdev_mc_count(dev) != old) { 1428 old = netdev_mc_count(dev); 1429 pr_debug("%s: setting Rx mode to %d addresses.\n", 1430 dev->name, old); 1431 } 1432 } 1433 #endif 1434 1435 /* Set multicast_num_addrs. */ 1436 lp->multicast_num_addrs = netdev_mc_count(dev); 1437 1438 /* Set multicast_ladrf. */ 1439 if (num_addrs > 0) { 1440 /* Calculate multicast logical address filter */ 1441 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN); 1442 netdev_for_each_mc_addr(ha, dev) { 1443 memcpy(adr, ha->addr, ETH_ALEN); 1444 BuildLAF(lp->multicast_ladrf, adr); 1445 } 1446 } 1447 1448 restore_multicast_list(dev); 1449 1450 } /* set_multicast_list */ 1451 1452 #endif /* BROKEN_MULTICAST */ 1453 1454 static void restore_multicast_list(struct net_device *dev) 1455 { 1456 unsigned int ioaddr = dev->base_addr; 1457 mace_private *lp = netdev_priv(dev); 1458 1459 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name, 1460 lp->multicast_num_addrs); 1461 1462 if (dev->flags & IFF_PROMISC) { 1463 /* Promiscuous mode: receive all packets */ 1464 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1465 mace_write(lp, ioaddr, MACE_MACCC, 1466 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV 1467 ); 1468 } else { 1469 /* Normal mode */ 1470 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL); 1471 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); 1472 } 1473 } /* restore_multicast_list */ 1474 1475 static void set_multicast_list(struct net_device *dev) 1476 { 1477 mace_private *lp = netdev_priv(dev); 1478 1479 #ifdef PCMCIA_DEBUG 1480 { 1481 static int old; 1482 if (netdev_mc_count(dev) != old) { 1483 old = netdev_mc_count(dev); 1484 pr_debug("%s: setting Rx mode to %d addresses.\n", 1485 dev->name, old); 1486 } 1487 } 1488 #endif 1489 1490 lp->multicast_num_addrs = netdev_mc_count(dev); 1491 restore_multicast_list(dev); 1492 1493 } /* set_multicast_list */ 1494 1495 static const struct pcmcia_device_id nmclan_ids[] = { 1496 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941), 1497 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf), 1498 PCMCIA_DEVICE_NULL, 1499 }; 1500 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids); 1501 1502 static struct pcmcia_driver nmclan_cs_driver = { 1503 .owner = THIS_MODULE, 1504 .name = "nmclan_cs", 1505 .probe = nmclan_probe, 1506 .remove = nmclan_detach, 1507 .id_table = nmclan_ids, 1508 .suspend = nmclan_suspend, 1509 .resume = nmclan_resume, 1510 }; 1511 1512 static int __init init_nmclan_cs(void) 1513 { 1514 return pcmcia_register_driver(&nmclan_cs_driver); 1515 } 1516 1517 static void __exit exit_nmclan_cs(void) 1518 { 1519 pcmcia_unregister_driver(&nmclan_cs_driver); 1520 } 1521 1522 module_init(init_nmclan_cs); 1523 module_exit(exit_nmclan_cs); 1524