1 /* 2 * 3 * Alchemy Au1x00 ethernet driver 4 * 5 * Copyright 2001-2003, 2006 MontaVista Software Inc. 6 * Copyright 2002 TimeSys Corp. 7 * Added ethtool/mii-tool support, 8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org> 9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de 10 * or riemer@riemer-nt.de: fixed the link beat detection with 11 * ioctls (SIOCGMIIPHY) 12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org> 13 * converted to use linux-2.6.x's PHY framework 14 * 15 * Author: MontaVista Software, Inc. 16 * ppopov@mvista.com or source@mvista.com 17 * 18 * ######################################################################## 19 * 20 * This program is free software; you can distribute it and/or modify it 21 * under the terms of the GNU General Public License (Version 2) as 22 * published by the Free Software Foundation. 23 * 24 * This program is distributed in the hope it will be useful, but WITHOUT 25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 27 * for more details. 28 * 29 * You should have received a copy of the GNU General Public License along 30 * with this program; if not, see <http://www.gnu.org/licenses/>. 31 * 32 * ######################################################################## 33 * 34 * 35 */ 36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 37 38 #include <linux/capability.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/module.h> 41 #include <linux/kernel.h> 42 #include <linux/string.h> 43 #include <linux/timer.h> 44 #include <linux/errno.h> 45 #include <linux/in.h> 46 #include <linux/ioport.h> 47 #include <linux/bitops.h> 48 #include <linux/slab.h> 49 #include <linux/interrupt.h> 50 #include <linux/netdevice.h> 51 #include <linux/etherdevice.h> 52 #include <linux/ethtool.h> 53 #include <linux/mii.h> 54 #include <linux/skbuff.h> 55 #include <linux/delay.h> 56 #include <linux/crc32.h> 57 #include <linux/phy.h> 58 #include <linux/platform_device.h> 59 #include <linux/cpu.h> 60 #include <linux/io.h> 61 62 #include <asm/mipsregs.h> 63 #include <asm/irq.h> 64 #include <asm/processor.h> 65 66 #include <au1000.h> 67 #include <au1xxx_eth.h> 68 #include <prom.h> 69 70 #include "au1000_eth.h" 71 72 #ifdef AU1000_ETH_DEBUG 73 static int au1000_debug = 5; 74 #else 75 static int au1000_debug = 3; 76 #endif 77 78 #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \ 79 NETIF_MSG_PROBE | \ 80 NETIF_MSG_LINK) 81 82 #define DRV_NAME "au1000_eth" 83 #define DRV_VERSION "1.7" 84 #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>" 85 #define DRV_DESC "Au1xxx on-chip Ethernet driver" 86 87 MODULE_AUTHOR(DRV_AUTHOR); 88 MODULE_DESCRIPTION(DRV_DESC); 89 MODULE_LICENSE("GPL"); 90 MODULE_VERSION(DRV_VERSION); 91 92 /* AU1000 MAC registers and bits */ 93 #define MAC_CONTROL 0x0 94 # define MAC_RX_ENABLE (1 << 2) 95 # define MAC_TX_ENABLE (1 << 3) 96 # define MAC_DEF_CHECK (1 << 5) 97 # define MAC_SET_BL(X) (((X) & 0x3) << 6) 98 # define MAC_AUTO_PAD (1 << 8) 99 # define MAC_DISABLE_RETRY (1 << 10) 100 # define MAC_DISABLE_BCAST (1 << 11) 101 # define MAC_LATE_COL (1 << 12) 102 # define MAC_HASH_MODE (1 << 13) 103 # define MAC_HASH_ONLY (1 << 15) 104 # define MAC_PASS_ALL (1 << 16) 105 # define MAC_INVERSE_FILTER (1 << 17) 106 # define MAC_PROMISCUOUS (1 << 18) 107 # define MAC_PASS_ALL_MULTI (1 << 19) 108 # define MAC_FULL_DUPLEX (1 << 20) 109 # define MAC_NORMAL_MODE 0 110 # define MAC_INT_LOOPBACK (1 << 21) 111 # define MAC_EXT_LOOPBACK (1 << 22) 112 # define MAC_DISABLE_RX_OWN (1 << 23) 113 # define MAC_BIG_ENDIAN (1 << 30) 114 # define MAC_RX_ALL (1 << 31) 115 #define MAC_ADDRESS_HIGH 0x4 116 #define MAC_ADDRESS_LOW 0x8 117 #define MAC_MCAST_HIGH 0xC 118 #define MAC_MCAST_LOW 0x10 119 #define MAC_MII_CNTRL 0x14 120 # define MAC_MII_BUSY (1 << 0) 121 # define MAC_MII_READ 0 122 # define MAC_MII_WRITE (1 << 1) 123 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6) 124 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11) 125 #define MAC_MII_DATA 0x18 126 #define MAC_FLOW_CNTRL 0x1C 127 # define MAC_FLOW_CNTRL_BUSY (1 << 0) 128 # define MAC_FLOW_CNTRL_ENABLE (1 << 1) 129 # define MAC_PASS_CONTROL (1 << 2) 130 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16) 131 #define MAC_VLAN1_TAG 0x20 132 #define MAC_VLAN2_TAG 0x24 133 134 /* Ethernet Controller Enable */ 135 # define MAC_EN_CLOCK_ENABLE (1 << 0) 136 # define MAC_EN_RESET0 (1 << 1) 137 # define MAC_EN_TOSS (0 << 2) 138 # define MAC_EN_CACHEABLE (1 << 3) 139 # define MAC_EN_RESET1 (1 << 4) 140 # define MAC_EN_RESET2 (1 << 5) 141 # define MAC_DMA_RESET (1 << 6) 142 143 /* Ethernet Controller DMA Channels */ 144 /* offsets from MAC_TX_RING_ADDR address */ 145 #define MAC_TX_BUFF0_STATUS 0x0 146 # define TX_FRAME_ABORTED (1 << 0) 147 # define TX_JAB_TIMEOUT (1 << 1) 148 # define TX_NO_CARRIER (1 << 2) 149 # define TX_LOSS_CARRIER (1 << 3) 150 # define TX_EXC_DEF (1 << 4) 151 # define TX_LATE_COLL_ABORT (1 << 5) 152 # define TX_EXC_COLL (1 << 6) 153 # define TX_UNDERRUN (1 << 7) 154 # define TX_DEFERRED (1 << 8) 155 # define TX_LATE_COLL (1 << 9) 156 # define TX_COLL_CNT_MASK (0xF << 10) 157 # define TX_PKT_RETRY (1 << 31) 158 #define MAC_TX_BUFF0_ADDR 0x4 159 # define TX_DMA_ENABLE (1 << 0) 160 # define TX_T_DONE (1 << 1) 161 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 162 #define MAC_TX_BUFF0_LEN 0x8 163 #define MAC_TX_BUFF1_STATUS 0x10 164 #define MAC_TX_BUFF1_ADDR 0x14 165 #define MAC_TX_BUFF1_LEN 0x18 166 #define MAC_TX_BUFF2_STATUS 0x20 167 #define MAC_TX_BUFF2_ADDR 0x24 168 #define MAC_TX_BUFF2_LEN 0x28 169 #define MAC_TX_BUFF3_STATUS 0x30 170 #define MAC_TX_BUFF3_ADDR 0x34 171 #define MAC_TX_BUFF3_LEN 0x38 172 173 /* offsets from MAC_RX_RING_ADDR */ 174 #define MAC_RX_BUFF0_STATUS 0x0 175 # define RX_FRAME_LEN_MASK 0x3fff 176 # define RX_WDOG_TIMER (1 << 14) 177 # define RX_RUNT (1 << 15) 178 # define RX_OVERLEN (1 << 16) 179 # define RX_COLL (1 << 17) 180 # define RX_ETHER (1 << 18) 181 # define RX_MII_ERROR (1 << 19) 182 # define RX_DRIBBLING (1 << 20) 183 # define RX_CRC_ERROR (1 << 21) 184 # define RX_VLAN1 (1 << 22) 185 # define RX_VLAN2 (1 << 23) 186 # define RX_LEN_ERROR (1 << 24) 187 # define RX_CNTRL_FRAME (1 << 25) 188 # define RX_U_CNTRL_FRAME (1 << 26) 189 # define RX_MCAST_FRAME (1 << 27) 190 # define RX_BCAST_FRAME (1 << 28) 191 # define RX_FILTER_FAIL (1 << 29) 192 # define RX_PACKET_FILTER (1 << 30) 193 # define RX_MISSED_FRAME (1 << 31) 194 195 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \ 196 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \ 197 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME) 198 #define MAC_RX_BUFF0_ADDR 0x4 199 # define RX_DMA_ENABLE (1 << 0) 200 # define RX_T_DONE (1 << 1) 201 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3) 202 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0) 203 #define MAC_RX_BUFF1_STATUS 0x10 204 #define MAC_RX_BUFF1_ADDR 0x14 205 #define MAC_RX_BUFF2_STATUS 0x20 206 #define MAC_RX_BUFF2_ADDR 0x24 207 #define MAC_RX_BUFF3_STATUS 0x30 208 #define MAC_RX_BUFF3_ADDR 0x34 209 210 /* 211 * Theory of operation 212 * 213 * The Au1000 MACs use a simple rx and tx descriptor ring scheme. 214 * There are four receive and four transmit descriptors. These 215 * descriptors are not in memory; rather, they are just a set of 216 * hardware registers. 217 * 218 * Since the Au1000 has a coherent data cache, the receive and 219 * transmit buffers are allocated from the KSEG0 segment. The 220 * hardware registers, however, are still mapped at KSEG1 to 221 * make sure there's no out-of-order writes, and that all writes 222 * complete immediately. 223 */ 224 225 /* 226 * board-specific configurations 227 * 228 * PHY detection algorithm 229 * 230 * If phy_static_config is undefined, the PHY setup is 231 * autodetected: 232 * 233 * mii_probe() first searches the current MAC's MII bus for a PHY, 234 * selecting the first (or last, if phy_search_highest_addr is 235 * defined) PHY address not already claimed by another netdev. 236 * 237 * If nothing was found that way when searching for the 2nd ethernet 238 * controller's PHY and phy1_search_mac0 is defined, then 239 * the first MII bus is searched as well for an unclaimed PHY; this is 240 * needed in case of a dual-PHY accessible only through the MAC0's MII 241 * bus. 242 * 243 * Finally, if no PHY is found, then the corresponding ethernet 244 * controller is not registered to the network subsystem. 245 */ 246 247 /* autodetection defaults: phy1_search_mac0 */ 248 249 /* static PHY setup 250 * 251 * most boards PHY setup should be detectable properly with the 252 * autodetection algorithm in mii_probe(), but in some cases (e.g. if 253 * you have a switch attached, or want to use the PHY's interrupt 254 * notification capabilities) you can provide a static PHY 255 * configuration here 256 * 257 * IRQs may only be set, if a PHY address was configured 258 * If a PHY address is given, also a bus id is required to be set 259 * 260 * ps: make sure the used irqs are configured properly in the board 261 * specific irq-map 262 */ 263 264 static void au1000_enable_mac(struct net_device *dev, int force_reset) 265 { 266 unsigned long flags; 267 struct au1000_private *aup = netdev_priv(dev); 268 269 spin_lock_irqsave(&aup->lock, flags); 270 271 if (force_reset || (!aup->mac_enabled)) { 272 writel(MAC_EN_CLOCK_ENABLE, aup->enable); 273 wmb(); /* drain writebuffer */ 274 mdelay(2); 275 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2 276 | MAC_EN_CLOCK_ENABLE), aup->enable); 277 wmb(); /* drain writebuffer */ 278 mdelay(2); 279 280 aup->mac_enabled = 1; 281 } 282 283 spin_unlock_irqrestore(&aup->lock, flags); 284 } 285 286 /* 287 * MII operations 288 */ 289 static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg) 290 { 291 struct au1000_private *aup = netdev_priv(dev); 292 u32 *const mii_control_reg = &aup->mac->mii_control; 293 u32 *const mii_data_reg = &aup->mac->mii_data; 294 u32 timedout = 20; 295 u32 mii_control; 296 297 while (readl(mii_control_reg) & MAC_MII_BUSY) { 298 mdelay(1); 299 if (--timedout == 0) { 300 netdev_err(dev, "read_MII busy timeout!!\n"); 301 return -1; 302 } 303 } 304 305 mii_control = MAC_SET_MII_SELECT_REG(reg) | 306 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ; 307 308 writel(mii_control, mii_control_reg); 309 310 timedout = 20; 311 while (readl(mii_control_reg) & MAC_MII_BUSY) { 312 mdelay(1); 313 if (--timedout == 0) { 314 netdev_err(dev, "mdio_read busy timeout!!\n"); 315 return -1; 316 } 317 } 318 return readl(mii_data_reg); 319 } 320 321 static void au1000_mdio_write(struct net_device *dev, int phy_addr, 322 int reg, u16 value) 323 { 324 struct au1000_private *aup = netdev_priv(dev); 325 u32 *const mii_control_reg = &aup->mac->mii_control; 326 u32 *const mii_data_reg = &aup->mac->mii_data; 327 u32 timedout = 20; 328 u32 mii_control; 329 330 while (readl(mii_control_reg) & MAC_MII_BUSY) { 331 mdelay(1); 332 if (--timedout == 0) { 333 netdev_err(dev, "mdio_write busy timeout!!\n"); 334 return; 335 } 336 } 337 338 mii_control = MAC_SET_MII_SELECT_REG(reg) | 339 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE; 340 341 writel(value, mii_data_reg); 342 writel(mii_control, mii_control_reg); 343 } 344 345 static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum) 346 { 347 struct net_device *const dev = bus->priv; 348 349 /* make sure the MAC associated with this 350 * mii_bus is enabled 351 */ 352 au1000_enable_mac(dev, 0); 353 354 return au1000_mdio_read(dev, phy_addr, regnum); 355 } 356 357 static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, 358 u16 value) 359 { 360 struct net_device *const dev = bus->priv; 361 362 /* make sure the MAC associated with this 363 * mii_bus is enabled 364 */ 365 au1000_enable_mac(dev, 0); 366 367 au1000_mdio_write(dev, phy_addr, regnum, value); 368 return 0; 369 } 370 371 static int au1000_mdiobus_reset(struct mii_bus *bus) 372 { 373 struct net_device *const dev = bus->priv; 374 375 /* make sure the MAC associated with this 376 * mii_bus is enabled 377 */ 378 au1000_enable_mac(dev, 0); 379 380 return 0; 381 } 382 383 static void au1000_hard_stop(struct net_device *dev) 384 { 385 struct au1000_private *aup = netdev_priv(dev); 386 u32 reg; 387 388 netif_dbg(aup, drv, dev, "hard stop\n"); 389 390 reg = readl(&aup->mac->control); 391 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE); 392 writel(reg, &aup->mac->control); 393 wmb(); /* drain writebuffer */ 394 mdelay(10); 395 } 396 397 static void au1000_enable_rx_tx(struct net_device *dev) 398 { 399 struct au1000_private *aup = netdev_priv(dev); 400 u32 reg; 401 402 netif_dbg(aup, hw, dev, "enable_rx_tx\n"); 403 404 reg = readl(&aup->mac->control); 405 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE); 406 writel(reg, &aup->mac->control); 407 wmb(); /* drain writebuffer */ 408 mdelay(10); 409 } 410 411 static void 412 au1000_adjust_link(struct net_device *dev) 413 { 414 struct au1000_private *aup = netdev_priv(dev); 415 struct phy_device *phydev = dev->phydev; 416 unsigned long flags; 417 u32 reg; 418 419 int status_change = 0; 420 421 BUG_ON(!phydev); 422 423 spin_lock_irqsave(&aup->lock, flags); 424 425 if (phydev->link && (aup->old_speed != phydev->speed)) { 426 /* speed changed */ 427 428 switch (phydev->speed) { 429 case SPEED_10: 430 case SPEED_100: 431 break; 432 default: 433 netdev_warn(dev, "Speed (%d) is not 10/100 ???\n", 434 phydev->speed); 435 break; 436 } 437 438 aup->old_speed = phydev->speed; 439 440 status_change = 1; 441 } 442 443 if (phydev->link && (aup->old_duplex != phydev->duplex)) { 444 /* duplex mode changed */ 445 446 /* switching duplex mode requires to disable rx and tx! */ 447 au1000_hard_stop(dev); 448 449 reg = readl(&aup->mac->control); 450 if (DUPLEX_FULL == phydev->duplex) { 451 reg |= MAC_FULL_DUPLEX; 452 reg &= ~MAC_DISABLE_RX_OWN; 453 } else { 454 reg &= ~MAC_FULL_DUPLEX; 455 reg |= MAC_DISABLE_RX_OWN; 456 } 457 writel(reg, &aup->mac->control); 458 wmb(); /* drain writebuffer */ 459 mdelay(1); 460 461 au1000_enable_rx_tx(dev); 462 aup->old_duplex = phydev->duplex; 463 464 status_change = 1; 465 } 466 467 if (phydev->link != aup->old_link) { 468 /* link state changed */ 469 470 if (!phydev->link) { 471 /* link went down */ 472 aup->old_speed = 0; 473 aup->old_duplex = -1; 474 } 475 476 aup->old_link = phydev->link; 477 status_change = 1; 478 } 479 480 spin_unlock_irqrestore(&aup->lock, flags); 481 482 if (status_change) { 483 if (phydev->link) 484 netdev_info(dev, "link up (%d/%s)\n", 485 phydev->speed, 486 DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); 487 else 488 netdev_info(dev, "link down\n"); 489 } 490 } 491 492 static int au1000_mii_probe(struct net_device *dev) 493 { 494 struct au1000_private *const aup = netdev_priv(dev); 495 struct phy_device *phydev = NULL; 496 int phy_addr; 497 498 if (aup->phy_static_config) { 499 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); 500 501 if (aup->phy_addr) 502 phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr); 503 else 504 netdev_info(dev, "using PHY-less setup\n"); 505 return 0; 506 } 507 508 /* find the first (lowest address) PHY 509 * on the current MAC's MII bus 510 */ 511 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) 512 if (mdiobus_get_phy(aup->mii_bus, phy_addr)) { 513 phydev = mdiobus_get_phy(aup->mii_bus, phy_addr); 514 if (!aup->phy_search_highest_addr) 515 /* break out with first one found */ 516 break; 517 } 518 519 if (aup->phy1_search_mac0) { 520 /* try harder to find a PHY */ 521 if (!phydev && (aup->mac_id == 1)) { 522 /* no PHY found, maybe we have a dual PHY? */ 523 dev_info(&dev->dev, ": no PHY found on MAC1, " 524 "let's see if it's attached to MAC0...\n"); 525 526 /* find the first (lowest address) non-attached 527 * PHY on the MAC0 MII bus 528 */ 529 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { 530 struct phy_device *const tmp_phydev = 531 mdiobus_get_phy(aup->mii_bus, 532 phy_addr); 533 534 if (aup->mac_id == 1) 535 break; 536 537 /* no PHY here... */ 538 if (!tmp_phydev) 539 continue; 540 541 /* already claimed by MAC0 */ 542 if (tmp_phydev->attached_dev) 543 continue; 544 545 phydev = tmp_phydev; 546 break; /* found it */ 547 } 548 } 549 } 550 551 if (!phydev) { 552 netdev_err(dev, "no PHY found\n"); 553 return -1; 554 } 555 556 /* now we are supposed to have a proper phydev, to attach to... */ 557 BUG_ON(phydev->attached_dev); 558 559 phydev = phy_connect(dev, phydev_name(phydev), 560 &au1000_adjust_link, PHY_INTERFACE_MODE_MII); 561 562 if (IS_ERR(phydev)) { 563 netdev_err(dev, "Could not attach to PHY\n"); 564 return PTR_ERR(phydev); 565 } 566 567 phy_set_max_speed(phydev, SPEED_100); 568 569 aup->old_link = 0; 570 aup->old_speed = 0; 571 aup->old_duplex = -1; 572 573 phy_attached_info(phydev); 574 575 return 0; 576 } 577 578 579 /* 580 * Buffer allocation/deallocation routines. The buffer descriptor returned 581 * has the virtual and dma address of a buffer suitable for 582 * both, receive and transmit operations. 583 */ 584 static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup) 585 { 586 struct db_dest *pDB; 587 pDB = aup->pDBfree; 588 589 if (pDB) 590 aup->pDBfree = pDB->pnext; 591 592 return pDB; 593 } 594 595 void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB) 596 { 597 struct db_dest *pDBfree = aup->pDBfree; 598 if (pDBfree) 599 pDBfree->pnext = pDB; 600 aup->pDBfree = pDB; 601 } 602 603 static void au1000_reset_mac_unlocked(struct net_device *dev) 604 { 605 struct au1000_private *const aup = netdev_priv(dev); 606 int i; 607 608 au1000_hard_stop(dev); 609 610 writel(MAC_EN_CLOCK_ENABLE, aup->enable); 611 wmb(); /* drain writebuffer */ 612 mdelay(2); 613 writel(0, aup->enable); 614 wmb(); /* drain writebuffer */ 615 mdelay(2); 616 617 aup->tx_full = 0; 618 for (i = 0; i < NUM_RX_DMA; i++) { 619 /* reset control bits */ 620 aup->rx_dma_ring[i]->buff_stat &= ~0xf; 621 } 622 for (i = 0; i < NUM_TX_DMA; i++) { 623 /* reset control bits */ 624 aup->tx_dma_ring[i]->buff_stat &= ~0xf; 625 } 626 627 aup->mac_enabled = 0; 628 629 } 630 631 static void au1000_reset_mac(struct net_device *dev) 632 { 633 struct au1000_private *const aup = netdev_priv(dev); 634 unsigned long flags; 635 636 netif_dbg(aup, hw, dev, "reset mac, aup %x\n", 637 (unsigned)aup); 638 639 spin_lock_irqsave(&aup->lock, flags); 640 641 au1000_reset_mac_unlocked(dev); 642 643 spin_unlock_irqrestore(&aup->lock, flags); 644 } 645 646 /* 647 * Setup the receive and transmit "rings". These pointers are the addresses 648 * of the rx and tx MAC DMA registers so they are fixed by the hardware -- 649 * these are not descriptors sitting in memory. 650 */ 651 static void 652 au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base) 653 { 654 int i; 655 656 for (i = 0; i < NUM_RX_DMA; i++) { 657 aup->rx_dma_ring[i] = (struct rx_dma *) 658 (tx_base + 0x100 + sizeof(struct rx_dma) * i); 659 } 660 for (i = 0; i < NUM_TX_DMA; i++) { 661 aup->tx_dma_ring[i] = (struct tx_dma *) 662 (tx_base + sizeof(struct tx_dma) * i); 663 } 664 } 665 666 /* 667 * ethtool operations 668 */ 669 670 static void 671 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 672 { 673 struct au1000_private *aup = netdev_priv(dev); 674 675 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 676 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 677 snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME, 678 aup->mac_id); 679 } 680 681 static void au1000_set_msglevel(struct net_device *dev, u32 value) 682 { 683 struct au1000_private *aup = netdev_priv(dev); 684 aup->msg_enable = value; 685 } 686 687 static u32 au1000_get_msglevel(struct net_device *dev) 688 { 689 struct au1000_private *aup = netdev_priv(dev); 690 return aup->msg_enable; 691 } 692 693 static const struct ethtool_ops au1000_ethtool_ops = { 694 .get_drvinfo = au1000_get_drvinfo, 695 .get_link = ethtool_op_get_link, 696 .get_msglevel = au1000_get_msglevel, 697 .set_msglevel = au1000_set_msglevel, 698 .get_link_ksettings = phy_ethtool_get_link_ksettings, 699 .set_link_ksettings = phy_ethtool_set_link_ksettings, 700 }; 701 702 703 /* 704 * Initialize the interface. 705 * 706 * When the device powers up, the clocks are disabled and the 707 * mac is in reset state. When the interface is closed, we 708 * do the same -- reset the device and disable the clocks to 709 * conserve power. Thus, whenever au1000_init() is called, 710 * the device should already be in reset state. 711 */ 712 static int au1000_init(struct net_device *dev) 713 { 714 struct au1000_private *aup = netdev_priv(dev); 715 unsigned long flags; 716 int i; 717 u32 control; 718 719 netif_dbg(aup, hw, dev, "au1000_init\n"); 720 721 /* bring the device out of reset */ 722 au1000_enable_mac(dev, 1); 723 724 spin_lock_irqsave(&aup->lock, flags); 725 726 writel(0, &aup->mac->control); 727 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2; 728 aup->tx_tail = aup->tx_head; 729 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2; 730 731 writel(dev->dev_addr[5]<<8 | dev->dev_addr[4], 732 &aup->mac->mac_addr_high); 733 writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 | 734 dev->dev_addr[1]<<8 | dev->dev_addr[0], 735 &aup->mac->mac_addr_low); 736 737 738 for (i = 0; i < NUM_RX_DMA; i++) 739 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE; 740 741 wmb(); /* drain writebuffer */ 742 743 control = MAC_RX_ENABLE | MAC_TX_ENABLE; 744 #ifndef CONFIG_CPU_LITTLE_ENDIAN 745 control |= MAC_BIG_ENDIAN; 746 #endif 747 if (dev->phydev) { 748 if (dev->phydev->link && (DUPLEX_FULL == dev->phydev->duplex)) 749 control |= MAC_FULL_DUPLEX; 750 else 751 control |= MAC_DISABLE_RX_OWN; 752 } else { /* PHY-less op, assume full-duplex */ 753 control |= MAC_FULL_DUPLEX; 754 } 755 756 writel(control, &aup->mac->control); 757 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */ 758 wmb(); /* drain writebuffer */ 759 760 spin_unlock_irqrestore(&aup->lock, flags); 761 return 0; 762 } 763 764 static inline void au1000_update_rx_stats(struct net_device *dev, u32 status) 765 { 766 struct net_device_stats *ps = &dev->stats; 767 768 ps->rx_packets++; 769 if (status & RX_MCAST_FRAME) 770 ps->multicast++; 771 772 if (status & RX_ERROR) { 773 ps->rx_errors++; 774 if (status & RX_MISSED_FRAME) 775 ps->rx_missed_errors++; 776 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR)) 777 ps->rx_length_errors++; 778 if (status & RX_CRC_ERROR) 779 ps->rx_crc_errors++; 780 if (status & RX_COLL) 781 ps->collisions++; 782 } else 783 ps->rx_bytes += status & RX_FRAME_LEN_MASK; 784 785 } 786 787 /* 788 * Au1000 receive routine. 789 */ 790 static int au1000_rx(struct net_device *dev) 791 { 792 struct au1000_private *aup = netdev_priv(dev); 793 struct sk_buff *skb; 794 struct rx_dma *prxd; 795 u32 buff_stat, status; 796 struct db_dest *pDB; 797 u32 frmlen; 798 799 netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head); 800 801 prxd = aup->rx_dma_ring[aup->rx_head]; 802 buff_stat = prxd->buff_stat; 803 while (buff_stat & RX_T_DONE) { 804 status = prxd->status; 805 pDB = aup->rx_db_inuse[aup->rx_head]; 806 au1000_update_rx_stats(dev, status); 807 if (!(status & RX_ERROR)) { 808 809 /* good frame */ 810 frmlen = (status & RX_FRAME_LEN_MASK); 811 frmlen -= 4; /* Remove FCS */ 812 skb = netdev_alloc_skb(dev, frmlen + 2); 813 if (skb == NULL) { 814 dev->stats.rx_dropped++; 815 continue; 816 } 817 skb_reserve(skb, 2); /* 16 byte IP header align */ 818 skb_copy_to_linear_data(skb, 819 (unsigned char *)pDB->vaddr, frmlen); 820 skb_put(skb, frmlen); 821 skb->protocol = eth_type_trans(skb, dev); 822 netif_rx(skb); /* pass the packet to upper layers */ 823 } else { 824 if (au1000_debug > 4) { 825 pr_err("rx_error(s):"); 826 if (status & RX_MISSED_FRAME) 827 pr_cont(" miss"); 828 if (status & RX_WDOG_TIMER) 829 pr_cont(" wdog"); 830 if (status & RX_RUNT) 831 pr_cont(" runt"); 832 if (status & RX_OVERLEN) 833 pr_cont(" overlen"); 834 if (status & RX_COLL) 835 pr_cont(" coll"); 836 if (status & RX_MII_ERROR) 837 pr_cont(" mii error"); 838 if (status & RX_CRC_ERROR) 839 pr_cont(" crc error"); 840 if (status & RX_LEN_ERROR) 841 pr_cont(" len error"); 842 if (status & RX_U_CNTRL_FRAME) 843 pr_cont(" u control frame"); 844 pr_cont("\n"); 845 } 846 } 847 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE); 848 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1); 849 wmb(); /* drain writebuffer */ 850 851 /* next descriptor */ 852 prxd = aup->rx_dma_ring[aup->rx_head]; 853 buff_stat = prxd->buff_stat; 854 } 855 return 0; 856 } 857 858 static void au1000_update_tx_stats(struct net_device *dev, u32 status) 859 { 860 struct net_device_stats *ps = &dev->stats; 861 862 if (status & TX_FRAME_ABORTED) { 863 if (!dev->phydev || (DUPLEX_FULL == dev->phydev->duplex)) { 864 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) { 865 /* any other tx errors are only valid 866 * in half duplex mode 867 */ 868 ps->tx_errors++; 869 ps->tx_aborted_errors++; 870 } 871 } else { 872 ps->tx_errors++; 873 ps->tx_aborted_errors++; 874 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER)) 875 ps->tx_carrier_errors++; 876 } 877 } 878 } 879 880 /* 881 * Called from the interrupt service routine to acknowledge 882 * the TX DONE bits. This is a must if the irq is setup as 883 * edge triggered. 884 */ 885 static void au1000_tx_ack(struct net_device *dev) 886 { 887 struct au1000_private *aup = netdev_priv(dev); 888 struct tx_dma *ptxd; 889 890 ptxd = aup->tx_dma_ring[aup->tx_tail]; 891 892 while (ptxd->buff_stat & TX_T_DONE) { 893 au1000_update_tx_stats(dev, ptxd->status); 894 ptxd->buff_stat &= ~TX_T_DONE; 895 ptxd->len = 0; 896 wmb(); /* drain writebuffer */ 897 898 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1); 899 ptxd = aup->tx_dma_ring[aup->tx_tail]; 900 901 if (aup->tx_full) { 902 aup->tx_full = 0; 903 netif_wake_queue(dev); 904 } 905 } 906 } 907 908 /* 909 * Au1000 interrupt service routine. 910 */ 911 static irqreturn_t au1000_interrupt(int irq, void *dev_id) 912 { 913 struct net_device *dev = dev_id; 914 915 /* Handle RX interrupts first to minimize chance of overrun */ 916 917 au1000_rx(dev); 918 au1000_tx_ack(dev); 919 return IRQ_RETVAL(1); 920 } 921 922 static int au1000_open(struct net_device *dev) 923 { 924 int retval; 925 struct au1000_private *aup = netdev_priv(dev); 926 927 netif_dbg(aup, drv, dev, "open: dev=%p\n", dev); 928 929 retval = request_irq(dev->irq, au1000_interrupt, 0, 930 dev->name, dev); 931 if (retval) { 932 netdev_err(dev, "unable to get IRQ %d\n", dev->irq); 933 return retval; 934 } 935 936 retval = au1000_init(dev); 937 if (retval) { 938 netdev_err(dev, "error in au1000_init\n"); 939 free_irq(dev->irq, dev); 940 return retval; 941 } 942 943 if (dev->phydev) 944 phy_start(dev->phydev); 945 946 netif_start_queue(dev); 947 948 netif_dbg(aup, drv, dev, "open: Initialization done.\n"); 949 950 return 0; 951 } 952 953 static int au1000_close(struct net_device *dev) 954 { 955 unsigned long flags; 956 struct au1000_private *const aup = netdev_priv(dev); 957 958 netif_dbg(aup, drv, dev, "close: dev=%p\n", dev); 959 960 if (dev->phydev) 961 phy_stop(dev->phydev); 962 963 spin_lock_irqsave(&aup->lock, flags); 964 965 au1000_reset_mac_unlocked(dev); 966 967 /* stop the device */ 968 netif_stop_queue(dev); 969 970 /* disable the interrupt */ 971 free_irq(dev->irq, dev); 972 spin_unlock_irqrestore(&aup->lock, flags); 973 974 return 0; 975 } 976 977 /* 978 * Au1000 transmit routine. 979 */ 980 static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) 981 { 982 struct au1000_private *aup = netdev_priv(dev); 983 struct net_device_stats *ps = &dev->stats; 984 struct tx_dma *ptxd; 985 u32 buff_stat; 986 struct db_dest *pDB; 987 int i; 988 989 netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n", 990 (unsigned)aup, skb->len, 991 skb->data, aup->tx_head); 992 993 ptxd = aup->tx_dma_ring[aup->tx_head]; 994 buff_stat = ptxd->buff_stat; 995 if (buff_stat & TX_DMA_ENABLE) { 996 /* We've wrapped around and the transmitter is still busy */ 997 netif_stop_queue(dev); 998 aup->tx_full = 1; 999 return NETDEV_TX_BUSY; 1000 } else if (buff_stat & TX_T_DONE) { 1001 au1000_update_tx_stats(dev, ptxd->status); 1002 ptxd->len = 0; 1003 } 1004 1005 if (aup->tx_full) { 1006 aup->tx_full = 0; 1007 netif_wake_queue(dev); 1008 } 1009 1010 pDB = aup->tx_db_inuse[aup->tx_head]; 1011 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); 1012 if (skb->len < ETH_ZLEN) { 1013 for (i = skb->len; i < ETH_ZLEN; i++) 1014 ((char *)pDB->vaddr)[i] = 0; 1015 1016 ptxd->len = ETH_ZLEN; 1017 } else 1018 ptxd->len = skb->len; 1019 1020 ps->tx_packets++; 1021 ps->tx_bytes += ptxd->len; 1022 1023 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE; 1024 wmb(); /* drain writebuffer */ 1025 dev_kfree_skb(skb); 1026 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1); 1027 return NETDEV_TX_OK; 1028 } 1029 1030 /* 1031 * The Tx ring has been full longer than the watchdog timeout 1032 * value. The transmitter must be hung? 1033 */ 1034 static void au1000_tx_timeout(struct net_device *dev) 1035 { 1036 netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev); 1037 au1000_reset_mac(dev); 1038 au1000_init(dev); 1039 netif_trans_update(dev); /* prevent tx timeout */ 1040 netif_wake_queue(dev); 1041 } 1042 1043 static void au1000_multicast_list(struct net_device *dev) 1044 { 1045 struct au1000_private *aup = netdev_priv(dev); 1046 u32 reg; 1047 1048 netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags); 1049 reg = readl(&aup->mac->control); 1050 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 1051 reg |= MAC_PROMISCUOUS; 1052 } else if ((dev->flags & IFF_ALLMULTI) || 1053 netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) { 1054 reg |= MAC_PASS_ALL_MULTI; 1055 reg &= ~MAC_PROMISCUOUS; 1056 netdev_info(dev, "Pass all multicast\n"); 1057 } else { 1058 struct netdev_hw_addr *ha; 1059 u32 mc_filter[2]; /* Multicast hash filter */ 1060 1061 mc_filter[1] = mc_filter[0] = 0; 1062 netdev_for_each_mc_addr(ha, dev) 1063 set_bit(ether_crc(ETH_ALEN, ha->addr)>>26, 1064 (long *)mc_filter); 1065 writel(mc_filter[1], &aup->mac->multi_hash_high); 1066 writel(mc_filter[0], &aup->mac->multi_hash_low); 1067 reg &= ~MAC_PROMISCUOUS; 1068 reg |= MAC_HASH_MODE; 1069 } 1070 writel(reg, &aup->mac->control); 1071 } 1072 1073 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1074 { 1075 if (!netif_running(dev)) 1076 return -EINVAL; 1077 1078 if (!dev->phydev) 1079 return -EINVAL; /* PHY not controllable */ 1080 1081 return phy_mii_ioctl(dev->phydev, rq, cmd); 1082 } 1083 1084 static const struct net_device_ops au1000_netdev_ops = { 1085 .ndo_open = au1000_open, 1086 .ndo_stop = au1000_close, 1087 .ndo_start_xmit = au1000_tx, 1088 .ndo_set_rx_mode = au1000_multicast_list, 1089 .ndo_do_ioctl = au1000_ioctl, 1090 .ndo_tx_timeout = au1000_tx_timeout, 1091 .ndo_set_mac_address = eth_mac_addr, 1092 .ndo_validate_addr = eth_validate_addr, 1093 }; 1094 1095 static int au1000_probe(struct platform_device *pdev) 1096 { 1097 struct au1000_private *aup = NULL; 1098 struct au1000_eth_platform_data *pd; 1099 struct net_device *dev = NULL; 1100 struct db_dest *pDB, *pDBfree; 1101 int irq, i, err = 0; 1102 struct resource *base, *macen, *macdma; 1103 1104 base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1105 if (!base) { 1106 dev_err(&pdev->dev, "failed to retrieve base register\n"); 1107 err = -ENODEV; 1108 goto out; 1109 } 1110 1111 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1112 if (!macen) { 1113 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n"); 1114 err = -ENODEV; 1115 goto out; 1116 } 1117 1118 irq = platform_get_irq(pdev, 0); 1119 if (irq < 0) { 1120 dev_err(&pdev->dev, "failed to retrieve IRQ\n"); 1121 err = -ENODEV; 1122 goto out; 1123 } 1124 1125 macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1126 if (!macdma) { 1127 dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n"); 1128 err = -ENODEV; 1129 goto out; 1130 } 1131 1132 if (!request_mem_region(base->start, resource_size(base), 1133 pdev->name)) { 1134 dev_err(&pdev->dev, "failed to request memory region for base registers\n"); 1135 err = -ENXIO; 1136 goto out; 1137 } 1138 1139 if (!request_mem_region(macen->start, resource_size(macen), 1140 pdev->name)) { 1141 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n"); 1142 err = -ENXIO; 1143 goto err_request; 1144 } 1145 1146 if (!request_mem_region(macdma->start, resource_size(macdma), 1147 pdev->name)) { 1148 dev_err(&pdev->dev, "failed to request MACDMA memory region\n"); 1149 err = -ENXIO; 1150 goto err_macdma; 1151 } 1152 1153 dev = alloc_etherdev(sizeof(struct au1000_private)); 1154 if (!dev) { 1155 err = -ENOMEM; 1156 goto err_alloc; 1157 } 1158 1159 SET_NETDEV_DEV(dev, &pdev->dev); 1160 platform_set_drvdata(pdev, dev); 1161 aup = netdev_priv(dev); 1162 1163 spin_lock_init(&aup->lock); 1164 aup->msg_enable = (au1000_debug < 4 ? 1165 AU1000_DEF_MSG_ENABLE : au1000_debug); 1166 1167 /* Allocate the data buffers 1168 * Snooping works fine with eth on all au1xxx 1169 */ 1170 aup->vaddr = (u32)dma_alloc_attrs(&pdev->dev, MAX_BUF_SIZE * 1171 (NUM_TX_BUFFS + NUM_RX_BUFFS), 1172 &aup->dma_addr, 0, 1173 DMA_ATTR_NON_CONSISTENT); 1174 if (!aup->vaddr) { 1175 dev_err(&pdev->dev, "failed to allocate data buffers\n"); 1176 err = -ENOMEM; 1177 goto err_vaddr; 1178 } 1179 1180 /* aup->mac is the base address of the MAC's registers */ 1181 aup->mac = (struct mac_reg *) 1182 ioremap_nocache(base->start, resource_size(base)); 1183 if (!aup->mac) { 1184 dev_err(&pdev->dev, "failed to ioremap MAC registers\n"); 1185 err = -ENXIO; 1186 goto err_remap1; 1187 } 1188 1189 /* Setup some variables for quick register address access */ 1190 aup->enable = (u32 *)ioremap_nocache(macen->start, 1191 resource_size(macen)); 1192 if (!aup->enable) { 1193 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n"); 1194 err = -ENXIO; 1195 goto err_remap2; 1196 } 1197 aup->mac_id = pdev->id; 1198 1199 aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma)); 1200 if (!aup->macdma) { 1201 dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n"); 1202 err = -ENXIO; 1203 goto err_remap3; 1204 } 1205 1206 au1000_setup_hw_rings(aup, aup->macdma); 1207 1208 writel(0, aup->enable); 1209 aup->mac_enabled = 0; 1210 1211 pd = dev_get_platdata(&pdev->dev); 1212 if (!pd) { 1213 dev_info(&pdev->dev, "no platform_data passed," 1214 " PHY search on MAC0\n"); 1215 aup->phy1_search_mac0 = 1; 1216 } else { 1217 if (is_valid_ether_addr(pd->mac)) { 1218 memcpy(dev->dev_addr, pd->mac, ETH_ALEN); 1219 } else { 1220 /* Set a random MAC since no valid provided by platform_data. */ 1221 eth_hw_addr_random(dev); 1222 } 1223 1224 aup->phy_static_config = pd->phy_static_config; 1225 aup->phy_search_highest_addr = pd->phy_search_highest_addr; 1226 aup->phy1_search_mac0 = pd->phy1_search_mac0; 1227 aup->phy_addr = pd->phy_addr; 1228 aup->phy_busid = pd->phy_busid; 1229 aup->phy_irq = pd->phy_irq; 1230 } 1231 1232 if (aup->phy_busid > 0) { 1233 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n"); 1234 err = -ENODEV; 1235 goto err_mdiobus_alloc; 1236 } 1237 1238 aup->mii_bus = mdiobus_alloc(); 1239 if (aup->mii_bus == NULL) { 1240 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n"); 1241 err = -ENOMEM; 1242 goto err_mdiobus_alloc; 1243 } 1244 1245 aup->mii_bus->priv = dev; 1246 aup->mii_bus->read = au1000_mdiobus_read; 1247 aup->mii_bus->write = au1000_mdiobus_write; 1248 aup->mii_bus->reset = au1000_mdiobus_reset; 1249 aup->mii_bus->name = "au1000_eth_mii"; 1250 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 1251 pdev->name, aup->mac_id); 1252 1253 /* if known, set corresponding PHY IRQs */ 1254 if (aup->phy_static_config) 1255 if (aup->phy_irq && aup->phy_busid == aup->mac_id) 1256 aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq; 1257 1258 err = mdiobus_register(aup->mii_bus); 1259 if (err) { 1260 dev_err(&pdev->dev, "failed to register MDIO bus\n"); 1261 goto err_mdiobus_reg; 1262 } 1263 1264 err = au1000_mii_probe(dev); 1265 if (err != 0) 1266 goto err_out; 1267 1268 pDBfree = NULL; 1269 /* setup the data buffer descriptors and attach a buffer to each one */ 1270 pDB = aup->db; 1271 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) { 1272 pDB->pnext = pDBfree; 1273 pDBfree = pDB; 1274 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i); 1275 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); 1276 pDB++; 1277 } 1278 aup->pDBfree = pDBfree; 1279 1280 err = -ENODEV; 1281 for (i = 0; i < NUM_RX_DMA; i++) { 1282 pDB = au1000_GetFreeDB(aup); 1283 if (!pDB) 1284 goto err_out; 1285 1286 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; 1287 aup->rx_db_inuse[i] = pDB; 1288 } 1289 1290 err = -ENODEV; 1291 for (i = 0; i < NUM_TX_DMA; i++) { 1292 pDB = au1000_GetFreeDB(aup); 1293 if (!pDB) 1294 goto err_out; 1295 1296 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr; 1297 aup->tx_dma_ring[i]->len = 0; 1298 aup->tx_db_inuse[i] = pDB; 1299 } 1300 1301 dev->base_addr = base->start; 1302 dev->irq = irq; 1303 dev->netdev_ops = &au1000_netdev_ops; 1304 dev->ethtool_ops = &au1000_ethtool_ops; 1305 dev->watchdog_timeo = ETH_TX_TIMEOUT; 1306 1307 /* 1308 * The boot code uses the ethernet controller, so reset it to start 1309 * fresh. au1000_init() expects that the device is in reset state. 1310 */ 1311 au1000_reset_mac(dev); 1312 1313 err = register_netdev(dev); 1314 if (err) { 1315 netdev_err(dev, "Cannot register net device, aborting.\n"); 1316 goto err_out; 1317 } 1318 1319 netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n", 1320 (unsigned long)base->start, irq); 1321 1322 pr_info_once("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR); 1323 1324 return 0; 1325 1326 err_out: 1327 if (aup->mii_bus != NULL) 1328 mdiobus_unregister(aup->mii_bus); 1329 1330 /* here we should have a valid dev plus aup-> register addresses 1331 * so we can reset the mac properly. 1332 */ 1333 au1000_reset_mac(dev); 1334 1335 for (i = 0; i < NUM_RX_DMA; i++) { 1336 if (aup->rx_db_inuse[i]) 1337 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); 1338 } 1339 for (i = 0; i < NUM_TX_DMA; i++) { 1340 if (aup->tx_db_inuse[i]) 1341 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); 1342 } 1343 err_mdiobus_reg: 1344 mdiobus_free(aup->mii_bus); 1345 err_mdiobus_alloc: 1346 iounmap(aup->macdma); 1347 err_remap3: 1348 iounmap(aup->enable); 1349 err_remap2: 1350 iounmap(aup->mac); 1351 err_remap1: 1352 dma_free_attrs(&pdev->dev, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), 1353 (void *)aup->vaddr, aup->dma_addr, 1354 DMA_ATTR_NON_CONSISTENT); 1355 err_vaddr: 1356 free_netdev(dev); 1357 err_alloc: 1358 release_mem_region(macdma->start, resource_size(macdma)); 1359 err_macdma: 1360 release_mem_region(macen->start, resource_size(macen)); 1361 err_request: 1362 release_mem_region(base->start, resource_size(base)); 1363 out: 1364 return err; 1365 } 1366 1367 static int au1000_remove(struct platform_device *pdev) 1368 { 1369 struct net_device *dev = platform_get_drvdata(pdev); 1370 struct au1000_private *aup = netdev_priv(dev); 1371 int i; 1372 struct resource *base, *macen; 1373 1374 unregister_netdev(dev); 1375 mdiobus_unregister(aup->mii_bus); 1376 mdiobus_free(aup->mii_bus); 1377 1378 for (i = 0; i < NUM_RX_DMA; i++) 1379 if (aup->rx_db_inuse[i]) 1380 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]); 1381 1382 for (i = 0; i < NUM_TX_DMA; i++) 1383 if (aup->tx_db_inuse[i]) 1384 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]); 1385 1386 dma_free_attrs(&pdev->dev, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), 1387 (void *)aup->vaddr, aup->dma_addr, 1388 DMA_ATTR_NON_CONSISTENT); 1389 1390 iounmap(aup->macdma); 1391 iounmap(aup->mac); 1392 iounmap(aup->enable); 1393 1394 base = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1395 release_mem_region(base->start, resource_size(base)); 1396 1397 base = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1398 release_mem_region(base->start, resource_size(base)); 1399 1400 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1401 release_mem_region(macen->start, resource_size(macen)); 1402 1403 free_netdev(dev); 1404 1405 return 0; 1406 } 1407 1408 static struct platform_driver au1000_eth_driver = { 1409 .probe = au1000_probe, 1410 .remove = au1000_remove, 1411 .driver = { 1412 .name = "au1000-eth", 1413 }, 1414 }; 1415 1416 module_platform_driver(au1000_eth_driver); 1417 1418 MODULE_ALIAS("platform:au1000-eth"); 1419