1 // SPDX-License-Identifier: GPL-2.0-or-later
2 
3 /* Advanced  Micro Devices Inc. AMD8111E Linux Network Driver
4  * Copyright (C) 2004 Advanced Micro Devices
5  *
6  * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
7  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
8  * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
9  * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
10  * Copyright 1993 United States Government as represented by the
11  *	Director, National Security Agency.[ pcnet32.c ]
12  * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
13  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
14  *
15 
16 Module Name:
17 
18 	amd8111e.c
19 
20 Abstract:
21 
22 	 AMD8111 based 10/100 Ethernet Controller Driver.
23 
24 Environment:
25 
26 	Kernel Mode
27 
28 Revision History:
29 	3.0.0
30 	   Initial Revision.
31 	3.0.1
32 	 1. Dynamic interrupt coalescing.
33 	 2. Removed prev_stats.
34 	 3. MII support.
35 	 4. Dynamic IPG support
36 	3.0.2  05/29/2003
37 	 1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
38 	 2. Bug fix: Fixed VLAN support failure.
39 	 3. Bug fix: Fixed receive interrupt coalescing bug.
40 	 4. Dynamic IPG support is disabled by default.
41 	3.0.3 06/05/2003
42 	 1. Bug fix: Fixed failure to close the interface if SMP is enabled.
43 	3.0.4 12/09/2003
44 	 1. Added set_mac_address routine for bonding driver support.
45 	 2. Tested the driver for bonding support
46 	 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
47 	    indicated to the h/w.
48 	 4. Modified amd8111e_rx() routine to receive all the received packets
49 	    in the first interrupt.
50 	 5. Bug fix: Corrected  rx_errors  reported in get_stats() function.
51 	3.0.5 03/22/2004
52 	 1. Added NAPI support
53 
54 */
55 
56 
57 #include <linux/module.h>
58 #include <linux/kernel.h>
59 #include <linux/types.h>
60 #include <linux/compiler.h>
61 #include <linux/delay.h>
62 #include <linux/interrupt.h>
63 #include <linux/ioport.h>
64 #include <linux/pci.h>
65 #include <linux/netdevice.h>
66 #include <linux/etherdevice.h>
67 #include <linux/skbuff.h>
68 #include <linux/ethtool.h>
69 #include <linux/mii.h>
70 #include <linux/if_vlan.h>
71 #include <linux/ctype.h>
72 #include <linux/crc32.h>
73 #include <linux/dma-mapping.h>
74 
75 #include <asm/io.h>
76 #include <asm/byteorder.h>
77 #include <linux/uaccess.h>
78 
79 #if IS_ENABLED(CONFIG_VLAN_8021Q)
80 #define AMD8111E_VLAN_TAG_USED 1
81 #else
82 #define AMD8111E_VLAN_TAG_USED 0
83 #endif
84 
85 #include "amd8111e.h"
86 #define MODULE_NAME	"amd8111e"
87 MODULE_AUTHOR("Advanced Micro Devices, Inc.");
88 MODULE_DESCRIPTION("AMD8111 based 10/100 Ethernet Controller.");
89 MODULE_LICENSE("GPL");
90 module_param_array(speed_duplex, int, NULL, 0);
91 MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotiate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
92 module_param_array(coalesce, bool, NULL, 0);
93 MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
94 module_param_array(dynamic_ipg, bool, NULL, 0);
95 MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
96 
97 /* This function will read the PHY registers. */
98 static int amd8111e_read_phy(struct amd8111e_priv *lp,
99 			     int phy_id, int reg, u32 *val)
100 {
101 	void __iomem *mmio = lp->mmio;
102 	unsigned int reg_val;
103 	unsigned int repeat = REPEAT_CNT;
104 
105 	reg_val = readl(mmio + PHY_ACCESS);
106 	while (reg_val & PHY_CMD_ACTIVE)
107 		reg_val = readl(mmio + PHY_ACCESS);
108 
109 	writel(PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
110 			   ((reg & 0x1f) << 16), mmio + PHY_ACCESS);
111 	do {
112 		reg_val = readl(mmio + PHY_ACCESS);
113 		udelay(30);  /* It takes 30 us to read/write data */
114 	} while (--repeat && (reg_val & PHY_CMD_ACTIVE));
115 	if (reg_val & PHY_RD_ERR)
116 		goto err_phy_read;
117 
118 	*val = reg_val & 0xffff;
119 	return 0;
120 err_phy_read:
121 	*val = 0;
122 	return -EINVAL;
123 
124 }
125 
126 /* This function will write into PHY registers. */
127 static int amd8111e_write_phy(struct amd8111e_priv *lp,
128 			      int phy_id, int reg, u32 val)
129 {
130 	unsigned int repeat = REPEAT_CNT;
131 	void __iomem *mmio = lp->mmio;
132 	unsigned int reg_val;
133 
134 	reg_val = readl(mmio + PHY_ACCESS);
135 	while (reg_val & PHY_CMD_ACTIVE)
136 		reg_val = readl(mmio + PHY_ACCESS);
137 
138 	writel(PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
139 			   ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
140 
141 	do {
142 		reg_val = readl(mmio + PHY_ACCESS);
143 		udelay(30);  /* It takes 30 us to read/write the data */
144 	} while (--repeat && (reg_val & PHY_CMD_ACTIVE));
145 
146 	if (reg_val & PHY_RD_ERR)
147 		goto err_phy_write;
148 
149 	return 0;
150 
151 err_phy_write:
152 	return -EINVAL;
153 
154 }
155 
156 /* This is the mii register read function provided to the mii interface. */
157 static int amd8111e_mdio_read(struct net_device *dev, int phy_id, int reg_num)
158 {
159 	struct amd8111e_priv *lp = netdev_priv(dev);
160 	unsigned int reg_val;
161 
162 	amd8111e_read_phy(lp, phy_id, reg_num, &reg_val);
163 	return reg_val;
164 
165 }
166 
167 /* This is the mii register write function provided to the mii interface. */
168 static void amd8111e_mdio_write(struct net_device *dev,
169 				int phy_id, int reg_num, int val)
170 {
171 	struct amd8111e_priv *lp = netdev_priv(dev);
172 
173 	amd8111e_write_phy(lp, phy_id, reg_num, val);
174 }
175 
176 /* This function will set PHY speed. During initialization sets
177  * the original speed to 100 full
178  */
179 static void amd8111e_set_ext_phy(struct net_device *dev)
180 {
181 	struct amd8111e_priv *lp = netdev_priv(dev);
182 	u32 bmcr, advert, tmp;
183 
184 	/* Determine mii register values to set the speed */
185 	advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
186 	tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
187 	switch (lp->ext_phy_option) {
188 
189 		default:
190 		case SPEED_AUTONEG: /* advertise all values */
191 			tmp |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
192 				ADVERTISE_100HALF | ADVERTISE_100FULL);
193 			break;
194 		case SPEED10_HALF:
195 			tmp |= ADVERTISE_10HALF;
196 			break;
197 		case SPEED10_FULL:
198 			tmp |= ADVERTISE_10FULL;
199 			break;
200 		case SPEED100_HALF:
201 			tmp |= ADVERTISE_100HALF;
202 			break;
203 		case SPEED100_FULL:
204 			tmp |= ADVERTISE_100FULL;
205 			break;
206 	}
207 
208 	if(advert != tmp)
209 		amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
210 	/* Restart auto negotiation */
211 	bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
212 	bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
213 	amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
214 
215 }
216 
217 /* This function will unmap skb->data space and will free
218  * all transmit and receive skbuffs.
219  */
220 static int amd8111e_free_skbs(struct net_device *dev)
221 {
222 	struct amd8111e_priv *lp = netdev_priv(dev);
223 	struct sk_buff *rx_skbuff;
224 	int i;
225 
226 	/* Freeing transmit skbs */
227 	for (i = 0; i < NUM_TX_BUFFERS; i++) {
228 		if (lp->tx_skbuff[i]) {
229 			dma_unmap_single(&lp->pci_dev->dev,
230 					 lp->tx_dma_addr[i],
231 					 lp->tx_skbuff[i]->len, DMA_TO_DEVICE);
232 			dev_kfree_skb(lp->tx_skbuff[i]);
233 			lp->tx_skbuff[i] = NULL;
234 			lp->tx_dma_addr[i] = 0;
235 		}
236 	}
237 	/* Freeing previously allocated receive buffers */
238 	for (i = 0; i < NUM_RX_BUFFERS; i++) {
239 		rx_skbuff = lp->rx_skbuff[i];
240 		if (rx_skbuff != NULL) {
241 			dma_unmap_single(&lp->pci_dev->dev,
242 					 lp->rx_dma_addr[i],
243 					 lp->rx_buff_len - 2, DMA_FROM_DEVICE);
244 			dev_kfree_skb(lp->rx_skbuff[i]);
245 			lp->rx_skbuff[i] = NULL;
246 			lp->rx_dma_addr[i] = 0;
247 		}
248 	}
249 
250 	return 0;
251 }
252 
253 /* This will set the receive buffer length corresponding
254  * to the mtu size of networkinterface.
255  */
256 static inline void amd8111e_set_rx_buff_len(struct net_device *dev)
257 {
258 	struct amd8111e_priv *lp = netdev_priv(dev);
259 	unsigned int mtu = dev->mtu;
260 
261 	if (mtu > ETH_DATA_LEN) {
262 		/* MTU + ethernet header + FCS
263 		 * + optional VLAN tag + skb reserve space 2
264 		 */
265 		lp->rx_buff_len = mtu + ETH_HLEN + 10;
266 		lp->options |= OPTION_JUMBO_ENABLE;
267 	} else {
268 		lp->rx_buff_len = PKT_BUFF_SZ;
269 		lp->options &= ~OPTION_JUMBO_ENABLE;
270 	}
271 }
272 
273 /* This function will free all the previously allocated buffers,
274  * determine new receive buffer length  and will allocate new receive buffers.
275  * This function also allocates and initializes both the transmitter
276  * and receive hardware descriptors.
277  */
278 static int amd8111e_init_ring(struct net_device *dev)
279 {
280 	struct amd8111e_priv *lp = netdev_priv(dev);
281 	int i;
282 
283 	lp->rx_idx = lp->tx_idx = 0;
284 	lp->tx_complete_idx = 0;
285 	lp->tx_ring_idx = 0;
286 
287 
288 	if (lp->opened)
289 		/* Free previously allocated transmit and receive skbs */
290 		amd8111e_free_skbs(dev);
291 
292 	else {
293 		/* allocate the tx and rx descriptors */
294 		lp->tx_ring = dma_alloc_coherent(&lp->pci_dev->dev,
295 			sizeof(struct amd8111e_tx_dr) * NUM_TX_RING_DR,
296 			&lp->tx_ring_dma_addr, GFP_ATOMIC);
297 		if (!lp->tx_ring)
298 			goto err_no_mem;
299 
300 		lp->rx_ring = dma_alloc_coherent(&lp->pci_dev->dev,
301 			sizeof(struct amd8111e_rx_dr) * NUM_RX_RING_DR,
302 			&lp->rx_ring_dma_addr, GFP_ATOMIC);
303 		if (!lp->rx_ring)
304 			goto err_free_tx_ring;
305 	}
306 
307 	/* Set new receive buff size */
308 	amd8111e_set_rx_buff_len(dev);
309 
310 	/* Allocating receive  skbs */
311 	for (i = 0; i < NUM_RX_BUFFERS; i++) {
312 
313 		lp->rx_skbuff[i] = netdev_alloc_skb(dev, lp->rx_buff_len);
314 		if (!lp->rx_skbuff[i]) {
315 			/* Release previos allocated skbs */
316 			for (--i; i >= 0; i--)
317 				dev_kfree_skb(lp->rx_skbuff[i]);
318 			goto err_free_rx_ring;
319 		}
320 		skb_reserve(lp->rx_skbuff[i], 2);
321 	}
322         /* Initilaizing receive descriptors */
323 	for (i = 0; i < NUM_RX_BUFFERS; i++) {
324 		lp->rx_dma_addr[i] = dma_map_single(&lp->pci_dev->dev,
325 						    lp->rx_skbuff[i]->data,
326 						    lp->rx_buff_len - 2,
327 						    DMA_FROM_DEVICE);
328 
329 		lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
330 		lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
331 		wmb();
332 		lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
333 	}
334 
335 	/* Initializing transmit descriptors */
336 	for (i = 0; i < NUM_TX_RING_DR; i++) {
337 		lp->tx_ring[i].buff_phy_addr = 0;
338 		lp->tx_ring[i].tx_flags = 0;
339 		lp->tx_ring[i].buff_count = 0;
340 	}
341 
342 	return 0;
343 
344 err_free_rx_ring:
345 
346 	dma_free_coherent(&lp->pci_dev->dev,
347 			  sizeof(struct amd8111e_rx_dr) * NUM_RX_RING_DR,
348 			  lp->rx_ring, lp->rx_ring_dma_addr);
349 
350 err_free_tx_ring:
351 
352 	dma_free_coherent(&lp->pci_dev->dev,
353 			  sizeof(struct amd8111e_tx_dr) * NUM_TX_RING_DR,
354 			  lp->tx_ring, lp->tx_ring_dma_addr);
355 
356 err_no_mem:
357 	return -ENOMEM;
358 }
359 
360 /* This function will set the interrupt coalescing according
361  * to the input arguments
362  */
363 static int amd8111e_set_coalesce(struct net_device *dev, enum coal_mode cmod)
364 {
365 	unsigned int timeout;
366 	unsigned int event_count;
367 
368 	struct amd8111e_priv *lp = netdev_priv(dev);
369 	void __iomem *mmio = lp->mmio;
370 	struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf;
371 
372 
373 	switch(cmod)
374 	{
375 		case RX_INTR_COAL :
376 			timeout = coal_conf->rx_timeout;
377 			event_count = coal_conf->rx_event_count;
378 			if (timeout > MAX_TIMEOUT ||
379 			    event_count > MAX_EVENT_COUNT)
380 				return -EINVAL;
381 
382 			timeout = timeout * DELAY_TIMER_CONV;
383 			writel(VAL0|STINTEN, mmio+INTEN0);
384 			writel((u32)DLY_INT_A_R0 | (event_count << 16) |
385 				timeout, mmio + DLY_INT_A);
386 			break;
387 
388 		case TX_INTR_COAL:
389 			timeout = coal_conf->tx_timeout;
390 			event_count = coal_conf->tx_event_count;
391 			if (timeout > MAX_TIMEOUT ||
392 			    event_count > MAX_EVENT_COUNT)
393 				return -EINVAL;
394 
395 
396 			timeout = timeout * DELAY_TIMER_CONV;
397 			writel(VAL0 | STINTEN, mmio + INTEN0);
398 			writel((u32)DLY_INT_B_T0 | (event_count << 16) |
399 				timeout, mmio + DLY_INT_B);
400 			break;
401 
402 		case DISABLE_COAL:
403 			writel(0, mmio + STVAL);
404 			writel(STINTEN, mmio + INTEN0);
405 			writel(0, mmio + DLY_INT_B);
406 			writel(0, mmio + DLY_INT_A);
407 			break;
408 		 case ENABLE_COAL:
409 		       /* Start the timer */
410 			writel((u32)SOFT_TIMER_FREQ, mmio + STVAL); /* 0.5 sec */
411 			writel(VAL0 | STINTEN, mmio + INTEN0);
412 			break;
413 		default:
414 			break;
415 
416    }
417 	return 0;
418 
419 }
420 
421 /* This function initializes the device registers  and starts the device. */
422 static int amd8111e_restart(struct net_device *dev)
423 {
424 	struct amd8111e_priv *lp = netdev_priv(dev);
425 	void __iomem *mmio = lp->mmio;
426 	int i, reg_val;
427 
428 	/* stop the chip */
429 	writel(RUN, mmio + CMD0);
430 
431 	if (amd8111e_init_ring(dev))
432 		return -ENOMEM;
433 
434 	/* enable the port manager and set auto negotiation always */
435 	writel((u32)VAL1 | EN_PMGR, mmio + CMD3);
436 	writel((u32)XPHYANE | XPHYRST, mmio + CTRL2);
437 
438 	amd8111e_set_ext_phy(dev);
439 
440 	/* set control registers */
441 	reg_val = readl(mmio + CTRL1);
442 	reg_val &= ~XMTSP_MASK;
443 	writel(reg_val | XMTSP_128 | CACHE_ALIGN, mmio + CTRL1);
444 
445 	/* enable interrupt */
446 	writel(APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
447 		APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
448 		SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
449 
450 	writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
451 
452 	/* initialize tx and rx ring base addresses */
453 	writel((u32)lp->tx_ring_dma_addr, mmio + XMT_RING_BASE_ADDR0);
454 	writel((u32)lp->rx_ring_dma_addr, mmio + RCV_RING_BASE_ADDR0);
455 
456 	writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
457 	writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
458 
459 	/* set default IPG to 96 */
460 	writew((u32)DEFAULT_IPG, mmio + IPG);
461 	writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
462 
463 	if (lp->options & OPTION_JUMBO_ENABLE) {
464 		writel((u32)VAL2|JUMBO, mmio + CMD3);
465 		/* Reset REX_UFLO */
466 		writel(REX_UFLO, mmio + CMD2);
467 		/* Should not set REX_UFLO for jumbo frames */
468 		writel(VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2);
469 	} else {
470 		writel(VAL0 | APAD_XMT | REX_RTRY | REX_UFLO, mmio + CMD2);
471 		writel((u32)JUMBO, mmio + CMD3);
472 	}
473 
474 #if AMD8111E_VLAN_TAG_USED
475 	writel((u32)VAL2 | VSIZE | VL_TAG_DEL, mmio + CMD3);
476 #endif
477 	writel(VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2);
478 
479 	/* Setting the MAC address to the device */
480 	for (i = 0; i < ETH_ALEN; i++)
481 		writeb(dev->dev_addr[i], mmio + PADR + i);
482 
483 	/* Enable interrupt coalesce */
484 	if (lp->options & OPTION_INTR_COAL_ENABLE) {
485 		netdev_info(dev, "Interrupt Coalescing Enabled.\n");
486 		amd8111e_set_coalesce(dev, ENABLE_COAL);
487 	}
488 
489 	/* set RUN bit to start the chip */
490 	writel(VAL2 | RDMD0, mmio + CMD0);
491 	writel(VAL0 | INTREN | RUN, mmio + CMD0);
492 
493 	/* To avoid PCI posting bug */
494 	readl(mmio+CMD0);
495 	return 0;
496 }
497 
498 /* This function clears necessary the device registers. */
499 static void amd8111e_init_hw_default(struct amd8111e_priv *lp)
500 {
501 	unsigned int reg_val;
502 	unsigned int logic_filter[2] = {0,};
503 	void __iomem *mmio = lp->mmio;
504 
505 
506 	/* stop the chip */
507 	writel(RUN, mmio + CMD0);
508 
509 	/* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
510 	writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
511 
512 	/* Clear RCV_RING_BASE_ADDR */
513 	writel(0, mmio + RCV_RING_BASE_ADDR0);
514 
515 	/* Clear XMT_RING_BASE_ADDR */
516 	writel(0, mmio + XMT_RING_BASE_ADDR0);
517 	writel(0, mmio + XMT_RING_BASE_ADDR1);
518 	writel(0, mmio + XMT_RING_BASE_ADDR2);
519 	writel(0, mmio + XMT_RING_BASE_ADDR3);
520 
521 	/* Clear CMD0  */
522 	writel(CMD0_CLEAR, mmio + CMD0);
523 
524 	/* Clear CMD2 */
525 	writel(CMD2_CLEAR, mmio + CMD2);
526 
527 	/* Clear CMD7 */
528 	writel(CMD7_CLEAR, mmio + CMD7);
529 
530 	/* Clear DLY_INT_A and DLY_INT_B */
531 	writel(0x0, mmio + DLY_INT_A);
532 	writel(0x0, mmio + DLY_INT_B);
533 
534 	/* Clear FLOW_CONTROL */
535 	writel(0x0, mmio + FLOW_CONTROL);
536 
537 	/* Clear INT0  write 1 to clear register */
538 	reg_val = readl(mmio + INT0);
539 	writel(reg_val, mmio + INT0);
540 
541 	/* Clear STVAL */
542 	writel(0x0, mmio + STVAL);
543 
544 	/* Clear INTEN0 */
545 	writel(INTEN0_CLEAR, mmio + INTEN0);
546 
547 	/* Clear LADRF */
548 	writel(0x0, mmio + LADRF);
549 
550 	/* Set SRAM_SIZE & SRAM_BOUNDARY registers  */
551 	writel(0x80010, mmio + SRAM_SIZE);
552 
553 	/* Clear RCV_RING0_LEN */
554 	writel(0x0, mmio + RCV_RING_LEN0);
555 
556 	/* Clear XMT_RING0/1/2/3_LEN */
557 	writel(0x0, mmio +  XMT_RING_LEN0);
558 	writel(0x0, mmio +  XMT_RING_LEN1);
559 	writel(0x0, mmio +  XMT_RING_LEN2);
560 	writel(0x0, mmio +  XMT_RING_LEN3);
561 
562 	/* Clear XMT_RING_LIMIT */
563 	writel(0x0, mmio + XMT_RING_LIMIT);
564 
565 	/* Clear MIB */
566 	writew(MIB_CLEAR, mmio + MIB_ADDR);
567 
568 	/* Clear LARF */
569 	amd8111e_writeq(*(u64 *)logic_filter, mmio + LADRF);
570 
571 	/* SRAM_SIZE register */
572 	reg_val = readl(mmio + SRAM_SIZE);
573 
574 	if (lp->options & OPTION_JUMBO_ENABLE)
575 		writel(VAL2 | JUMBO, mmio + CMD3);
576 #if AMD8111E_VLAN_TAG_USED
577 	writel(VAL2 | VSIZE | VL_TAG_DEL, mmio + CMD3);
578 #endif
579 	/* Set default value to CTRL1 Register */
580 	writel(CTRL1_DEFAULT, mmio + CTRL1);
581 
582 	/* To avoid PCI posting bug */
583 	readl(mmio + CMD2);
584 
585 }
586 
587 /* This function disables the interrupt and clears all the pending
588  * interrupts in INT0
589  */
590 static void amd8111e_disable_interrupt(struct amd8111e_priv *lp)
591 {
592 	u32 intr0;
593 
594 	/* Disable interrupt */
595 	writel(INTREN, lp->mmio + CMD0);
596 
597 	/* Clear INT0 */
598 	intr0 = readl(lp->mmio + INT0);
599 	writel(intr0, lp->mmio + INT0);
600 
601 	/* To avoid PCI posting bug */
602 	readl(lp->mmio + INT0);
603 
604 }
605 
606 /* This function stops the chip. */
607 static void amd8111e_stop_chip(struct amd8111e_priv *lp)
608 {
609 	writel(RUN, lp->mmio + CMD0);
610 
611 	/* To avoid PCI posting bug */
612 	readl(lp->mmio + CMD0);
613 }
614 
615 /* This function frees the  transmiter and receiver descriptor rings. */
616 static void amd8111e_free_ring(struct amd8111e_priv *lp)
617 {
618 	/* Free transmit and receive descriptor rings */
619 	if (lp->rx_ring) {
620 		dma_free_coherent(&lp->pci_dev->dev,
621 				  sizeof(struct amd8111e_rx_dr) * NUM_RX_RING_DR,
622 				  lp->rx_ring, lp->rx_ring_dma_addr);
623 		lp->rx_ring = NULL;
624 	}
625 
626 	if (lp->tx_ring) {
627 		dma_free_coherent(&lp->pci_dev->dev,
628 				  sizeof(struct amd8111e_tx_dr) * NUM_TX_RING_DR,
629 				  lp->tx_ring, lp->tx_ring_dma_addr);
630 
631 		lp->tx_ring = NULL;
632 	}
633 
634 }
635 
636 /* This function will free all the transmit skbs that are actually
637  * transmitted by the device. It will check the ownership of the
638  * skb before freeing the skb.
639  */
640 static int amd8111e_tx(struct net_device *dev)
641 {
642 	struct amd8111e_priv *lp = netdev_priv(dev);
643 	int tx_index;
644 	int status;
645 	/* Complete all the transmit packet */
646 	while (lp->tx_complete_idx != lp->tx_idx) {
647 		tx_index =  lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
648 		status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
649 
650 		if (status & OWN_BIT)
651 			break;	/* It still hasn't been Txed */
652 
653 		lp->tx_ring[tx_index].buff_phy_addr = 0;
654 
655 		/* We must free the original skb */
656 		if (lp->tx_skbuff[tx_index]) {
657 			dma_unmap_single(&lp->pci_dev->dev,
658 					 lp->tx_dma_addr[tx_index],
659 					 lp->tx_skbuff[tx_index]->len,
660 					 DMA_TO_DEVICE);
661 			dev_consume_skb_irq(lp->tx_skbuff[tx_index]);
662 			lp->tx_skbuff[tx_index] = NULL;
663 			lp->tx_dma_addr[tx_index] = 0;
664 		}
665 		lp->tx_complete_idx++;
666 		/*COAL update tx coalescing parameters */
667 		lp->coal_conf.tx_packets++;
668 		lp->coal_conf.tx_bytes +=
669 			le16_to_cpu(lp->tx_ring[tx_index].buff_count);
670 
671 		if (netif_queue_stopped(dev) &&
672 			lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS + 2) {
673 			/* The ring is no longer full, clear tbusy. */
674 			/* lp->tx_full = 0; */
675 			netif_wake_queue(dev);
676 		}
677 	}
678 	return 0;
679 }
680 
681 /* This function handles the driver receive operation in polling mode */
682 static int amd8111e_rx_poll(struct napi_struct *napi, int budget)
683 {
684 	struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi);
685 	struct net_device *dev = lp->amd8111e_net_dev;
686 	int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
687 	void __iomem *mmio = lp->mmio;
688 	struct sk_buff *skb, *new_skb;
689 	int min_pkt_len, status;
690 	int num_rx_pkt = 0;
691 	short pkt_len;
692 #if AMD8111E_VLAN_TAG_USED
693 	short vtag;
694 #endif
695 
696 	while (num_rx_pkt < budget) {
697 		status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
698 		if (status & OWN_BIT)
699 			break;
700 
701 		/* There is a tricky error noted by John Murphy,
702 		 * <murf@perftech.com> to Russ Nelson: Even with
703 		 * full-sized * buffers it's possible for a
704 		 * jabber packet to use two buffers, with only
705 		 * the last correctly noting the error.
706 		 */
707 		if (status & ERR_BIT) {
708 			/* resetting flags */
709 			lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
710 			goto err_next_pkt;
711 		}
712 		/* check for STP and ENP */
713 		if (!((status & STP_BIT) && (status & ENP_BIT))) {
714 			/* resetting flags */
715 			lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
716 			goto err_next_pkt;
717 		}
718 		pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
719 
720 #if AMD8111E_VLAN_TAG_USED
721 		vtag = status & TT_MASK;
722 		/* MAC will strip vlan tag */
723 		if (vtag != 0)
724 			min_pkt_len = MIN_PKT_LEN - 4;
725 			else
726 #endif
727 			min_pkt_len = MIN_PKT_LEN;
728 
729 		if (pkt_len < min_pkt_len) {
730 			lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
731 			lp->drv_rx_errors++;
732 			goto err_next_pkt;
733 		}
734 		new_skb = netdev_alloc_skb(dev, lp->rx_buff_len);
735 		if (!new_skb) {
736 			/* if allocation fail,
737 			 * ignore that pkt and go to next one
738 			 */
739 			lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
740 			lp->drv_rx_errors++;
741 			goto err_next_pkt;
742 		}
743 
744 		skb_reserve(new_skb, 2);
745 		skb = lp->rx_skbuff[rx_index];
746 		dma_unmap_single(&lp->pci_dev->dev, lp->rx_dma_addr[rx_index],
747 				 lp->rx_buff_len - 2, DMA_FROM_DEVICE);
748 		skb_put(skb, pkt_len);
749 		lp->rx_skbuff[rx_index] = new_skb;
750 		lp->rx_dma_addr[rx_index] = dma_map_single(&lp->pci_dev->dev,
751 							   new_skb->data,
752 							   lp->rx_buff_len - 2,
753 							   DMA_FROM_DEVICE);
754 
755 		skb->protocol = eth_type_trans(skb, dev);
756 
757 #if AMD8111E_VLAN_TAG_USED
758 		if (vtag == TT_VLAN_TAGGED) {
759 			u16 vlan_tag = le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info);
760 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
761 		}
762 #endif
763 		napi_gro_receive(napi, skb);
764 		/* COAL update rx coalescing parameters */
765 		lp->coal_conf.rx_packets++;
766 		lp->coal_conf.rx_bytes += pkt_len;
767 		num_rx_pkt++;
768 
769 err_next_pkt:
770 		lp->rx_ring[rx_index].buff_phy_addr
771 			= cpu_to_le32(lp->rx_dma_addr[rx_index]);
772 		lp->rx_ring[rx_index].buff_count =
773 			cpu_to_le16(lp->rx_buff_len-2);
774 		wmb();
775 		lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
776 		rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
777 	}
778 
779 	if (num_rx_pkt < budget && napi_complete_done(napi, num_rx_pkt)) {
780 		unsigned long flags;
781 
782 		/* Receive descriptor is empty now */
783 		spin_lock_irqsave(&lp->lock, flags);
784 		writel(VAL0|RINTEN0, mmio + INTEN0);
785 		writel(VAL2 | RDMD0, mmio + CMD0);
786 		spin_unlock_irqrestore(&lp->lock, flags);
787 	}
788 
789 	return num_rx_pkt;
790 }
791 
792 /* This function will indicate the link status to the kernel. */
793 static int amd8111e_link_change(struct net_device *dev)
794 {
795 	struct amd8111e_priv *lp = netdev_priv(dev);
796 	int status0, speed;
797 
798 	/* read the link change */
799 	status0 = readl(lp->mmio + STAT0);
800 
801 	if (status0 & LINK_STATS) {
802 		if (status0 & AUTONEG_COMPLETE)
803 			lp->link_config.autoneg = AUTONEG_ENABLE;
804 		else
805 			lp->link_config.autoneg = AUTONEG_DISABLE;
806 
807 		if (status0 & FULL_DPLX)
808 			lp->link_config.duplex = DUPLEX_FULL;
809 		else
810 			lp->link_config.duplex = DUPLEX_HALF;
811 		speed = (status0 & SPEED_MASK) >> 7;
812 		if (speed == PHY_SPEED_10)
813 			lp->link_config.speed = SPEED_10;
814 		else if (speed == PHY_SPEED_100)
815 			lp->link_config.speed = SPEED_100;
816 
817 		netdev_info(dev, "Link is Up. Speed is %s Mbps %s Duplex\n",
818 			    (lp->link_config.speed == SPEED_100) ?
819 							"100" : "10",
820 			    (lp->link_config.duplex == DUPLEX_FULL) ?
821 							"Full" : "Half");
822 
823 		netif_carrier_on(dev);
824 	} else {
825 		lp->link_config.speed = SPEED_INVALID;
826 		lp->link_config.duplex = DUPLEX_INVALID;
827 		lp->link_config.autoneg = AUTONEG_INVALID;
828 		netdev_info(dev, "Link is Down.\n");
829 		netif_carrier_off(dev);
830 	}
831 
832 	return 0;
833 }
834 
835 /* This function reads the mib counters. */
836 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
837 {
838 	unsigned int  status;
839 	unsigned  int data;
840 	unsigned int repeat = REPEAT_CNT;
841 
842 	writew(MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
843 	do {
844 		status = readw(mmio + MIB_ADDR);
845 		udelay(2);	/* controller takes MAX 2 us to get mib data */
846 	}
847 	while (--repeat && (status & MIB_CMD_ACTIVE));
848 
849 	data = readl(mmio + MIB_DATA);
850 	return data;
851 }
852 
853 /* This function reads the mib registers and returns the hardware statistics.
854  * It updates previous internal driver statistics with new values.
855  */
856 static struct net_device_stats *amd8111e_get_stats(struct net_device *dev)
857 {
858 	struct amd8111e_priv *lp = netdev_priv(dev);
859 	void __iomem *mmio = lp->mmio;
860 	unsigned long flags;
861 	struct net_device_stats *new_stats = &dev->stats;
862 
863 	if (!lp->opened)
864 		return new_stats;
865 	spin_lock_irqsave(&lp->lock, flags);
866 
867 	/* stats.rx_packets */
868 	new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
869 				amd8111e_read_mib(mmio, rcv_multicast_pkts)+
870 				amd8111e_read_mib(mmio, rcv_unicast_pkts);
871 
872 	/* stats.tx_packets */
873 	new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
874 
875 	/*stats.rx_bytes */
876 	new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
877 
878 	/* stats.tx_bytes */
879 	new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
880 
881 	/* stats.rx_errors */
882 	/* hw errors + errors driver reported */
883 	new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
884 				amd8111e_read_mib(mmio, rcv_fragments)+
885 				amd8111e_read_mib(mmio, rcv_jabbers)+
886 				amd8111e_read_mib(mmio, rcv_alignment_errors)+
887 				amd8111e_read_mib(mmio, rcv_fcs_errors)+
888 				amd8111e_read_mib(mmio, rcv_miss_pkts)+
889 				lp->drv_rx_errors;
890 
891 	/* stats.tx_errors */
892 	new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
893 
894 	/* stats.rx_dropped*/
895 	new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
896 
897 	/* stats.tx_dropped*/
898 	new_stats->tx_dropped = amd8111e_read_mib(mmio,  xmt_underrun_pkts);
899 
900 	/* stats.multicast*/
901 	new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
902 
903 	/* stats.collisions*/
904 	new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
905 
906 	/* stats.rx_length_errors*/
907 	new_stats->rx_length_errors =
908 		amd8111e_read_mib(mmio, rcv_undersize_pkts)+
909 		amd8111e_read_mib(mmio, rcv_oversize_pkts);
910 
911 	/* stats.rx_over_errors*/
912 	new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
913 
914 	/* stats.rx_crc_errors*/
915 	new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
916 
917 	/* stats.rx_frame_errors*/
918 	new_stats->rx_frame_errors =
919 		amd8111e_read_mib(mmio, rcv_alignment_errors);
920 
921 	/* stats.rx_fifo_errors */
922 	new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
923 
924 	/* stats.rx_missed_errors */
925 	new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
926 
927 	/* stats.tx_aborted_errors*/
928 	new_stats->tx_aborted_errors =
929 		amd8111e_read_mib(mmio, xmt_excessive_collision);
930 
931 	/* stats.tx_carrier_errors*/
932 	new_stats->tx_carrier_errors =
933 		amd8111e_read_mib(mmio, xmt_loss_carrier);
934 
935 	/* stats.tx_fifo_errors*/
936 	new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
937 
938 	/* stats.tx_window_errors*/
939 	new_stats->tx_window_errors =
940 		amd8111e_read_mib(mmio, xmt_late_collision);
941 
942 	/* Reset the mibs for collecting new statistics */
943 	/* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
944 
945 	spin_unlock_irqrestore(&lp->lock, flags);
946 
947 	return new_stats;
948 }
949 
950 /* This function recalculate the interrupt coalescing  mode on every interrupt
951  * according to the datarate and the packet rate.
952  */
953 static int amd8111e_calc_coalesce(struct net_device *dev)
954 {
955 	struct amd8111e_priv *lp = netdev_priv(dev);
956 	struct amd8111e_coalesce_conf *coal_conf = &lp->coal_conf;
957 	int tx_pkt_rate;
958 	int rx_pkt_rate;
959 	int tx_data_rate;
960 	int rx_data_rate;
961 	int rx_pkt_size;
962 	int tx_pkt_size;
963 
964 	tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
965 	coal_conf->tx_prev_packets =  coal_conf->tx_packets;
966 
967 	tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
968 	coal_conf->tx_prev_bytes =  coal_conf->tx_bytes;
969 
970 	rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
971 	coal_conf->rx_prev_packets =  coal_conf->rx_packets;
972 
973 	rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
974 	coal_conf->rx_prev_bytes =  coal_conf->rx_bytes;
975 
976 	if (rx_pkt_rate < 800) {
977 		if (coal_conf->rx_coal_type != NO_COALESCE) {
978 
979 			coal_conf->rx_timeout = 0x0;
980 			coal_conf->rx_event_count = 0;
981 			amd8111e_set_coalesce(dev, RX_INTR_COAL);
982 			coal_conf->rx_coal_type = NO_COALESCE;
983 		}
984 	} else {
985 
986 		rx_pkt_size = rx_data_rate/rx_pkt_rate;
987 		if (rx_pkt_size < 128) {
988 			if (coal_conf->rx_coal_type != NO_COALESCE) {
989 
990 				coal_conf->rx_timeout = 0;
991 				coal_conf->rx_event_count = 0;
992 				amd8111e_set_coalesce(dev, RX_INTR_COAL);
993 				coal_conf->rx_coal_type = NO_COALESCE;
994 			}
995 
996 		} else if ((rx_pkt_size >= 128) && (rx_pkt_size < 512)) {
997 
998 			if (coal_conf->rx_coal_type !=  LOW_COALESCE) {
999 				coal_conf->rx_timeout = 1;
1000 				coal_conf->rx_event_count = 4;
1001 				amd8111e_set_coalesce(dev, RX_INTR_COAL);
1002 				coal_conf->rx_coal_type = LOW_COALESCE;
1003 			}
1004 		} else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)) {
1005 
1006 			if (coal_conf->rx_coal_type != MEDIUM_COALESCE) {
1007 				coal_conf->rx_timeout = 1;
1008 				coal_conf->rx_event_count = 4;
1009 				amd8111e_set_coalesce(dev, RX_INTR_COAL);
1010 				coal_conf->rx_coal_type = MEDIUM_COALESCE;
1011 			}
1012 
1013 		} else if (rx_pkt_size >= 1024) {
1014 
1015 			if (coal_conf->rx_coal_type !=  HIGH_COALESCE) {
1016 				coal_conf->rx_timeout = 2;
1017 				coal_conf->rx_event_count = 3;
1018 				amd8111e_set_coalesce(dev, RX_INTR_COAL);
1019 				coal_conf->rx_coal_type = HIGH_COALESCE;
1020 			}
1021 		}
1022 	}
1023 	/* NOW FOR TX INTR COALESC */
1024 	if (tx_pkt_rate < 800) {
1025 		if (coal_conf->tx_coal_type != NO_COALESCE) {
1026 
1027 			coal_conf->tx_timeout = 0x0;
1028 			coal_conf->tx_event_count = 0;
1029 			amd8111e_set_coalesce(dev, TX_INTR_COAL);
1030 			coal_conf->tx_coal_type = NO_COALESCE;
1031 		}
1032 	} else {
1033 
1034 		tx_pkt_size = tx_data_rate/tx_pkt_rate;
1035 		if (tx_pkt_size < 128) {
1036 
1037 			if (coal_conf->tx_coal_type != NO_COALESCE) {
1038 
1039 				coal_conf->tx_timeout = 0;
1040 				coal_conf->tx_event_count = 0;
1041 				amd8111e_set_coalesce(dev, TX_INTR_COAL);
1042 				coal_conf->tx_coal_type = NO_COALESCE;
1043 			}
1044 
1045 		} else if ((tx_pkt_size >= 128) && (tx_pkt_size < 512)) {
1046 
1047 			if (coal_conf->tx_coal_type != LOW_COALESCE) {
1048 				coal_conf->tx_timeout = 1;
1049 				coal_conf->tx_event_count = 2;
1050 				amd8111e_set_coalesce(dev, TX_INTR_COAL);
1051 				coal_conf->tx_coal_type = LOW_COALESCE;
1052 
1053 			}
1054 		} else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)) {
1055 
1056 			if (coal_conf->tx_coal_type != MEDIUM_COALESCE) {
1057 				coal_conf->tx_timeout = 2;
1058 				coal_conf->tx_event_count = 5;
1059 				amd8111e_set_coalesce(dev, TX_INTR_COAL);
1060 				coal_conf->tx_coal_type = MEDIUM_COALESCE;
1061 			}
1062 		} else if (tx_pkt_size >= 1024) {
1063 			if (coal_conf->tx_coal_type != HIGH_COALESCE) {
1064 				coal_conf->tx_timeout = 4;
1065 				coal_conf->tx_event_count = 8;
1066 				amd8111e_set_coalesce(dev, TX_INTR_COAL);
1067 				coal_conf->tx_coal_type = HIGH_COALESCE;
1068 			}
1069 		}
1070 	}
1071 	return 0;
1072 
1073 }
1074 
1075 /* This is device interrupt function. It handles transmit,
1076  * receive,link change and hardware timer interrupts.
1077  */
1078 static irqreturn_t amd8111e_interrupt(int irq, void *dev_id)
1079 {
1080 
1081 	struct net_device *dev = (struct net_device *)dev_id;
1082 	struct amd8111e_priv *lp = netdev_priv(dev);
1083 	void __iomem *mmio = lp->mmio;
1084 	unsigned int intr0, intren0;
1085 	unsigned int handled = 1;
1086 
1087 	if (unlikely(dev == NULL))
1088 		return IRQ_NONE;
1089 
1090 	spin_lock(&lp->lock);
1091 
1092 	/* disabling interrupt */
1093 	writel(INTREN, mmio + CMD0);
1094 
1095 	/* Read interrupt status */
1096 	intr0 = readl(mmio + INT0);
1097 	intren0 = readl(mmio + INTEN0);
1098 
1099 	/* Process all the INT event until INTR bit is clear. */
1100 
1101 	if (!(intr0 & INTR)) {
1102 		handled = 0;
1103 		goto err_no_interrupt;
1104 	}
1105 
1106 	/* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1107 	writel(intr0, mmio + INT0);
1108 
1109 	/* Check if Receive Interrupt has occurred. */
1110 	if (intr0 & RINT0) {
1111 		if (napi_schedule_prep(&lp->napi)) {
1112 			/* Disable receive interupts */
1113 			writel(RINTEN0, mmio + INTEN0);
1114 			/* Schedule a polling routine */
1115 			__napi_schedule(&lp->napi);
1116 		} else if (intren0 & RINTEN0) {
1117 			netdev_dbg(dev, "************Driver bug! interrupt while in poll\n");
1118 			/* Fix by disable receive interrupts */
1119 			writel(RINTEN0, mmio + INTEN0);
1120 		}
1121 	}
1122 
1123 	/* Check if  Transmit Interrupt has occurred. */
1124 	if (intr0 & TINT0)
1125 		amd8111e_tx(dev);
1126 
1127 	/* Check if  Link Change Interrupt has occurred. */
1128 	if (intr0 & LCINT)
1129 		amd8111e_link_change(dev);
1130 
1131 	/* Check if Hardware Timer Interrupt has occurred. */
1132 	if (intr0 & STINT)
1133 		amd8111e_calc_coalesce(dev);
1134 
1135 err_no_interrupt:
1136 	writel(VAL0 | INTREN, mmio + CMD0);
1137 
1138 	spin_unlock(&lp->lock);
1139 
1140 	return IRQ_RETVAL(handled);
1141 }
1142 
1143 #ifdef CONFIG_NET_POLL_CONTROLLER
1144 static void amd8111e_poll(struct net_device *dev)
1145 {
1146 	unsigned long flags;
1147 	local_irq_save(flags);
1148 	amd8111e_interrupt(0, dev);
1149 	local_irq_restore(flags);
1150 }
1151 #endif
1152 
1153 
1154 /* This function closes the network interface and updates
1155  * the statistics so that most recent statistics will be
1156  * available after the interface is down.
1157  */
1158 static int amd8111e_close(struct net_device *dev)
1159 {
1160 	struct amd8111e_priv *lp = netdev_priv(dev);
1161 	netif_stop_queue(dev);
1162 
1163 	napi_disable(&lp->napi);
1164 
1165 	spin_lock_irq(&lp->lock);
1166 
1167 	amd8111e_disable_interrupt(lp);
1168 	amd8111e_stop_chip(lp);
1169 
1170 	/* Free transmit and receive skbs */
1171 	amd8111e_free_skbs(lp->amd8111e_net_dev);
1172 
1173 	netif_carrier_off(lp->amd8111e_net_dev);
1174 
1175 	/* Delete ipg timer */
1176 	if (lp->options & OPTION_DYN_IPG_ENABLE)
1177 		del_timer_sync(&lp->ipg_data.ipg_timer);
1178 
1179 	spin_unlock_irq(&lp->lock);
1180 	free_irq(dev->irq, dev);
1181 	amd8111e_free_ring(lp);
1182 
1183 	/* Update the statistics before closing */
1184 	amd8111e_get_stats(dev);
1185 	lp->opened = 0;
1186 	return 0;
1187 }
1188 
1189 /* This function opens new interface.It requests irq for the device,
1190  * initializes the device,buffers and descriptors, and starts the device.
1191  */
1192 static int amd8111e_open(struct net_device *dev)
1193 {
1194 	struct amd8111e_priv *lp = netdev_priv(dev);
1195 
1196 	if (dev->irq == 0 || request_irq(dev->irq, amd8111e_interrupt,
1197 					 IRQF_SHARED, dev->name, dev))
1198 		return -EAGAIN;
1199 
1200 	napi_enable(&lp->napi);
1201 
1202 	spin_lock_irq(&lp->lock);
1203 
1204 	amd8111e_init_hw_default(lp);
1205 
1206 	if (amd8111e_restart(dev)) {
1207 		spin_unlock_irq(&lp->lock);
1208 		napi_disable(&lp->napi);
1209 		if (dev->irq)
1210 			free_irq(dev->irq, dev);
1211 		return -ENOMEM;
1212 	}
1213 	/* Start ipg timer */
1214 	if (lp->options & OPTION_DYN_IPG_ENABLE) {
1215 		add_timer(&lp->ipg_data.ipg_timer);
1216 		netdev_info(dev, "Dynamic IPG Enabled\n");
1217 	}
1218 
1219 	lp->opened = 1;
1220 
1221 	spin_unlock_irq(&lp->lock);
1222 
1223 	netif_start_queue(dev);
1224 
1225 	return 0;
1226 }
1227 
1228 /* This function checks if there is any transmit  descriptors
1229  * available to queue more packet.
1230  */
1231 static int amd8111e_tx_queue_avail(struct amd8111e_priv *lp)
1232 {
1233 	int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1234 	if (lp->tx_skbuff[tx_index])
1235 		return -1;
1236 	else
1237 		return 0;
1238 
1239 }
1240 
1241 /* This function will queue the transmit packets to the
1242  * descriptors and will trigger the send operation. It also
1243  * initializes the transmit descriptors with buffer physical address,
1244  * byte count, ownership to hardware etc.
1245  */
1246 static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb,
1247 				       struct net_device *dev)
1248 {
1249 	struct amd8111e_priv *lp = netdev_priv(dev);
1250 	int tx_index;
1251 	unsigned long flags;
1252 
1253 	spin_lock_irqsave(&lp->lock, flags);
1254 
1255 	tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1256 
1257 	lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1258 
1259 	lp->tx_skbuff[tx_index] = skb;
1260 	lp->tx_ring[tx_index].tx_flags = 0;
1261 
1262 #if AMD8111E_VLAN_TAG_USED
1263 	if (skb_vlan_tag_present(skb)) {
1264 		lp->tx_ring[tx_index].tag_ctrl_cmd |=
1265 				cpu_to_le16(TCC_VLAN_INSERT);
1266 		lp->tx_ring[tx_index].tag_ctrl_info =
1267 				cpu_to_le16(skb_vlan_tag_get(skb));
1268 
1269 	}
1270 #endif
1271 	lp->tx_dma_addr[tx_index] =
1272 	    dma_map_single(&lp->pci_dev->dev, skb->data, skb->len,
1273 			   DMA_TO_DEVICE);
1274 	lp->tx_ring[tx_index].buff_phy_addr =
1275 	    cpu_to_le32(lp->tx_dma_addr[tx_index]);
1276 
1277 	/*  Set FCS and LTINT bits */
1278 	wmb();
1279 	lp->tx_ring[tx_index].tx_flags |=
1280 	    cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1281 
1282 	lp->tx_idx++;
1283 
1284 	/* Trigger an immediate send poll. */
1285 	writel(VAL1 | TDMD0, lp->mmio + CMD0);
1286 	writel(VAL2 | RDMD0, lp->mmio + CMD0);
1287 
1288 	if (amd8111e_tx_queue_avail(lp) < 0) {
1289 		netif_stop_queue(dev);
1290 	}
1291 	spin_unlock_irqrestore(&lp->lock, flags);
1292 	return NETDEV_TX_OK;
1293 }
1294 /* This function returns all the memory mapped registers of the device. */
1295 static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1296 {
1297 	void __iomem *mmio = lp->mmio;
1298 	/* Read only necessary registers */
1299 	buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1300 	buf[1] = readl(mmio + XMT_RING_LEN0);
1301 	buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1302 	buf[3] = readl(mmio + RCV_RING_LEN0);
1303 	buf[4] = readl(mmio + CMD0);
1304 	buf[5] = readl(mmio + CMD2);
1305 	buf[6] = readl(mmio + CMD3);
1306 	buf[7] = readl(mmio + CMD7);
1307 	buf[8] = readl(mmio + INT0);
1308 	buf[9] = readl(mmio + INTEN0);
1309 	buf[10] = readl(mmio + LADRF);
1310 	buf[11] = readl(mmio + LADRF+4);
1311 	buf[12] = readl(mmio + STAT0);
1312 }
1313 
1314 
1315 /* This function sets promiscuos mode, all-multi mode or the multicast address
1316  * list to the device.
1317  */
1318 static void amd8111e_set_multicast_list(struct net_device *dev)
1319 {
1320 	struct netdev_hw_addr *ha;
1321 	struct amd8111e_priv *lp = netdev_priv(dev);
1322 	u32 mc_filter[2];
1323 	int bit_num;
1324 
1325 	if (dev->flags & IFF_PROMISC) {
1326 		writel(VAL2 | PROM, lp->mmio + CMD2);
1327 		return;
1328 	}
1329 	else
1330 		writel(PROM, lp->mmio + CMD2);
1331 	if (dev->flags & IFF_ALLMULTI ||
1332 	    netdev_mc_count(dev) > MAX_FILTER_SIZE) {
1333 		/* get all multicast packet */
1334 		mc_filter[1] = mc_filter[0] = 0xffffffff;
1335 		lp->options |= OPTION_MULTICAST_ENABLE;
1336 		amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1337 		return;
1338 	}
1339 	if (netdev_mc_empty(dev)) {
1340 		/* get only own packets */
1341 		mc_filter[1] = mc_filter[0] = 0;
1342 		lp->options &= ~OPTION_MULTICAST_ENABLE;
1343 		amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1344 		/* disable promiscuous mode */
1345 		writel(PROM, lp->mmio + CMD2);
1346 		return;
1347 	}
1348 	/* load all the multicast addresses in the logic filter */
1349 	lp->options |= OPTION_MULTICAST_ENABLE;
1350 	mc_filter[1] = mc_filter[0] = 0;
1351 	netdev_for_each_mc_addr(ha, dev) {
1352 		bit_num = (ether_crc_le(ETH_ALEN, ha->addr) >> 26) & 0x3f;
1353 		mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1354 	}
1355 	amd8111e_writeq(*(u64 *)mc_filter, lp->mmio + LADRF);
1356 
1357 	/* To eliminate PCI posting bug */
1358 	readl(lp->mmio + CMD2);
1359 
1360 }
1361 
1362 static void amd8111e_get_drvinfo(struct net_device *dev,
1363 				 struct ethtool_drvinfo *info)
1364 {
1365 	struct amd8111e_priv *lp = netdev_priv(dev);
1366 	struct pci_dev *pci_dev = lp->pci_dev;
1367 	strlcpy(info->driver, MODULE_NAME, sizeof(info->driver));
1368 	snprintf(info->fw_version, sizeof(info->fw_version),
1369 		"%u", chip_version);
1370 	strlcpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info));
1371 }
1372 
1373 static int amd8111e_get_regs_len(struct net_device *dev)
1374 {
1375 	return AMD8111E_REG_DUMP_LEN;
1376 }
1377 
1378 static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1379 {
1380 	struct amd8111e_priv *lp = netdev_priv(dev);
1381 	regs->version = 0;
1382 	amd8111e_read_regs(lp, buf);
1383 }
1384 
1385 static int amd8111e_get_link_ksettings(struct net_device *dev,
1386 				       struct ethtool_link_ksettings *cmd)
1387 {
1388 	struct amd8111e_priv *lp = netdev_priv(dev);
1389 	spin_lock_irq(&lp->lock);
1390 	mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
1391 	spin_unlock_irq(&lp->lock);
1392 	return 0;
1393 }
1394 
1395 static int amd8111e_set_link_ksettings(struct net_device *dev,
1396 				       const struct ethtool_link_ksettings *cmd)
1397 {
1398 	struct amd8111e_priv *lp = netdev_priv(dev);
1399 	int res;
1400 	spin_lock_irq(&lp->lock);
1401 	res = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
1402 	spin_unlock_irq(&lp->lock);
1403 	return res;
1404 }
1405 
1406 static int amd8111e_nway_reset(struct net_device *dev)
1407 {
1408 	struct amd8111e_priv *lp = netdev_priv(dev);
1409 	return mii_nway_restart(&lp->mii_if);
1410 }
1411 
1412 static u32 amd8111e_get_link(struct net_device *dev)
1413 {
1414 	struct amd8111e_priv *lp = netdev_priv(dev);
1415 	return mii_link_ok(&lp->mii_if);
1416 }
1417 
1418 static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1419 {
1420 	struct amd8111e_priv *lp = netdev_priv(dev);
1421 	wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1422 	if (lp->options & OPTION_WOL_ENABLE)
1423 		wol_info->wolopts = WAKE_MAGIC;
1424 }
1425 
1426 static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1427 {
1428 	struct amd8111e_priv *lp = netdev_priv(dev);
1429 	if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1430 		return -EINVAL;
1431 	spin_lock_irq(&lp->lock);
1432 	if (wol_info->wolopts & WAKE_MAGIC)
1433 		lp->options |=
1434 			(OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1435 	else if (wol_info->wolopts & WAKE_PHY)
1436 		lp->options |=
1437 			(OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1438 	else
1439 		lp->options &= ~OPTION_WOL_ENABLE;
1440 	spin_unlock_irq(&lp->lock);
1441 	return 0;
1442 }
1443 
1444 static const struct ethtool_ops ops = {
1445 	.get_drvinfo = amd8111e_get_drvinfo,
1446 	.get_regs_len = amd8111e_get_regs_len,
1447 	.get_regs = amd8111e_get_regs,
1448 	.nway_reset = amd8111e_nway_reset,
1449 	.get_link = amd8111e_get_link,
1450 	.get_wol = amd8111e_get_wol,
1451 	.set_wol = amd8111e_set_wol,
1452 	.get_link_ksettings = amd8111e_get_link_ksettings,
1453 	.set_link_ksettings = amd8111e_set_link_ksettings,
1454 };
1455 
1456 /* This function handles all the  ethtool ioctls. It gives driver info,
1457  * gets/sets driver speed, gets memory mapped register values, forces
1458  * auto negotiation, sets/gets WOL options for ethtool application.
1459  */
1460 static int amd8111e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1461 {
1462 	struct mii_ioctl_data *data = if_mii(ifr);
1463 	struct amd8111e_priv *lp = netdev_priv(dev);
1464 	int err;
1465 	u32 mii_regval;
1466 
1467 	switch (cmd) {
1468 	case SIOCGMIIPHY:
1469 		data->phy_id = lp->ext_phy_addr;
1470 
1471 		fallthrough;
1472 	case SIOCGMIIREG:
1473 
1474 		spin_lock_irq(&lp->lock);
1475 		err = amd8111e_read_phy(lp, data->phy_id,
1476 			data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1477 		spin_unlock_irq(&lp->lock);
1478 
1479 		data->val_out = mii_regval;
1480 		return err;
1481 
1482 	case SIOCSMIIREG:
1483 
1484 		spin_lock_irq(&lp->lock);
1485 		err = amd8111e_write_phy(lp, data->phy_id,
1486 			data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1487 		spin_unlock_irq(&lp->lock);
1488 
1489 		return err;
1490 
1491 	default:
1492 		/* do nothing */
1493 		break;
1494 	}
1495 	return -EOPNOTSUPP;
1496 }
1497 static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1498 {
1499 	struct amd8111e_priv *lp = netdev_priv(dev);
1500 	int i;
1501 	struct sockaddr *addr = p;
1502 
1503 	eth_hw_addr_set(dev, addr->sa_data);
1504 	spin_lock_irq(&lp->lock);
1505 	/* Setting the MAC address to the device */
1506 	for (i = 0; i < ETH_ALEN; i++)
1507 		writeb(dev->dev_addr[i], lp->mmio + PADR + i);
1508 
1509 	spin_unlock_irq(&lp->lock);
1510 
1511 	return 0;
1512 }
1513 
1514 /* This function changes the mtu of the device. It restarts the device  to
1515  * initialize the descriptor with new receive buffers.
1516  */
1517 static int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1518 {
1519 	struct amd8111e_priv *lp = netdev_priv(dev);
1520 	int err;
1521 
1522 	if (!netif_running(dev)) {
1523 		/* new_mtu will be used
1524 		 * when device starts netxt time
1525 		 */
1526 		dev->mtu = new_mtu;
1527 		return 0;
1528 	}
1529 
1530 	spin_lock_irq(&lp->lock);
1531 
1532 	/* stop the chip */
1533 	writel(RUN, lp->mmio + CMD0);
1534 
1535 	dev->mtu = new_mtu;
1536 
1537 	err = amd8111e_restart(dev);
1538 	spin_unlock_irq(&lp->lock);
1539 	if (!err)
1540 		netif_start_queue(dev);
1541 	return err;
1542 }
1543 
1544 static int amd8111e_enable_magicpkt(struct amd8111e_priv *lp)
1545 {
1546 	writel(VAL1 | MPPLBA, lp->mmio + CMD3);
1547 	writel(VAL0 | MPEN_SW, lp->mmio + CMD7);
1548 
1549 	/* To eliminate PCI posting bug */
1550 	readl(lp->mmio + CMD7);
1551 	return 0;
1552 }
1553 
1554 static int amd8111e_enable_link_change(struct amd8111e_priv *lp)
1555 {
1556 
1557 	/* Adapter is already stoped/suspended/interrupt-disabled */
1558 	writel(VAL0 | LCMODE_SW, lp->mmio + CMD7);
1559 
1560 	/* To eliminate PCI posting bug */
1561 	readl(lp->mmio + CMD7);
1562 	return 0;
1563 }
1564 
1565 /* This function is called when a packet transmission fails to complete
1566  * within a reasonable period, on the assumption that an interrupt have
1567  * failed or the interface is locked up. This function will reinitialize
1568  * the hardware.
1569  */
1570 static void amd8111e_tx_timeout(struct net_device *dev, unsigned int txqueue)
1571 {
1572 	struct amd8111e_priv *lp = netdev_priv(dev);
1573 	int err;
1574 
1575 	netdev_err(dev, "transmit timed out, resetting\n");
1576 
1577 	spin_lock_irq(&lp->lock);
1578 	err = amd8111e_restart(dev);
1579 	spin_unlock_irq(&lp->lock);
1580 	if (!err)
1581 		netif_wake_queue(dev);
1582 }
1583 
1584 static int __maybe_unused amd8111e_suspend(struct device *dev_d)
1585 {
1586 	struct net_device *dev = dev_get_drvdata(dev_d);
1587 	struct amd8111e_priv *lp = netdev_priv(dev);
1588 
1589 	if (!netif_running(dev))
1590 		return 0;
1591 
1592 	/* disable the interrupt */
1593 	spin_lock_irq(&lp->lock);
1594 	amd8111e_disable_interrupt(lp);
1595 	spin_unlock_irq(&lp->lock);
1596 
1597 	netif_device_detach(dev);
1598 
1599 	/* stop chip */
1600 	spin_lock_irq(&lp->lock);
1601 	if (lp->options & OPTION_DYN_IPG_ENABLE)
1602 		del_timer_sync(&lp->ipg_data.ipg_timer);
1603 	amd8111e_stop_chip(lp);
1604 	spin_unlock_irq(&lp->lock);
1605 
1606 	if (lp->options & OPTION_WOL_ENABLE) {
1607 		 /* enable wol */
1608 		if (lp->options & OPTION_WAKE_MAGIC_ENABLE)
1609 			amd8111e_enable_magicpkt(lp);
1610 		if (lp->options & OPTION_WAKE_PHY_ENABLE)
1611 			amd8111e_enable_link_change(lp);
1612 
1613 		device_set_wakeup_enable(dev_d, 1);
1614 
1615 	} else {
1616 		device_set_wakeup_enable(dev_d, 0);
1617 	}
1618 
1619 	return 0;
1620 }
1621 
1622 static int __maybe_unused amd8111e_resume(struct device *dev_d)
1623 {
1624 	struct net_device *dev = dev_get_drvdata(dev_d);
1625 	struct amd8111e_priv *lp = netdev_priv(dev);
1626 
1627 	if (!netif_running(dev))
1628 		return 0;
1629 
1630 	netif_device_attach(dev);
1631 
1632 	spin_lock_irq(&lp->lock);
1633 	amd8111e_restart(dev);
1634 	/* Restart ipg timer */
1635 	if (lp->options & OPTION_DYN_IPG_ENABLE)
1636 		mod_timer(&lp->ipg_data.ipg_timer,
1637 				jiffies + IPG_CONVERGE_JIFFIES);
1638 	spin_unlock_irq(&lp->lock);
1639 
1640 	return 0;
1641 }
1642 
1643 static void amd8111e_config_ipg(struct timer_list *t)
1644 {
1645 	struct amd8111e_priv *lp = from_timer(lp, t, ipg_data.ipg_timer);
1646 	struct ipg_info *ipg_data = &lp->ipg_data;
1647 	void __iomem *mmio = lp->mmio;
1648 	unsigned int prev_col_cnt = ipg_data->col_cnt;
1649 	unsigned int total_col_cnt;
1650 	unsigned int tmp_ipg;
1651 
1652 	if (lp->link_config.duplex == DUPLEX_FULL) {
1653 		ipg_data->ipg = DEFAULT_IPG;
1654 		return;
1655 	}
1656 
1657 	if (ipg_data->ipg_state == SSTATE) {
1658 
1659 		if (ipg_data->timer_tick == IPG_STABLE_TIME) {
1660 
1661 			ipg_data->timer_tick = 0;
1662 			ipg_data->ipg = MIN_IPG - IPG_STEP;
1663 			ipg_data->current_ipg = MIN_IPG;
1664 			ipg_data->diff_col_cnt = 0xFFFFFFFF;
1665 			ipg_data->ipg_state = CSTATE;
1666 		}
1667 		else
1668 			ipg_data->timer_tick++;
1669 	}
1670 
1671 	if (ipg_data->ipg_state == CSTATE) {
1672 
1673 		/* Get the current collision count */
1674 
1675 		total_col_cnt = ipg_data->col_cnt =
1676 				amd8111e_read_mib(mmio, xmt_collisions);
1677 
1678 		if ((total_col_cnt - prev_col_cnt) <
1679 				(ipg_data->diff_col_cnt)) {
1680 
1681 			ipg_data->diff_col_cnt =
1682 				total_col_cnt - prev_col_cnt;
1683 
1684 			ipg_data->ipg = ipg_data->current_ipg;
1685 		}
1686 
1687 		ipg_data->current_ipg += IPG_STEP;
1688 
1689 		if (ipg_data->current_ipg <= MAX_IPG)
1690 			tmp_ipg = ipg_data->current_ipg;
1691 		else {
1692 			tmp_ipg = ipg_data->ipg;
1693 			ipg_data->ipg_state = SSTATE;
1694 		}
1695 		writew((u32)tmp_ipg, mmio + IPG);
1696 		writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1697 	}
1698 	mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1699 	return;
1700 
1701 }
1702 
1703 static void amd8111e_probe_ext_phy(struct net_device *dev)
1704 {
1705 	struct amd8111e_priv *lp = netdev_priv(dev);
1706 	int i;
1707 
1708 	for (i = 0x1e; i >= 0; i--) {
1709 		u32 id1, id2;
1710 
1711 		if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1712 			continue;
1713 		if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1714 			continue;
1715 		lp->ext_phy_id = (id1 << 16) | id2;
1716 		lp->ext_phy_addr = i;
1717 		return;
1718 	}
1719 	lp->ext_phy_id = 0;
1720 	lp->ext_phy_addr = 1;
1721 }
1722 
1723 static const struct net_device_ops amd8111e_netdev_ops = {
1724 	.ndo_open		= amd8111e_open,
1725 	.ndo_stop		= amd8111e_close,
1726 	.ndo_start_xmit		= amd8111e_start_xmit,
1727 	.ndo_tx_timeout		= amd8111e_tx_timeout,
1728 	.ndo_get_stats		= amd8111e_get_stats,
1729 	.ndo_set_rx_mode	= amd8111e_set_multicast_list,
1730 	.ndo_validate_addr	= eth_validate_addr,
1731 	.ndo_set_mac_address	= amd8111e_set_mac_address,
1732 	.ndo_eth_ioctl		= amd8111e_ioctl,
1733 	.ndo_change_mtu		= amd8111e_change_mtu,
1734 #ifdef CONFIG_NET_POLL_CONTROLLER
1735 	.ndo_poll_controller	 = amd8111e_poll,
1736 #endif
1737 };
1738 
1739 static int amd8111e_probe_one(struct pci_dev *pdev,
1740 				  const struct pci_device_id *ent)
1741 {
1742 	int err, i;
1743 	unsigned long reg_addr, reg_len;
1744 	struct amd8111e_priv *lp;
1745 	struct net_device *dev;
1746 	u8 addr[ETH_ALEN];
1747 
1748 	err = pci_enable_device(pdev);
1749 	if (err) {
1750 		dev_err(&pdev->dev, "Cannot enable new PCI device\n");
1751 		return err;
1752 	}
1753 
1754 	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1755 		dev_err(&pdev->dev, "Cannot find PCI base address\n");
1756 		err = -ENODEV;
1757 		goto err_disable_pdev;
1758 	}
1759 
1760 	err = pci_request_regions(pdev, MODULE_NAME);
1761 	if (err) {
1762 		dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
1763 		goto err_disable_pdev;
1764 	}
1765 
1766 	pci_set_master(pdev);
1767 
1768 	/* Find power-management capability. */
1769 	if (!pdev->pm_cap) {
1770 		dev_err(&pdev->dev, "No Power Management capability\n");
1771 		err = -ENODEV;
1772 		goto err_free_reg;
1773 	}
1774 
1775 	/* Initialize DMA */
1776 	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) < 0) {
1777 		dev_err(&pdev->dev, "DMA not supported\n");
1778 		err = -ENODEV;
1779 		goto err_free_reg;
1780 	}
1781 
1782 	reg_addr = pci_resource_start(pdev, 0);
1783 	reg_len = pci_resource_len(pdev, 0);
1784 
1785 	dev = alloc_etherdev(sizeof(struct amd8111e_priv));
1786 	if (!dev) {
1787 		err = -ENOMEM;
1788 		goto err_free_reg;
1789 	}
1790 
1791 	SET_NETDEV_DEV(dev, &pdev->dev);
1792 
1793 #if AMD8111E_VLAN_TAG_USED
1794 	dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1795 #endif
1796 
1797 	lp = netdev_priv(dev);
1798 	lp->pci_dev = pdev;
1799 	lp->amd8111e_net_dev = dev;
1800 	lp->pm_cap = pdev->pm_cap;
1801 
1802 	spin_lock_init(&lp->lock);
1803 
1804 	lp->mmio = devm_ioremap(&pdev->dev, reg_addr, reg_len);
1805 	if (!lp->mmio) {
1806 		dev_err(&pdev->dev, "Cannot map device registers\n");
1807 		err = -ENOMEM;
1808 		goto err_free_dev;
1809 	}
1810 
1811 	/* Initializing MAC address */
1812 	for (i = 0; i < ETH_ALEN; i++)
1813 		addr[i] = readb(lp->mmio + PADR + i);
1814 	eth_hw_addr_set(dev, addr);
1815 
1816 	/* Setting user defined parametrs */
1817 	lp->ext_phy_option = speed_duplex[card_idx];
1818 	if (coalesce[card_idx])
1819 		lp->options |= OPTION_INTR_COAL_ENABLE;
1820 	if (dynamic_ipg[card_idx++])
1821 		lp->options |= OPTION_DYN_IPG_ENABLE;
1822 
1823 
1824 	/* Initialize driver entry points */
1825 	dev->netdev_ops = &amd8111e_netdev_ops;
1826 	dev->ethtool_ops = &ops;
1827 	dev->irq = pdev->irq;
1828 	dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
1829 	dev->min_mtu = AMD8111E_MIN_MTU;
1830 	dev->max_mtu = AMD8111E_MAX_MTU;
1831 	netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32);
1832 
1833 #if AMD8111E_VLAN_TAG_USED
1834 	dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
1835 #endif
1836 	/* Probe the external PHY */
1837 	amd8111e_probe_ext_phy(dev);
1838 
1839 	/* setting mii default values */
1840 	lp->mii_if.dev = dev;
1841 	lp->mii_if.mdio_read = amd8111e_mdio_read;
1842 	lp->mii_if.mdio_write = amd8111e_mdio_write;
1843 	lp->mii_if.phy_id = lp->ext_phy_addr;
1844 
1845 	/* Set receive buffer length and set jumbo option*/
1846 	amd8111e_set_rx_buff_len(dev);
1847 
1848 
1849 	err = register_netdev(dev);
1850 	if (err) {
1851 		dev_err(&pdev->dev, "Cannot register net device\n");
1852 		goto err_free_dev;
1853 	}
1854 
1855 	pci_set_drvdata(pdev, dev);
1856 
1857 	/* Initialize software ipg timer */
1858 	if (lp->options & OPTION_DYN_IPG_ENABLE) {
1859 		timer_setup(&lp->ipg_data.ipg_timer, amd8111e_config_ipg, 0);
1860 		lp->ipg_data.ipg_timer.expires = jiffies +
1861 						 IPG_CONVERGE_JIFFIES;
1862 		lp->ipg_data.ipg = DEFAULT_IPG;
1863 		lp->ipg_data.ipg_state = CSTATE;
1864 	}
1865 
1866 	/*  display driver and device information */
1867 	chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000) >> 28;
1868 	dev_info(&pdev->dev, "[ Rev %x ] PCI 10/100BaseT Ethernet %pM\n",
1869 		 chip_version, dev->dev_addr);
1870 	if (lp->ext_phy_id)
1871 		dev_info(&pdev->dev, "Found MII PHY ID 0x%08x at address 0x%02x\n",
1872 			 lp->ext_phy_id, lp->ext_phy_addr);
1873 	else
1874 		dev_info(&pdev->dev, "Couldn't detect MII PHY, assuming address 0x01\n");
1875 
1876 	return 0;
1877 
1878 err_free_dev:
1879 	free_netdev(dev);
1880 
1881 err_free_reg:
1882 	pci_release_regions(pdev);
1883 
1884 err_disable_pdev:
1885 	pci_disable_device(pdev);
1886 	return err;
1887 
1888 }
1889 
1890 static void amd8111e_remove_one(struct pci_dev *pdev)
1891 {
1892 	struct net_device *dev = pci_get_drvdata(pdev);
1893 
1894 	if (dev) {
1895 		unregister_netdev(dev);
1896 		free_netdev(dev);
1897 		pci_release_regions(pdev);
1898 		pci_disable_device(pdev);
1899 	}
1900 }
1901 
1902 static const struct pci_device_id amd8111e_pci_tbl[] = {
1903 	{
1904 	 .vendor = PCI_VENDOR_ID_AMD,
1905 	 .device = PCI_DEVICE_ID_AMD8111E_7462,
1906 	},
1907 	{
1908 	 .vendor = 0,
1909 	}
1910 };
1911 MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl);
1912 
1913 static SIMPLE_DEV_PM_OPS(amd8111e_pm_ops, amd8111e_suspend, amd8111e_resume);
1914 
1915 static struct pci_driver amd8111e_driver = {
1916 	.name		= MODULE_NAME,
1917 	.id_table	= amd8111e_pci_tbl,
1918 	.probe		= amd8111e_probe_one,
1919 	.remove		= amd8111e_remove_one,
1920 	.driver.pm	= &amd8111e_pm_ops
1921 };
1922 
1923 module_pci_driver(amd8111e_driver);
1924