1 2 /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver 3 * Copyright (C) 2004 Advanced Micro Devices 4 * 5 * 6 * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ] 7 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c] 8 * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ] 9 * Derived from the lance driver written 1993,1994,1995 by Donald Becker. 10 * Copyright 1993 United States Government as represented by the 11 * Director, National Security Agency.[ pcnet32.c ] 12 * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ] 13 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 14 * 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 29 * USA 30 31 Module Name: 32 33 amd8111e.c 34 35 Abstract: 36 37 AMD8111 based 10/100 Ethernet Controller Driver. 38 39 Environment: 40 41 Kernel Mode 42 43 Revision History: 44 3.0.0 45 Initial Revision. 46 3.0.1 47 1. Dynamic interrupt coalescing. 48 2. Removed prev_stats. 49 3. MII support. 50 4. Dynamic IPG support 51 3.0.2 05/29/2003 52 1. Bug fix: Fixed failure to send jumbo packets larger than 4k. 53 2. Bug fix: Fixed VLAN support failure. 54 3. Bug fix: Fixed receive interrupt coalescing bug. 55 4. Dynamic IPG support is disabled by default. 56 3.0.3 06/05/2003 57 1. Bug fix: Fixed failure to close the interface if SMP is enabled. 58 3.0.4 12/09/2003 59 1. Added set_mac_address routine for bonding driver support. 60 2. Tested the driver for bonding support 61 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth 62 indicated to the h/w. 63 4. Modified amd8111e_rx() routine to receive all the received packets 64 in the first interrupt. 65 5. Bug fix: Corrected rx_errors reported in get_stats() function. 66 3.0.5 03/22/2004 67 1. Added NAPI support 68 69 */ 70 71 72 #include <linux/module.h> 73 #include <linux/kernel.h> 74 #include <linux/types.h> 75 #include <linux/compiler.h> 76 #include <linux/delay.h> 77 #include <linux/init.h> 78 #include <linux/interrupt.h> 79 #include <linux/ioport.h> 80 #include <linux/pci.h> 81 #include <linux/netdevice.h> 82 #include <linux/etherdevice.h> 83 #include <linux/skbuff.h> 84 #include <linux/ethtool.h> 85 #include <linux/mii.h> 86 #include <linux/if_vlan.h> 87 #include <linux/ctype.h> 88 #include <linux/crc32.h> 89 #include <linux/dma-mapping.h> 90 91 #include <asm/system.h> 92 #include <asm/io.h> 93 #include <asm/byteorder.h> 94 #include <asm/uaccess.h> 95 96 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 97 #define AMD8111E_VLAN_TAG_USED 1 98 #else 99 #define AMD8111E_VLAN_TAG_USED 0 100 #endif 101 102 #include "amd8111e.h" 103 #define MODULE_NAME "amd8111e" 104 #define MODULE_VERS "3.0.7" 105 MODULE_AUTHOR("Advanced Micro Devices, Inc."); 106 MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS); 107 MODULE_LICENSE("GPL"); 108 MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl); 109 module_param_array(speed_duplex, int, NULL, 0); 110 MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotiate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex"); 111 module_param_array(coalesce, bool, NULL, 0); 112 MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable"); 113 module_param_array(dynamic_ipg, bool, NULL, 0); 114 MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable"); 115 116 static DEFINE_PCI_DEVICE_TABLE(amd8111e_pci_tbl) = { 117 118 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462, 119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 120 { 0, } 121 122 }; 123 /* 124 This function will read the PHY registers. 125 */ 126 static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val) 127 { 128 void __iomem *mmio = lp->mmio; 129 unsigned int reg_val; 130 unsigned int repeat= REPEAT_CNT; 131 132 reg_val = readl(mmio + PHY_ACCESS); 133 while (reg_val & PHY_CMD_ACTIVE) 134 reg_val = readl( mmio + PHY_ACCESS ); 135 136 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) | 137 ((reg & 0x1f) << 16), mmio +PHY_ACCESS); 138 do{ 139 reg_val = readl(mmio + PHY_ACCESS); 140 udelay(30); /* It takes 30 us to read/write data */ 141 } while (--repeat && (reg_val & PHY_CMD_ACTIVE)); 142 if(reg_val & PHY_RD_ERR) 143 goto err_phy_read; 144 145 *val = reg_val & 0xffff; 146 return 0; 147 err_phy_read: 148 *val = 0; 149 return -EINVAL; 150 151 } 152 153 /* 154 This function will write into PHY registers. 155 */ 156 static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val) 157 { 158 unsigned int repeat = REPEAT_CNT; 159 void __iomem *mmio = lp->mmio; 160 unsigned int reg_val; 161 162 reg_val = readl(mmio + PHY_ACCESS); 163 while (reg_val & PHY_CMD_ACTIVE) 164 reg_val = readl( mmio + PHY_ACCESS ); 165 166 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) | 167 ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); 168 169 do{ 170 reg_val = readl(mmio + PHY_ACCESS); 171 udelay(30); /* It takes 30 us to read/write the data */ 172 } while (--repeat && (reg_val & PHY_CMD_ACTIVE)); 173 174 if(reg_val & PHY_RD_ERR) 175 goto err_phy_write; 176 177 return 0; 178 179 err_phy_write: 180 return -EINVAL; 181 182 } 183 /* 184 This is the mii register read function provided to the mii interface. 185 */ 186 static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num) 187 { 188 struct amd8111e_priv* lp = netdev_priv(dev); 189 unsigned int reg_val; 190 191 amd8111e_read_phy(lp,phy_id,reg_num,®_val); 192 return reg_val; 193 194 } 195 196 /* 197 This is the mii register write function provided to the mii interface. 198 */ 199 static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val) 200 { 201 struct amd8111e_priv* lp = netdev_priv(dev); 202 203 amd8111e_write_phy(lp, phy_id, reg_num, val); 204 } 205 206 /* 207 This function will set PHY speed. During initialization sets the original speed to 100 full. 208 */ 209 static void amd8111e_set_ext_phy(struct net_device *dev) 210 { 211 struct amd8111e_priv *lp = netdev_priv(dev); 212 u32 bmcr,advert,tmp; 213 214 /* Determine mii register values to set the speed */ 215 advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE); 216 tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4); 217 switch (lp->ext_phy_option){ 218 219 default: 220 case SPEED_AUTONEG: /* advertise all values */ 221 tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL| 222 ADVERTISE_100HALF|ADVERTISE_100FULL) ; 223 break; 224 case SPEED10_HALF: 225 tmp |= ADVERTISE_10HALF; 226 break; 227 case SPEED10_FULL: 228 tmp |= ADVERTISE_10FULL; 229 break; 230 case SPEED100_HALF: 231 tmp |= ADVERTISE_100HALF; 232 break; 233 case SPEED100_FULL: 234 tmp |= ADVERTISE_100FULL; 235 break; 236 } 237 238 if(advert != tmp) 239 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp); 240 /* Restart auto negotiation */ 241 bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR); 242 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 243 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr); 244 245 } 246 247 /* 248 This function will unmap skb->data space and will free 249 all transmit and receive skbuffs. 250 */ 251 static int amd8111e_free_skbs(struct net_device *dev) 252 { 253 struct amd8111e_priv *lp = netdev_priv(dev); 254 struct sk_buff* rx_skbuff; 255 int i; 256 257 /* Freeing transmit skbs */ 258 for(i = 0; i < NUM_TX_BUFFERS; i++){ 259 if(lp->tx_skbuff[i]){ 260 pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE); 261 dev_kfree_skb (lp->tx_skbuff[i]); 262 lp->tx_skbuff[i] = NULL; 263 lp->tx_dma_addr[i] = 0; 264 } 265 } 266 /* Freeing previously allocated receive buffers */ 267 for (i = 0; i < NUM_RX_BUFFERS; i++){ 268 rx_skbuff = lp->rx_skbuff[i]; 269 if(rx_skbuff != NULL){ 270 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i], 271 lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE); 272 dev_kfree_skb(lp->rx_skbuff[i]); 273 lp->rx_skbuff[i] = NULL; 274 lp->rx_dma_addr[i] = 0; 275 } 276 } 277 278 return 0; 279 } 280 281 /* 282 This will set the receive buffer length corresponding to the mtu size of networkinterface. 283 */ 284 static inline void amd8111e_set_rx_buff_len(struct net_device* dev) 285 { 286 struct amd8111e_priv* lp = netdev_priv(dev); 287 unsigned int mtu = dev->mtu; 288 289 if (mtu > ETH_DATA_LEN){ 290 /* MTU + ethernet header + FCS 291 + optional VLAN tag + skb reserve space 2 */ 292 293 lp->rx_buff_len = mtu + ETH_HLEN + 10; 294 lp->options |= OPTION_JUMBO_ENABLE; 295 } else{ 296 lp->rx_buff_len = PKT_BUFF_SZ; 297 lp->options &= ~OPTION_JUMBO_ENABLE; 298 } 299 } 300 301 /* 302 This function will free all the previously allocated buffers, determine new receive buffer length and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors. 303 */ 304 static int amd8111e_init_ring(struct net_device *dev) 305 { 306 struct amd8111e_priv *lp = netdev_priv(dev); 307 int i; 308 309 lp->rx_idx = lp->tx_idx = 0; 310 lp->tx_complete_idx = 0; 311 lp->tx_ring_idx = 0; 312 313 314 if(lp->opened) 315 /* Free previously allocated transmit and receive skbs */ 316 amd8111e_free_skbs(dev); 317 318 else{ 319 /* allocate the tx and rx descriptors */ 320 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev, 321 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR, 322 &lp->tx_ring_dma_addr)) == NULL) 323 324 goto err_no_mem; 325 326 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev, 327 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR, 328 &lp->rx_ring_dma_addr)) == NULL) 329 330 goto err_free_tx_ring; 331 332 } 333 /* Set new receive buff size */ 334 amd8111e_set_rx_buff_len(dev); 335 336 /* Allocating receive skbs */ 337 for (i = 0; i < NUM_RX_BUFFERS; i++) { 338 339 lp->rx_skbuff[i] = netdev_alloc_skb(dev, lp->rx_buff_len); 340 if (!lp->rx_skbuff[i]) { 341 /* Release previos allocated skbs */ 342 for(--i; i >= 0 ;i--) 343 dev_kfree_skb(lp->rx_skbuff[i]); 344 goto err_free_rx_ring; 345 } 346 skb_reserve(lp->rx_skbuff[i],2); 347 } 348 /* Initilaizing receive descriptors */ 349 for (i = 0; i < NUM_RX_BUFFERS; i++) { 350 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, 351 lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE); 352 353 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]); 354 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2); 355 wmb(); 356 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT); 357 } 358 359 /* Initializing transmit descriptors */ 360 for (i = 0; i < NUM_TX_RING_DR; i++) { 361 lp->tx_ring[i].buff_phy_addr = 0; 362 lp->tx_ring[i].tx_flags = 0; 363 lp->tx_ring[i].buff_count = 0; 364 } 365 366 return 0; 367 368 err_free_rx_ring: 369 370 pci_free_consistent(lp->pci_dev, 371 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring, 372 lp->rx_ring_dma_addr); 373 374 err_free_tx_ring: 375 376 pci_free_consistent(lp->pci_dev, 377 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring, 378 lp->tx_ring_dma_addr); 379 380 err_no_mem: 381 return -ENOMEM; 382 } 383 /* This function will set the interrupt coalescing according to the input arguments */ 384 static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod) 385 { 386 unsigned int timeout; 387 unsigned int event_count; 388 389 struct amd8111e_priv *lp = netdev_priv(dev); 390 void __iomem *mmio = lp->mmio; 391 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf; 392 393 394 switch(cmod) 395 { 396 case RX_INTR_COAL : 397 timeout = coal_conf->rx_timeout; 398 event_count = coal_conf->rx_event_count; 399 if( timeout > MAX_TIMEOUT || 400 event_count > MAX_EVENT_COUNT ) 401 return -EINVAL; 402 403 timeout = timeout * DELAY_TIMER_CONV; 404 writel(VAL0|STINTEN, mmio+INTEN0); 405 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout, 406 mmio+DLY_INT_A); 407 break; 408 409 case TX_INTR_COAL : 410 timeout = coal_conf->tx_timeout; 411 event_count = coal_conf->tx_event_count; 412 if( timeout > MAX_TIMEOUT || 413 event_count > MAX_EVENT_COUNT ) 414 return -EINVAL; 415 416 417 timeout = timeout * DELAY_TIMER_CONV; 418 writel(VAL0|STINTEN,mmio+INTEN0); 419 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout, 420 mmio+DLY_INT_B); 421 break; 422 423 case DISABLE_COAL: 424 writel(0,mmio+STVAL); 425 writel(STINTEN, mmio+INTEN0); 426 writel(0, mmio +DLY_INT_B); 427 writel(0, mmio+DLY_INT_A); 428 break; 429 case ENABLE_COAL: 430 /* Start the timer */ 431 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */ 432 writel(VAL0|STINTEN, mmio+INTEN0); 433 break; 434 default: 435 break; 436 437 } 438 return 0; 439 440 } 441 442 /* 443 This function initializes the device registers and starts the device. 444 */ 445 static int amd8111e_restart(struct net_device *dev) 446 { 447 struct amd8111e_priv *lp = netdev_priv(dev); 448 void __iomem *mmio = lp->mmio; 449 int i,reg_val; 450 451 /* stop the chip */ 452 writel(RUN, mmio + CMD0); 453 454 if(amd8111e_init_ring(dev)) 455 return -ENOMEM; 456 457 /* enable the port manager and set auto negotiation always */ 458 writel((u32) VAL1|EN_PMGR, mmio + CMD3 ); 459 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2); 460 461 amd8111e_set_ext_phy(dev); 462 463 /* set control registers */ 464 reg_val = readl(mmio + CTRL1); 465 reg_val &= ~XMTSP_MASK; 466 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 ); 467 468 /* enable interrupt */ 469 writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN | 470 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN | 471 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0); 472 473 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0); 474 475 /* initialize tx and rx ring base addresses */ 476 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0); 477 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0); 478 479 writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0); 480 writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0); 481 482 /* set default IPG to 96 */ 483 writew((u32)DEFAULT_IPG,mmio+IPG); 484 writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1); 485 486 if(lp->options & OPTION_JUMBO_ENABLE){ 487 writel((u32)VAL2|JUMBO, mmio + CMD3); 488 /* Reset REX_UFLO */ 489 writel( REX_UFLO, mmio + CMD2); 490 /* Should not set REX_UFLO for jumbo frames */ 491 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2); 492 }else{ 493 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2); 494 writel((u32)JUMBO, mmio + CMD3); 495 } 496 497 #if AMD8111E_VLAN_TAG_USED 498 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3); 499 #endif 500 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 ); 501 502 /* Setting the MAC address to the device */ 503 for (i = 0; i < ETH_ALEN; i++) 504 writeb( dev->dev_addr[i], mmio + PADR + i ); 505 506 /* Enable interrupt coalesce */ 507 if(lp->options & OPTION_INTR_COAL_ENABLE){ 508 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n", 509 dev->name); 510 amd8111e_set_coalesce(dev,ENABLE_COAL); 511 } 512 513 /* set RUN bit to start the chip */ 514 writel(VAL2 | RDMD0, mmio + CMD0); 515 writel(VAL0 | INTREN | RUN, mmio + CMD0); 516 517 /* To avoid PCI posting bug */ 518 readl(mmio+CMD0); 519 return 0; 520 } 521 /* 522 This function clears necessary the device registers. 523 */ 524 static void amd8111e_init_hw_default( struct amd8111e_priv* lp) 525 { 526 unsigned int reg_val; 527 unsigned int logic_filter[2] ={0,}; 528 void __iomem *mmio = lp->mmio; 529 530 531 /* stop the chip */ 532 writel(RUN, mmio + CMD0); 533 534 /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */ 535 writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0); 536 537 /* Clear RCV_RING_BASE_ADDR */ 538 writel(0, mmio + RCV_RING_BASE_ADDR0); 539 540 /* Clear XMT_RING_BASE_ADDR */ 541 writel(0, mmio + XMT_RING_BASE_ADDR0); 542 writel(0, mmio + XMT_RING_BASE_ADDR1); 543 writel(0, mmio + XMT_RING_BASE_ADDR2); 544 writel(0, mmio + XMT_RING_BASE_ADDR3); 545 546 /* Clear CMD0 */ 547 writel(CMD0_CLEAR,mmio + CMD0); 548 549 /* Clear CMD2 */ 550 writel(CMD2_CLEAR, mmio +CMD2); 551 552 /* Clear CMD7 */ 553 writel(CMD7_CLEAR , mmio + CMD7); 554 555 /* Clear DLY_INT_A and DLY_INT_B */ 556 writel(0x0, mmio + DLY_INT_A); 557 writel(0x0, mmio + DLY_INT_B); 558 559 /* Clear FLOW_CONTROL */ 560 writel(0x0, mmio + FLOW_CONTROL); 561 562 /* Clear INT0 write 1 to clear register */ 563 reg_val = readl(mmio + INT0); 564 writel(reg_val, mmio + INT0); 565 566 /* Clear STVAL */ 567 writel(0x0, mmio + STVAL); 568 569 /* Clear INTEN0 */ 570 writel( INTEN0_CLEAR, mmio + INTEN0); 571 572 /* Clear LADRF */ 573 writel(0x0 , mmio + LADRF); 574 575 /* Set SRAM_SIZE & SRAM_BOUNDARY registers */ 576 writel( 0x80010,mmio + SRAM_SIZE); 577 578 /* Clear RCV_RING0_LEN */ 579 writel(0x0, mmio + RCV_RING_LEN0); 580 581 /* Clear XMT_RING0/1/2/3_LEN */ 582 writel(0x0, mmio + XMT_RING_LEN0); 583 writel(0x0, mmio + XMT_RING_LEN1); 584 writel(0x0, mmio + XMT_RING_LEN2); 585 writel(0x0, mmio + XMT_RING_LEN3); 586 587 /* Clear XMT_RING_LIMIT */ 588 writel(0x0, mmio + XMT_RING_LIMIT); 589 590 /* Clear MIB */ 591 writew(MIB_CLEAR, mmio + MIB_ADDR); 592 593 /* Clear LARF */ 594 amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF); 595 596 /* SRAM_SIZE register */ 597 reg_val = readl(mmio + SRAM_SIZE); 598 599 if(lp->options & OPTION_JUMBO_ENABLE) 600 writel( VAL2|JUMBO, mmio + CMD3); 601 #if AMD8111E_VLAN_TAG_USED 602 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 ); 603 #endif 604 /* Set default value to CTRL1 Register */ 605 writel(CTRL1_DEFAULT, mmio + CTRL1); 606 607 /* To avoid PCI posting bug */ 608 readl(mmio + CMD2); 609 610 } 611 612 /* 613 This function disables the interrupt and clears all the pending 614 interrupts in INT0 615 */ 616 static void amd8111e_disable_interrupt(struct amd8111e_priv* lp) 617 { 618 u32 intr0; 619 620 /* Disable interrupt */ 621 writel(INTREN, lp->mmio + CMD0); 622 623 /* Clear INT0 */ 624 intr0 = readl(lp->mmio + INT0); 625 writel(intr0, lp->mmio + INT0); 626 627 /* To avoid PCI posting bug */ 628 readl(lp->mmio + INT0); 629 630 } 631 632 /* 633 This function stops the chip. 634 */ 635 static void amd8111e_stop_chip(struct amd8111e_priv* lp) 636 { 637 writel(RUN, lp->mmio + CMD0); 638 639 /* To avoid PCI posting bug */ 640 readl(lp->mmio + CMD0); 641 } 642 643 /* 644 This function frees the transmiter and receiver descriptor rings. 645 */ 646 static void amd8111e_free_ring(struct amd8111e_priv* lp) 647 { 648 /* Free transmit and receive descriptor rings */ 649 if(lp->rx_ring){ 650 pci_free_consistent(lp->pci_dev, 651 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR, 652 lp->rx_ring, lp->rx_ring_dma_addr); 653 lp->rx_ring = NULL; 654 } 655 656 if(lp->tx_ring){ 657 pci_free_consistent(lp->pci_dev, 658 sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR, 659 lp->tx_ring, lp->tx_ring_dma_addr); 660 661 lp->tx_ring = NULL; 662 } 663 664 } 665 666 /* 667 This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb. 668 */ 669 static int amd8111e_tx(struct net_device *dev) 670 { 671 struct amd8111e_priv* lp = netdev_priv(dev); 672 int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK; 673 int status; 674 /* Complete all the transmit packet */ 675 while (lp->tx_complete_idx != lp->tx_idx){ 676 tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK; 677 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags); 678 679 if(status & OWN_BIT) 680 break; /* It still hasn't been Txed */ 681 682 lp->tx_ring[tx_index].buff_phy_addr = 0; 683 684 /* We must free the original skb */ 685 if (lp->tx_skbuff[tx_index]) { 686 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index], 687 lp->tx_skbuff[tx_index]->len, 688 PCI_DMA_TODEVICE); 689 dev_kfree_skb_irq (lp->tx_skbuff[tx_index]); 690 lp->tx_skbuff[tx_index] = NULL; 691 lp->tx_dma_addr[tx_index] = 0; 692 } 693 lp->tx_complete_idx++; 694 /*COAL update tx coalescing parameters */ 695 lp->coal_conf.tx_packets++; 696 lp->coal_conf.tx_bytes += 697 le16_to_cpu(lp->tx_ring[tx_index].buff_count); 698 699 if (netif_queue_stopped(dev) && 700 lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){ 701 /* The ring is no longer full, clear tbusy. */ 702 /* lp->tx_full = 0; */ 703 netif_wake_queue (dev); 704 } 705 } 706 return 0; 707 } 708 709 /* This function handles the driver receive operation in polling mode */ 710 static int amd8111e_rx_poll(struct napi_struct *napi, int budget) 711 { 712 struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi); 713 struct net_device *dev = lp->amd8111e_net_dev; 714 int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK; 715 void __iomem *mmio = lp->mmio; 716 struct sk_buff *skb,*new_skb; 717 int min_pkt_len, status; 718 unsigned int intr0; 719 int num_rx_pkt = 0; 720 short pkt_len; 721 #if AMD8111E_VLAN_TAG_USED 722 short vtag; 723 #endif 724 int rx_pkt_limit = budget; 725 unsigned long flags; 726 727 do{ 728 /* process receive packets until we use the quota*/ 729 /* If we own the next entry, it's a new packet. Send it up. */ 730 while(1) { 731 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags); 732 if (status & OWN_BIT) 733 break; 734 735 /* 736 * There is a tricky error noted by John Murphy, 737 * <murf@perftech.com> to Russ Nelson: Even with 738 * full-sized * buffers it's possible for a 739 * jabber packet to use two buffers, with only 740 * the last correctly noting the error. 741 */ 742 743 if(status & ERR_BIT) { 744 /* reseting flags */ 745 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; 746 goto err_next_pkt; 747 } 748 /* check for STP and ENP */ 749 if(!((status & STP_BIT) && (status & ENP_BIT))){ 750 /* reseting flags */ 751 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; 752 goto err_next_pkt; 753 } 754 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4; 755 756 #if AMD8111E_VLAN_TAG_USED 757 vtag = status & TT_MASK; 758 /*MAC will strip vlan tag*/ 759 if (vtag != 0) 760 min_pkt_len =MIN_PKT_LEN - 4; 761 else 762 #endif 763 min_pkt_len =MIN_PKT_LEN; 764 765 if (pkt_len < min_pkt_len) { 766 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; 767 lp->drv_rx_errors++; 768 goto err_next_pkt; 769 } 770 if(--rx_pkt_limit < 0) 771 goto rx_not_empty; 772 new_skb = netdev_alloc_skb(dev, lp->rx_buff_len); 773 if (!new_skb) { 774 /* if allocation fail, 775 ignore that pkt and go to next one */ 776 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; 777 lp->drv_rx_errors++; 778 goto err_next_pkt; 779 } 780 781 skb_reserve(new_skb, 2); 782 skb = lp->rx_skbuff[rx_index]; 783 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index], 784 lp->rx_buff_len-2, PCI_DMA_FROMDEVICE); 785 skb_put(skb, pkt_len); 786 lp->rx_skbuff[rx_index] = new_skb; 787 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev, 788 new_skb->data, 789 lp->rx_buff_len-2, 790 PCI_DMA_FROMDEVICE); 791 792 skb->protocol = eth_type_trans(skb, dev); 793 794 #if AMD8111E_VLAN_TAG_USED 795 if (vtag == TT_VLAN_TAGGED){ 796 u16 vlan_tag = le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info); 797 __vlan_hwaccel_put_tag(skb, vlan_tag); 798 } 799 #endif 800 netif_receive_skb(skb); 801 /*COAL update rx coalescing parameters*/ 802 lp->coal_conf.rx_packets++; 803 lp->coal_conf.rx_bytes += pkt_len; 804 num_rx_pkt++; 805 806 err_next_pkt: 807 lp->rx_ring[rx_index].buff_phy_addr 808 = cpu_to_le32(lp->rx_dma_addr[rx_index]); 809 lp->rx_ring[rx_index].buff_count = 810 cpu_to_le16(lp->rx_buff_len-2); 811 wmb(); 812 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT); 813 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK; 814 } 815 /* Check the interrupt status register for more packets in the 816 mean time. Process them since we have not used up our quota.*/ 817 818 intr0 = readl(mmio + INT0); 819 /*Ack receive packets */ 820 writel(intr0 & RINT0,mmio + INT0); 821 822 } while(intr0 & RINT0); 823 824 if (rx_pkt_limit > 0) { 825 /* Receive descriptor is empty now */ 826 spin_lock_irqsave(&lp->lock, flags); 827 __napi_complete(napi); 828 writel(VAL0|RINTEN0, mmio + INTEN0); 829 writel(VAL2 | RDMD0, mmio + CMD0); 830 spin_unlock_irqrestore(&lp->lock, flags); 831 } 832 833 rx_not_empty: 834 return num_rx_pkt; 835 } 836 837 /* 838 This function will indicate the link status to the kernel. 839 */ 840 static int amd8111e_link_change(struct net_device* dev) 841 { 842 struct amd8111e_priv *lp = netdev_priv(dev); 843 int status0,speed; 844 845 /* read the link change */ 846 status0 = readl(lp->mmio + STAT0); 847 848 if(status0 & LINK_STATS){ 849 if(status0 & AUTONEG_COMPLETE) 850 lp->link_config.autoneg = AUTONEG_ENABLE; 851 else 852 lp->link_config.autoneg = AUTONEG_DISABLE; 853 854 if(status0 & FULL_DPLX) 855 lp->link_config.duplex = DUPLEX_FULL; 856 else 857 lp->link_config.duplex = DUPLEX_HALF; 858 speed = (status0 & SPEED_MASK) >> 7; 859 if(speed == PHY_SPEED_10) 860 lp->link_config.speed = SPEED_10; 861 else if(speed == PHY_SPEED_100) 862 lp->link_config.speed = SPEED_100; 863 864 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n", dev->name, 865 (lp->link_config.speed == SPEED_100) ? "100": "10", 866 (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half"); 867 netif_carrier_on(dev); 868 } 869 else{ 870 lp->link_config.speed = SPEED_INVALID; 871 lp->link_config.duplex = DUPLEX_INVALID; 872 lp->link_config.autoneg = AUTONEG_INVALID; 873 printk(KERN_INFO "%s: Link is Down.\n",dev->name); 874 netif_carrier_off(dev); 875 } 876 877 return 0; 878 } 879 /* 880 This function reads the mib counters. 881 */ 882 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER) 883 { 884 unsigned int status; 885 unsigned int data; 886 unsigned int repeat = REPEAT_CNT; 887 888 writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR); 889 do { 890 status = readw(mmio + MIB_ADDR); 891 udelay(2); /* controller takes MAX 2 us to get mib data */ 892 } 893 while (--repeat && (status & MIB_CMD_ACTIVE)); 894 895 data = readl(mmio + MIB_DATA); 896 return data; 897 } 898 899 /* 900 * This function reads the mib registers and returns the hardware statistics. 901 * It updates previous internal driver statistics with new values. 902 */ 903 static struct net_device_stats *amd8111e_get_stats(struct net_device *dev) 904 { 905 struct amd8111e_priv *lp = netdev_priv(dev); 906 void __iomem *mmio = lp->mmio; 907 unsigned long flags; 908 struct net_device_stats *new_stats = &dev->stats; 909 910 if (!lp->opened) 911 return new_stats; 912 spin_lock_irqsave (&lp->lock, flags); 913 914 /* stats.rx_packets */ 915 new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+ 916 amd8111e_read_mib(mmio, rcv_multicast_pkts)+ 917 amd8111e_read_mib(mmio, rcv_unicast_pkts); 918 919 /* stats.tx_packets */ 920 new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets); 921 922 /*stats.rx_bytes */ 923 new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets); 924 925 /* stats.tx_bytes */ 926 new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets); 927 928 /* stats.rx_errors */ 929 /* hw errors + errors driver reported */ 930 new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+ 931 amd8111e_read_mib(mmio, rcv_fragments)+ 932 amd8111e_read_mib(mmio, rcv_jabbers)+ 933 amd8111e_read_mib(mmio, rcv_alignment_errors)+ 934 amd8111e_read_mib(mmio, rcv_fcs_errors)+ 935 amd8111e_read_mib(mmio, rcv_miss_pkts)+ 936 lp->drv_rx_errors; 937 938 /* stats.tx_errors */ 939 new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts); 940 941 /* stats.rx_dropped*/ 942 new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts); 943 944 /* stats.tx_dropped*/ 945 new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts); 946 947 /* stats.multicast*/ 948 new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts); 949 950 /* stats.collisions*/ 951 new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions); 952 953 /* stats.rx_length_errors*/ 954 new_stats->rx_length_errors = 955 amd8111e_read_mib(mmio, rcv_undersize_pkts)+ 956 amd8111e_read_mib(mmio, rcv_oversize_pkts); 957 958 /* stats.rx_over_errors*/ 959 new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts); 960 961 /* stats.rx_crc_errors*/ 962 new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors); 963 964 /* stats.rx_frame_errors*/ 965 new_stats->rx_frame_errors = 966 amd8111e_read_mib(mmio, rcv_alignment_errors); 967 968 /* stats.rx_fifo_errors */ 969 new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts); 970 971 /* stats.rx_missed_errors */ 972 new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts); 973 974 /* stats.tx_aborted_errors*/ 975 new_stats->tx_aborted_errors = 976 amd8111e_read_mib(mmio, xmt_excessive_collision); 977 978 /* stats.tx_carrier_errors*/ 979 new_stats->tx_carrier_errors = 980 amd8111e_read_mib(mmio, xmt_loss_carrier); 981 982 /* stats.tx_fifo_errors*/ 983 new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts); 984 985 /* stats.tx_window_errors*/ 986 new_stats->tx_window_errors = 987 amd8111e_read_mib(mmio, xmt_late_collision); 988 989 /* Reset the mibs for collecting new statistics */ 990 /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/ 991 992 spin_unlock_irqrestore (&lp->lock, flags); 993 994 return new_stats; 995 } 996 /* This function recalculate the interrupt coalescing mode on every interrupt 997 according to the datarate and the packet rate. 998 */ 999 static int amd8111e_calc_coalesce(struct net_device *dev) 1000 { 1001 struct amd8111e_priv *lp = netdev_priv(dev); 1002 struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf; 1003 int tx_pkt_rate; 1004 int rx_pkt_rate; 1005 int tx_data_rate; 1006 int rx_data_rate; 1007 int rx_pkt_size; 1008 int tx_pkt_size; 1009 1010 tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets; 1011 coal_conf->tx_prev_packets = coal_conf->tx_packets; 1012 1013 tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes; 1014 coal_conf->tx_prev_bytes = coal_conf->tx_bytes; 1015 1016 rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets; 1017 coal_conf->rx_prev_packets = coal_conf->rx_packets; 1018 1019 rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes; 1020 coal_conf->rx_prev_bytes = coal_conf->rx_bytes; 1021 1022 if(rx_pkt_rate < 800){ 1023 if(coal_conf->rx_coal_type != NO_COALESCE){ 1024 1025 coal_conf->rx_timeout = 0x0; 1026 coal_conf->rx_event_count = 0; 1027 amd8111e_set_coalesce(dev,RX_INTR_COAL); 1028 coal_conf->rx_coal_type = NO_COALESCE; 1029 } 1030 } 1031 else{ 1032 1033 rx_pkt_size = rx_data_rate/rx_pkt_rate; 1034 if (rx_pkt_size < 128){ 1035 if(coal_conf->rx_coal_type != NO_COALESCE){ 1036 1037 coal_conf->rx_timeout = 0; 1038 coal_conf->rx_event_count = 0; 1039 amd8111e_set_coalesce(dev,RX_INTR_COAL); 1040 coal_conf->rx_coal_type = NO_COALESCE; 1041 } 1042 1043 } 1044 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){ 1045 1046 if(coal_conf->rx_coal_type != LOW_COALESCE){ 1047 coal_conf->rx_timeout = 1; 1048 coal_conf->rx_event_count = 4; 1049 amd8111e_set_coalesce(dev,RX_INTR_COAL); 1050 coal_conf->rx_coal_type = LOW_COALESCE; 1051 } 1052 } 1053 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){ 1054 1055 if(coal_conf->rx_coal_type != MEDIUM_COALESCE){ 1056 coal_conf->rx_timeout = 1; 1057 coal_conf->rx_event_count = 4; 1058 amd8111e_set_coalesce(dev,RX_INTR_COAL); 1059 coal_conf->rx_coal_type = MEDIUM_COALESCE; 1060 } 1061 1062 } 1063 else if(rx_pkt_size >= 1024){ 1064 if(coal_conf->rx_coal_type != HIGH_COALESCE){ 1065 coal_conf->rx_timeout = 2; 1066 coal_conf->rx_event_count = 3; 1067 amd8111e_set_coalesce(dev,RX_INTR_COAL); 1068 coal_conf->rx_coal_type = HIGH_COALESCE; 1069 } 1070 } 1071 } 1072 /* NOW FOR TX INTR COALESC */ 1073 if(tx_pkt_rate < 800){ 1074 if(coal_conf->tx_coal_type != NO_COALESCE){ 1075 1076 coal_conf->tx_timeout = 0x0; 1077 coal_conf->tx_event_count = 0; 1078 amd8111e_set_coalesce(dev,TX_INTR_COAL); 1079 coal_conf->tx_coal_type = NO_COALESCE; 1080 } 1081 } 1082 else{ 1083 1084 tx_pkt_size = tx_data_rate/tx_pkt_rate; 1085 if (tx_pkt_size < 128){ 1086 1087 if(coal_conf->tx_coal_type != NO_COALESCE){ 1088 1089 coal_conf->tx_timeout = 0; 1090 coal_conf->tx_event_count = 0; 1091 amd8111e_set_coalesce(dev,TX_INTR_COAL); 1092 coal_conf->tx_coal_type = NO_COALESCE; 1093 } 1094 1095 } 1096 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){ 1097 1098 if(coal_conf->tx_coal_type != LOW_COALESCE){ 1099 coal_conf->tx_timeout = 1; 1100 coal_conf->tx_event_count = 2; 1101 amd8111e_set_coalesce(dev,TX_INTR_COAL); 1102 coal_conf->tx_coal_type = LOW_COALESCE; 1103 1104 } 1105 } 1106 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){ 1107 1108 if(coal_conf->tx_coal_type != MEDIUM_COALESCE){ 1109 coal_conf->tx_timeout = 2; 1110 coal_conf->tx_event_count = 5; 1111 amd8111e_set_coalesce(dev,TX_INTR_COAL); 1112 coal_conf->tx_coal_type = MEDIUM_COALESCE; 1113 } 1114 1115 } 1116 else if(tx_pkt_size >= 1024){ 1117 if (tx_pkt_size >= 1024){ 1118 if(coal_conf->tx_coal_type != HIGH_COALESCE){ 1119 coal_conf->tx_timeout = 4; 1120 coal_conf->tx_event_count = 8; 1121 amd8111e_set_coalesce(dev,TX_INTR_COAL); 1122 coal_conf->tx_coal_type = HIGH_COALESCE; 1123 } 1124 } 1125 } 1126 } 1127 return 0; 1128 1129 } 1130 /* 1131 This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts. 1132 */ 1133 static irqreturn_t amd8111e_interrupt(int irq, void *dev_id) 1134 { 1135 1136 struct net_device * dev = (struct net_device *) dev_id; 1137 struct amd8111e_priv *lp = netdev_priv(dev); 1138 void __iomem *mmio = lp->mmio; 1139 unsigned int intr0, intren0; 1140 unsigned int handled = 1; 1141 1142 if(unlikely(dev == NULL)) 1143 return IRQ_NONE; 1144 1145 spin_lock(&lp->lock); 1146 1147 /* disabling interrupt */ 1148 writel(INTREN, mmio + CMD0); 1149 1150 /* Read interrupt status */ 1151 intr0 = readl(mmio + INT0); 1152 intren0 = readl(mmio + INTEN0); 1153 1154 /* Process all the INT event until INTR bit is clear. */ 1155 1156 if (!(intr0 & INTR)){ 1157 handled = 0; 1158 goto err_no_interrupt; 1159 } 1160 1161 /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */ 1162 writel(intr0, mmio + INT0); 1163 1164 /* Check if Receive Interrupt has occurred. */ 1165 if (intr0 & RINT0) { 1166 if (napi_schedule_prep(&lp->napi)) { 1167 /* Disable receive interupts */ 1168 writel(RINTEN0, mmio + INTEN0); 1169 /* Schedule a polling routine */ 1170 __napi_schedule(&lp->napi); 1171 } else if (intren0 & RINTEN0) { 1172 printk("************Driver bug! interrupt while in poll\n"); 1173 /* Fix by disable receive interrupts */ 1174 writel(RINTEN0, mmio + INTEN0); 1175 } 1176 } 1177 1178 /* Check if Transmit Interrupt has occurred. */ 1179 if (intr0 & TINT0) 1180 amd8111e_tx(dev); 1181 1182 /* Check if Link Change Interrupt has occurred. */ 1183 if (intr0 & LCINT) 1184 amd8111e_link_change(dev); 1185 1186 /* Check if Hardware Timer Interrupt has occurred. */ 1187 if (intr0 & STINT) 1188 amd8111e_calc_coalesce(dev); 1189 1190 err_no_interrupt: 1191 writel( VAL0 | INTREN,mmio + CMD0); 1192 1193 spin_unlock(&lp->lock); 1194 1195 return IRQ_RETVAL(handled); 1196 } 1197 1198 #ifdef CONFIG_NET_POLL_CONTROLLER 1199 static void amd8111e_poll(struct net_device *dev) 1200 { 1201 unsigned long flags; 1202 local_irq_save(flags); 1203 amd8111e_interrupt(0, dev); 1204 local_irq_restore(flags); 1205 } 1206 #endif 1207 1208 1209 /* 1210 This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down. 1211 */ 1212 static int amd8111e_close(struct net_device * dev) 1213 { 1214 struct amd8111e_priv *lp = netdev_priv(dev); 1215 netif_stop_queue(dev); 1216 1217 napi_disable(&lp->napi); 1218 1219 spin_lock_irq(&lp->lock); 1220 1221 amd8111e_disable_interrupt(lp); 1222 amd8111e_stop_chip(lp); 1223 1224 /* Free transmit and receive skbs */ 1225 amd8111e_free_skbs(lp->amd8111e_net_dev); 1226 1227 netif_carrier_off(lp->amd8111e_net_dev); 1228 1229 /* Delete ipg timer */ 1230 if(lp->options & OPTION_DYN_IPG_ENABLE) 1231 del_timer_sync(&lp->ipg_data.ipg_timer); 1232 1233 spin_unlock_irq(&lp->lock); 1234 free_irq(dev->irq, dev); 1235 amd8111e_free_ring(lp); 1236 1237 /* Update the statistics before closing */ 1238 amd8111e_get_stats(dev); 1239 lp->opened = 0; 1240 return 0; 1241 } 1242 /* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device. 1243 */ 1244 static int amd8111e_open(struct net_device * dev ) 1245 { 1246 struct amd8111e_priv *lp = netdev_priv(dev); 1247 1248 if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED, 1249 dev->name, dev)) 1250 return -EAGAIN; 1251 1252 napi_enable(&lp->napi); 1253 1254 spin_lock_irq(&lp->lock); 1255 1256 amd8111e_init_hw_default(lp); 1257 1258 if(amd8111e_restart(dev)){ 1259 spin_unlock_irq(&lp->lock); 1260 napi_disable(&lp->napi); 1261 if (dev->irq) 1262 free_irq(dev->irq, dev); 1263 return -ENOMEM; 1264 } 1265 /* Start ipg timer */ 1266 if(lp->options & OPTION_DYN_IPG_ENABLE){ 1267 add_timer(&lp->ipg_data.ipg_timer); 1268 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name); 1269 } 1270 1271 lp->opened = 1; 1272 1273 spin_unlock_irq(&lp->lock); 1274 1275 netif_start_queue(dev); 1276 1277 return 0; 1278 } 1279 /* 1280 This function checks if there is any transmit descriptors available to queue more packet. 1281 */ 1282 static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp ) 1283 { 1284 int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK; 1285 if (lp->tx_skbuff[tx_index]) 1286 return -1; 1287 else 1288 return 0; 1289 1290 } 1291 /* 1292 This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc. 1293 */ 1294 1295 static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb, 1296 struct net_device * dev) 1297 { 1298 struct amd8111e_priv *lp = netdev_priv(dev); 1299 int tx_index; 1300 unsigned long flags; 1301 1302 spin_lock_irqsave(&lp->lock, flags); 1303 1304 tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK; 1305 1306 lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len); 1307 1308 lp->tx_skbuff[tx_index] = skb; 1309 lp->tx_ring[tx_index].tx_flags = 0; 1310 1311 #if AMD8111E_VLAN_TAG_USED 1312 if (vlan_tx_tag_present(skb)) { 1313 lp->tx_ring[tx_index].tag_ctrl_cmd |= 1314 cpu_to_le16(TCC_VLAN_INSERT); 1315 lp->tx_ring[tx_index].tag_ctrl_info = 1316 cpu_to_le16(vlan_tx_tag_get(skb)); 1317 1318 } 1319 #endif 1320 lp->tx_dma_addr[tx_index] = 1321 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); 1322 lp->tx_ring[tx_index].buff_phy_addr = 1323 cpu_to_le32(lp->tx_dma_addr[tx_index]); 1324 1325 /* Set FCS and LTINT bits */ 1326 wmb(); 1327 lp->tx_ring[tx_index].tx_flags |= 1328 cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT); 1329 1330 lp->tx_idx++; 1331 1332 /* Trigger an immediate send poll. */ 1333 writel( VAL1 | TDMD0, lp->mmio + CMD0); 1334 writel( VAL2 | RDMD0,lp->mmio + CMD0); 1335 1336 if(amd8111e_tx_queue_avail(lp) < 0){ 1337 netif_stop_queue(dev); 1338 } 1339 spin_unlock_irqrestore(&lp->lock, flags); 1340 return NETDEV_TX_OK; 1341 } 1342 /* 1343 This function returns all the memory mapped registers of the device. 1344 */ 1345 static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf) 1346 { 1347 void __iomem *mmio = lp->mmio; 1348 /* Read only necessary registers */ 1349 buf[0] = readl(mmio + XMT_RING_BASE_ADDR0); 1350 buf[1] = readl(mmio + XMT_RING_LEN0); 1351 buf[2] = readl(mmio + RCV_RING_BASE_ADDR0); 1352 buf[3] = readl(mmio + RCV_RING_LEN0); 1353 buf[4] = readl(mmio + CMD0); 1354 buf[5] = readl(mmio + CMD2); 1355 buf[6] = readl(mmio + CMD3); 1356 buf[7] = readl(mmio + CMD7); 1357 buf[8] = readl(mmio + INT0); 1358 buf[9] = readl(mmio + INTEN0); 1359 buf[10] = readl(mmio + LADRF); 1360 buf[11] = readl(mmio + LADRF+4); 1361 buf[12] = readl(mmio + STAT0); 1362 } 1363 1364 1365 /* 1366 This function sets promiscuos mode, all-multi mode or the multicast address 1367 list to the device. 1368 */ 1369 static void amd8111e_set_multicast_list(struct net_device *dev) 1370 { 1371 struct netdev_hw_addr *ha; 1372 struct amd8111e_priv *lp = netdev_priv(dev); 1373 u32 mc_filter[2] ; 1374 int bit_num; 1375 1376 if(dev->flags & IFF_PROMISC){ 1377 writel( VAL2 | PROM, lp->mmio + CMD2); 1378 return; 1379 } 1380 else 1381 writel( PROM, lp->mmio + CMD2); 1382 if (dev->flags & IFF_ALLMULTI || 1383 netdev_mc_count(dev) > MAX_FILTER_SIZE) { 1384 /* get all multicast packet */ 1385 mc_filter[1] = mc_filter[0] = 0xffffffff; 1386 lp->options |= OPTION_MULTICAST_ENABLE; 1387 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF); 1388 return; 1389 } 1390 if (netdev_mc_empty(dev)) { 1391 /* get only own packets */ 1392 mc_filter[1] = mc_filter[0] = 0; 1393 lp->options &= ~OPTION_MULTICAST_ENABLE; 1394 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF); 1395 /* disable promiscuous mode */ 1396 writel(PROM, lp->mmio + CMD2); 1397 return; 1398 } 1399 /* load all the multicast addresses in the logic filter */ 1400 lp->options |= OPTION_MULTICAST_ENABLE; 1401 mc_filter[1] = mc_filter[0] = 0; 1402 netdev_for_each_mc_addr(ha, dev) { 1403 bit_num = (ether_crc_le(ETH_ALEN, ha->addr) >> 26) & 0x3f; 1404 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31); 1405 } 1406 amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF); 1407 1408 /* To eliminate PCI posting bug */ 1409 readl(lp->mmio + CMD2); 1410 1411 } 1412 1413 static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info) 1414 { 1415 struct amd8111e_priv *lp = netdev_priv(dev); 1416 struct pci_dev *pci_dev = lp->pci_dev; 1417 strlcpy(info->driver, MODULE_NAME, sizeof(info->driver)); 1418 strlcpy(info->version, MODULE_VERS, sizeof(info->version)); 1419 snprintf(info->fw_version, sizeof(info->fw_version), 1420 "%u", chip_version); 1421 strlcpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info)); 1422 } 1423 1424 static int amd8111e_get_regs_len(struct net_device *dev) 1425 { 1426 return AMD8111E_REG_DUMP_LEN; 1427 } 1428 1429 static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) 1430 { 1431 struct amd8111e_priv *lp = netdev_priv(dev); 1432 regs->version = 0; 1433 amd8111e_read_regs(lp, buf); 1434 } 1435 1436 static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 1437 { 1438 struct amd8111e_priv *lp = netdev_priv(dev); 1439 spin_lock_irq(&lp->lock); 1440 mii_ethtool_gset(&lp->mii_if, ecmd); 1441 spin_unlock_irq(&lp->lock); 1442 return 0; 1443 } 1444 1445 static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 1446 { 1447 struct amd8111e_priv *lp = netdev_priv(dev); 1448 int res; 1449 spin_lock_irq(&lp->lock); 1450 res = mii_ethtool_sset(&lp->mii_if, ecmd); 1451 spin_unlock_irq(&lp->lock); 1452 return res; 1453 } 1454 1455 static int amd8111e_nway_reset(struct net_device *dev) 1456 { 1457 struct amd8111e_priv *lp = netdev_priv(dev); 1458 return mii_nway_restart(&lp->mii_if); 1459 } 1460 1461 static u32 amd8111e_get_link(struct net_device *dev) 1462 { 1463 struct amd8111e_priv *lp = netdev_priv(dev); 1464 return mii_link_ok(&lp->mii_if); 1465 } 1466 1467 static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info) 1468 { 1469 struct amd8111e_priv *lp = netdev_priv(dev); 1470 wol_info->supported = WAKE_MAGIC|WAKE_PHY; 1471 if (lp->options & OPTION_WOL_ENABLE) 1472 wol_info->wolopts = WAKE_MAGIC; 1473 } 1474 1475 static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info) 1476 { 1477 struct amd8111e_priv *lp = netdev_priv(dev); 1478 if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY)) 1479 return -EINVAL; 1480 spin_lock_irq(&lp->lock); 1481 if (wol_info->wolopts & WAKE_MAGIC) 1482 lp->options |= 1483 (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE); 1484 else if(wol_info->wolopts & WAKE_PHY) 1485 lp->options |= 1486 (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE); 1487 else 1488 lp->options &= ~OPTION_WOL_ENABLE; 1489 spin_unlock_irq(&lp->lock); 1490 return 0; 1491 } 1492 1493 static const struct ethtool_ops ops = { 1494 .get_drvinfo = amd8111e_get_drvinfo, 1495 .get_regs_len = amd8111e_get_regs_len, 1496 .get_regs = amd8111e_get_regs, 1497 .get_settings = amd8111e_get_settings, 1498 .set_settings = amd8111e_set_settings, 1499 .nway_reset = amd8111e_nway_reset, 1500 .get_link = amd8111e_get_link, 1501 .get_wol = amd8111e_get_wol, 1502 .set_wol = amd8111e_set_wol, 1503 }; 1504 1505 /* 1506 This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application. 1507 */ 1508 1509 static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd) 1510 { 1511 struct mii_ioctl_data *data = if_mii(ifr); 1512 struct amd8111e_priv *lp = netdev_priv(dev); 1513 int err; 1514 u32 mii_regval; 1515 1516 switch(cmd) { 1517 case SIOCGMIIPHY: 1518 data->phy_id = lp->ext_phy_addr; 1519 1520 /* fallthru */ 1521 case SIOCGMIIREG: 1522 1523 spin_lock_irq(&lp->lock); 1524 err = amd8111e_read_phy(lp, data->phy_id, 1525 data->reg_num & PHY_REG_ADDR_MASK, &mii_regval); 1526 spin_unlock_irq(&lp->lock); 1527 1528 data->val_out = mii_regval; 1529 return err; 1530 1531 case SIOCSMIIREG: 1532 1533 spin_lock_irq(&lp->lock); 1534 err = amd8111e_write_phy(lp, data->phy_id, 1535 data->reg_num & PHY_REG_ADDR_MASK, data->val_in); 1536 spin_unlock_irq(&lp->lock); 1537 1538 return err; 1539 1540 default: 1541 /* do nothing */ 1542 break; 1543 } 1544 return -EOPNOTSUPP; 1545 } 1546 static int amd8111e_set_mac_address(struct net_device *dev, void *p) 1547 { 1548 struct amd8111e_priv *lp = netdev_priv(dev); 1549 int i; 1550 struct sockaddr *addr = p; 1551 1552 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 1553 spin_lock_irq(&lp->lock); 1554 /* Setting the MAC address to the device */ 1555 for (i = 0; i < ETH_ALEN; i++) 1556 writeb( dev->dev_addr[i], lp->mmio + PADR + i ); 1557 1558 spin_unlock_irq(&lp->lock); 1559 1560 return 0; 1561 } 1562 1563 /* 1564 This function changes the mtu of the device. It restarts the device to initialize the descriptor with new receive buffers. 1565 */ 1566 static int amd8111e_change_mtu(struct net_device *dev, int new_mtu) 1567 { 1568 struct amd8111e_priv *lp = netdev_priv(dev); 1569 int err; 1570 1571 if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU)) 1572 return -EINVAL; 1573 1574 if (!netif_running(dev)) { 1575 /* new_mtu will be used 1576 when device starts netxt time */ 1577 dev->mtu = new_mtu; 1578 return 0; 1579 } 1580 1581 spin_lock_irq(&lp->lock); 1582 1583 /* stop the chip */ 1584 writel(RUN, lp->mmio + CMD0); 1585 1586 dev->mtu = new_mtu; 1587 1588 err = amd8111e_restart(dev); 1589 spin_unlock_irq(&lp->lock); 1590 if(!err) 1591 netif_start_queue(dev); 1592 return err; 1593 } 1594 1595 static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp) 1596 { 1597 writel( VAL1|MPPLBA, lp->mmio + CMD3); 1598 writel( VAL0|MPEN_SW, lp->mmio + CMD7); 1599 1600 /* To eliminate PCI posting bug */ 1601 readl(lp->mmio + CMD7); 1602 return 0; 1603 } 1604 1605 static int amd8111e_enable_link_change(struct amd8111e_priv* lp) 1606 { 1607 1608 /* Adapter is already stoped/suspended/interrupt-disabled */ 1609 writel(VAL0|LCMODE_SW,lp->mmio + CMD7); 1610 1611 /* To eliminate PCI posting bug */ 1612 readl(lp->mmio + CMD7); 1613 return 0; 1614 } 1615 1616 /* 1617 * This function is called when a packet transmission fails to complete 1618 * within a reasonable period, on the assumption that an interrupt have 1619 * failed or the interface is locked up. This function will reinitialize 1620 * the hardware. 1621 */ 1622 static void amd8111e_tx_timeout(struct net_device *dev) 1623 { 1624 struct amd8111e_priv* lp = netdev_priv(dev); 1625 int err; 1626 1627 printk(KERN_ERR "%s: transmit timed out, resetting\n", 1628 dev->name); 1629 spin_lock_irq(&lp->lock); 1630 err = amd8111e_restart(dev); 1631 spin_unlock_irq(&lp->lock); 1632 if(!err) 1633 netif_wake_queue(dev); 1634 } 1635 static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state) 1636 { 1637 struct net_device *dev = pci_get_drvdata(pci_dev); 1638 struct amd8111e_priv *lp = netdev_priv(dev); 1639 1640 if (!netif_running(dev)) 1641 return 0; 1642 1643 /* disable the interrupt */ 1644 spin_lock_irq(&lp->lock); 1645 amd8111e_disable_interrupt(lp); 1646 spin_unlock_irq(&lp->lock); 1647 1648 netif_device_detach(dev); 1649 1650 /* stop chip */ 1651 spin_lock_irq(&lp->lock); 1652 if(lp->options & OPTION_DYN_IPG_ENABLE) 1653 del_timer_sync(&lp->ipg_data.ipg_timer); 1654 amd8111e_stop_chip(lp); 1655 spin_unlock_irq(&lp->lock); 1656 1657 if(lp->options & OPTION_WOL_ENABLE){ 1658 /* enable wol */ 1659 if(lp->options & OPTION_WAKE_MAGIC_ENABLE) 1660 amd8111e_enable_magicpkt(lp); 1661 if(lp->options & OPTION_WAKE_PHY_ENABLE) 1662 amd8111e_enable_link_change(lp); 1663 1664 pci_enable_wake(pci_dev, PCI_D3hot, 1); 1665 pci_enable_wake(pci_dev, PCI_D3cold, 1); 1666 1667 } 1668 else{ 1669 pci_enable_wake(pci_dev, PCI_D3hot, 0); 1670 pci_enable_wake(pci_dev, PCI_D3cold, 0); 1671 } 1672 1673 pci_save_state(pci_dev); 1674 pci_set_power_state(pci_dev, PCI_D3hot); 1675 1676 return 0; 1677 } 1678 static int amd8111e_resume(struct pci_dev *pci_dev) 1679 { 1680 struct net_device *dev = pci_get_drvdata(pci_dev); 1681 struct amd8111e_priv *lp = netdev_priv(dev); 1682 1683 if (!netif_running(dev)) 1684 return 0; 1685 1686 pci_set_power_state(pci_dev, PCI_D0); 1687 pci_restore_state(pci_dev); 1688 1689 pci_enable_wake(pci_dev, PCI_D3hot, 0); 1690 pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */ 1691 1692 netif_device_attach(dev); 1693 1694 spin_lock_irq(&lp->lock); 1695 amd8111e_restart(dev); 1696 /* Restart ipg timer */ 1697 if(lp->options & OPTION_DYN_IPG_ENABLE) 1698 mod_timer(&lp->ipg_data.ipg_timer, 1699 jiffies + IPG_CONVERGE_JIFFIES); 1700 spin_unlock_irq(&lp->lock); 1701 1702 return 0; 1703 } 1704 1705 1706 static void __devexit amd8111e_remove_one(struct pci_dev *pdev) 1707 { 1708 struct net_device *dev = pci_get_drvdata(pdev); 1709 if (dev) { 1710 unregister_netdev(dev); 1711 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio); 1712 free_netdev(dev); 1713 pci_release_regions(pdev); 1714 pci_disable_device(pdev); 1715 pci_set_drvdata(pdev, NULL); 1716 } 1717 } 1718 static void amd8111e_config_ipg(struct net_device* dev) 1719 { 1720 struct amd8111e_priv *lp = netdev_priv(dev); 1721 struct ipg_info* ipg_data = &lp->ipg_data; 1722 void __iomem *mmio = lp->mmio; 1723 unsigned int prev_col_cnt = ipg_data->col_cnt; 1724 unsigned int total_col_cnt; 1725 unsigned int tmp_ipg; 1726 1727 if(lp->link_config.duplex == DUPLEX_FULL){ 1728 ipg_data->ipg = DEFAULT_IPG; 1729 return; 1730 } 1731 1732 if(ipg_data->ipg_state == SSTATE){ 1733 1734 if(ipg_data->timer_tick == IPG_STABLE_TIME){ 1735 1736 ipg_data->timer_tick = 0; 1737 ipg_data->ipg = MIN_IPG - IPG_STEP; 1738 ipg_data->current_ipg = MIN_IPG; 1739 ipg_data->diff_col_cnt = 0xFFFFFFFF; 1740 ipg_data->ipg_state = CSTATE; 1741 } 1742 else 1743 ipg_data->timer_tick++; 1744 } 1745 1746 if(ipg_data->ipg_state == CSTATE){ 1747 1748 /* Get the current collision count */ 1749 1750 total_col_cnt = ipg_data->col_cnt = 1751 amd8111e_read_mib(mmio, xmt_collisions); 1752 1753 if ((total_col_cnt - prev_col_cnt) < 1754 (ipg_data->diff_col_cnt)){ 1755 1756 ipg_data->diff_col_cnt = 1757 total_col_cnt - prev_col_cnt ; 1758 1759 ipg_data->ipg = ipg_data->current_ipg; 1760 } 1761 1762 ipg_data->current_ipg += IPG_STEP; 1763 1764 if (ipg_data->current_ipg <= MAX_IPG) 1765 tmp_ipg = ipg_data->current_ipg; 1766 else{ 1767 tmp_ipg = ipg_data->ipg; 1768 ipg_data->ipg_state = SSTATE; 1769 } 1770 writew((u32)tmp_ipg, mmio + IPG); 1771 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1); 1772 } 1773 mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES); 1774 return; 1775 1776 } 1777 1778 static void __devinit amd8111e_probe_ext_phy(struct net_device* dev) 1779 { 1780 struct amd8111e_priv *lp = netdev_priv(dev); 1781 int i; 1782 1783 for (i = 0x1e; i >= 0; i--) { 1784 u32 id1, id2; 1785 1786 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1)) 1787 continue; 1788 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2)) 1789 continue; 1790 lp->ext_phy_id = (id1 << 16) | id2; 1791 lp->ext_phy_addr = i; 1792 return; 1793 } 1794 lp->ext_phy_id = 0; 1795 lp->ext_phy_addr = 1; 1796 } 1797 1798 static const struct net_device_ops amd8111e_netdev_ops = { 1799 .ndo_open = amd8111e_open, 1800 .ndo_stop = amd8111e_close, 1801 .ndo_start_xmit = amd8111e_start_xmit, 1802 .ndo_tx_timeout = amd8111e_tx_timeout, 1803 .ndo_get_stats = amd8111e_get_stats, 1804 .ndo_set_rx_mode = amd8111e_set_multicast_list, 1805 .ndo_validate_addr = eth_validate_addr, 1806 .ndo_set_mac_address = amd8111e_set_mac_address, 1807 .ndo_do_ioctl = amd8111e_ioctl, 1808 .ndo_change_mtu = amd8111e_change_mtu, 1809 #ifdef CONFIG_NET_POLL_CONTROLLER 1810 .ndo_poll_controller = amd8111e_poll, 1811 #endif 1812 }; 1813 1814 static int __devinit amd8111e_probe_one(struct pci_dev *pdev, 1815 const struct pci_device_id *ent) 1816 { 1817 int err,i,pm_cap; 1818 unsigned long reg_addr,reg_len; 1819 struct amd8111e_priv* lp; 1820 struct net_device* dev; 1821 1822 err = pci_enable_device(pdev); 1823 if(err){ 1824 printk(KERN_ERR "amd8111e: Cannot enable new PCI device, " 1825 "exiting.\n"); 1826 return err; 1827 } 1828 1829 if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){ 1830 printk(KERN_ERR "amd8111e: Cannot find PCI base address, " 1831 "exiting.\n"); 1832 err = -ENODEV; 1833 goto err_disable_pdev; 1834 } 1835 1836 err = pci_request_regions(pdev, MODULE_NAME); 1837 if(err){ 1838 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, " 1839 "exiting.\n"); 1840 goto err_disable_pdev; 1841 } 1842 1843 pci_set_master(pdev); 1844 1845 /* Find power-management capability. */ 1846 if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){ 1847 printk(KERN_ERR "amd8111e: No Power Management capability, " 1848 "exiting.\n"); 1849 goto err_free_reg; 1850 } 1851 1852 /* Initialize DMA */ 1853 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) < 0) { 1854 printk(KERN_ERR "amd8111e: DMA not supported," 1855 "exiting.\n"); 1856 goto err_free_reg; 1857 } 1858 1859 reg_addr = pci_resource_start(pdev, 0); 1860 reg_len = pci_resource_len(pdev, 0); 1861 1862 dev = alloc_etherdev(sizeof(struct amd8111e_priv)); 1863 if (!dev) { 1864 err = -ENOMEM; 1865 goto err_free_reg; 1866 } 1867 1868 SET_NETDEV_DEV(dev, &pdev->dev); 1869 1870 #if AMD8111E_VLAN_TAG_USED 1871 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ; 1872 #endif 1873 1874 lp = netdev_priv(dev); 1875 lp->pci_dev = pdev; 1876 lp->amd8111e_net_dev = dev; 1877 lp->pm_cap = pm_cap; 1878 1879 spin_lock_init(&lp->lock); 1880 1881 lp->mmio = ioremap(reg_addr, reg_len); 1882 if (!lp->mmio) { 1883 printk(KERN_ERR "amd8111e: Cannot map device registers, " 1884 "exiting\n"); 1885 err = -ENOMEM; 1886 goto err_free_dev; 1887 } 1888 1889 /* Initializing MAC address */ 1890 for (i = 0; i < ETH_ALEN; i++) 1891 dev->dev_addr[i] = readb(lp->mmio + PADR + i); 1892 1893 /* Setting user defined parametrs */ 1894 lp->ext_phy_option = speed_duplex[card_idx]; 1895 if(coalesce[card_idx]) 1896 lp->options |= OPTION_INTR_COAL_ENABLE; 1897 if(dynamic_ipg[card_idx++]) 1898 lp->options |= OPTION_DYN_IPG_ENABLE; 1899 1900 1901 /* Initialize driver entry points */ 1902 dev->netdev_ops = &amd8111e_netdev_ops; 1903 SET_ETHTOOL_OPS(dev, &ops); 1904 dev->irq =pdev->irq; 1905 dev->watchdog_timeo = AMD8111E_TX_TIMEOUT; 1906 netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32); 1907 1908 #if AMD8111E_VLAN_TAG_USED 1909 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 1910 #endif 1911 /* Probe the external PHY */ 1912 amd8111e_probe_ext_phy(dev); 1913 1914 /* setting mii default values */ 1915 lp->mii_if.dev = dev; 1916 lp->mii_if.mdio_read = amd8111e_mdio_read; 1917 lp->mii_if.mdio_write = amd8111e_mdio_write; 1918 lp->mii_if.phy_id = lp->ext_phy_addr; 1919 1920 /* Set receive buffer length and set jumbo option*/ 1921 amd8111e_set_rx_buff_len(dev); 1922 1923 1924 err = register_netdev(dev); 1925 if (err) { 1926 printk(KERN_ERR "amd8111e: Cannot register net device, " 1927 "exiting.\n"); 1928 goto err_iounmap; 1929 } 1930 1931 pci_set_drvdata(pdev, dev); 1932 1933 /* Initialize software ipg timer */ 1934 if(lp->options & OPTION_DYN_IPG_ENABLE){ 1935 init_timer(&lp->ipg_data.ipg_timer); 1936 lp->ipg_data.ipg_timer.data = (unsigned long) dev; 1937 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg; 1938 lp->ipg_data.ipg_timer.expires = jiffies + 1939 IPG_CONVERGE_JIFFIES; 1940 lp->ipg_data.ipg = DEFAULT_IPG; 1941 lp->ipg_data.ipg_state = CSTATE; 1942 } 1943 1944 /* display driver and device information */ 1945 1946 chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28; 1947 printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n", 1948 dev->name,MODULE_VERS); 1949 printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet %pM\n", 1950 dev->name, chip_version, dev->dev_addr); 1951 if (lp->ext_phy_id) 1952 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n", 1953 dev->name, lp->ext_phy_id, lp->ext_phy_addr); 1954 else 1955 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n", 1956 dev->name); 1957 return 0; 1958 err_iounmap: 1959 iounmap(lp->mmio); 1960 1961 err_free_dev: 1962 free_netdev(dev); 1963 1964 err_free_reg: 1965 pci_release_regions(pdev); 1966 1967 err_disable_pdev: 1968 pci_disable_device(pdev); 1969 pci_set_drvdata(pdev, NULL); 1970 return err; 1971 1972 } 1973 1974 static struct pci_driver amd8111e_driver = { 1975 .name = MODULE_NAME, 1976 .id_table = amd8111e_pci_tbl, 1977 .probe = amd8111e_probe_one, 1978 .remove = __devexit_p(amd8111e_remove_one), 1979 .suspend = amd8111e_suspend, 1980 .resume = amd8111e_resume 1981 }; 1982 1983 static int __init amd8111e_init(void) 1984 { 1985 return pci_register_driver(&amd8111e_driver); 1986 } 1987 1988 static void __exit amd8111e_cleanup(void) 1989 { 1990 pci_unregister_driver(&amd8111e_driver); 1991 } 1992 1993 module_init(amd8111e_init); 1994 module_exit(amd8111e_cleanup); 1995