1b955f6caSJeff Kirsher 2b955f6caSJeff Kirsher /* Advanced Micro Devices Inc. AMD8111E Linux Network Driver 3b955f6caSJeff Kirsher * Copyright (C) 2004 Advanced Micro Devices 4b955f6caSJeff Kirsher * 5b955f6caSJeff Kirsher * 6b955f6caSJeff Kirsher * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ] 7b955f6caSJeff Kirsher * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c] 8b955f6caSJeff Kirsher * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ] 9b955f6caSJeff Kirsher * Derived from the lance driver written 1993,1994,1995 by Donald Becker. 10b955f6caSJeff Kirsher * Copyright 1993 United States Government as represented by the 11b955f6caSJeff Kirsher * Director, National Security Agency.[ pcnet32.c ] 12b955f6caSJeff Kirsher * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ] 13b955f6caSJeff Kirsher * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 14b955f6caSJeff Kirsher * 15b955f6caSJeff Kirsher * 16b955f6caSJeff Kirsher * This program is free software; you can redistribute it and/or modify 17b955f6caSJeff Kirsher * it under the terms of the GNU General Public License as published by 18b955f6caSJeff Kirsher * the Free Software Foundation; either version 2 of the License, or 19b955f6caSJeff Kirsher * (at your option) any later version. 20b955f6caSJeff Kirsher * 21b955f6caSJeff Kirsher * This program is distributed in the hope that it will be useful, 22b955f6caSJeff Kirsher * but WITHOUT ANY WARRANTY; without even the implied warranty of 23b955f6caSJeff Kirsher * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24b955f6caSJeff Kirsher * GNU General Public License for more details. 25b955f6caSJeff Kirsher * 26b955f6caSJeff Kirsher * You should have received a copy of the GNU General Public License 27b955f6caSJeff Kirsher * along with this program; if not, write to the Free Software 28b955f6caSJeff Kirsher * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 29b955f6caSJeff Kirsher * USA 30b955f6caSJeff Kirsher 31b955f6caSJeff Kirsher Module Name: 32b955f6caSJeff Kirsher 33b955f6caSJeff Kirsher amd8111e.c 34b955f6caSJeff Kirsher 35b955f6caSJeff Kirsher Abstract: 36b955f6caSJeff Kirsher 37b955f6caSJeff Kirsher AMD8111 based 10/100 Ethernet Controller Driver. 38b955f6caSJeff Kirsher 39b955f6caSJeff Kirsher Environment: 40b955f6caSJeff Kirsher 41b955f6caSJeff Kirsher Kernel Mode 42b955f6caSJeff Kirsher 43b955f6caSJeff Kirsher Revision History: 44b955f6caSJeff Kirsher 3.0.0 45b955f6caSJeff Kirsher Initial Revision. 46b955f6caSJeff Kirsher 3.0.1 47b955f6caSJeff Kirsher 1. Dynamic interrupt coalescing. 48b955f6caSJeff Kirsher 2. Removed prev_stats. 49b955f6caSJeff Kirsher 3. MII support. 50b955f6caSJeff Kirsher 4. Dynamic IPG support 51b955f6caSJeff Kirsher 3.0.2 05/29/2003 52b955f6caSJeff Kirsher 1. Bug fix: Fixed failure to send jumbo packets larger than 4k. 53b955f6caSJeff Kirsher 2. Bug fix: Fixed VLAN support failure. 54b955f6caSJeff Kirsher 3. Bug fix: Fixed receive interrupt coalescing bug. 55b955f6caSJeff Kirsher 4. Dynamic IPG support is disabled by default. 56b955f6caSJeff Kirsher 3.0.3 06/05/2003 57b955f6caSJeff Kirsher 1. Bug fix: Fixed failure to close the interface if SMP is enabled. 58b955f6caSJeff Kirsher 3.0.4 12/09/2003 59b955f6caSJeff Kirsher 1. Added set_mac_address routine for bonding driver support. 60b955f6caSJeff Kirsher 2. Tested the driver for bonding support 61b955f6caSJeff Kirsher 3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth 62b955f6caSJeff Kirsher indicated to the h/w. 63b955f6caSJeff Kirsher 4. Modified amd8111e_rx() routine to receive all the received packets 64b955f6caSJeff Kirsher in the first interrupt. 65b955f6caSJeff Kirsher 5. Bug fix: Corrected rx_errors reported in get_stats() function. 66b955f6caSJeff Kirsher 3.0.5 03/22/2004 67b955f6caSJeff Kirsher 1. Added NAPI support 68b955f6caSJeff Kirsher 69b955f6caSJeff Kirsher */ 70b955f6caSJeff Kirsher 71b955f6caSJeff Kirsher 72b955f6caSJeff Kirsher #include <linux/module.h> 73b955f6caSJeff Kirsher #include <linux/kernel.h> 74b955f6caSJeff Kirsher #include <linux/types.h> 75b955f6caSJeff Kirsher #include <linux/compiler.h> 76b955f6caSJeff Kirsher #include <linux/delay.h> 77b955f6caSJeff Kirsher #include <linux/init.h> 78b955f6caSJeff Kirsher #include <linux/interrupt.h> 79b955f6caSJeff Kirsher #include <linux/ioport.h> 80b955f6caSJeff Kirsher #include <linux/pci.h> 81b955f6caSJeff Kirsher #include <linux/netdevice.h> 82b955f6caSJeff Kirsher #include <linux/etherdevice.h> 83b955f6caSJeff Kirsher #include <linux/skbuff.h> 84b955f6caSJeff Kirsher #include <linux/ethtool.h> 85b955f6caSJeff Kirsher #include <linux/mii.h> 86b955f6caSJeff Kirsher #include <linux/if_vlan.h> 87b955f6caSJeff Kirsher #include <linux/ctype.h> 88b955f6caSJeff Kirsher #include <linux/crc32.h> 89b955f6caSJeff Kirsher #include <linux/dma-mapping.h> 90b955f6caSJeff Kirsher 91b955f6caSJeff Kirsher #include <asm/system.h> 92b955f6caSJeff Kirsher #include <asm/io.h> 93b955f6caSJeff Kirsher #include <asm/byteorder.h> 94b955f6caSJeff Kirsher #include <asm/uaccess.h> 95b955f6caSJeff Kirsher 96b955f6caSJeff Kirsher #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 97b955f6caSJeff Kirsher #define AMD8111E_VLAN_TAG_USED 1 98b955f6caSJeff Kirsher #else 99b955f6caSJeff Kirsher #define AMD8111E_VLAN_TAG_USED 0 100b955f6caSJeff Kirsher #endif 101b955f6caSJeff Kirsher 102b955f6caSJeff Kirsher #include "amd8111e.h" 103b955f6caSJeff Kirsher #define MODULE_NAME "amd8111e" 104b955f6caSJeff Kirsher #define MODULE_VERS "3.0.7" 105b955f6caSJeff Kirsher MODULE_AUTHOR("Advanced Micro Devices, Inc."); 106b955f6caSJeff Kirsher MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version "MODULE_VERS); 107b955f6caSJeff Kirsher MODULE_LICENSE("GPL"); 108b955f6caSJeff Kirsher MODULE_DEVICE_TABLE(pci, amd8111e_pci_tbl); 109b955f6caSJeff Kirsher module_param_array(speed_duplex, int, NULL, 0); 110b955f6caSJeff Kirsher MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotiate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex"); 111b955f6caSJeff Kirsher module_param_array(coalesce, bool, NULL, 0); 112b955f6caSJeff Kirsher MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable"); 113b955f6caSJeff Kirsher module_param_array(dynamic_ipg, bool, NULL, 0); 114b955f6caSJeff Kirsher MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable"); 115b955f6caSJeff Kirsher 116b955f6caSJeff Kirsher static DEFINE_PCI_DEVICE_TABLE(amd8111e_pci_tbl) = { 117b955f6caSJeff Kirsher 118b955f6caSJeff Kirsher { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462, 119b955f6caSJeff Kirsher PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 120b955f6caSJeff Kirsher { 0, } 121b955f6caSJeff Kirsher 122b955f6caSJeff Kirsher }; 123b955f6caSJeff Kirsher /* 124b955f6caSJeff Kirsher This function will read the PHY registers. 125b955f6caSJeff Kirsher */ 126b955f6caSJeff Kirsher static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val) 127b955f6caSJeff Kirsher { 128b955f6caSJeff Kirsher void __iomem *mmio = lp->mmio; 129b955f6caSJeff Kirsher unsigned int reg_val; 130b955f6caSJeff Kirsher unsigned int repeat= REPEAT_CNT; 131b955f6caSJeff Kirsher 132b955f6caSJeff Kirsher reg_val = readl(mmio + PHY_ACCESS); 133b955f6caSJeff Kirsher while (reg_val & PHY_CMD_ACTIVE) 134b955f6caSJeff Kirsher reg_val = readl( mmio + PHY_ACCESS ); 135b955f6caSJeff Kirsher 136b955f6caSJeff Kirsher writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) | 137b955f6caSJeff Kirsher ((reg & 0x1f) << 16), mmio +PHY_ACCESS); 138b955f6caSJeff Kirsher do{ 139b955f6caSJeff Kirsher reg_val = readl(mmio + PHY_ACCESS); 140b955f6caSJeff Kirsher udelay(30); /* It takes 30 us to read/write data */ 141b955f6caSJeff Kirsher } while (--repeat && (reg_val & PHY_CMD_ACTIVE)); 142b955f6caSJeff Kirsher if(reg_val & PHY_RD_ERR) 143b955f6caSJeff Kirsher goto err_phy_read; 144b955f6caSJeff Kirsher 145b955f6caSJeff Kirsher *val = reg_val & 0xffff; 146b955f6caSJeff Kirsher return 0; 147b955f6caSJeff Kirsher err_phy_read: 148b955f6caSJeff Kirsher *val = 0; 149b955f6caSJeff Kirsher return -EINVAL; 150b955f6caSJeff Kirsher 151b955f6caSJeff Kirsher } 152b955f6caSJeff Kirsher 153b955f6caSJeff Kirsher /* 154b955f6caSJeff Kirsher This function will write into PHY registers. 155b955f6caSJeff Kirsher */ 156b955f6caSJeff Kirsher static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val) 157b955f6caSJeff Kirsher { 158b955f6caSJeff Kirsher unsigned int repeat = REPEAT_CNT; 159b955f6caSJeff Kirsher void __iomem *mmio = lp->mmio; 160b955f6caSJeff Kirsher unsigned int reg_val; 161b955f6caSJeff Kirsher 162b955f6caSJeff Kirsher reg_val = readl(mmio + PHY_ACCESS); 163b955f6caSJeff Kirsher while (reg_val & PHY_CMD_ACTIVE) 164b955f6caSJeff Kirsher reg_val = readl( mmio + PHY_ACCESS ); 165b955f6caSJeff Kirsher 166b955f6caSJeff Kirsher writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) | 167b955f6caSJeff Kirsher ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS); 168b955f6caSJeff Kirsher 169b955f6caSJeff Kirsher do{ 170b955f6caSJeff Kirsher reg_val = readl(mmio + PHY_ACCESS); 171b955f6caSJeff Kirsher udelay(30); /* It takes 30 us to read/write the data */ 172b955f6caSJeff Kirsher } while (--repeat && (reg_val & PHY_CMD_ACTIVE)); 173b955f6caSJeff Kirsher 174b955f6caSJeff Kirsher if(reg_val & PHY_RD_ERR) 175b955f6caSJeff Kirsher goto err_phy_write; 176b955f6caSJeff Kirsher 177b955f6caSJeff Kirsher return 0; 178b955f6caSJeff Kirsher 179b955f6caSJeff Kirsher err_phy_write: 180b955f6caSJeff Kirsher return -EINVAL; 181b955f6caSJeff Kirsher 182b955f6caSJeff Kirsher } 183b955f6caSJeff Kirsher /* 184b955f6caSJeff Kirsher This is the mii register read function provided to the mii interface. 185b955f6caSJeff Kirsher */ 186b955f6caSJeff Kirsher static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num) 187b955f6caSJeff Kirsher { 188b955f6caSJeff Kirsher struct amd8111e_priv* lp = netdev_priv(dev); 189b955f6caSJeff Kirsher unsigned int reg_val; 190b955f6caSJeff Kirsher 191b955f6caSJeff Kirsher amd8111e_read_phy(lp,phy_id,reg_num,®_val); 192b955f6caSJeff Kirsher return reg_val; 193b955f6caSJeff Kirsher 194b955f6caSJeff Kirsher } 195b955f6caSJeff Kirsher 196b955f6caSJeff Kirsher /* 197b955f6caSJeff Kirsher This is the mii register write function provided to the mii interface. 198b955f6caSJeff Kirsher */ 199b955f6caSJeff Kirsher static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val) 200b955f6caSJeff Kirsher { 201b955f6caSJeff Kirsher struct amd8111e_priv* lp = netdev_priv(dev); 202b955f6caSJeff Kirsher 203b955f6caSJeff Kirsher amd8111e_write_phy(lp, phy_id, reg_num, val); 204b955f6caSJeff Kirsher } 205b955f6caSJeff Kirsher 206b955f6caSJeff Kirsher /* 207b955f6caSJeff Kirsher This function will set PHY speed. During initialization sets the original speed to 100 full. 208b955f6caSJeff Kirsher */ 209b955f6caSJeff Kirsher static void amd8111e_set_ext_phy(struct net_device *dev) 210b955f6caSJeff Kirsher { 211b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 212b955f6caSJeff Kirsher u32 bmcr,advert,tmp; 213b955f6caSJeff Kirsher 214b955f6caSJeff Kirsher /* Determine mii register values to set the speed */ 215b955f6caSJeff Kirsher advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE); 216b955f6caSJeff Kirsher tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4); 217b955f6caSJeff Kirsher switch (lp->ext_phy_option){ 218b955f6caSJeff Kirsher 219b955f6caSJeff Kirsher default: 220b955f6caSJeff Kirsher case SPEED_AUTONEG: /* advertise all values */ 221b955f6caSJeff Kirsher tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL| 222b955f6caSJeff Kirsher ADVERTISE_100HALF|ADVERTISE_100FULL) ; 223b955f6caSJeff Kirsher break; 224b955f6caSJeff Kirsher case SPEED10_HALF: 225b955f6caSJeff Kirsher tmp |= ADVERTISE_10HALF; 226b955f6caSJeff Kirsher break; 227b955f6caSJeff Kirsher case SPEED10_FULL: 228b955f6caSJeff Kirsher tmp |= ADVERTISE_10FULL; 229b955f6caSJeff Kirsher break; 230b955f6caSJeff Kirsher case SPEED100_HALF: 231b955f6caSJeff Kirsher tmp |= ADVERTISE_100HALF; 232b955f6caSJeff Kirsher break; 233b955f6caSJeff Kirsher case SPEED100_FULL: 234b955f6caSJeff Kirsher tmp |= ADVERTISE_100FULL; 235b955f6caSJeff Kirsher break; 236b955f6caSJeff Kirsher } 237b955f6caSJeff Kirsher 238b955f6caSJeff Kirsher if(advert != tmp) 239b955f6caSJeff Kirsher amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp); 240b955f6caSJeff Kirsher /* Restart auto negotiation */ 241b955f6caSJeff Kirsher bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR); 242b955f6caSJeff Kirsher bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 243b955f6caSJeff Kirsher amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr); 244b955f6caSJeff Kirsher 245b955f6caSJeff Kirsher } 246b955f6caSJeff Kirsher 247b955f6caSJeff Kirsher /* 248b955f6caSJeff Kirsher This function will unmap skb->data space and will free 249b955f6caSJeff Kirsher all transmit and receive skbuffs. 250b955f6caSJeff Kirsher */ 251b955f6caSJeff Kirsher static int amd8111e_free_skbs(struct net_device *dev) 252b955f6caSJeff Kirsher { 253b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 254b955f6caSJeff Kirsher struct sk_buff* rx_skbuff; 255b955f6caSJeff Kirsher int i; 256b955f6caSJeff Kirsher 257b955f6caSJeff Kirsher /* Freeing transmit skbs */ 258b955f6caSJeff Kirsher for(i = 0; i < NUM_TX_BUFFERS; i++){ 259b955f6caSJeff Kirsher if(lp->tx_skbuff[i]){ 260b955f6caSJeff Kirsher pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i], lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE); 261b955f6caSJeff Kirsher dev_kfree_skb (lp->tx_skbuff[i]); 262b955f6caSJeff Kirsher lp->tx_skbuff[i] = NULL; 263b955f6caSJeff Kirsher lp->tx_dma_addr[i] = 0; 264b955f6caSJeff Kirsher } 265b955f6caSJeff Kirsher } 266b955f6caSJeff Kirsher /* Freeing previously allocated receive buffers */ 267b955f6caSJeff Kirsher for (i = 0; i < NUM_RX_BUFFERS; i++){ 268b955f6caSJeff Kirsher rx_skbuff = lp->rx_skbuff[i]; 269b955f6caSJeff Kirsher if(rx_skbuff != NULL){ 270b955f6caSJeff Kirsher pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i], 271b955f6caSJeff Kirsher lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE); 272b955f6caSJeff Kirsher dev_kfree_skb(lp->rx_skbuff[i]); 273b955f6caSJeff Kirsher lp->rx_skbuff[i] = NULL; 274b955f6caSJeff Kirsher lp->rx_dma_addr[i] = 0; 275b955f6caSJeff Kirsher } 276b955f6caSJeff Kirsher } 277b955f6caSJeff Kirsher 278b955f6caSJeff Kirsher return 0; 279b955f6caSJeff Kirsher } 280b955f6caSJeff Kirsher 281b955f6caSJeff Kirsher /* 282b955f6caSJeff Kirsher This will set the receive buffer length corresponding to the mtu size of networkinterface. 283b955f6caSJeff Kirsher */ 284b955f6caSJeff Kirsher static inline void amd8111e_set_rx_buff_len(struct net_device* dev) 285b955f6caSJeff Kirsher { 286b955f6caSJeff Kirsher struct amd8111e_priv* lp = netdev_priv(dev); 287b955f6caSJeff Kirsher unsigned int mtu = dev->mtu; 288b955f6caSJeff Kirsher 289b955f6caSJeff Kirsher if (mtu > ETH_DATA_LEN){ 290b955f6caSJeff Kirsher /* MTU + ethernet header + FCS 291b955f6caSJeff Kirsher + optional VLAN tag + skb reserve space 2 */ 292b955f6caSJeff Kirsher 293b955f6caSJeff Kirsher lp->rx_buff_len = mtu + ETH_HLEN + 10; 294b955f6caSJeff Kirsher lp->options |= OPTION_JUMBO_ENABLE; 295b955f6caSJeff Kirsher } else{ 296b955f6caSJeff Kirsher lp->rx_buff_len = PKT_BUFF_SZ; 297b955f6caSJeff Kirsher lp->options &= ~OPTION_JUMBO_ENABLE; 298b955f6caSJeff Kirsher } 299b955f6caSJeff Kirsher } 300b955f6caSJeff Kirsher 301b955f6caSJeff Kirsher /* 302b955f6caSJeff Kirsher This function will free all the previously allocated buffers, determine new receive buffer length and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors. 303b955f6caSJeff Kirsher */ 304b955f6caSJeff Kirsher static int amd8111e_init_ring(struct net_device *dev) 305b955f6caSJeff Kirsher { 306b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 307b955f6caSJeff Kirsher int i; 308b955f6caSJeff Kirsher 309b955f6caSJeff Kirsher lp->rx_idx = lp->tx_idx = 0; 310b955f6caSJeff Kirsher lp->tx_complete_idx = 0; 311b955f6caSJeff Kirsher lp->tx_ring_idx = 0; 312b955f6caSJeff Kirsher 313b955f6caSJeff Kirsher 314b955f6caSJeff Kirsher if(lp->opened) 315b955f6caSJeff Kirsher /* Free previously allocated transmit and receive skbs */ 316b955f6caSJeff Kirsher amd8111e_free_skbs(dev); 317b955f6caSJeff Kirsher 318b955f6caSJeff Kirsher else{ 319b955f6caSJeff Kirsher /* allocate the tx and rx descriptors */ 320b955f6caSJeff Kirsher if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev, 321b955f6caSJeff Kirsher sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR, 322b955f6caSJeff Kirsher &lp->tx_ring_dma_addr)) == NULL) 323b955f6caSJeff Kirsher 324b955f6caSJeff Kirsher goto err_no_mem; 325b955f6caSJeff Kirsher 326b955f6caSJeff Kirsher if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev, 327b955f6caSJeff Kirsher sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR, 328b955f6caSJeff Kirsher &lp->rx_ring_dma_addr)) == NULL) 329b955f6caSJeff Kirsher 330b955f6caSJeff Kirsher goto err_free_tx_ring; 331b955f6caSJeff Kirsher 332b955f6caSJeff Kirsher } 333b955f6caSJeff Kirsher /* Set new receive buff size */ 334b955f6caSJeff Kirsher amd8111e_set_rx_buff_len(dev); 335b955f6caSJeff Kirsher 336b955f6caSJeff Kirsher /* Allocating receive skbs */ 337b955f6caSJeff Kirsher for (i = 0; i < NUM_RX_BUFFERS; i++) { 338b955f6caSJeff Kirsher 339b955f6caSJeff Kirsher if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) { 340b955f6caSJeff Kirsher /* Release previos allocated skbs */ 341b955f6caSJeff Kirsher for(--i; i >= 0 ;i--) 342b955f6caSJeff Kirsher dev_kfree_skb(lp->rx_skbuff[i]); 343b955f6caSJeff Kirsher goto err_free_rx_ring; 344b955f6caSJeff Kirsher } 345b955f6caSJeff Kirsher skb_reserve(lp->rx_skbuff[i],2); 346b955f6caSJeff Kirsher } 347b955f6caSJeff Kirsher /* Initilaizing receive descriptors */ 348b955f6caSJeff Kirsher for (i = 0; i < NUM_RX_BUFFERS; i++) { 349b955f6caSJeff Kirsher lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, 350b955f6caSJeff Kirsher lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE); 351b955f6caSJeff Kirsher 352b955f6caSJeff Kirsher lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]); 353b955f6caSJeff Kirsher lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2); 354b955f6caSJeff Kirsher wmb(); 355b955f6caSJeff Kirsher lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT); 356b955f6caSJeff Kirsher } 357b955f6caSJeff Kirsher 358b955f6caSJeff Kirsher /* Initializing transmit descriptors */ 359b955f6caSJeff Kirsher for (i = 0; i < NUM_TX_RING_DR; i++) { 360b955f6caSJeff Kirsher lp->tx_ring[i].buff_phy_addr = 0; 361b955f6caSJeff Kirsher lp->tx_ring[i].tx_flags = 0; 362b955f6caSJeff Kirsher lp->tx_ring[i].buff_count = 0; 363b955f6caSJeff Kirsher } 364b955f6caSJeff Kirsher 365b955f6caSJeff Kirsher return 0; 366b955f6caSJeff Kirsher 367b955f6caSJeff Kirsher err_free_rx_ring: 368b955f6caSJeff Kirsher 369b955f6caSJeff Kirsher pci_free_consistent(lp->pci_dev, 370b955f6caSJeff Kirsher sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring, 371b955f6caSJeff Kirsher lp->rx_ring_dma_addr); 372b955f6caSJeff Kirsher 373b955f6caSJeff Kirsher err_free_tx_ring: 374b955f6caSJeff Kirsher 375b955f6caSJeff Kirsher pci_free_consistent(lp->pci_dev, 376b955f6caSJeff Kirsher sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring, 377b955f6caSJeff Kirsher lp->tx_ring_dma_addr); 378b955f6caSJeff Kirsher 379b955f6caSJeff Kirsher err_no_mem: 380b955f6caSJeff Kirsher return -ENOMEM; 381b955f6caSJeff Kirsher } 382b955f6caSJeff Kirsher /* This function will set the interrupt coalescing according to the input arguments */ 383b955f6caSJeff Kirsher static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod) 384b955f6caSJeff Kirsher { 385b955f6caSJeff Kirsher unsigned int timeout; 386b955f6caSJeff Kirsher unsigned int event_count; 387b955f6caSJeff Kirsher 388b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 389b955f6caSJeff Kirsher void __iomem *mmio = lp->mmio; 390b955f6caSJeff Kirsher struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf; 391b955f6caSJeff Kirsher 392b955f6caSJeff Kirsher 393b955f6caSJeff Kirsher switch(cmod) 394b955f6caSJeff Kirsher { 395b955f6caSJeff Kirsher case RX_INTR_COAL : 396b955f6caSJeff Kirsher timeout = coal_conf->rx_timeout; 397b955f6caSJeff Kirsher event_count = coal_conf->rx_event_count; 398b955f6caSJeff Kirsher if( timeout > MAX_TIMEOUT || 399b955f6caSJeff Kirsher event_count > MAX_EVENT_COUNT ) 400b955f6caSJeff Kirsher return -EINVAL; 401b955f6caSJeff Kirsher 402b955f6caSJeff Kirsher timeout = timeout * DELAY_TIMER_CONV; 403b955f6caSJeff Kirsher writel(VAL0|STINTEN, mmio+INTEN0); 404b955f6caSJeff Kirsher writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout, 405b955f6caSJeff Kirsher mmio+DLY_INT_A); 406b955f6caSJeff Kirsher break; 407b955f6caSJeff Kirsher 408b955f6caSJeff Kirsher case TX_INTR_COAL : 409b955f6caSJeff Kirsher timeout = coal_conf->tx_timeout; 410b955f6caSJeff Kirsher event_count = coal_conf->tx_event_count; 411b955f6caSJeff Kirsher if( timeout > MAX_TIMEOUT || 412b955f6caSJeff Kirsher event_count > MAX_EVENT_COUNT ) 413b955f6caSJeff Kirsher return -EINVAL; 414b955f6caSJeff Kirsher 415b955f6caSJeff Kirsher 416b955f6caSJeff Kirsher timeout = timeout * DELAY_TIMER_CONV; 417b955f6caSJeff Kirsher writel(VAL0|STINTEN,mmio+INTEN0); 418b955f6caSJeff Kirsher writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout, 419b955f6caSJeff Kirsher mmio+DLY_INT_B); 420b955f6caSJeff Kirsher break; 421b955f6caSJeff Kirsher 422b955f6caSJeff Kirsher case DISABLE_COAL: 423b955f6caSJeff Kirsher writel(0,mmio+STVAL); 424b955f6caSJeff Kirsher writel(STINTEN, mmio+INTEN0); 425b955f6caSJeff Kirsher writel(0, mmio +DLY_INT_B); 426b955f6caSJeff Kirsher writel(0, mmio+DLY_INT_A); 427b955f6caSJeff Kirsher break; 428b955f6caSJeff Kirsher case ENABLE_COAL: 429b955f6caSJeff Kirsher /* Start the timer */ 430b955f6caSJeff Kirsher writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */ 431b955f6caSJeff Kirsher writel(VAL0|STINTEN, mmio+INTEN0); 432b955f6caSJeff Kirsher break; 433b955f6caSJeff Kirsher default: 434b955f6caSJeff Kirsher break; 435b955f6caSJeff Kirsher 436b955f6caSJeff Kirsher } 437b955f6caSJeff Kirsher return 0; 438b955f6caSJeff Kirsher 439b955f6caSJeff Kirsher } 440b955f6caSJeff Kirsher 441b955f6caSJeff Kirsher /* 442b955f6caSJeff Kirsher This function initializes the device registers and starts the device. 443b955f6caSJeff Kirsher */ 444b955f6caSJeff Kirsher static int amd8111e_restart(struct net_device *dev) 445b955f6caSJeff Kirsher { 446b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 447b955f6caSJeff Kirsher void __iomem *mmio = lp->mmio; 448b955f6caSJeff Kirsher int i,reg_val; 449b955f6caSJeff Kirsher 450b955f6caSJeff Kirsher /* stop the chip */ 451b955f6caSJeff Kirsher writel(RUN, mmio + CMD0); 452b955f6caSJeff Kirsher 453b955f6caSJeff Kirsher if(amd8111e_init_ring(dev)) 454b955f6caSJeff Kirsher return -ENOMEM; 455b955f6caSJeff Kirsher 456b955f6caSJeff Kirsher /* enable the port manager and set auto negotiation always */ 457b955f6caSJeff Kirsher writel((u32) VAL1|EN_PMGR, mmio + CMD3 ); 458b955f6caSJeff Kirsher writel((u32)XPHYANE|XPHYRST , mmio + CTRL2); 459b955f6caSJeff Kirsher 460b955f6caSJeff Kirsher amd8111e_set_ext_phy(dev); 461b955f6caSJeff Kirsher 462b955f6caSJeff Kirsher /* set control registers */ 463b955f6caSJeff Kirsher reg_val = readl(mmio + CTRL1); 464b955f6caSJeff Kirsher reg_val &= ~XMTSP_MASK; 465b955f6caSJeff Kirsher writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 ); 466b955f6caSJeff Kirsher 467b955f6caSJeff Kirsher /* enable interrupt */ 468b955f6caSJeff Kirsher writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN | 469b955f6caSJeff Kirsher APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN | 470b955f6caSJeff Kirsher SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0); 471b955f6caSJeff Kirsher 472b955f6caSJeff Kirsher writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0); 473b955f6caSJeff Kirsher 474b955f6caSJeff Kirsher /* initialize tx and rx ring base addresses */ 475b955f6caSJeff Kirsher writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0); 476b955f6caSJeff Kirsher writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0); 477b955f6caSJeff Kirsher 478b955f6caSJeff Kirsher writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0); 479b955f6caSJeff Kirsher writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0); 480b955f6caSJeff Kirsher 481b955f6caSJeff Kirsher /* set default IPG to 96 */ 482b955f6caSJeff Kirsher writew((u32)DEFAULT_IPG,mmio+IPG); 483b955f6caSJeff Kirsher writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1); 484b955f6caSJeff Kirsher 485b955f6caSJeff Kirsher if(lp->options & OPTION_JUMBO_ENABLE){ 486b955f6caSJeff Kirsher writel((u32)VAL2|JUMBO, mmio + CMD3); 487b955f6caSJeff Kirsher /* Reset REX_UFLO */ 488b955f6caSJeff Kirsher writel( REX_UFLO, mmio + CMD2); 489b955f6caSJeff Kirsher /* Should not set REX_UFLO for jumbo frames */ 490b955f6caSJeff Kirsher writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2); 491b955f6caSJeff Kirsher }else{ 492b955f6caSJeff Kirsher writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2); 493b955f6caSJeff Kirsher writel((u32)JUMBO, mmio + CMD3); 494b955f6caSJeff Kirsher } 495b955f6caSJeff Kirsher 496b955f6caSJeff Kirsher #if AMD8111E_VLAN_TAG_USED 497b955f6caSJeff Kirsher writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3); 498b955f6caSJeff Kirsher #endif 499b955f6caSJeff Kirsher writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 ); 500b955f6caSJeff Kirsher 501b955f6caSJeff Kirsher /* Setting the MAC address to the device */ 502c857ff6eSJoe Perches for (i = 0; i < ETH_ALEN; i++) 503b955f6caSJeff Kirsher writeb( dev->dev_addr[i], mmio + PADR + i ); 504b955f6caSJeff Kirsher 505b955f6caSJeff Kirsher /* Enable interrupt coalesce */ 506b955f6caSJeff Kirsher if(lp->options & OPTION_INTR_COAL_ENABLE){ 507b955f6caSJeff Kirsher printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n", 508b955f6caSJeff Kirsher dev->name); 509b955f6caSJeff Kirsher amd8111e_set_coalesce(dev,ENABLE_COAL); 510b955f6caSJeff Kirsher } 511b955f6caSJeff Kirsher 512b955f6caSJeff Kirsher /* set RUN bit to start the chip */ 513b955f6caSJeff Kirsher writel(VAL2 | RDMD0, mmio + CMD0); 514b955f6caSJeff Kirsher writel(VAL0 | INTREN | RUN, mmio + CMD0); 515b955f6caSJeff Kirsher 516b955f6caSJeff Kirsher /* To avoid PCI posting bug */ 517b955f6caSJeff Kirsher readl(mmio+CMD0); 518b955f6caSJeff Kirsher return 0; 519b955f6caSJeff Kirsher } 520b955f6caSJeff Kirsher /* 521b955f6caSJeff Kirsher This function clears necessary the device registers. 522b955f6caSJeff Kirsher */ 523b955f6caSJeff Kirsher static void amd8111e_init_hw_default( struct amd8111e_priv* lp) 524b955f6caSJeff Kirsher { 525b955f6caSJeff Kirsher unsigned int reg_val; 526b955f6caSJeff Kirsher unsigned int logic_filter[2] ={0,}; 527b955f6caSJeff Kirsher void __iomem *mmio = lp->mmio; 528b955f6caSJeff Kirsher 529b955f6caSJeff Kirsher 530b955f6caSJeff Kirsher /* stop the chip */ 531b955f6caSJeff Kirsher writel(RUN, mmio + CMD0); 532b955f6caSJeff Kirsher 533b955f6caSJeff Kirsher /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */ 534b955f6caSJeff Kirsher writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0); 535b955f6caSJeff Kirsher 536b955f6caSJeff Kirsher /* Clear RCV_RING_BASE_ADDR */ 537b955f6caSJeff Kirsher writel(0, mmio + RCV_RING_BASE_ADDR0); 538b955f6caSJeff Kirsher 539b955f6caSJeff Kirsher /* Clear XMT_RING_BASE_ADDR */ 540b955f6caSJeff Kirsher writel(0, mmio + XMT_RING_BASE_ADDR0); 541b955f6caSJeff Kirsher writel(0, mmio + XMT_RING_BASE_ADDR1); 542b955f6caSJeff Kirsher writel(0, mmio + XMT_RING_BASE_ADDR2); 543b955f6caSJeff Kirsher writel(0, mmio + XMT_RING_BASE_ADDR3); 544b955f6caSJeff Kirsher 545b955f6caSJeff Kirsher /* Clear CMD0 */ 546b955f6caSJeff Kirsher writel(CMD0_CLEAR,mmio + CMD0); 547b955f6caSJeff Kirsher 548b955f6caSJeff Kirsher /* Clear CMD2 */ 549b955f6caSJeff Kirsher writel(CMD2_CLEAR, mmio +CMD2); 550b955f6caSJeff Kirsher 551b955f6caSJeff Kirsher /* Clear CMD7 */ 552b955f6caSJeff Kirsher writel(CMD7_CLEAR , mmio + CMD7); 553b955f6caSJeff Kirsher 554b955f6caSJeff Kirsher /* Clear DLY_INT_A and DLY_INT_B */ 555b955f6caSJeff Kirsher writel(0x0, mmio + DLY_INT_A); 556b955f6caSJeff Kirsher writel(0x0, mmio + DLY_INT_B); 557b955f6caSJeff Kirsher 558b955f6caSJeff Kirsher /* Clear FLOW_CONTROL */ 559b955f6caSJeff Kirsher writel(0x0, mmio + FLOW_CONTROL); 560b955f6caSJeff Kirsher 561b955f6caSJeff Kirsher /* Clear INT0 write 1 to clear register */ 562b955f6caSJeff Kirsher reg_val = readl(mmio + INT0); 563b955f6caSJeff Kirsher writel(reg_val, mmio + INT0); 564b955f6caSJeff Kirsher 565b955f6caSJeff Kirsher /* Clear STVAL */ 566b955f6caSJeff Kirsher writel(0x0, mmio + STVAL); 567b955f6caSJeff Kirsher 568b955f6caSJeff Kirsher /* Clear INTEN0 */ 569b955f6caSJeff Kirsher writel( INTEN0_CLEAR, mmio + INTEN0); 570b955f6caSJeff Kirsher 571b955f6caSJeff Kirsher /* Clear LADRF */ 572b955f6caSJeff Kirsher writel(0x0 , mmio + LADRF); 573b955f6caSJeff Kirsher 574b955f6caSJeff Kirsher /* Set SRAM_SIZE & SRAM_BOUNDARY registers */ 575b955f6caSJeff Kirsher writel( 0x80010,mmio + SRAM_SIZE); 576b955f6caSJeff Kirsher 577b955f6caSJeff Kirsher /* Clear RCV_RING0_LEN */ 578b955f6caSJeff Kirsher writel(0x0, mmio + RCV_RING_LEN0); 579b955f6caSJeff Kirsher 580b955f6caSJeff Kirsher /* Clear XMT_RING0/1/2/3_LEN */ 581b955f6caSJeff Kirsher writel(0x0, mmio + XMT_RING_LEN0); 582b955f6caSJeff Kirsher writel(0x0, mmio + XMT_RING_LEN1); 583b955f6caSJeff Kirsher writel(0x0, mmio + XMT_RING_LEN2); 584b955f6caSJeff Kirsher writel(0x0, mmio + XMT_RING_LEN3); 585b955f6caSJeff Kirsher 586b955f6caSJeff Kirsher /* Clear XMT_RING_LIMIT */ 587b955f6caSJeff Kirsher writel(0x0, mmio + XMT_RING_LIMIT); 588b955f6caSJeff Kirsher 589b955f6caSJeff Kirsher /* Clear MIB */ 590b955f6caSJeff Kirsher writew(MIB_CLEAR, mmio + MIB_ADDR); 591b955f6caSJeff Kirsher 592b955f6caSJeff Kirsher /* Clear LARF */ 593b955f6caSJeff Kirsher amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF); 594b955f6caSJeff Kirsher 595b955f6caSJeff Kirsher /* SRAM_SIZE register */ 596b955f6caSJeff Kirsher reg_val = readl(mmio + SRAM_SIZE); 597b955f6caSJeff Kirsher 598b955f6caSJeff Kirsher if(lp->options & OPTION_JUMBO_ENABLE) 599b955f6caSJeff Kirsher writel( VAL2|JUMBO, mmio + CMD3); 600b955f6caSJeff Kirsher #if AMD8111E_VLAN_TAG_USED 601b955f6caSJeff Kirsher writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 ); 602b955f6caSJeff Kirsher #endif 603b955f6caSJeff Kirsher /* Set default value to CTRL1 Register */ 604b955f6caSJeff Kirsher writel(CTRL1_DEFAULT, mmio + CTRL1); 605b955f6caSJeff Kirsher 606b955f6caSJeff Kirsher /* To avoid PCI posting bug */ 607b955f6caSJeff Kirsher readl(mmio + CMD2); 608b955f6caSJeff Kirsher 609b955f6caSJeff Kirsher } 610b955f6caSJeff Kirsher 611b955f6caSJeff Kirsher /* 612b955f6caSJeff Kirsher This function disables the interrupt and clears all the pending 613b955f6caSJeff Kirsher interrupts in INT0 614b955f6caSJeff Kirsher */ 615b955f6caSJeff Kirsher static void amd8111e_disable_interrupt(struct amd8111e_priv* lp) 616b955f6caSJeff Kirsher { 617b955f6caSJeff Kirsher u32 intr0; 618b955f6caSJeff Kirsher 619b955f6caSJeff Kirsher /* Disable interrupt */ 620b955f6caSJeff Kirsher writel(INTREN, lp->mmio + CMD0); 621b955f6caSJeff Kirsher 622b955f6caSJeff Kirsher /* Clear INT0 */ 623b955f6caSJeff Kirsher intr0 = readl(lp->mmio + INT0); 624b955f6caSJeff Kirsher writel(intr0, lp->mmio + INT0); 625b955f6caSJeff Kirsher 626b955f6caSJeff Kirsher /* To avoid PCI posting bug */ 627b955f6caSJeff Kirsher readl(lp->mmio + INT0); 628b955f6caSJeff Kirsher 629b955f6caSJeff Kirsher } 630b955f6caSJeff Kirsher 631b955f6caSJeff Kirsher /* 632b955f6caSJeff Kirsher This function stops the chip. 633b955f6caSJeff Kirsher */ 634b955f6caSJeff Kirsher static void amd8111e_stop_chip(struct amd8111e_priv* lp) 635b955f6caSJeff Kirsher { 636b955f6caSJeff Kirsher writel(RUN, lp->mmio + CMD0); 637b955f6caSJeff Kirsher 638b955f6caSJeff Kirsher /* To avoid PCI posting bug */ 639b955f6caSJeff Kirsher readl(lp->mmio + CMD0); 640b955f6caSJeff Kirsher } 641b955f6caSJeff Kirsher 642b955f6caSJeff Kirsher /* 643b955f6caSJeff Kirsher This function frees the transmiter and receiver descriptor rings. 644b955f6caSJeff Kirsher */ 645b955f6caSJeff Kirsher static void amd8111e_free_ring(struct amd8111e_priv* lp) 646b955f6caSJeff Kirsher { 647b955f6caSJeff Kirsher /* Free transmit and receive descriptor rings */ 648b955f6caSJeff Kirsher if(lp->rx_ring){ 649b955f6caSJeff Kirsher pci_free_consistent(lp->pci_dev, 650b955f6caSJeff Kirsher sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR, 651b955f6caSJeff Kirsher lp->rx_ring, lp->rx_ring_dma_addr); 652b955f6caSJeff Kirsher lp->rx_ring = NULL; 653b955f6caSJeff Kirsher } 654b955f6caSJeff Kirsher 655b955f6caSJeff Kirsher if(lp->tx_ring){ 656b955f6caSJeff Kirsher pci_free_consistent(lp->pci_dev, 657b955f6caSJeff Kirsher sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR, 658b955f6caSJeff Kirsher lp->tx_ring, lp->tx_ring_dma_addr); 659b955f6caSJeff Kirsher 660b955f6caSJeff Kirsher lp->tx_ring = NULL; 661b955f6caSJeff Kirsher } 662b955f6caSJeff Kirsher 663b955f6caSJeff Kirsher } 664b955f6caSJeff Kirsher 665b955f6caSJeff Kirsher /* 666b955f6caSJeff Kirsher This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb. 667b955f6caSJeff Kirsher */ 668b955f6caSJeff Kirsher static int amd8111e_tx(struct net_device *dev) 669b955f6caSJeff Kirsher { 670b955f6caSJeff Kirsher struct amd8111e_priv* lp = netdev_priv(dev); 671b955f6caSJeff Kirsher int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK; 672b955f6caSJeff Kirsher int status; 673b955f6caSJeff Kirsher /* Complete all the transmit packet */ 674b955f6caSJeff Kirsher while (lp->tx_complete_idx != lp->tx_idx){ 675b955f6caSJeff Kirsher tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK; 676b955f6caSJeff Kirsher status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags); 677b955f6caSJeff Kirsher 678b955f6caSJeff Kirsher if(status & OWN_BIT) 679b955f6caSJeff Kirsher break; /* It still hasn't been Txed */ 680b955f6caSJeff Kirsher 681b955f6caSJeff Kirsher lp->tx_ring[tx_index].buff_phy_addr = 0; 682b955f6caSJeff Kirsher 683b955f6caSJeff Kirsher /* We must free the original skb */ 684b955f6caSJeff Kirsher if (lp->tx_skbuff[tx_index]) { 685b955f6caSJeff Kirsher pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index], 686b955f6caSJeff Kirsher lp->tx_skbuff[tx_index]->len, 687b955f6caSJeff Kirsher PCI_DMA_TODEVICE); 688b955f6caSJeff Kirsher dev_kfree_skb_irq (lp->tx_skbuff[tx_index]); 689b955f6caSJeff Kirsher lp->tx_skbuff[tx_index] = NULL; 690b955f6caSJeff Kirsher lp->tx_dma_addr[tx_index] = 0; 691b955f6caSJeff Kirsher } 692b955f6caSJeff Kirsher lp->tx_complete_idx++; 693b955f6caSJeff Kirsher /*COAL update tx coalescing parameters */ 694b955f6caSJeff Kirsher lp->coal_conf.tx_packets++; 695b955f6caSJeff Kirsher lp->coal_conf.tx_bytes += 696b955f6caSJeff Kirsher le16_to_cpu(lp->tx_ring[tx_index].buff_count); 697b955f6caSJeff Kirsher 698b955f6caSJeff Kirsher if (netif_queue_stopped(dev) && 699b955f6caSJeff Kirsher lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){ 700b955f6caSJeff Kirsher /* The ring is no longer full, clear tbusy. */ 701b955f6caSJeff Kirsher /* lp->tx_full = 0; */ 702b955f6caSJeff Kirsher netif_wake_queue (dev); 703b955f6caSJeff Kirsher } 704b955f6caSJeff Kirsher } 705b955f6caSJeff Kirsher return 0; 706b955f6caSJeff Kirsher } 707b955f6caSJeff Kirsher 708b955f6caSJeff Kirsher /* This function handles the driver receive operation in polling mode */ 709b955f6caSJeff Kirsher static int amd8111e_rx_poll(struct napi_struct *napi, int budget) 710b955f6caSJeff Kirsher { 711b955f6caSJeff Kirsher struct amd8111e_priv *lp = container_of(napi, struct amd8111e_priv, napi); 712b955f6caSJeff Kirsher struct net_device *dev = lp->amd8111e_net_dev; 713b955f6caSJeff Kirsher int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK; 714b955f6caSJeff Kirsher void __iomem *mmio = lp->mmio; 715b955f6caSJeff Kirsher struct sk_buff *skb,*new_skb; 716b955f6caSJeff Kirsher int min_pkt_len, status; 717b955f6caSJeff Kirsher unsigned int intr0; 718b955f6caSJeff Kirsher int num_rx_pkt = 0; 719b955f6caSJeff Kirsher short pkt_len; 720b955f6caSJeff Kirsher #if AMD8111E_VLAN_TAG_USED 721b955f6caSJeff Kirsher short vtag; 722b955f6caSJeff Kirsher #endif 723b955f6caSJeff Kirsher int rx_pkt_limit = budget; 724b955f6caSJeff Kirsher unsigned long flags; 725b955f6caSJeff Kirsher 726b955f6caSJeff Kirsher do{ 727b955f6caSJeff Kirsher /* process receive packets until we use the quota*/ 728b955f6caSJeff Kirsher /* If we own the next entry, it's a new packet. Send it up. */ 729b955f6caSJeff Kirsher while(1) { 730b955f6caSJeff Kirsher status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags); 731b955f6caSJeff Kirsher if (status & OWN_BIT) 732b955f6caSJeff Kirsher break; 733b955f6caSJeff Kirsher 734b955f6caSJeff Kirsher /* 735b955f6caSJeff Kirsher * There is a tricky error noted by John Murphy, 736b955f6caSJeff Kirsher * <murf@perftech.com> to Russ Nelson: Even with 737b955f6caSJeff Kirsher * full-sized * buffers it's possible for a 738b955f6caSJeff Kirsher * jabber packet to use two buffers, with only 739b955f6caSJeff Kirsher * the last correctly noting the error. 740b955f6caSJeff Kirsher */ 741b955f6caSJeff Kirsher 742b955f6caSJeff Kirsher if(status & ERR_BIT) { 743b955f6caSJeff Kirsher /* reseting flags */ 744b955f6caSJeff Kirsher lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; 745b955f6caSJeff Kirsher goto err_next_pkt; 746b955f6caSJeff Kirsher } 747b955f6caSJeff Kirsher /* check for STP and ENP */ 748b955f6caSJeff Kirsher if(!((status & STP_BIT) && (status & ENP_BIT))){ 749b955f6caSJeff Kirsher /* reseting flags */ 750b955f6caSJeff Kirsher lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; 751b955f6caSJeff Kirsher goto err_next_pkt; 752b955f6caSJeff Kirsher } 753b955f6caSJeff Kirsher pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4; 754b955f6caSJeff Kirsher 755b955f6caSJeff Kirsher #if AMD8111E_VLAN_TAG_USED 756b955f6caSJeff Kirsher vtag = status & TT_MASK; 757b955f6caSJeff Kirsher /*MAC will strip vlan tag*/ 758b955f6caSJeff Kirsher if (vtag != 0) 759b955f6caSJeff Kirsher min_pkt_len =MIN_PKT_LEN - 4; 760b955f6caSJeff Kirsher else 761b955f6caSJeff Kirsher #endif 762b955f6caSJeff Kirsher min_pkt_len =MIN_PKT_LEN; 763b955f6caSJeff Kirsher 764b955f6caSJeff Kirsher if (pkt_len < min_pkt_len) { 765b955f6caSJeff Kirsher lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; 766b955f6caSJeff Kirsher lp->drv_rx_errors++; 767b955f6caSJeff Kirsher goto err_next_pkt; 768b955f6caSJeff Kirsher } 769b955f6caSJeff Kirsher if(--rx_pkt_limit < 0) 770b955f6caSJeff Kirsher goto rx_not_empty; 771b955f6caSJeff Kirsher if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){ 772b955f6caSJeff Kirsher /* if allocation fail, 773b955f6caSJeff Kirsher ignore that pkt and go to next one */ 774b955f6caSJeff Kirsher lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS; 775b955f6caSJeff Kirsher lp->drv_rx_errors++; 776b955f6caSJeff Kirsher goto err_next_pkt; 777b955f6caSJeff Kirsher } 778b955f6caSJeff Kirsher 779b955f6caSJeff Kirsher skb_reserve(new_skb, 2); 780b955f6caSJeff Kirsher skb = lp->rx_skbuff[rx_index]; 781b955f6caSJeff Kirsher pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index], 782b955f6caSJeff Kirsher lp->rx_buff_len-2, PCI_DMA_FROMDEVICE); 783b955f6caSJeff Kirsher skb_put(skb, pkt_len); 784b955f6caSJeff Kirsher lp->rx_skbuff[rx_index] = new_skb; 785b955f6caSJeff Kirsher lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev, 786b955f6caSJeff Kirsher new_skb->data, 787b955f6caSJeff Kirsher lp->rx_buff_len-2, 788b955f6caSJeff Kirsher PCI_DMA_FROMDEVICE); 789b955f6caSJeff Kirsher 790b955f6caSJeff Kirsher skb->protocol = eth_type_trans(skb, dev); 791b955f6caSJeff Kirsher 792b955f6caSJeff Kirsher #if AMD8111E_VLAN_TAG_USED 793b955f6caSJeff Kirsher if (vtag == TT_VLAN_TAGGED){ 794b955f6caSJeff Kirsher u16 vlan_tag = le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info); 795b955f6caSJeff Kirsher __vlan_hwaccel_put_tag(skb, vlan_tag); 796b955f6caSJeff Kirsher } 797b955f6caSJeff Kirsher #endif 798b955f6caSJeff Kirsher netif_receive_skb(skb); 799b955f6caSJeff Kirsher /*COAL update rx coalescing parameters*/ 800b955f6caSJeff Kirsher lp->coal_conf.rx_packets++; 801b955f6caSJeff Kirsher lp->coal_conf.rx_bytes += pkt_len; 802b955f6caSJeff Kirsher num_rx_pkt++; 803b955f6caSJeff Kirsher 804b955f6caSJeff Kirsher err_next_pkt: 805b955f6caSJeff Kirsher lp->rx_ring[rx_index].buff_phy_addr 806b955f6caSJeff Kirsher = cpu_to_le32(lp->rx_dma_addr[rx_index]); 807b955f6caSJeff Kirsher lp->rx_ring[rx_index].buff_count = 808b955f6caSJeff Kirsher cpu_to_le16(lp->rx_buff_len-2); 809b955f6caSJeff Kirsher wmb(); 810b955f6caSJeff Kirsher lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT); 811b955f6caSJeff Kirsher rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK; 812b955f6caSJeff Kirsher } 813b955f6caSJeff Kirsher /* Check the interrupt status register for more packets in the 814b955f6caSJeff Kirsher mean time. Process them since we have not used up our quota.*/ 815b955f6caSJeff Kirsher 816b955f6caSJeff Kirsher intr0 = readl(mmio + INT0); 817b955f6caSJeff Kirsher /*Ack receive packets */ 818b955f6caSJeff Kirsher writel(intr0 & RINT0,mmio + INT0); 819b955f6caSJeff Kirsher 820b955f6caSJeff Kirsher } while(intr0 & RINT0); 821b955f6caSJeff Kirsher 822b955f6caSJeff Kirsher if (rx_pkt_limit > 0) { 823b955f6caSJeff Kirsher /* Receive descriptor is empty now */ 824b955f6caSJeff Kirsher spin_lock_irqsave(&lp->lock, flags); 825b955f6caSJeff Kirsher __napi_complete(napi); 826b955f6caSJeff Kirsher writel(VAL0|RINTEN0, mmio + INTEN0); 827b955f6caSJeff Kirsher writel(VAL2 | RDMD0, mmio + CMD0); 828b955f6caSJeff Kirsher spin_unlock_irqrestore(&lp->lock, flags); 829b955f6caSJeff Kirsher } 830b955f6caSJeff Kirsher 831b955f6caSJeff Kirsher rx_not_empty: 832b955f6caSJeff Kirsher return num_rx_pkt; 833b955f6caSJeff Kirsher } 834b955f6caSJeff Kirsher 835b955f6caSJeff Kirsher /* 836b955f6caSJeff Kirsher This function will indicate the link status to the kernel. 837b955f6caSJeff Kirsher */ 838b955f6caSJeff Kirsher static int amd8111e_link_change(struct net_device* dev) 839b955f6caSJeff Kirsher { 840b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 841b955f6caSJeff Kirsher int status0,speed; 842b955f6caSJeff Kirsher 843b955f6caSJeff Kirsher /* read the link change */ 844b955f6caSJeff Kirsher status0 = readl(lp->mmio + STAT0); 845b955f6caSJeff Kirsher 846b955f6caSJeff Kirsher if(status0 & LINK_STATS){ 847b955f6caSJeff Kirsher if(status0 & AUTONEG_COMPLETE) 848b955f6caSJeff Kirsher lp->link_config.autoneg = AUTONEG_ENABLE; 849b955f6caSJeff Kirsher else 850b955f6caSJeff Kirsher lp->link_config.autoneg = AUTONEG_DISABLE; 851b955f6caSJeff Kirsher 852b955f6caSJeff Kirsher if(status0 & FULL_DPLX) 853b955f6caSJeff Kirsher lp->link_config.duplex = DUPLEX_FULL; 854b955f6caSJeff Kirsher else 855b955f6caSJeff Kirsher lp->link_config.duplex = DUPLEX_HALF; 856b955f6caSJeff Kirsher speed = (status0 & SPEED_MASK) >> 7; 857b955f6caSJeff Kirsher if(speed == PHY_SPEED_10) 858b955f6caSJeff Kirsher lp->link_config.speed = SPEED_10; 859b955f6caSJeff Kirsher else if(speed == PHY_SPEED_100) 860b955f6caSJeff Kirsher lp->link_config.speed = SPEED_100; 861b955f6caSJeff Kirsher 862b955f6caSJeff Kirsher printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n", dev->name, 863b955f6caSJeff Kirsher (lp->link_config.speed == SPEED_100) ? "100": "10", 864b955f6caSJeff Kirsher (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half"); 865b955f6caSJeff Kirsher netif_carrier_on(dev); 866b955f6caSJeff Kirsher } 867b955f6caSJeff Kirsher else{ 868b955f6caSJeff Kirsher lp->link_config.speed = SPEED_INVALID; 869b955f6caSJeff Kirsher lp->link_config.duplex = DUPLEX_INVALID; 870b955f6caSJeff Kirsher lp->link_config.autoneg = AUTONEG_INVALID; 871b955f6caSJeff Kirsher printk(KERN_INFO "%s: Link is Down.\n",dev->name); 872b955f6caSJeff Kirsher netif_carrier_off(dev); 873b955f6caSJeff Kirsher } 874b955f6caSJeff Kirsher 875b955f6caSJeff Kirsher return 0; 876b955f6caSJeff Kirsher } 877b955f6caSJeff Kirsher /* 878b955f6caSJeff Kirsher This function reads the mib counters. 879b955f6caSJeff Kirsher */ 880b955f6caSJeff Kirsher static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER) 881b955f6caSJeff Kirsher { 882b955f6caSJeff Kirsher unsigned int status; 883b955f6caSJeff Kirsher unsigned int data; 884b955f6caSJeff Kirsher unsigned int repeat = REPEAT_CNT; 885b955f6caSJeff Kirsher 886b955f6caSJeff Kirsher writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR); 887b955f6caSJeff Kirsher do { 888b955f6caSJeff Kirsher status = readw(mmio + MIB_ADDR); 889b955f6caSJeff Kirsher udelay(2); /* controller takes MAX 2 us to get mib data */ 890b955f6caSJeff Kirsher } 891b955f6caSJeff Kirsher while (--repeat && (status & MIB_CMD_ACTIVE)); 892b955f6caSJeff Kirsher 893b955f6caSJeff Kirsher data = readl(mmio + MIB_DATA); 894b955f6caSJeff Kirsher return data; 895b955f6caSJeff Kirsher } 896b955f6caSJeff Kirsher 897b955f6caSJeff Kirsher /* 898b955f6caSJeff Kirsher * This function reads the mib registers and returns the hardware statistics. 899b955f6caSJeff Kirsher * It updates previous internal driver statistics with new values. 900b955f6caSJeff Kirsher */ 901b955f6caSJeff Kirsher static struct net_device_stats *amd8111e_get_stats(struct net_device *dev) 902b955f6caSJeff Kirsher { 903b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 904b955f6caSJeff Kirsher void __iomem *mmio = lp->mmio; 905b955f6caSJeff Kirsher unsigned long flags; 906b955f6caSJeff Kirsher struct net_device_stats *new_stats = &dev->stats; 907b955f6caSJeff Kirsher 908b955f6caSJeff Kirsher if (!lp->opened) 909b955f6caSJeff Kirsher return new_stats; 910b955f6caSJeff Kirsher spin_lock_irqsave (&lp->lock, flags); 911b955f6caSJeff Kirsher 912b955f6caSJeff Kirsher /* stats.rx_packets */ 913b955f6caSJeff Kirsher new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+ 914b955f6caSJeff Kirsher amd8111e_read_mib(mmio, rcv_multicast_pkts)+ 915b955f6caSJeff Kirsher amd8111e_read_mib(mmio, rcv_unicast_pkts); 916b955f6caSJeff Kirsher 917b955f6caSJeff Kirsher /* stats.tx_packets */ 918b955f6caSJeff Kirsher new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets); 919b955f6caSJeff Kirsher 920b955f6caSJeff Kirsher /*stats.rx_bytes */ 921b955f6caSJeff Kirsher new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets); 922b955f6caSJeff Kirsher 923b955f6caSJeff Kirsher /* stats.tx_bytes */ 924b955f6caSJeff Kirsher new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets); 925b955f6caSJeff Kirsher 926b955f6caSJeff Kirsher /* stats.rx_errors */ 927b955f6caSJeff Kirsher /* hw errors + errors driver reported */ 928b955f6caSJeff Kirsher new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+ 929b955f6caSJeff Kirsher amd8111e_read_mib(mmio, rcv_fragments)+ 930b955f6caSJeff Kirsher amd8111e_read_mib(mmio, rcv_jabbers)+ 931b955f6caSJeff Kirsher amd8111e_read_mib(mmio, rcv_alignment_errors)+ 932b955f6caSJeff Kirsher amd8111e_read_mib(mmio, rcv_fcs_errors)+ 933b955f6caSJeff Kirsher amd8111e_read_mib(mmio, rcv_miss_pkts)+ 934b955f6caSJeff Kirsher lp->drv_rx_errors; 935b955f6caSJeff Kirsher 936b955f6caSJeff Kirsher /* stats.tx_errors */ 937b955f6caSJeff Kirsher new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts); 938b955f6caSJeff Kirsher 939b955f6caSJeff Kirsher /* stats.rx_dropped*/ 940b955f6caSJeff Kirsher new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts); 941b955f6caSJeff Kirsher 942b955f6caSJeff Kirsher /* stats.tx_dropped*/ 943b955f6caSJeff Kirsher new_stats->tx_dropped = amd8111e_read_mib(mmio, xmt_underrun_pkts); 944b955f6caSJeff Kirsher 945b955f6caSJeff Kirsher /* stats.multicast*/ 946b955f6caSJeff Kirsher new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts); 947b955f6caSJeff Kirsher 948b955f6caSJeff Kirsher /* stats.collisions*/ 949b955f6caSJeff Kirsher new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions); 950b955f6caSJeff Kirsher 951b955f6caSJeff Kirsher /* stats.rx_length_errors*/ 952b955f6caSJeff Kirsher new_stats->rx_length_errors = 953b955f6caSJeff Kirsher amd8111e_read_mib(mmio, rcv_undersize_pkts)+ 954b955f6caSJeff Kirsher amd8111e_read_mib(mmio, rcv_oversize_pkts); 955b955f6caSJeff Kirsher 956b955f6caSJeff Kirsher /* stats.rx_over_errors*/ 957b955f6caSJeff Kirsher new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts); 958b955f6caSJeff Kirsher 959b955f6caSJeff Kirsher /* stats.rx_crc_errors*/ 960b955f6caSJeff Kirsher new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors); 961b955f6caSJeff Kirsher 962b955f6caSJeff Kirsher /* stats.rx_frame_errors*/ 963b955f6caSJeff Kirsher new_stats->rx_frame_errors = 964b955f6caSJeff Kirsher amd8111e_read_mib(mmio, rcv_alignment_errors); 965b955f6caSJeff Kirsher 966b955f6caSJeff Kirsher /* stats.rx_fifo_errors */ 967b955f6caSJeff Kirsher new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts); 968b955f6caSJeff Kirsher 969b955f6caSJeff Kirsher /* stats.rx_missed_errors */ 970b955f6caSJeff Kirsher new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts); 971b955f6caSJeff Kirsher 972b955f6caSJeff Kirsher /* stats.tx_aborted_errors*/ 973b955f6caSJeff Kirsher new_stats->tx_aborted_errors = 974b955f6caSJeff Kirsher amd8111e_read_mib(mmio, xmt_excessive_collision); 975b955f6caSJeff Kirsher 976b955f6caSJeff Kirsher /* stats.tx_carrier_errors*/ 977b955f6caSJeff Kirsher new_stats->tx_carrier_errors = 978b955f6caSJeff Kirsher amd8111e_read_mib(mmio, xmt_loss_carrier); 979b955f6caSJeff Kirsher 980b955f6caSJeff Kirsher /* stats.tx_fifo_errors*/ 981b955f6caSJeff Kirsher new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts); 982b955f6caSJeff Kirsher 983b955f6caSJeff Kirsher /* stats.tx_window_errors*/ 984b955f6caSJeff Kirsher new_stats->tx_window_errors = 985b955f6caSJeff Kirsher amd8111e_read_mib(mmio, xmt_late_collision); 986b955f6caSJeff Kirsher 987b955f6caSJeff Kirsher /* Reset the mibs for collecting new statistics */ 988b955f6caSJeff Kirsher /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/ 989b955f6caSJeff Kirsher 990b955f6caSJeff Kirsher spin_unlock_irqrestore (&lp->lock, flags); 991b955f6caSJeff Kirsher 992b955f6caSJeff Kirsher return new_stats; 993b955f6caSJeff Kirsher } 994b955f6caSJeff Kirsher /* This function recalculate the interrupt coalescing mode on every interrupt 995b955f6caSJeff Kirsher according to the datarate and the packet rate. 996b955f6caSJeff Kirsher */ 997b955f6caSJeff Kirsher static int amd8111e_calc_coalesce(struct net_device *dev) 998b955f6caSJeff Kirsher { 999b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1000b955f6caSJeff Kirsher struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf; 1001b955f6caSJeff Kirsher int tx_pkt_rate; 1002b955f6caSJeff Kirsher int rx_pkt_rate; 1003b955f6caSJeff Kirsher int tx_data_rate; 1004b955f6caSJeff Kirsher int rx_data_rate; 1005b955f6caSJeff Kirsher int rx_pkt_size; 1006b955f6caSJeff Kirsher int tx_pkt_size; 1007b955f6caSJeff Kirsher 1008b955f6caSJeff Kirsher tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets; 1009b955f6caSJeff Kirsher coal_conf->tx_prev_packets = coal_conf->tx_packets; 1010b955f6caSJeff Kirsher 1011b955f6caSJeff Kirsher tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes; 1012b955f6caSJeff Kirsher coal_conf->tx_prev_bytes = coal_conf->tx_bytes; 1013b955f6caSJeff Kirsher 1014b955f6caSJeff Kirsher rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets; 1015b955f6caSJeff Kirsher coal_conf->rx_prev_packets = coal_conf->rx_packets; 1016b955f6caSJeff Kirsher 1017b955f6caSJeff Kirsher rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes; 1018b955f6caSJeff Kirsher coal_conf->rx_prev_bytes = coal_conf->rx_bytes; 1019b955f6caSJeff Kirsher 1020b955f6caSJeff Kirsher if(rx_pkt_rate < 800){ 1021b955f6caSJeff Kirsher if(coal_conf->rx_coal_type != NO_COALESCE){ 1022b955f6caSJeff Kirsher 1023b955f6caSJeff Kirsher coal_conf->rx_timeout = 0x0; 1024b955f6caSJeff Kirsher coal_conf->rx_event_count = 0; 1025b955f6caSJeff Kirsher amd8111e_set_coalesce(dev,RX_INTR_COAL); 1026b955f6caSJeff Kirsher coal_conf->rx_coal_type = NO_COALESCE; 1027b955f6caSJeff Kirsher } 1028b955f6caSJeff Kirsher } 1029b955f6caSJeff Kirsher else{ 1030b955f6caSJeff Kirsher 1031b955f6caSJeff Kirsher rx_pkt_size = rx_data_rate/rx_pkt_rate; 1032b955f6caSJeff Kirsher if (rx_pkt_size < 128){ 1033b955f6caSJeff Kirsher if(coal_conf->rx_coal_type != NO_COALESCE){ 1034b955f6caSJeff Kirsher 1035b955f6caSJeff Kirsher coal_conf->rx_timeout = 0; 1036b955f6caSJeff Kirsher coal_conf->rx_event_count = 0; 1037b955f6caSJeff Kirsher amd8111e_set_coalesce(dev,RX_INTR_COAL); 1038b955f6caSJeff Kirsher coal_conf->rx_coal_type = NO_COALESCE; 1039b955f6caSJeff Kirsher } 1040b955f6caSJeff Kirsher 1041b955f6caSJeff Kirsher } 1042b955f6caSJeff Kirsher else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){ 1043b955f6caSJeff Kirsher 1044b955f6caSJeff Kirsher if(coal_conf->rx_coal_type != LOW_COALESCE){ 1045b955f6caSJeff Kirsher coal_conf->rx_timeout = 1; 1046b955f6caSJeff Kirsher coal_conf->rx_event_count = 4; 1047b955f6caSJeff Kirsher amd8111e_set_coalesce(dev,RX_INTR_COAL); 1048b955f6caSJeff Kirsher coal_conf->rx_coal_type = LOW_COALESCE; 1049b955f6caSJeff Kirsher } 1050b955f6caSJeff Kirsher } 1051b955f6caSJeff Kirsher else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){ 1052b955f6caSJeff Kirsher 1053b955f6caSJeff Kirsher if(coal_conf->rx_coal_type != MEDIUM_COALESCE){ 1054b955f6caSJeff Kirsher coal_conf->rx_timeout = 1; 1055b955f6caSJeff Kirsher coal_conf->rx_event_count = 4; 1056b955f6caSJeff Kirsher amd8111e_set_coalesce(dev,RX_INTR_COAL); 1057b955f6caSJeff Kirsher coal_conf->rx_coal_type = MEDIUM_COALESCE; 1058b955f6caSJeff Kirsher } 1059b955f6caSJeff Kirsher 1060b955f6caSJeff Kirsher } 1061b955f6caSJeff Kirsher else if(rx_pkt_size >= 1024){ 1062b955f6caSJeff Kirsher if(coal_conf->rx_coal_type != HIGH_COALESCE){ 1063b955f6caSJeff Kirsher coal_conf->rx_timeout = 2; 1064b955f6caSJeff Kirsher coal_conf->rx_event_count = 3; 1065b955f6caSJeff Kirsher amd8111e_set_coalesce(dev,RX_INTR_COAL); 1066b955f6caSJeff Kirsher coal_conf->rx_coal_type = HIGH_COALESCE; 1067b955f6caSJeff Kirsher } 1068b955f6caSJeff Kirsher } 1069b955f6caSJeff Kirsher } 1070b955f6caSJeff Kirsher /* NOW FOR TX INTR COALESC */ 1071b955f6caSJeff Kirsher if(tx_pkt_rate < 800){ 1072b955f6caSJeff Kirsher if(coal_conf->tx_coal_type != NO_COALESCE){ 1073b955f6caSJeff Kirsher 1074b955f6caSJeff Kirsher coal_conf->tx_timeout = 0x0; 1075b955f6caSJeff Kirsher coal_conf->tx_event_count = 0; 1076b955f6caSJeff Kirsher amd8111e_set_coalesce(dev,TX_INTR_COAL); 1077b955f6caSJeff Kirsher coal_conf->tx_coal_type = NO_COALESCE; 1078b955f6caSJeff Kirsher } 1079b955f6caSJeff Kirsher } 1080b955f6caSJeff Kirsher else{ 1081b955f6caSJeff Kirsher 1082b955f6caSJeff Kirsher tx_pkt_size = tx_data_rate/tx_pkt_rate; 1083b955f6caSJeff Kirsher if (tx_pkt_size < 128){ 1084b955f6caSJeff Kirsher 1085b955f6caSJeff Kirsher if(coal_conf->tx_coal_type != NO_COALESCE){ 1086b955f6caSJeff Kirsher 1087b955f6caSJeff Kirsher coal_conf->tx_timeout = 0; 1088b955f6caSJeff Kirsher coal_conf->tx_event_count = 0; 1089b955f6caSJeff Kirsher amd8111e_set_coalesce(dev,TX_INTR_COAL); 1090b955f6caSJeff Kirsher coal_conf->tx_coal_type = NO_COALESCE; 1091b955f6caSJeff Kirsher } 1092b955f6caSJeff Kirsher 1093b955f6caSJeff Kirsher } 1094b955f6caSJeff Kirsher else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){ 1095b955f6caSJeff Kirsher 1096b955f6caSJeff Kirsher if(coal_conf->tx_coal_type != LOW_COALESCE){ 1097b955f6caSJeff Kirsher coal_conf->tx_timeout = 1; 1098b955f6caSJeff Kirsher coal_conf->tx_event_count = 2; 1099b955f6caSJeff Kirsher amd8111e_set_coalesce(dev,TX_INTR_COAL); 1100b955f6caSJeff Kirsher coal_conf->tx_coal_type = LOW_COALESCE; 1101b955f6caSJeff Kirsher 1102b955f6caSJeff Kirsher } 1103b955f6caSJeff Kirsher } 1104b955f6caSJeff Kirsher else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){ 1105b955f6caSJeff Kirsher 1106b955f6caSJeff Kirsher if(coal_conf->tx_coal_type != MEDIUM_COALESCE){ 1107b955f6caSJeff Kirsher coal_conf->tx_timeout = 2; 1108b955f6caSJeff Kirsher coal_conf->tx_event_count = 5; 1109b955f6caSJeff Kirsher amd8111e_set_coalesce(dev,TX_INTR_COAL); 1110b955f6caSJeff Kirsher coal_conf->tx_coal_type = MEDIUM_COALESCE; 1111b955f6caSJeff Kirsher } 1112b955f6caSJeff Kirsher 1113b955f6caSJeff Kirsher } 1114b955f6caSJeff Kirsher else if(tx_pkt_size >= 1024){ 1115b955f6caSJeff Kirsher if (tx_pkt_size >= 1024){ 1116b955f6caSJeff Kirsher if(coal_conf->tx_coal_type != HIGH_COALESCE){ 1117b955f6caSJeff Kirsher coal_conf->tx_timeout = 4; 1118b955f6caSJeff Kirsher coal_conf->tx_event_count = 8; 1119b955f6caSJeff Kirsher amd8111e_set_coalesce(dev,TX_INTR_COAL); 1120b955f6caSJeff Kirsher coal_conf->tx_coal_type = HIGH_COALESCE; 1121b955f6caSJeff Kirsher } 1122b955f6caSJeff Kirsher } 1123b955f6caSJeff Kirsher } 1124b955f6caSJeff Kirsher } 1125b955f6caSJeff Kirsher return 0; 1126b955f6caSJeff Kirsher 1127b955f6caSJeff Kirsher } 1128b955f6caSJeff Kirsher /* 1129b955f6caSJeff Kirsher This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts. 1130b955f6caSJeff Kirsher */ 1131b955f6caSJeff Kirsher static irqreturn_t amd8111e_interrupt(int irq, void *dev_id) 1132b955f6caSJeff Kirsher { 1133b955f6caSJeff Kirsher 1134b955f6caSJeff Kirsher struct net_device * dev = (struct net_device *) dev_id; 1135b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1136b955f6caSJeff Kirsher void __iomem *mmio = lp->mmio; 1137b955f6caSJeff Kirsher unsigned int intr0, intren0; 1138b955f6caSJeff Kirsher unsigned int handled = 1; 1139b955f6caSJeff Kirsher 1140b955f6caSJeff Kirsher if(unlikely(dev == NULL)) 1141b955f6caSJeff Kirsher return IRQ_NONE; 1142b955f6caSJeff Kirsher 1143b955f6caSJeff Kirsher spin_lock(&lp->lock); 1144b955f6caSJeff Kirsher 1145b955f6caSJeff Kirsher /* disabling interrupt */ 1146b955f6caSJeff Kirsher writel(INTREN, mmio + CMD0); 1147b955f6caSJeff Kirsher 1148b955f6caSJeff Kirsher /* Read interrupt status */ 1149b955f6caSJeff Kirsher intr0 = readl(mmio + INT0); 1150b955f6caSJeff Kirsher intren0 = readl(mmio + INTEN0); 1151b955f6caSJeff Kirsher 1152b955f6caSJeff Kirsher /* Process all the INT event until INTR bit is clear. */ 1153b955f6caSJeff Kirsher 1154b955f6caSJeff Kirsher if (!(intr0 & INTR)){ 1155b955f6caSJeff Kirsher handled = 0; 1156b955f6caSJeff Kirsher goto err_no_interrupt; 1157b955f6caSJeff Kirsher } 1158b955f6caSJeff Kirsher 1159b955f6caSJeff Kirsher /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */ 1160b955f6caSJeff Kirsher writel(intr0, mmio + INT0); 1161b955f6caSJeff Kirsher 1162b955f6caSJeff Kirsher /* Check if Receive Interrupt has occurred. */ 1163b955f6caSJeff Kirsher if (intr0 & RINT0) { 1164b955f6caSJeff Kirsher if (napi_schedule_prep(&lp->napi)) { 1165b955f6caSJeff Kirsher /* Disable receive interupts */ 1166b955f6caSJeff Kirsher writel(RINTEN0, mmio + INTEN0); 1167b955f6caSJeff Kirsher /* Schedule a polling routine */ 1168b955f6caSJeff Kirsher __napi_schedule(&lp->napi); 1169b955f6caSJeff Kirsher } else if (intren0 & RINTEN0) { 1170b955f6caSJeff Kirsher printk("************Driver bug! interrupt while in poll\n"); 1171b955f6caSJeff Kirsher /* Fix by disable receive interrupts */ 1172b955f6caSJeff Kirsher writel(RINTEN0, mmio + INTEN0); 1173b955f6caSJeff Kirsher } 1174b955f6caSJeff Kirsher } 1175b955f6caSJeff Kirsher 1176b955f6caSJeff Kirsher /* Check if Transmit Interrupt has occurred. */ 1177b955f6caSJeff Kirsher if (intr0 & TINT0) 1178b955f6caSJeff Kirsher amd8111e_tx(dev); 1179b955f6caSJeff Kirsher 1180b955f6caSJeff Kirsher /* Check if Link Change Interrupt has occurred. */ 1181b955f6caSJeff Kirsher if (intr0 & LCINT) 1182b955f6caSJeff Kirsher amd8111e_link_change(dev); 1183b955f6caSJeff Kirsher 1184b955f6caSJeff Kirsher /* Check if Hardware Timer Interrupt has occurred. */ 1185b955f6caSJeff Kirsher if (intr0 & STINT) 1186b955f6caSJeff Kirsher amd8111e_calc_coalesce(dev); 1187b955f6caSJeff Kirsher 1188b955f6caSJeff Kirsher err_no_interrupt: 1189b955f6caSJeff Kirsher writel( VAL0 | INTREN,mmio + CMD0); 1190b955f6caSJeff Kirsher 1191b955f6caSJeff Kirsher spin_unlock(&lp->lock); 1192b955f6caSJeff Kirsher 1193b955f6caSJeff Kirsher return IRQ_RETVAL(handled); 1194b955f6caSJeff Kirsher } 1195b955f6caSJeff Kirsher 1196b955f6caSJeff Kirsher #ifdef CONFIG_NET_POLL_CONTROLLER 1197b955f6caSJeff Kirsher static void amd8111e_poll(struct net_device *dev) 1198b955f6caSJeff Kirsher { 1199b955f6caSJeff Kirsher unsigned long flags; 1200b955f6caSJeff Kirsher local_irq_save(flags); 1201b955f6caSJeff Kirsher amd8111e_interrupt(0, dev); 1202b955f6caSJeff Kirsher local_irq_restore(flags); 1203b955f6caSJeff Kirsher } 1204b955f6caSJeff Kirsher #endif 1205b955f6caSJeff Kirsher 1206b955f6caSJeff Kirsher 1207b955f6caSJeff Kirsher /* 1208b955f6caSJeff Kirsher This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down. 1209b955f6caSJeff Kirsher */ 1210b955f6caSJeff Kirsher static int amd8111e_close(struct net_device * dev) 1211b955f6caSJeff Kirsher { 1212b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1213b955f6caSJeff Kirsher netif_stop_queue(dev); 1214b955f6caSJeff Kirsher 1215b955f6caSJeff Kirsher napi_disable(&lp->napi); 1216b955f6caSJeff Kirsher 1217b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1218b955f6caSJeff Kirsher 1219b955f6caSJeff Kirsher amd8111e_disable_interrupt(lp); 1220b955f6caSJeff Kirsher amd8111e_stop_chip(lp); 1221b955f6caSJeff Kirsher 1222b955f6caSJeff Kirsher /* Free transmit and receive skbs */ 1223b955f6caSJeff Kirsher amd8111e_free_skbs(lp->amd8111e_net_dev); 1224b955f6caSJeff Kirsher 1225b955f6caSJeff Kirsher netif_carrier_off(lp->amd8111e_net_dev); 1226b955f6caSJeff Kirsher 1227b955f6caSJeff Kirsher /* Delete ipg timer */ 1228b955f6caSJeff Kirsher if(lp->options & OPTION_DYN_IPG_ENABLE) 1229b955f6caSJeff Kirsher del_timer_sync(&lp->ipg_data.ipg_timer); 1230b955f6caSJeff Kirsher 1231b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1232b955f6caSJeff Kirsher free_irq(dev->irq, dev); 1233b955f6caSJeff Kirsher amd8111e_free_ring(lp); 1234b955f6caSJeff Kirsher 1235b955f6caSJeff Kirsher /* Update the statistics before closing */ 1236b955f6caSJeff Kirsher amd8111e_get_stats(dev); 1237b955f6caSJeff Kirsher lp->opened = 0; 1238b955f6caSJeff Kirsher return 0; 1239b955f6caSJeff Kirsher } 1240b955f6caSJeff Kirsher /* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device. 1241b955f6caSJeff Kirsher */ 1242b955f6caSJeff Kirsher static int amd8111e_open(struct net_device * dev ) 1243b955f6caSJeff Kirsher { 1244b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1245b955f6caSJeff Kirsher 1246b955f6caSJeff Kirsher if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, IRQF_SHARED, 1247b955f6caSJeff Kirsher dev->name, dev)) 1248b955f6caSJeff Kirsher return -EAGAIN; 1249b955f6caSJeff Kirsher 1250b955f6caSJeff Kirsher napi_enable(&lp->napi); 1251b955f6caSJeff Kirsher 1252b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1253b955f6caSJeff Kirsher 1254b955f6caSJeff Kirsher amd8111e_init_hw_default(lp); 1255b955f6caSJeff Kirsher 1256b955f6caSJeff Kirsher if(amd8111e_restart(dev)){ 1257b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1258b955f6caSJeff Kirsher napi_disable(&lp->napi); 1259b955f6caSJeff Kirsher if (dev->irq) 1260b955f6caSJeff Kirsher free_irq(dev->irq, dev); 1261b955f6caSJeff Kirsher return -ENOMEM; 1262b955f6caSJeff Kirsher } 1263b955f6caSJeff Kirsher /* Start ipg timer */ 1264b955f6caSJeff Kirsher if(lp->options & OPTION_DYN_IPG_ENABLE){ 1265b955f6caSJeff Kirsher add_timer(&lp->ipg_data.ipg_timer); 1266b955f6caSJeff Kirsher printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name); 1267b955f6caSJeff Kirsher } 1268b955f6caSJeff Kirsher 1269b955f6caSJeff Kirsher lp->opened = 1; 1270b955f6caSJeff Kirsher 1271b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1272b955f6caSJeff Kirsher 1273b955f6caSJeff Kirsher netif_start_queue(dev); 1274b955f6caSJeff Kirsher 1275b955f6caSJeff Kirsher return 0; 1276b955f6caSJeff Kirsher } 1277b955f6caSJeff Kirsher /* 1278b955f6caSJeff Kirsher This function checks if there is any transmit descriptors available to queue more packet. 1279b955f6caSJeff Kirsher */ 1280b955f6caSJeff Kirsher static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp ) 1281b955f6caSJeff Kirsher { 1282b955f6caSJeff Kirsher int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK; 1283b955f6caSJeff Kirsher if (lp->tx_skbuff[tx_index]) 1284b955f6caSJeff Kirsher return -1; 1285b955f6caSJeff Kirsher else 1286b955f6caSJeff Kirsher return 0; 1287b955f6caSJeff Kirsher 1288b955f6caSJeff Kirsher } 1289b955f6caSJeff Kirsher /* 1290b955f6caSJeff Kirsher This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc. 1291b955f6caSJeff Kirsher */ 1292b955f6caSJeff Kirsher 1293b955f6caSJeff Kirsher static netdev_tx_t amd8111e_start_xmit(struct sk_buff *skb, 1294b955f6caSJeff Kirsher struct net_device * dev) 1295b955f6caSJeff Kirsher { 1296b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1297b955f6caSJeff Kirsher int tx_index; 1298b955f6caSJeff Kirsher unsigned long flags; 1299b955f6caSJeff Kirsher 1300b955f6caSJeff Kirsher spin_lock_irqsave(&lp->lock, flags); 1301b955f6caSJeff Kirsher 1302b955f6caSJeff Kirsher tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK; 1303b955f6caSJeff Kirsher 1304b955f6caSJeff Kirsher lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len); 1305b955f6caSJeff Kirsher 1306b955f6caSJeff Kirsher lp->tx_skbuff[tx_index] = skb; 1307b955f6caSJeff Kirsher lp->tx_ring[tx_index].tx_flags = 0; 1308b955f6caSJeff Kirsher 1309b955f6caSJeff Kirsher #if AMD8111E_VLAN_TAG_USED 1310b955f6caSJeff Kirsher if (vlan_tx_tag_present(skb)) { 1311b955f6caSJeff Kirsher lp->tx_ring[tx_index].tag_ctrl_cmd |= 1312b955f6caSJeff Kirsher cpu_to_le16(TCC_VLAN_INSERT); 1313b955f6caSJeff Kirsher lp->tx_ring[tx_index].tag_ctrl_info = 1314b955f6caSJeff Kirsher cpu_to_le16(vlan_tx_tag_get(skb)); 1315b955f6caSJeff Kirsher 1316b955f6caSJeff Kirsher } 1317b955f6caSJeff Kirsher #endif 1318b955f6caSJeff Kirsher lp->tx_dma_addr[tx_index] = 1319b955f6caSJeff Kirsher pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); 1320b955f6caSJeff Kirsher lp->tx_ring[tx_index].buff_phy_addr = 1321b955f6caSJeff Kirsher cpu_to_le32(lp->tx_dma_addr[tx_index]); 1322b955f6caSJeff Kirsher 1323b955f6caSJeff Kirsher /* Set FCS and LTINT bits */ 1324b955f6caSJeff Kirsher wmb(); 1325b955f6caSJeff Kirsher lp->tx_ring[tx_index].tx_flags |= 1326b955f6caSJeff Kirsher cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT); 1327b955f6caSJeff Kirsher 1328b955f6caSJeff Kirsher lp->tx_idx++; 1329b955f6caSJeff Kirsher 1330b955f6caSJeff Kirsher /* Trigger an immediate send poll. */ 1331b955f6caSJeff Kirsher writel( VAL1 | TDMD0, lp->mmio + CMD0); 1332b955f6caSJeff Kirsher writel( VAL2 | RDMD0,lp->mmio + CMD0); 1333b955f6caSJeff Kirsher 1334b955f6caSJeff Kirsher if(amd8111e_tx_queue_avail(lp) < 0){ 1335b955f6caSJeff Kirsher netif_stop_queue(dev); 1336b955f6caSJeff Kirsher } 1337b955f6caSJeff Kirsher spin_unlock_irqrestore(&lp->lock, flags); 1338b955f6caSJeff Kirsher return NETDEV_TX_OK; 1339b955f6caSJeff Kirsher } 1340b955f6caSJeff Kirsher /* 1341b955f6caSJeff Kirsher This function returns all the memory mapped registers of the device. 1342b955f6caSJeff Kirsher */ 1343b955f6caSJeff Kirsher static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf) 1344b955f6caSJeff Kirsher { 1345b955f6caSJeff Kirsher void __iomem *mmio = lp->mmio; 1346b955f6caSJeff Kirsher /* Read only necessary registers */ 1347b955f6caSJeff Kirsher buf[0] = readl(mmio + XMT_RING_BASE_ADDR0); 1348b955f6caSJeff Kirsher buf[1] = readl(mmio + XMT_RING_LEN0); 1349b955f6caSJeff Kirsher buf[2] = readl(mmio + RCV_RING_BASE_ADDR0); 1350b955f6caSJeff Kirsher buf[3] = readl(mmio + RCV_RING_LEN0); 1351b955f6caSJeff Kirsher buf[4] = readl(mmio + CMD0); 1352b955f6caSJeff Kirsher buf[5] = readl(mmio + CMD2); 1353b955f6caSJeff Kirsher buf[6] = readl(mmio + CMD3); 1354b955f6caSJeff Kirsher buf[7] = readl(mmio + CMD7); 1355b955f6caSJeff Kirsher buf[8] = readl(mmio + INT0); 1356b955f6caSJeff Kirsher buf[9] = readl(mmio + INTEN0); 1357b955f6caSJeff Kirsher buf[10] = readl(mmio + LADRF); 1358b955f6caSJeff Kirsher buf[11] = readl(mmio + LADRF+4); 1359b955f6caSJeff Kirsher buf[12] = readl(mmio + STAT0); 1360b955f6caSJeff Kirsher } 1361b955f6caSJeff Kirsher 1362b955f6caSJeff Kirsher 1363b955f6caSJeff Kirsher /* 1364b955f6caSJeff Kirsher This function sets promiscuos mode, all-multi mode or the multicast address 1365b955f6caSJeff Kirsher list to the device. 1366b955f6caSJeff Kirsher */ 1367b955f6caSJeff Kirsher static void amd8111e_set_multicast_list(struct net_device *dev) 1368b955f6caSJeff Kirsher { 1369b955f6caSJeff Kirsher struct netdev_hw_addr *ha; 1370b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1371b955f6caSJeff Kirsher u32 mc_filter[2] ; 1372b955f6caSJeff Kirsher int bit_num; 1373b955f6caSJeff Kirsher 1374b955f6caSJeff Kirsher if(dev->flags & IFF_PROMISC){ 1375b955f6caSJeff Kirsher writel( VAL2 | PROM, lp->mmio + CMD2); 1376b955f6caSJeff Kirsher return; 1377b955f6caSJeff Kirsher } 1378b955f6caSJeff Kirsher else 1379b955f6caSJeff Kirsher writel( PROM, lp->mmio + CMD2); 1380b955f6caSJeff Kirsher if (dev->flags & IFF_ALLMULTI || 1381b955f6caSJeff Kirsher netdev_mc_count(dev) > MAX_FILTER_SIZE) { 1382b955f6caSJeff Kirsher /* get all multicast packet */ 1383b955f6caSJeff Kirsher mc_filter[1] = mc_filter[0] = 0xffffffff; 1384b955f6caSJeff Kirsher lp->options |= OPTION_MULTICAST_ENABLE; 1385b955f6caSJeff Kirsher amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF); 1386b955f6caSJeff Kirsher return; 1387b955f6caSJeff Kirsher } 1388b955f6caSJeff Kirsher if (netdev_mc_empty(dev)) { 1389b955f6caSJeff Kirsher /* get only own packets */ 1390b955f6caSJeff Kirsher mc_filter[1] = mc_filter[0] = 0; 1391b955f6caSJeff Kirsher lp->options &= ~OPTION_MULTICAST_ENABLE; 1392b955f6caSJeff Kirsher amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF); 1393b955f6caSJeff Kirsher /* disable promiscuous mode */ 1394b955f6caSJeff Kirsher writel(PROM, lp->mmio + CMD2); 1395b955f6caSJeff Kirsher return; 1396b955f6caSJeff Kirsher } 1397b955f6caSJeff Kirsher /* load all the multicast addresses in the logic filter */ 1398b955f6caSJeff Kirsher lp->options |= OPTION_MULTICAST_ENABLE; 1399b955f6caSJeff Kirsher mc_filter[1] = mc_filter[0] = 0; 1400b955f6caSJeff Kirsher netdev_for_each_mc_addr(ha, dev) { 1401b955f6caSJeff Kirsher bit_num = (ether_crc_le(ETH_ALEN, ha->addr) >> 26) & 0x3f; 1402b955f6caSJeff Kirsher mc_filter[bit_num >> 5] |= 1 << (bit_num & 31); 1403b955f6caSJeff Kirsher } 1404b955f6caSJeff Kirsher amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF); 1405b955f6caSJeff Kirsher 1406b955f6caSJeff Kirsher /* To eliminate PCI posting bug */ 1407b955f6caSJeff Kirsher readl(lp->mmio + CMD2); 1408b955f6caSJeff Kirsher 1409b955f6caSJeff Kirsher } 1410b955f6caSJeff Kirsher 1411b955f6caSJeff Kirsher static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info) 1412b955f6caSJeff Kirsher { 1413b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1414b955f6caSJeff Kirsher struct pci_dev *pci_dev = lp->pci_dev; 141523020ab3SRick Jones strlcpy(info->driver, MODULE_NAME, sizeof(info->driver)); 141623020ab3SRick Jones strlcpy(info->version, MODULE_VERS, sizeof(info->version)); 141723020ab3SRick Jones snprintf(info->fw_version, sizeof(info->fw_version), 141823020ab3SRick Jones "%u", chip_version); 141923020ab3SRick Jones strlcpy(info->bus_info, pci_name(pci_dev), sizeof(info->bus_info)); 1420b955f6caSJeff Kirsher } 1421b955f6caSJeff Kirsher 1422b955f6caSJeff Kirsher static int amd8111e_get_regs_len(struct net_device *dev) 1423b955f6caSJeff Kirsher { 1424b955f6caSJeff Kirsher return AMD8111E_REG_DUMP_LEN; 1425b955f6caSJeff Kirsher } 1426b955f6caSJeff Kirsher 1427b955f6caSJeff Kirsher static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) 1428b955f6caSJeff Kirsher { 1429b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1430b955f6caSJeff Kirsher regs->version = 0; 1431b955f6caSJeff Kirsher amd8111e_read_regs(lp, buf); 1432b955f6caSJeff Kirsher } 1433b955f6caSJeff Kirsher 1434b955f6caSJeff Kirsher static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 1435b955f6caSJeff Kirsher { 1436b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1437b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1438b955f6caSJeff Kirsher mii_ethtool_gset(&lp->mii_if, ecmd); 1439b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1440b955f6caSJeff Kirsher return 0; 1441b955f6caSJeff Kirsher } 1442b955f6caSJeff Kirsher 1443b955f6caSJeff Kirsher static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 1444b955f6caSJeff Kirsher { 1445b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1446b955f6caSJeff Kirsher int res; 1447b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1448b955f6caSJeff Kirsher res = mii_ethtool_sset(&lp->mii_if, ecmd); 1449b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1450b955f6caSJeff Kirsher return res; 1451b955f6caSJeff Kirsher } 1452b955f6caSJeff Kirsher 1453b955f6caSJeff Kirsher static int amd8111e_nway_reset(struct net_device *dev) 1454b955f6caSJeff Kirsher { 1455b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1456b955f6caSJeff Kirsher return mii_nway_restart(&lp->mii_if); 1457b955f6caSJeff Kirsher } 1458b955f6caSJeff Kirsher 1459b955f6caSJeff Kirsher static u32 amd8111e_get_link(struct net_device *dev) 1460b955f6caSJeff Kirsher { 1461b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1462b955f6caSJeff Kirsher return mii_link_ok(&lp->mii_if); 1463b955f6caSJeff Kirsher } 1464b955f6caSJeff Kirsher 1465b955f6caSJeff Kirsher static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info) 1466b955f6caSJeff Kirsher { 1467b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1468b955f6caSJeff Kirsher wol_info->supported = WAKE_MAGIC|WAKE_PHY; 1469b955f6caSJeff Kirsher if (lp->options & OPTION_WOL_ENABLE) 1470b955f6caSJeff Kirsher wol_info->wolopts = WAKE_MAGIC; 1471b955f6caSJeff Kirsher } 1472b955f6caSJeff Kirsher 1473b955f6caSJeff Kirsher static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info) 1474b955f6caSJeff Kirsher { 1475b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1476b955f6caSJeff Kirsher if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY)) 1477b955f6caSJeff Kirsher return -EINVAL; 1478b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1479b955f6caSJeff Kirsher if (wol_info->wolopts & WAKE_MAGIC) 1480b955f6caSJeff Kirsher lp->options |= 1481b955f6caSJeff Kirsher (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE); 1482b955f6caSJeff Kirsher else if(wol_info->wolopts & WAKE_PHY) 1483b955f6caSJeff Kirsher lp->options |= 1484b955f6caSJeff Kirsher (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE); 1485b955f6caSJeff Kirsher else 1486b955f6caSJeff Kirsher lp->options &= ~OPTION_WOL_ENABLE; 1487b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1488b955f6caSJeff Kirsher return 0; 1489b955f6caSJeff Kirsher } 1490b955f6caSJeff Kirsher 1491b955f6caSJeff Kirsher static const struct ethtool_ops ops = { 1492b955f6caSJeff Kirsher .get_drvinfo = amd8111e_get_drvinfo, 1493b955f6caSJeff Kirsher .get_regs_len = amd8111e_get_regs_len, 1494b955f6caSJeff Kirsher .get_regs = amd8111e_get_regs, 1495b955f6caSJeff Kirsher .get_settings = amd8111e_get_settings, 1496b955f6caSJeff Kirsher .set_settings = amd8111e_set_settings, 1497b955f6caSJeff Kirsher .nway_reset = amd8111e_nway_reset, 1498b955f6caSJeff Kirsher .get_link = amd8111e_get_link, 1499b955f6caSJeff Kirsher .get_wol = amd8111e_get_wol, 1500b955f6caSJeff Kirsher .set_wol = amd8111e_set_wol, 1501b955f6caSJeff Kirsher }; 1502b955f6caSJeff Kirsher 1503b955f6caSJeff Kirsher /* 1504b955f6caSJeff Kirsher This function handles all the ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application. 1505b955f6caSJeff Kirsher */ 1506b955f6caSJeff Kirsher 1507b955f6caSJeff Kirsher static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd) 1508b955f6caSJeff Kirsher { 1509b955f6caSJeff Kirsher struct mii_ioctl_data *data = if_mii(ifr); 1510b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1511b955f6caSJeff Kirsher int err; 1512b955f6caSJeff Kirsher u32 mii_regval; 1513b955f6caSJeff Kirsher 1514b955f6caSJeff Kirsher switch(cmd) { 1515b955f6caSJeff Kirsher case SIOCGMIIPHY: 1516b955f6caSJeff Kirsher data->phy_id = lp->ext_phy_addr; 1517b955f6caSJeff Kirsher 1518b955f6caSJeff Kirsher /* fallthru */ 1519b955f6caSJeff Kirsher case SIOCGMIIREG: 1520b955f6caSJeff Kirsher 1521b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1522b955f6caSJeff Kirsher err = amd8111e_read_phy(lp, data->phy_id, 1523b955f6caSJeff Kirsher data->reg_num & PHY_REG_ADDR_MASK, &mii_regval); 1524b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1525b955f6caSJeff Kirsher 1526b955f6caSJeff Kirsher data->val_out = mii_regval; 1527b955f6caSJeff Kirsher return err; 1528b955f6caSJeff Kirsher 1529b955f6caSJeff Kirsher case SIOCSMIIREG: 1530b955f6caSJeff Kirsher 1531b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1532b955f6caSJeff Kirsher err = amd8111e_write_phy(lp, data->phy_id, 1533b955f6caSJeff Kirsher data->reg_num & PHY_REG_ADDR_MASK, data->val_in); 1534b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1535b955f6caSJeff Kirsher 1536b955f6caSJeff Kirsher return err; 1537b955f6caSJeff Kirsher 1538b955f6caSJeff Kirsher default: 1539b955f6caSJeff Kirsher /* do nothing */ 1540b955f6caSJeff Kirsher break; 1541b955f6caSJeff Kirsher } 1542b955f6caSJeff Kirsher return -EOPNOTSUPP; 1543b955f6caSJeff Kirsher } 1544b955f6caSJeff Kirsher static int amd8111e_set_mac_address(struct net_device *dev, void *p) 1545b955f6caSJeff Kirsher { 1546b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1547b955f6caSJeff Kirsher int i; 1548b955f6caSJeff Kirsher struct sockaddr *addr = p; 1549b955f6caSJeff Kirsher 1550b955f6caSJeff Kirsher memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 1551b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1552b955f6caSJeff Kirsher /* Setting the MAC address to the device */ 1553c857ff6eSJoe Perches for (i = 0; i < ETH_ALEN; i++) 1554b955f6caSJeff Kirsher writeb( dev->dev_addr[i], lp->mmio + PADR + i ); 1555b955f6caSJeff Kirsher 1556b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1557b955f6caSJeff Kirsher 1558b955f6caSJeff Kirsher return 0; 1559b955f6caSJeff Kirsher } 1560b955f6caSJeff Kirsher 1561b955f6caSJeff Kirsher /* 1562b955f6caSJeff Kirsher This function changes the mtu of the device. It restarts the device to initialize the descriptor with new receive buffers. 1563b955f6caSJeff Kirsher */ 1564b955f6caSJeff Kirsher static int amd8111e_change_mtu(struct net_device *dev, int new_mtu) 1565b955f6caSJeff Kirsher { 1566b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1567b955f6caSJeff Kirsher int err; 1568b955f6caSJeff Kirsher 1569b955f6caSJeff Kirsher if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU)) 1570b955f6caSJeff Kirsher return -EINVAL; 1571b955f6caSJeff Kirsher 1572b955f6caSJeff Kirsher if (!netif_running(dev)) { 1573b955f6caSJeff Kirsher /* new_mtu will be used 1574b955f6caSJeff Kirsher when device starts netxt time */ 1575b955f6caSJeff Kirsher dev->mtu = new_mtu; 1576b955f6caSJeff Kirsher return 0; 1577b955f6caSJeff Kirsher } 1578b955f6caSJeff Kirsher 1579b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1580b955f6caSJeff Kirsher 1581b955f6caSJeff Kirsher /* stop the chip */ 1582b955f6caSJeff Kirsher writel(RUN, lp->mmio + CMD0); 1583b955f6caSJeff Kirsher 1584b955f6caSJeff Kirsher dev->mtu = new_mtu; 1585b955f6caSJeff Kirsher 1586b955f6caSJeff Kirsher err = amd8111e_restart(dev); 1587b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1588b955f6caSJeff Kirsher if(!err) 1589b955f6caSJeff Kirsher netif_start_queue(dev); 1590b955f6caSJeff Kirsher return err; 1591b955f6caSJeff Kirsher } 1592b955f6caSJeff Kirsher 1593b955f6caSJeff Kirsher static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp) 1594b955f6caSJeff Kirsher { 1595b955f6caSJeff Kirsher writel( VAL1|MPPLBA, lp->mmio + CMD3); 1596b955f6caSJeff Kirsher writel( VAL0|MPEN_SW, lp->mmio + CMD7); 1597b955f6caSJeff Kirsher 1598b955f6caSJeff Kirsher /* To eliminate PCI posting bug */ 1599b955f6caSJeff Kirsher readl(lp->mmio + CMD7); 1600b955f6caSJeff Kirsher return 0; 1601b955f6caSJeff Kirsher } 1602b955f6caSJeff Kirsher 1603b955f6caSJeff Kirsher static int amd8111e_enable_link_change(struct amd8111e_priv* lp) 1604b955f6caSJeff Kirsher { 1605b955f6caSJeff Kirsher 1606b955f6caSJeff Kirsher /* Adapter is already stoped/suspended/interrupt-disabled */ 1607b955f6caSJeff Kirsher writel(VAL0|LCMODE_SW,lp->mmio + CMD7); 1608b955f6caSJeff Kirsher 1609b955f6caSJeff Kirsher /* To eliminate PCI posting bug */ 1610b955f6caSJeff Kirsher readl(lp->mmio + CMD7); 1611b955f6caSJeff Kirsher return 0; 1612b955f6caSJeff Kirsher } 1613b955f6caSJeff Kirsher 1614b955f6caSJeff Kirsher /* 1615b955f6caSJeff Kirsher * This function is called when a packet transmission fails to complete 1616b955f6caSJeff Kirsher * within a reasonable period, on the assumption that an interrupt have 1617b955f6caSJeff Kirsher * failed or the interface is locked up. This function will reinitialize 1618b955f6caSJeff Kirsher * the hardware. 1619b955f6caSJeff Kirsher */ 1620b955f6caSJeff Kirsher static void amd8111e_tx_timeout(struct net_device *dev) 1621b955f6caSJeff Kirsher { 1622b955f6caSJeff Kirsher struct amd8111e_priv* lp = netdev_priv(dev); 1623b955f6caSJeff Kirsher int err; 1624b955f6caSJeff Kirsher 1625b955f6caSJeff Kirsher printk(KERN_ERR "%s: transmit timed out, resetting\n", 1626b955f6caSJeff Kirsher dev->name); 1627b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1628b955f6caSJeff Kirsher err = amd8111e_restart(dev); 1629b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1630b955f6caSJeff Kirsher if(!err) 1631b955f6caSJeff Kirsher netif_wake_queue(dev); 1632b955f6caSJeff Kirsher } 1633b955f6caSJeff Kirsher static int amd8111e_suspend(struct pci_dev *pci_dev, pm_message_t state) 1634b955f6caSJeff Kirsher { 1635b955f6caSJeff Kirsher struct net_device *dev = pci_get_drvdata(pci_dev); 1636b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1637b955f6caSJeff Kirsher 1638b955f6caSJeff Kirsher if (!netif_running(dev)) 1639b955f6caSJeff Kirsher return 0; 1640b955f6caSJeff Kirsher 1641b955f6caSJeff Kirsher /* disable the interrupt */ 1642b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1643b955f6caSJeff Kirsher amd8111e_disable_interrupt(lp); 1644b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1645b955f6caSJeff Kirsher 1646b955f6caSJeff Kirsher netif_device_detach(dev); 1647b955f6caSJeff Kirsher 1648b955f6caSJeff Kirsher /* stop chip */ 1649b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1650b955f6caSJeff Kirsher if(lp->options & OPTION_DYN_IPG_ENABLE) 1651b955f6caSJeff Kirsher del_timer_sync(&lp->ipg_data.ipg_timer); 1652b955f6caSJeff Kirsher amd8111e_stop_chip(lp); 1653b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1654b955f6caSJeff Kirsher 1655b955f6caSJeff Kirsher if(lp->options & OPTION_WOL_ENABLE){ 1656b955f6caSJeff Kirsher /* enable wol */ 1657b955f6caSJeff Kirsher if(lp->options & OPTION_WAKE_MAGIC_ENABLE) 1658b955f6caSJeff Kirsher amd8111e_enable_magicpkt(lp); 1659b955f6caSJeff Kirsher if(lp->options & OPTION_WAKE_PHY_ENABLE) 1660b955f6caSJeff Kirsher amd8111e_enable_link_change(lp); 1661b955f6caSJeff Kirsher 1662b955f6caSJeff Kirsher pci_enable_wake(pci_dev, PCI_D3hot, 1); 1663b955f6caSJeff Kirsher pci_enable_wake(pci_dev, PCI_D3cold, 1); 1664b955f6caSJeff Kirsher 1665b955f6caSJeff Kirsher } 1666b955f6caSJeff Kirsher else{ 1667b955f6caSJeff Kirsher pci_enable_wake(pci_dev, PCI_D3hot, 0); 1668b955f6caSJeff Kirsher pci_enable_wake(pci_dev, PCI_D3cold, 0); 1669b955f6caSJeff Kirsher } 1670b955f6caSJeff Kirsher 1671b955f6caSJeff Kirsher pci_save_state(pci_dev); 1672b955f6caSJeff Kirsher pci_set_power_state(pci_dev, PCI_D3hot); 1673b955f6caSJeff Kirsher 1674b955f6caSJeff Kirsher return 0; 1675b955f6caSJeff Kirsher } 1676b955f6caSJeff Kirsher static int amd8111e_resume(struct pci_dev *pci_dev) 1677b955f6caSJeff Kirsher { 1678b955f6caSJeff Kirsher struct net_device *dev = pci_get_drvdata(pci_dev); 1679b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1680b955f6caSJeff Kirsher 1681b955f6caSJeff Kirsher if (!netif_running(dev)) 1682b955f6caSJeff Kirsher return 0; 1683b955f6caSJeff Kirsher 1684b955f6caSJeff Kirsher pci_set_power_state(pci_dev, PCI_D0); 1685b955f6caSJeff Kirsher pci_restore_state(pci_dev); 1686b955f6caSJeff Kirsher 1687b955f6caSJeff Kirsher pci_enable_wake(pci_dev, PCI_D3hot, 0); 1688b955f6caSJeff Kirsher pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */ 1689b955f6caSJeff Kirsher 1690b955f6caSJeff Kirsher netif_device_attach(dev); 1691b955f6caSJeff Kirsher 1692b955f6caSJeff Kirsher spin_lock_irq(&lp->lock); 1693b955f6caSJeff Kirsher amd8111e_restart(dev); 1694b955f6caSJeff Kirsher /* Restart ipg timer */ 1695b955f6caSJeff Kirsher if(lp->options & OPTION_DYN_IPG_ENABLE) 1696b955f6caSJeff Kirsher mod_timer(&lp->ipg_data.ipg_timer, 1697b955f6caSJeff Kirsher jiffies + IPG_CONVERGE_JIFFIES); 1698b955f6caSJeff Kirsher spin_unlock_irq(&lp->lock); 1699b955f6caSJeff Kirsher 1700b955f6caSJeff Kirsher return 0; 1701b955f6caSJeff Kirsher } 1702b955f6caSJeff Kirsher 1703b955f6caSJeff Kirsher 1704b955f6caSJeff Kirsher static void __devexit amd8111e_remove_one(struct pci_dev *pdev) 1705b955f6caSJeff Kirsher { 1706b955f6caSJeff Kirsher struct net_device *dev = pci_get_drvdata(pdev); 1707b955f6caSJeff Kirsher if (dev) { 1708b955f6caSJeff Kirsher unregister_netdev(dev); 1709b955f6caSJeff Kirsher iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio); 1710b955f6caSJeff Kirsher free_netdev(dev); 1711b955f6caSJeff Kirsher pci_release_regions(pdev); 1712b955f6caSJeff Kirsher pci_disable_device(pdev); 1713b955f6caSJeff Kirsher pci_set_drvdata(pdev, NULL); 1714b955f6caSJeff Kirsher } 1715b955f6caSJeff Kirsher } 1716b955f6caSJeff Kirsher static void amd8111e_config_ipg(struct net_device* dev) 1717b955f6caSJeff Kirsher { 1718b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1719b955f6caSJeff Kirsher struct ipg_info* ipg_data = &lp->ipg_data; 1720b955f6caSJeff Kirsher void __iomem *mmio = lp->mmio; 1721b955f6caSJeff Kirsher unsigned int prev_col_cnt = ipg_data->col_cnt; 1722b955f6caSJeff Kirsher unsigned int total_col_cnt; 1723b955f6caSJeff Kirsher unsigned int tmp_ipg; 1724b955f6caSJeff Kirsher 1725b955f6caSJeff Kirsher if(lp->link_config.duplex == DUPLEX_FULL){ 1726b955f6caSJeff Kirsher ipg_data->ipg = DEFAULT_IPG; 1727b955f6caSJeff Kirsher return; 1728b955f6caSJeff Kirsher } 1729b955f6caSJeff Kirsher 1730b955f6caSJeff Kirsher if(ipg_data->ipg_state == SSTATE){ 1731b955f6caSJeff Kirsher 1732b955f6caSJeff Kirsher if(ipg_data->timer_tick == IPG_STABLE_TIME){ 1733b955f6caSJeff Kirsher 1734b955f6caSJeff Kirsher ipg_data->timer_tick = 0; 1735b955f6caSJeff Kirsher ipg_data->ipg = MIN_IPG - IPG_STEP; 1736b955f6caSJeff Kirsher ipg_data->current_ipg = MIN_IPG; 1737b955f6caSJeff Kirsher ipg_data->diff_col_cnt = 0xFFFFFFFF; 1738b955f6caSJeff Kirsher ipg_data->ipg_state = CSTATE; 1739b955f6caSJeff Kirsher } 1740b955f6caSJeff Kirsher else 1741b955f6caSJeff Kirsher ipg_data->timer_tick++; 1742b955f6caSJeff Kirsher } 1743b955f6caSJeff Kirsher 1744b955f6caSJeff Kirsher if(ipg_data->ipg_state == CSTATE){ 1745b955f6caSJeff Kirsher 1746b955f6caSJeff Kirsher /* Get the current collision count */ 1747b955f6caSJeff Kirsher 1748b955f6caSJeff Kirsher total_col_cnt = ipg_data->col_cnt = 1749b955f6caSJeff Kirsher amd8111e_read_mib(mmio, xmt_collisions); 1750b955f6caSJeff Kirsher 1751b955f6caSJeff Kirsher if ((total_col_cnt - prev_col_cnt) < 1752b955f6caSJeff Kirsher (ipg_data->diff_col_cnt)){ 1753b955f6caSJeff Kirsher 1754b955f6caSJeff Kirsher ipg_data->diff_col_cnt = 1755b955f6caSJeff Kirsher total_col_cnt - prev_col_cnt ; 1756b955f6caSJeff Kirsher 1757b955f6caSJeff Kirsher ipg_data->ipg = ipg_data->current_ipg; 1758b955f6caSJeff Kirsher } 1759b955f6caSJeff Kirsher 1760b955f6caSJeff Kirsher ipg_data->current_ipg += IPG_STEP; 1761b955f6caSJeff Kirsher 1762b955f6caSJeff Kirsher if (ipg_data->current_ipg <= MAX_IPG) 1763b955f6caSJeff Kirsher tmp_ipg = ipg_data->current_ipg; 1764b955f6caSJeff Kirsher else{ 1765b955f6caSJeff Kirsher tmp_ipg = ipg_data->ipg; 1766b955f6caSJeff Kirsher ipg_data->ipg_state = SSTATE; 1767b955f6caSJeff Kirsher } 1768b955f6caSJeff Kirsher writew((u32)tmp_ipg, mmio + IPG); 1769b955f6caSJeff Kirsher writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1); 1770b955f6caSJeff Kirsher } 1771b955f6caSJeff Kirsher mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES); 1772b955f6caSJeff Kirsher return; 1773b955f6caSJeff Kirsher 1774b955f6caSJeff Kirsher } 1775b955f6caSJeff Kirsher 1776b955f6caSJeff Kirsher static void __devinit amd8111e_probe_ext_phy(struct net_device* dev) 1777b955f6caSJeff Kirsher { 1778b955f6caSJeff Kirsher struct amd8111e_priv *lp = netdev_priv(dev); 1779b955f6caSJeff Kirsher int i; 1780b955f6caSJeff Kirsher 1781b955f6caSJeff Kirsher for (i = 0x1e; i >= 0; i--) { 1782b955f6caSJeff Kirsher u32 id1, id2; 1783b955f6caSJeff Kirsher 1784b955f6caSJeff Kirsher if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1)) 1785b955f6caSJeff Kirsher continue; 1786b955f6caSJeff Kirsher if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2)) 1787b955f6caSJeff Kirsher continue; 1788b955f6caSJeff Kirsher lp->ext_phy_id = (id1 << 16) | id2; 1789b955f6caSJeff Kirsher lp->ext_phy_addr = i; 1790b955f6caSJeff Kirsher return; 1791b955f6caSJeff Kirsher } 1792b955f6caSJeff Kirsher lp->ext_phy_id = 0; 1793b955f6caSJeff Kirsher lp->ext_phy_addr = 1; 1794b955f6caSJeff Kirsher } 1795b955f6caSJeff Kirsher 1796b955f6caSJeff Kirsher static const struct net_device_ops amd8111e_netdev_ops = { 1797b955f6caSJeff Kirsher .ndo_open = amd8111e_open, 1798b955f6caSJeff Kirsher .ndo_stop = amd8111e_close, 1799b955f6caSJeff Kirsher .ndo_start_xmit = amd8111e_start_xmit, 1800b955f6caSJeff Kirsher .ndo_tx_timeout = amd8111e_tx_timeout, 1801b955f6caSJeff Kirsher .ndo_get_stats = amd8111e_get_stats, 1802afc4b13dSJiri Pirko .ndo_set_rx_mode = amd8111e_set_multicast_list, 1803b955f6caSJeff Kirsher .ndo_validate_addr = eth_validate_addr, 1804b955f6caSJeff Kirsher .ndo_set_mac_address = amd8111e_set_mac_address, 1805b955f6caSJeff Kirsher .ndo_do_ioctl = amd8111e_ioctl, 1806b955f6caSJeff Kirsher .ndo_change_mtu = amd8111e_change_mtu, 1807b955f6caSJeff Kirsher #ifdef CONFIG_NET_POLL_CONTROLLER 1808b955f6caSJeff Kirsher .ndo_poll_controller = amd8111e_poll, 1809b955f6caSJeff Kirsher #endif 1810b955f6caSJeff Kirsher }; 1811b955f6caSJeff Kirsher 1812b955f6caSJeff Kirsher static int __devinit amd8111e_probe_one(struct pci_dev *pdev, 1813b955f6caSJeff Kirsher const struct pci_device_id *ent) 1814b955f6caSJeff Kirsher { 1815b955f6caSJeff Kirsher int err,i,pm_cap; 1816b955f6caSJeff Kirsher unsigned long reg_addr,reg_len; 1817b955f6caSJeff Kirsher struct amd8111e_priv* lp; 1818b955f6caSJeff Kirsher struct net_device* dev; 1819b955f6caSJeff Kirsher 1820b955f6caSJeff Kirsher err = pci_enable_device(pdev); 1821b955f6caSJeff Kirsher if(err){ 1822b955f6caSJeff Kirsher printk(KERN_ERR "amd8111e: Cannot enable new PCI device, " 1823b955f6caSJeff Kirsher "exiting.\n"); 1824b955f6caSJeff Kirsher return err; 1825b955f6caSJeff Kirsher } 1826b955f6caSJeff Kirsher 1827b955f6caSJeff Kirsher if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){ 1828b955f6caSJeff Kirsher printk(KERN_ERR "amd8111e: Cannot find PCI base address, " 1829b955f6caSJeff Kirsher "exiting.\n"); 1830b955f6caSJeff Kirsher err = -ENODEV; 1831b955f6caSJeff Kirsher goto err_disable_pdev; 1832b955f6caSJeff Kirsher } 1833b955f6caSJeff Kirsher 1834b955f6caSJeff Kirsher err = pci_request_regions(pdev, MODULE_NAME); 1835b955f6caSJeff Kirsher if(err){ 1836b955f6caSJeff Kirsher printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, " 1837b955f6caSJeff Kirsher "exiting.\n"); 1838b955f6caSJeff Kirsher goto err_disable_pdev; 1839b955f6caSJeff Kirsher } 1840b955f6caSJeff Kirsher 1841b955f6caSJeff Kirsher pci_set_master(pdev); 1842b955f6caSJeff Kirsher 1843b955f6caSJeff Kirsher /* Find power-management capability. */ 1844b955f6caSJeff Kirsher if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){ 1845b955f6caSJeff Kirsher printk(KERN_ERR "amd8111e: No Power Management capability, " 1846b955f6caSJeff Kirsher "exiting.\n"); 1847b955f6caSJeff Kirsher goto err_free_reg; 1848b955f6caSJeff Kirsher } 1849b955f6caSJeff Kirsher 1850b955f6caSJeff Kirsher /* Initialize DMA */ 1851b955f6caSJeff Kirsher if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) < 0) { 1852b955f6caSJeff Kirsher printk(KERN_ERR "amd8111e: DMA not supported," 1853b955f6caSJeff Kirsher "exiting.\n"); 1854b955f6caSJeff Kirsher goto err_free_reg; 1855b955f6caSJeff Kirsher } 1856b955f6caSJeff Kirsher 1857b955f6caSJeff Kirsher reg_addr = pci_resource_start(pdev, 0); 1858b955f6caSJeff Kirsher reg_len = pci_resource_len(pdev, 0); 1859b955f6caSJeff Kirsher 1860b955f6caSJeff Kirsher dev = alloc_etherdev(sizeof(struct amd8111e_priv)); 1861b955f6caSJeff Kirsher if (!dev) { 1862b955f6caSJeff Kirsher printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n"); 1863b955f6caSJeff Kirsher err = -ENOMEM; 1864b955f6caSJeff Kirsher goto err_free_reg; 1865b955f6caSJeff Kirsher } 1866b955f6caSJeff Kirsher 1867b955f6caSJeff Kirsher SET_NETDEV_DEV(dev, &pdev->dev); 1868b955f6caSJeff Kirsher 1869b955f6caSJeff Kirsher #if AMD8111E_VLAN_TAG_USED 1870b955f6caSJeff Kirsher dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ; 1871b955f6caSJeff Kirsher #endif 1872b955f6caSJeff Kirsher 1873b955f6caSJeff Kirsher lp = netdev_priv(dev); 1874b955f6caSJeff Kirsher lp->pci_dev = pdev; 1875b955f6caSJeff Kirsher lp->amd8111e_net_dev = dev; 1876b955f6caSJeff Kirsher lp->pm_cap = pm_cap; 1877b955f6caSJeff Kirsher 1878b955f6caSJeff Kirsher spin_lock_init(&lp->lock); 1879b955f6caSJeff Kirsher 1880b955f6caSJeff Kirsher lp->mmio = ioremap(reg_addr, reg_len); 1881b955f6caSJeff Kirsher if (!lp->mmio) { 1882b955f6caSJeff Kirsher printk(KERN_ERR "amd8111e: Cannot map device registers, " 1883b955f6caSJeff Kirsher "exiting\n"); 1884b955f6caSJeff Kirsher err = -ENOMEM; 1885b955f6caSJeff Kirsher goto err_free_dev; 1886b955f6caSJeff Kirsher } 1887b955f6caSJeff Kirsher 1888b955f6caSJeff Kirsher /* Initializing MAC address */ 1889c857ff6eSJoe Perches for (i = 0; i < ETH_ALEN; i++) 1890b955f6caSJeff Kirsher dev->dev_addr[i] = readb(lp->mmio + PADR + i); 1891b955f6caSJeff Kirsher 1892b955f6caSJeff Kirsher /* Setting user defined parametrs */ 1893b955f6caSJeff Kirsher lp->ext_phy_option = speed_duplex[card_idx]; 1894b955f6caSJeff Kirsher if(coalesce[card_idx]) 1895b955f6caSJeff Kirsher lp->options |= OPTION_INTR_COAL_ENABLE; 1896b955f6caSJeff Kirsher if(dynamic_ipg[card_idx++]) 1897b955f6caSJeff Kirsher lp->options |= OPTION_DYN_IPG_ENABLE; 1898b955f6caSJeff Kirsher 1899b955f6caSJeff Kirsher 1900b955f6caSJeff Kirsher /* Initialize driver entry points */ 1901b955f6caSJeff Kirsher dev->netdev_ops = &amd8111e_netdev_ops; 1902b955f6caSJeff Kirsher SET_ETHTOOL_OPS(dev, &ops); 1903b955f6caSJeff Kirsher dev->irq =pdev->irq; 1904b955f6caSJeff Kirsher dev->watchdog_timeo = AMD8111E_TX_TIMEOUT; 1905b955f6caSJeff Kirsher netif_napi_add(dev, &lp->napi, amd8111e_rx_poll, 32); 1906b955f6caSJeff Kirsher 1907b955f6caSJeff Kirsher #if AMD8111E_VLAN_TAG_USED 1908b955f6caSJeff Kirsher dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 1909b955f6caSJeff Kirsher #endif 1910b955f6caSJeff Kirsher /* Probe the external PHY */ 1911b955f6caSJeff Kirsher amd8111e_probe_ext_phy(dev); 1912b955f6caSJeff Kirsher 1913b955f6caSJeff Kirsher /* setting mii default values */ 1914b955f6caSJeff Kirsher lp->mii_if.dev = dev; 1915b955f6caSJeff Kirsher lp->mii_if.mdio_read = amd8111e_mdio_read; 1916b955f6caSJeff Kirsher lp->mii_if.mdio_write = amd8111e_mdio_write; 1917b955f6caSJeff Kirsher lp->mii_if.phy_id = lp->ext_phy_addr; 1918b955f6caSJeff Kirsher 1919b955f6caSJeff Kirsher /* Set receive buffer length and set jumbo option*/ 1920b955f6caSJeff Kirsher amd8111e_set_rx_buff_len(dev); 1921b955f6caSJeff Kirsher 1922b955f6caSJeff Kirsher 1923b955f6caSJeff Kirsher err = register_netdev(dev); 1924b955f6caSJeff Kirsher if (err) { 1925b955f6caSJeff Kirsher printk(KERN_ERR "amd8111e: Cannot register net device, " 1926b955f6caSJeff Kirsher "exiting.\n"); 1927b955f6caSJeff Kirsher goto err_iounmap; 1928b955f6caSJeff Kirsher } 1929b955f6caSJeff Kirsher 1930b955f6caSJeff Kirsher pci_set_drvdata(pdev, dev); 1931b955f6caSJeff Kirsher 1932b955f6caSJeff Kirsher /* Initialize software ipg timer */ 1933b955f6caSJeff Kirsher if(lp->options & OPTION_DYN_IPG_ENABLE){ 1934b955f6caSJeff Kirsher init_timer(&lp->ipg_data.ipg_timer); 1935b955f6caSJeff Kirsher lp->ipg_data.ipg_timer.data = (unsigned long) dev; 1936b955f6caSJeff Kirsher lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg; 1937b955f6caSJeff Kirsher lp->ipg_data.ipg_timer.expires = jiffies + 1938b955f6caSJeff Kirsher IPG_CONVERGE_JIFFIES; 1939b955f6caSJeff Kirsher lp->ipg_data.ipg = DEFAULT_IPG; 1940b955f6caSJeff Kirsher lp->ipg_data.ipg_state = CSTATE; 1941b955f6caSJeff Kirsher } 1942b955f6caSJeff Kirsher 1943b955f6caSJeff Kirsher /* display driver and device information */ 1944b955f6caSJeff Kirsher 1945b955f6caSJeff Kirsher chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28; 1946b955f6caSJeff Kirsher printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n", 1947b955f6caSJeff Kirsher dev->name,MODULE_VERS); 1948b955f6caSJeff Kirsher printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet %pM\n", 1949b955f6caSJeff Kirsher dev->name, chip_version, dev->dev_addr); 1950b955f6caSJeff Kirsher if (lp->ext_phy_id) 1951b955f6caSJeff Kirsher printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n", 1952b955f6caSJeff Kirsher dev->name, lp->ext_phy_id, lp->ext_phy_addr); 1953b955f6caSJeff Kirsher else 1954b955f6caSJeff Kirsher printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n", 1955b955f6caSJeff Kirsher dev->name); 1956b955f6caSJeff Kirsher return 0; 1957b955f6caSJeff Kirsher err_iounmap: 1958b955f6caSJeff Kirsher iounmap(lp->mmio); 1959b955f6caSJeff Kirsher 1960b955f6caSJeff Kirsher err_free_dev: 1961b955f6caSJeff Kirsher free_netdev(dev); 1962b955f6caSJeff Kirsher 1963b955f6caSJeff Kirsher err_free_reg: 1964b955f6caSJeff Kirsher pci_release_regions(pdev); 1965b955f6caSJeff Kirsher 1966b955f6caSJeff Kirsher err_disable_pdev: 1967b955f6caSJeff Kirsher pci_disable_device(pdev); 1968b955f6caSJeff Kirsher pci_set_drvdata(pdev, NULL); 1969b955f6caSJeff Kirsher return err; 1970b955f6caSJeff Kirsher 1971b955f6caSJeff Kirsher } 1972b955f6caSJeff Kirsher 1973b955f6caSJeff Kirsher static struct pci_driver amd8111e_driver = { 1974b955f6caSJeff Kirsher .name = MODULE_NAME, 1975b955f6caSJeff Kirsher .id_table = amd8111e_pci_tbl, 1976b955f6caSJeff Kirsher .probe = amd8111e_probe_one, 1977b955f6caSJeff Kirsher .remove = __devexit_p(amd8111e_remove_one), 1978b955f6caSJeff Kirsher .suspend = amd8111e_suspend, 1979b955f6caSJeff Kirsher .resume = amd8111e_resume 1980b955f6caSJeff Kirsher }; 1981b955f6caSJeff Kirsher 1982b955f6caSJeff Kirsher static int __init amd8111e_init(void) 1983b955f6caSJeff Kirsher { 1984b955f6caSJeff Kirsher return pci_register_driver(&amd8111e_driver); 1985b955f6caSJeff Kirsher } 1986b955f6caSJeff Kirsher 1987b955f6caSJeff Kirsher static void __exit amd8111e_cleanup(void) 1988b955f6caSJeff Kirsher { 1989b955f6caSJeff Kirsher pci_unregister_driver(&amd8111e_driver); 1990b955f6caSJeff Kirsher } 1991b955f6caSJeff Kirsher 1992b955f6caSJeff Kirsher module_init(amd8111e_init); 1993b955f6caSJeff Kirsher module_exit(amd8111e_cleanup); 1994