1 /* 2 * Copyright 2015 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef ENA_H 34 #define ENA_H 35 36 #include <linux/bitops.h> 37 #include <linux/etherdevice.h> 38 #include <linux/inetdevice.h> 39 #include <linux/interrupt.h> 40 #include <linux/netdevice.h> 41 #include <linux/skbuff.h> 42 43 #include "ena_com.h" 44 #include "ena_eth_com.h" 45 46 #define DRV_MODULE_VER_MAJOR 2 47 #define DRV_MODULE_VER_MINOR 1 48 #define DRV_MODULE_VER_SUBMINOR 0 49 50 #define DRV_MODULE_NAME "ena" 51 #ifndef DRV_MODULE_VERSION 52 #define DRV_MODULE_VERSION \ 53 __stringify(DRV_MODULE_VER_MAJOR) "." \ 54 __stringify(DRV_MODULE_VER_MINOR) "." \ 55 __stringify(DRV_MODULE_VER_SUBMINOR) "K" 56 #endif 57 58 #define DEVICE_NAME "Elastic Network Adapter (ENA)" 59 60 /* 1 for AENQ + ADMIN */ 61 #define ENA_ADMIN_MSIX_VEC 1 62 #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues)) 63 64 /* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the 65 * driver passes 0. 66 * Since the max packet size the ENA handles is ~9kB limit the buffer length to 67 * 16kB. 68 */ 69 #if PAGE_SIZE > SZ_16K 70 #define ENA_PAGE_SIZE SZ_16K 71 #else 72 #define ENA_PAGE_SIZE PAGE_SIZE 73 #endif 74 75 #define ENA_MIN_MSIX_VEC 2 76 77 #define ENA_REG_BAR 0 78 #define ENA_MEM_BAR 2 79 #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR)) 80 81 #define ENA_DEFAULT_RING_SIZE (1024) 82 #define ENA_MIN_RING_SIZE (256) 83 84 #define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2) 85 #define ENA_DEFAULT_RX_COPYBREAK (256 - NET_IP_ALIGN) 86 87 /* limit the buffer size to 600 bytes to handle MTU changes from very 88 * small to very large, in which case the number of buffers per packet 89 * could exceed ENA_PKT_MAX_BUFS 90 */ 91 #define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600 92 93 #define ENA_MIN_MTU 128 94 95 #define ENA_NAME_MAX_LEN 20 96 #define ENA_IRQNAME_SIZE 40 97 98 #define ENA_PKT_MAX_BUFS 19 99 100 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 101 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 102 103 #define ENA_HASH_KEY_SIZE 40 104 105 /* The number of tx packet completions that will be handled each NAPI poll 106 * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER. 107 */ 108 #define ENA_TX_POLL_BUDGET_DIVIDER 4 109 110 /* Refill Rx queue when number of required descriptors is above 111 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET 112 */ 113 #define ENA_RX_REFILL_THRESH_DIVIDER 8 114 #define ENA_RX_REFILL_THRESH_PACKET 256 115 116 /* Number of queues to check for missing queues per timer service */ 117 #define ENA_MONITORED_TX_QUEUES 4 118 /* Max timeout packets before device reset */ 119 #define MAX_NUM_OF_TIMEOUTED_PACKETS 128 120 121 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 122 123 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 124 #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \ 125 (((idx) + (n)) & ((ring_size) - 1)) 126 127 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 128 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 129 130 #define ENA_MGMNT_IRQ_IDX 0 131 #define ENA_IO_IRQ_FIRST_IDX 1 132 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q)) 133 134 /* ENA device should send keep alive msg every 1 sec. 135 * We wait for 6 sec just to be on the safe side. 136 */ 137 #define ENA_DEVICE_KALIVE_TIMEOUT (6 * HZ) 138 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3 139 140 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 141 142 struct ena_irq { 143 irq_handler_t handler; 144 void *data; 145 int cpu; 146 u32 vector; 147 cpumask_t affinity_hint_mask; 148 char name[ENA_IRQNAME_SIZE]; 149 }; 150 151 struct ena_napi { 152 struct napi_struct napi ____cacheline_aligned; 153 struct ena_ring *tx_ring; 154 struct ena_ring *rx_ring; 155 u32 qid; 156 }; 157 158 struct ena_calc_queue_size_ctx { 159 struct ena_com_dev_get_features_ctx *get_feat_ctx; 160 struct ena_com_dev *ena_dev; 161 struct pci_dev *pdev; 162 u16 tx_queue_size; 163 u16 rx_queue_size; 164 u16 max_tx_queue_size; 165 u16 max_rx_queue_size; 166 u16 max_tx_sgl_size; 167 u16 max_rx_sgl_size; 168 }; 169 170 struct ena_tx_buffer { 171 struct sk_buff *skb; 172 /* num of ena desc for this specific skb 173 * (includes data desc and metadata desc) 174 */ 175 u32 tx_descs; 176 /* num of buffers used by this skb */ 177 u32 num_of_bufs; 178 179 /* Indicate if bufs[0] map the linear data of the skb. */ 180 u8 map_linear_data; 181 182 /* Used for detect missing tx packets to limit the number of prints */ 183 u32 print_once; 184 /* Save the last jiffies to detect missing tx packets 185 * 186 * sets to non zero value on ena_start_xmit and set to zero on 187 * napi and timer_Service_routine. 188 * 189 * while this value is not protected by lock, 190 * a given packet is not expected to be handled by ena_start_xmit 191 * and by napi/timer_service at the same time. 192 */ 193 unsigned long last_jiffies; 194 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 195 } ____cacheline_aligned; 196 197 struct ena_rx_buffer { 198 struct sk_buff *skb; 199 struct page *page; 200 u32 page_offset; 201 struct ena_com_buf ena_buf; 202 } ____cacheline_aligned; 203 204 struct ena_stats_tx { 205 u64 cnt; 206 u64 bytes; 207 u64 queue_stop; 208 u64 prepare_ctx_err; 209 u64 queue_wakeup; 210 u64 dma_mapping_err; 211 u64 linearize; 212 u64 linearize_failed; 213 u64 napi_comp; 214 u64 tx_poll; 215 u64 doorbells; 216 u64 bad_req_id; 217 u64 llq_buffer_copy; 218 u64 missed_tx; 219 }; 220 221 struct ena_stats_rx { 222 u64 cnt; 223 u64 bytes; 224 u64 rx_copybreak_pkt; 225 u64 csum_good; 226 u64 refil_partial; 227 u64 bad_csum; 228 u64 page_alloc_fail; 229 u64 skb_alloc_fail; 230 u64 dma_mapping_err; 231 u64 bad_desc_num; 232 u64 bad_req_id; 233 u64 empty_rx_ring; 234 u64 csum_unchecked; 235 }; 236 237 struct ena_ring { 238 /* Holds the empty requests for TX/RX 239 * out of order completions 240 */ 241 u16 *free_ids; 242 243 union { 244 struct ena_tx_buffer *tx_buffer_info; 245 struct ena_rx_buffer *rx_buffer_info; 246 }; 247 248 /* cache ptr to avoid using the adapter */ 249 struct device *dev; 250 struct pci_dev *pdev; 251 struct napi_struct *napi; 252 struct net_device *netdev; 253 struct ena_com_dev *ena_dev; 254 struct ena_adapter *adapter; 255 struct ena_com_io_cq *ena_com_io_cq; 256 struct ena_com_io_sq *ena_com_io_sq; 257 258 u16 next_to_use; 259 u16 next_to_clean; 260 u16 rx_copybreak; 261 u16 qid; 262 u16 mtu; 263 u16 sgl_size; 264 265 /* The maximum header length the device can handle */ 266 u8 tx_max_header_size; 267 268 bool first_interrupt; 269 u16 no_interrupt_event_cnt; 270 271 /* cpu for TPH */ 272 int cpu; 273 /* number of tx/rx_buffer_info's entries */ 274 int ring_size; 275 276 enum ena_admin_placement_policy_type tx_mem_queue_type; 277 278 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]; 279 u32 smoothed_interval; 280 u32 per_napi_packets; 281 u32 per_napi_bytes; 282 enum ena_intr_moder_level moder_tbl_idx; 283 struct u64_stats_sync syncp; 284 union { 285 struct ena_stats_tx tx_stats; 286 struct ena_stats_rx rx_stats; 287 }; 288 289 u8 *push_buf_intermediate_buf; 290 int empty_rx_queue; 291 } ____cacheline_aligned; 292 293 struct ena_stats_dev { 294 u64 tx_timeout; 295 u64 suspend; 296 u64 resume; 297 u64 wd_expired; 298 u64 interface_up; 299 u64 interface_down; 300 u64 admin_q_pause; 301 u64 rx_drops; 302 }; 303 304 enum ena_flags_t { 305 ENA_FLAG_DEVICE_RUNNING, 306 ENA_FLAG_DEV_UP, 307 ENA_FLAG_LINK_UP, 308 ENA_FLAG_MSIX_ENABLED, 309 ENA_FLAG_TRIGGER_RESET, 310 ENA_FLAG_ONGOING_RESET 311 }; 312 313 /* adapter specific private data structure */ 314 struct ena_adapter { 315 struct ena_com_dev *ena_dev; 316 /* OS defined structs */ 317 struct net_device *netdev; 318 struct pci_dev *pdev; 319 320 /* rx packets that shorter that this len will be copied to the skb 321 * header 322 */ 323 u32 rx_copybreak; 324 u32 max_mtu; 325 326 int num_queues; 327 328 int msix_vecs; 329 330 u32 missing_tx_completion_threshold; 331 332 u32 tx_usecs, rx_usecs; /* interrupt moderation */ 333 u32 tx_frames, rx_frames; /* interrupt moderation */ 334 335 u32 requested_tx_ring_size; 336 u32 requested_rx_ring_size; 337 338 u32 max_tx_ring_size; 339 u32 max_rx_ring_size; 340 341 u32 msg_enable; 342 343 u16 max_tx_sgl_size; 344 u16 max_rx_sgl_size; 345 346 u8 mac_addr[ETH_ALEN]; 347 348 unsigned long keep_alive_timeout; 349 unsigned long missing_tx_completion_to; 350 351 char name[ENA_NAME_MAX_LEN]; 352 353 unsigned long flags; 354 /* TX */ 355 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES] 356 ____cacheline_aligned_in_smp; 357 358 /* RX */ 359 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES] 360 ____cacheline_aligned_in_smp; 361 362 struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES]; 363 364 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)]; 365 366 /* timer service */ 367 struct work_struct reset_task; 368 struct timer_list timer_service; 369 370 bool wd_state; 371 bool dev_up_before_reset; 372 unsigned long last_keep_alive_jiffies; 373 374 struct u64_stats_sync syncp; 375 struct ena_stats_dev dev_stats; 376 377 /* last queue index that was checked for uncompleted tx packets */ 378 u32 last_monitored_tx_qid; 379 380 enum ena_regs_reset_reason_types reset_reason; 381 }; 382 383 void ena_set_ethtool_ops(struct net_device *netdev); 384 385 void ena_dump_stats_to_dmesg(struct ena_adapter *adapter); 386 387 void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf); 388 389 int ena_update_queue_sizes(struct ena_adapter *adapter, 390 u32 new_tx_size, 391 u32 new_rx_size); 392 393 int ena_get_sset_count(struct net_device *netdev, int sset); 394 395 #endif /* !(ENA_H) */ 396