1 /* 2 * Copyright 2015 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef ENA_H 34 #define ENA_H 35 36 #include <linux/bitops.h> 37 #include <linux/dim.h> 38 #include <linux/etherdevice.h> 39 #include <linux/if_vlan.h> 40 #include <linux/inetdevice.h> 41 #include <linux/interrupt.h> 42 #include <linux/netdevice.h> 43 #include <linux/skbuff.h> 44 45 #include "ena_com.h" 46 #include "ena_eth_com.h" 47 48 #define DRV_MODULE_GEN_MAJOR 2 49 #define DRV_MODULE_GEN_MINOR 1 50 #define DRV_MODULE_GEN_SUBMINOR 0 51 52 #define DRV_MODULE_NAME "ena" 53 54 #define DEVICE_NAME "Elastic Network Adapter (ENA)" 55 56 /* 1 for AENQ + ADMIN */ 57 #define ENA_ADMIN_MSIX_VEC 1 58 #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues)) 59 60 /* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the 61 * driver passes 0. 62 * Since the max packet size the ENA handles is ~9kB limit the buffer length to 63 * 16kB. 64 */ 65 #if PAGE_SIZE > SZ_16K 66 #define ENA_PAGE_SIZE (_AC(SZ_16K, UL)) 67 #else 68 #define ENA_PAGE_SIZE PAGE_SIZE 69 #endif 70 71 #define ENA_MIN_MSIX_VEC 2 72 73 #define ENA_REG_BAR 0 74 #define ENA_MEM_BAR 2 75 #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR)) 76 77 #define ENA_DEFAULT_RING_SIZE (1024) 78 #define ENA_MIN_RING_SIZE (256) 79 80 #define ENA_MIN_NUM_IO_QUEUES (1) 81 82 #define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2) 83 #define ENA_DEFAULT_RX_COPYBREAK (256 - NET_IP_ALIGN) 84 85 /* limit the buffer size to 600 bytes to handle MTU changes from very 86 * small to very large, in which case the number of buffers per packet 87 * could exceed ENA_PKT_MAX_BUFS 88 */ 89 #define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600 90 91 #define ENA_MIN_MTU 128 92 93 #define ENA_NAME_MAX_LEN 20 94 #define ENA_IRQNAME_SIZE 40 95 96 #define ENA_PKT_MAX_BUFS 19 97 98 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 99 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 100 101 /* The number of tx packet completions that will be handled each NAPI poll 102 * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER. 103 */ 104 #define ENA_TX_POLL_BUDGET_DIVIDER 4 105 106 /* Refill Rx queue when number of required descriptors is above 107 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER or ENA_RX_REFILL_THRESH_PACKET 108 */ 109 #define ENA_RX_REFILL_THRESH_DIVIDER 8 110 #define ENA_RX_REFILL_THRESH_PACKET 256 111 112 /* Number of queues to check for missing queues per timer service */ 113 #define ENA_MONITORED_TX_QUEUES 4 114 /* Max timeout packets before device reset */ 115 #define MAX_NUM_OF_TIMEOUTED_PACKETS 128 116 117 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 118 119 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 120 #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \ 121 (((idx) + (n)) & ((ring_size) - 1)) 122 123 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 124 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 125 #define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2) 126 #define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2) 127 128 #define ENA_MGMNT_IRQ_IDX 0 129 #define ENA_IO_IRQ_FIRST_IDX 1 130 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q)) 131 132 #define ENA_ADMIN_POLL_DELAY_US 100 133 134 /* ENA device should send keep alive msg every 1 sec. 135 * We wait for 6 sec just to be on the safe side. 136 */ 137 #define ENA_DEVICE_KALIVE_TIMEOUT (6 * HZ) 138 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3 139 140 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 141 142 /* The max MTU size is configured to be the ethernet frame size without 143 * the overhead of the ethernet header, which can have a VLAN header, and 144 * a frame check sequence (FCS). 145 * The buffer size we share with the device is defined to be ENA_PAGE_SIZE 146 */ 147 148 #define ENA_XDP_MAX_MTU (ENA_PAGE_SIZE - ETH_HLEN - ETH_FCS_LEN - \ 149 VLAN_HLEN - XDP_PACKET_HEADROOM - \ 150 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 151 152 #define ENA_IS_XDP_INDEX(adapter, index) (((index) >= (adapter)->xdp_first_ring) && \ 153 ((index) < (adapter)->xdp_first_ring + (adapter)->xdp_num_queues)) 154 155 struct ena_irq { 156 irq_handler_t handler; 157 void *data; 158 int cpu; 159 u32 vector; 160 cpumask_t affinity_hint_mask; 161 char name[ENA_IRQNAME_SIZE]; 162 }; 163 164 struct ena_napi { 165 struct napi_struct napi ____cacheline_aligned; 166 struct ena_ring *tx_ring; 167 struct ena_ring *rx_ring; 168 struct ena_ring *xdp_ring; 169 bool first_interrupt; 170 bool interrupts_masked; 171 u32 qid; 172 struct dim dim; 173 }; 174 175 struct ena_calc_queue_size_ctx { 176 struct ena_com_dev_get_features_ctx *get_feat_ctx; 177 struct ena_com_dev *ena_dev; 178 struct pci_dev *pdev; 179 u32 tx_queue_size; 180 u32 rx_queue_size; 181 u32 max_tx_queue_size; 182 u32 max_rx_queue_size; 183 u16 max_tx_sgl_size; 184 u16 max_rx_sgl_size; 185 }; 186 187 struct ena_tx_buffer { 188 struct sk_buff *skb; 189 /* num of ena desc for this specific skb 190 * (includes data desc and metadata desc) 191 */ 192 u32 tx_descs; 193 /* num of buffers used by this skb */ 194 u32 num_of_bufs; 195 196 /* XDP buffer structure which is used for sending packets in 197 * the xdp queues 198 */ 199 struct xdp_frame *xdpf; 200 /* The rx page for the rx buffer that was received in rx and 201 * re transmitted on xdp tx queues as a result of XDP_TX action. 202 * We need to free the page once we finished cleaning the buffer in 203 * clean_xdp_irq() 204 */ 205 struct page *xdp_rx_page; 206 207 /* Indicate if bufs[0] map the linear data of the skb. */ 208 u8 map_linear_data; 209 210 /* Used for detect missing tx packets to limit the number of prints */ 211 u32 print_once; 212 /* Save the last jiffies to detect missing tx packets 213 * 214 * sets to non zero value on ena_start_xmit and set to zero on 215 * napi and timer_Service_routine. 216 * 217 * while this value is not protected by lock, 218 * a given packet is not expected to be handled by ena_start_xmit 219 * and by napi/timer_service at the same time. 220 */ 221 unsigned long last_jiffies; 222 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 223 } ____cacheline_aligned; 224 225 struct ena_rx_buffer { 226 struct sk_buff *skb; 227 struct page *page; 228 u32 page_offset; 229 struct ena_com_buf ena_buf; 230 } ____cacheline_aligned; 231 232 struct ena_stats_tx { 233 u64 cnt; 234 u64 bytes; 235 u64 queue_stop; 236 u64 prepare_ctx_err; 237 u64 queue_wakeup; 238 u64 dma_mapping_err; 239 u64 linearize; 240 u64 linearize_failed; 241 u64 napi_comp; 242 u64 tx_poll; 243 u64 doorbells; 244 u64 bad_req_id; 245 u64 llq_buffer_copy; 246 u64 missed_tx; 247 u64 unmask_interrupt; 248 }; 249 250 struct ena_stats_rx { 251 u64 cnt; 252 u64 bytes; 253 u64 rx_copybreak_pkt; 254 u64 csum_good; 255 u64 refil_partial; 256 u64 bad_csum; 257 u64 page_alloc_fail; 258 u64 skb_alloc_fail; 259 u64 dma_mapping_err; 260 u64 bad_desc_num; 261 u64 bad_req_id; 262 u64 empty_rx_ring; 263 u64 csum_unchecked; 264 u64 xdp_aborted; 265 u64 xdp_drop; 266 u64 xdp_pass; 267 u64 xdp_tx; 268 u64 xdp_invalid; 269 }; 270 271 struct ena_ring { 272 /* Holds the empty requests for TX/RX 273 * out of order completions 274 */ 275 u16 *free_ids; 276 277 union { 278 struct ena_tx_buffer *tx_buffer_info; 279 struct ena_rx_buffer *rx_buffer_info; 280 }; 281 282 /* cache ptr to avoid using the adapter */ 283 struct device *dev; 284 struct pci_dev *pdev; 285 struct napi_struct *napi; 286 struct net_device *netdev; 287 struct ena_com_dev *ena_dev; 288 struct ena_adapter *adapter; 289 struct ena_com_io_cq *ena_com_io_cq; 290 struct ena_com_io_sq *ena_com_io_sq; 291 struct bpf_prog *xdp_bpf_prog; 292 struct xdp_rxq_info xdp_rxq; 293 294 u16 next_to_use; 295 u16 next_to_clean; 296 u16 rx_copybreak; 297 u16 rx_headroom; 298 u16 qid; 299 u16 mtu; 300 u16 sgl_size; 301 302 /* The maximum header length the device can handle */ 303 u8 tx_max_header_size; 304 305 bool first_interrupt; 306 bool disable_meta_caching; 307 u16 no_interrupt_event_cnt; 308 309 /* cpu for TPH */ 310 int cpu; 311 /* number of tx/rx_buffer_info's entries */ 312 int ring_size; 313 314 enum ena_admin_placement_policy_type tx_mem_queue_type; 315 316 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]; 317 u32 smoothed_interval; 318 u32 per_napi_packets; 319 u16 non_empty_napi_events; 320 struct u64_stats_sync syncp; 321 union { 322 struct ena_stats_tx tx_stats; 323 struct ena_stats_rx rx_stats; 324 }; 325 326 u8 *push_buf_intermediate_buf; 327 int empty_rx_queue; 328 } ____cacheline_aligned; 329 330 struct ena_stats_dev { 331 u64 tx_timeout; 332 u64 suspend; 333 u64 resume; 334 u64 wd_expired; 335 u64 interface_up; 336 u64 interface_down; 337 u64 admin_q_pause; 338 u64 rx_drops; 339 u64 tx_drops; 340 }; 341 342 enum ena_flags_t { 343 ENA_FLAG_DEVICE_RUNNING, 344 ENA_FLAG_DEV_UP, 345 ENA_FLAG_LINK_UP, 346 ENA_FLAG_MSIX_ENABLED, 347 ENA_FLAG_TRIGGER_RESET, 348 ENA_FLAG_ONGOING_RESET 349 }; 350 351 /* adapter specific private data structure */ 352 struct ena_adapter { 353 struct ena_com_dev *ena_dev; 354 /* OS defined structs */ 355 struct net_device *netdev; 356 struct pci_dev *pdev; 357 358 /* rx packets that shorter that this len will be copied to the skb 359 * header 360 */ 361 u32 rx_copybreak; 362 u32 max_mtu; 363 364 u32 num_io_queues; 365 u32 max_num_io_queues; 366 367 int msix_vecs; 368 369 u32 missing_tx_completion_threshold; 370 371 u32 requested_tx_ring_size; 372 u32 requested_rx_ring_size; 373 374 u32 max_tx_ring_size; 375 u32 max_rx_ring_size; 376 377 u32 msg_enable; 378 379 u16 max_tx_sgl_size; 380 u16 max_rx_sgl_size; 381 382 u8 mac_addr[ETH_ALEN]; 383 384 unsigned long keep_alive_timeout; 385 unsigned long missing_tx_completion_to; 386 387 char name[ENA_NAME_MAX_LEN]; 388 389 unsigned long flags; 390 /* TX */ 391 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES] 392 ____cacheline_aligned_in_smp; 393 394 /* RX */ 395 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES] 396 ____cacheline_aligned_in_smp; 397 398 struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES]; 399 400 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)]; 401 402 /* timer service */ 403 struct work_struct reset_task; 404 struct timer_list timer_service; 405 406 bool wd_state; 407 bool dev_up_before_reset; 408 bool disable_meta_caching; 409 unsigned long last_keep_alive_jiffies; 410 411 struct u64_stats_sync syncp; 412 struct ena_stats_dev dev_stats; 413 struct ena_admin_eni_stats eni_stats; 414 bool eni_stats_supported; 415 416 /* last queue index that was checked for uncompleted tx packets */ 417 u32 last_monitored_tx_qid; 418 419 enum ena_regs_reset_reason_types reset_reason; 420 421 struct bpf_prog *xdp_bpf_prog; 422 u32 xdp_first_ring; 423 u32 xdp_num_queues; 424 }; 425 426 void ena_set_ethtool_ops(struct net_device *netdev); 427 428 void ena_dump_stats_to_dmesg(struct ena_adapter *adapter); 429 430 void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf); 431 432 int ena_update_hw_stats(struct ena_adapter *adapter); 433 434 int ena_update_queue_sizes(struct ena_adapter *adapter, 435 u32 new_tx_size, 436 u32 new_rx_size); 437 438 int ena_update_queue_count(struct ena_adapter *adapter, u32 new_channel_count); 439 440 int ena_get_sset_count(struct net_device *netdev, int sset); 441 442 enum ena_xdp_errors_t { 443 ENA_XDP_ALLOWED = 0, 444 ENA_XDP_CURRENT_MTU_TOO_LARGE, 445 ENA_XDP_NO_ENOUGH_QUEUES, 446 }; 447 448 static inline bool ena_xdp_queues_present(struct ena_adapter *adapter) 449 { 450 return adapter->xdp_first_ring != 0; 451 } 452 453 static inline bool ena_xdp_present(struct ena_adapter *adapter) 454 { 455 return !!adapter->xdp_bpf_prog; 456 } 457 458 static inline bool ena_xdp_present_ring(struct ena_ring *ring) 459 { 460 return !!ring->xdp_bpf_prog; 461 } 462 463 static inline int ena_xdp_legal_queue_count(struct ena_adapter *adapter, 464 u32 queues) 465 { 466 return 2 * queues <= adapter->max_num_io_queues; 467 } 468 469 static inline enum ena_xdp_errors_t ena_xdp_allowed(struct ena_adapter *adapter) 470 { 471 enum ena_xdp_errors_t rc = ENA_XDP_ALLOWED; 472 473 if (adapter->netdev->mtu > ENA_XDP_MAX_MTU) 474 rc = ENA_XDP_CURRENT_MTU_TOO_LARGE; 475 else if (!ena_xdp_legal_queue_count(adapter, adapter->num_io_queues)) 476 rc = ENA_XDP_NO_ENOUGH_QUEUES; 477 478 return rc; 479 } 480 481 #endif /* !(ENA_H) */ 482