1 /* 2 * Copyright 2015 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef ENA_COM 34 #define ENA_COM 35 36 #include <linux/compiler.h> 37 #include <linux/delay.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/gfp.h> 40 #include <linux/io.h> 41 #include <linux/prefetch.h> 42 #include <linux/sched.h> 43 #include <linux/sizes.h> 44 #include <linux/spinlock.h> 45 #include <linux/types.h> 46 #include <linux/wait.h> 47 48 #include "ena_common_defs.h" 49 #include "ena_admin_defs.h" 50 #include "ena_eth_io_defs.h" 51 #include "ena_regs_defs.h" 52 53 #undef pr_fmt 54 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 55 56 #define ENA_MAX_NUM_IO_QUEUES 128U 57 /* We need to queues for each IO (on for Tx and one for Rx) */ 58 #define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES)) 59 60 #define ENA_MAX_HANDLERS 256 61 62 #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48 63 64 /* Unit in usec */ 65 #define ENA_REG_READ_TIMEOUT 200000 66 67 #define ADMIN_SQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aq_entry)) 68 #define ADMIN_CQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_acq_entry)) 69 #define ADMIN_AENQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aenq_entry)) 70 71 /*****************************************************************************/ 72 /*****************************************************************************/ 73 /* ENA adaptive interrupt moderation settings */ 74 75 #define ENA_INTR_LOWEST_USECS (0) 76 #define ENA_INTR_LOWEST_PKTS (3) 77 #define ENA_INTR_LOWEST_BYTES (2 * 1524) 78 79 #define ENA_INTR_LOW_USECS (32) 80 #define ENA_INTR_LOW_PKTS (12) 81 #define ENA_INTR_LOW_BYTES (16 * 1024) 82 83 #define ENA_INTR_MID_USECS (80) 84 #define ENA_INTR_MID_PKTS (48) 85 #define ENA_INTR_MID_BYTES (64 * 1024) 86 87 #define ENA_INTR_HIGH_USECS (128) 88 #define ENA_INTR_HIGH_PKTS (96) 89 #define ENA_INTR_HIGH_BYTES (128 * 1024) 90 91 #define ENA_INTR_HIGHEST_USECS (192) 92 #define ENA_INTR_HIGHEST_PKTS (128) 93 #define ENA_INTR_HIGHEST_BYTES (192 * 1024) 94 95 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS 196 96 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 4 97 #define ENA_INTR_DELAY_OLD_VALUE_WEIGHT 6 98 #define ENA_INTR_DELAY_NEW_VALUE_WEIGHT 4 99 #define ENA_INTR_MODER_LEVEL_STRIDE 2 100 #define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED 0xFFFFFF 101 102 #define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF 103 104 #define ENA_FEATURE_MAX_QUEUE_EXT_VER 1 105 106 enum ena_intr_moder_level { 107 ENA_INTR_MODER_LOWEST = 0, 108 ENA_INTR_MODER_LOW, 109 ENA_INTR_MODER_MID, 110 ENA_INTR_MODER_HIGH, 111 ENA_INTR_MODER_HIGHEST, 112 ENA_INTR_MAX_NUM_OF_LEVELS, 113 }; 114 115 struct ena_llq_configurations { 116 enum ena_admin_llq_header_location llq_header_location; 117 enum ena_admin_llq_ring_entry_size llq_ring_entry_size; 118 enum ena_admin_llq_stride_ctrl llq_stride_ctrl; 119 enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header; 120 u16 llq_ring_entry_size_value; 121 }; 122 123 struct ena_intr_moder_entry { 124 unsigned int intr_moder_interval; 125 unsigned int pkts_per_interval; 126 unsigned int bytes_per_interval; 127 }; 128 129 enum queue_direction { 130 ENA_COM_IO_QUEUE_DIRECTION_TX, 131 ENA_COM_IO_QUEUE_DIRECTION_RX 132 }; 133 134 struct ena_com_buf { 135 dma_addr_t paddr; /**< Buffer physical address */ 136 u16 len; /**< Buffer length in bytes */ 137 }; 138 139 struct ena_com_rx_buf_info { 140 u16 len; 141 u16 req_id; 142 }; 143 144 struct ena_com_io_desc_addr { 145 u8 __iomem *pbuf_dev_addr; /* LLQ address */ 146 u8 *virt_addr; 147 dma_addr_t phys_addr; 148 }; 149 150 struct ena_com_tx_meta { 151 u16 mss; 152 u16 l3_hdr_len; 153 u16 l3_hdr_offset; 154 u16 l4_hdr_len; /* In words */ 155 }; 156 157 struct ena_com_llq_info { 158 u16 header_location_ctrl; 159 u16 desc_stride_ctrl; 160 u16 desc_list_entry_size_ctrl; 161 u16 desc_list_entry_size; 162 u16 descs_num_before_header; 163 u16 descs_per_entry; 164 u16 max_entries_in_tx_burst; 165 }; 166 167 struct ena_com_io_cq { 168 struct ena_com_io_desc_addr cdesc_addr; 169 170 /* Interrupt unmask register */ 171 u32 __iomem *unmask_reg; 172 173 /* The completion queue head doorbell register */ 174 u32 __iomem *cq_head_db_reg; 175 176 /* numa configuration register (for TPH) */ 177 u32 __iomem *numa_node_cfg_reg; 178 179 /* The value to write to the above register to unmask 180 * the interrupt of this queue 181 */ 182 u32 msix_vector; 183 184 enum queue_direction direction; 185 186 /* holds the number of cdesc of the current packet */ 187 u16 cur_rx_pkt_cdesc_count; 188 /* save the firt cdesc idx of the current packet */ 189 u16 cur_rx_pkt_cdesc_start_idx; 190 191 u16 q_depth; 192 /* Caller qid */ 193 u16 qid; 194 195 /* Device queue index */ 196 u16 idx; 197 u16 head; 198 u16 last_head_update; 199 u8 phase; 200 u8 cdesc_entry_size_in_bytes; 201 202 } ____cacheline_aligned; 203 204 struct ena_com_io_bounce_buffer_control { 205 u8 *base_buffer; 206 u16 next_to_use; 207 u16 buffer_size; 208 u16 buffers_num; /* Must be a power of 2 */ 209 }; 210 211 /* This struct is to keep tracking the current location of the next llq entry */ 212 struct ena_com_llq_pkt_ctrl { 213 u8 *curr_bounce_buf; 214 u16 idx; 215 u16 descs_left_in_line; 216 }; 217 218 struct ena_com_io_sq { 219 struct ena_com_io_desc_addr desc_addr; 220 221 u32 __iomem *db_addr; 222 u8 __iomem *header_addr; 223 224 enum queue_direction direction; 225 enum ena_admin_placement_policy_type mem_queue_type; 226 227 u32 msix_vector; 228 struct ena_com_tx_meta cached_tx_meta; 229 struct ena_com_llq_info llq_info; 230 struct ena_com_llq_pkt_ctrl llq_buf_ctrl; 231 struct ena_com_io_bounce_buffer_control bounce_buf_ctrl; 232 233 u16 q_depth; 234 u16 qid; 235 236 u16 idx; 237 u16 tail; 238 u16 next_to_comp; 239 u16 llq_last_copy_tail; 240 u32 tx_max_header_size; 241 u8 phase; 242 u8 desc_entry_size; 243 u8 dma_addr_bits; 244 u16 entries_in_tx_burst_left; 245 } ____cacheline_aligned; 246 247 struct ena_com_admin_cq { 248 struct ena_admin_acq_entry *entries; 249 dma_addr_t dma_addr; 250 251 u16 head; 252 u8 phase; 253 }; 254 255 struct ena_com_admin_sq { 256 struct ena_admin_aq_entry *entries; 257 dma_addr_t dma_addr; 258 259 u32 __iomem *db_addr; 260 261 u16 head; 262 u16 tail; 263 u8 phase; 264 265 }; 266 267 struct ena_com_stats_admin { 268 u32 aborted_cmd; 269 u32 submitted_cmd; 270 u32 completed_cmd; 271 u32 out_of_space; 272 u32 no_completion; 273 }; 274 275 struct ena_com_admin_queue { 276 void *q_dmadev; 277 spinlock_t q_lock; /* spinlock for the admin queue */ 278 279 struct ena_comp_ctx *comp_ctx; 280 u32 completion_timeout; 281 u16 q_depth; 282 struct ena_com_admin_cq cq; 283 struct ena_com_admin_sq sq; 284 285 /* Indicate if the admin queue should poll for completion */ 286 bool polling; 287 288 /* Define if fallback to polling mode should occur */ 289 bool auto_polling; 290 291 u16 curr_cmd_id; 292 293 /* Indicate that the ena was initialized and can 294 * process new admin commands 295 */ 296 bool running_state; 297 298 /* Count the number of outstanding admin commands */ 299 atomic_t outstanding_cmds; 300 301 struct ena_com_stats_admin stats; 302 }; 303 304 struct ena_aenq_handlers; 305 306 struct ena_com_aenq { 307 u16 head; 308 u8 phase; 309 struct ena_admin_aenq_entry *entries; 310 dma_addr_t dma_addr; 311 u16 q_depth; 312 struct ena_aenq_handlers *aenq_handlers; 313 }; 314 315 struct ena_com_mmio_read { 316 struct ena_admin_ena_mmio_req_read_less_resp *read_resp; 317 dma_addr_t read_resp_dma_addr; 318 u32 reg_read_to; /* in us */ 319 u16 seq_num; 320 bool readless_supported; 321 /* spin lock to ensure a single outstanding read */ 322 spinlock_t lock; 323 }; 324 325 struct ena_rss { 326 /* Indirect table */ 327 u16 *host_rss_ind_tbl; 328 struct ena_admin_rss_ind_table_entry *rss_ind_tbl; 329 dma_addr_t rss_ind_tbl_dma_addr; 330 u16 tbl_log_size; 331 332 /* Hash key */ 333 enum ena_admin_hash_functions hash_func; 334 struct ena_admin_feature_rss_flow_hash_control *hash_key; 335 dma_addr_t hash_key_dma_addr; 336 u32 hash_init_val; 337 338 /* Flow Control */ 339 struct ena_admin_feature_rss_hash_control *hash_ctrl; 340 dma_addr_t hash_ctrl_dma_addr; 341 342 }; 343 344 struct ena_host_attribute { 345 /* Debug area */ 346 u8 *debug_area_virt_addr; 347 dma_addr_t debug_area_dma_addr; 348 u32 debug_area_size; 349 350 /* Host information */ 351 struct ena_admin_host_info *host_info; 352 dma_addr_t host_info_dma_addr; 353 }; 354 355 struct ena_extra_properties_strings { 356 u8 *virt_addr; 357 dma_addr_t dma_addr; 358 u32 size; 359 }; 360 361 /* Each ena_dev is a PCI function. */ 362 struct ena_com_dev { 363 struct ena_com_admin_queue admin_queue; 364 struct ena_com_aenq aenq; 365 struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES]; 366 struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES]; 367 u8 __iomem *reg_bar; 368 void __iomem *mem_bar; 369 void *dmadev; 370 371 enum ena_admin_placement_policy_type tx_mem_queue_type; 372 u32 tx_max_header_size; 373 u16 stats_func; /* Selected function for extended statistic dump */ 374 u16 stats_queue; /* Selected queue for extended statistic dump */ 375 376 struct ena_com_mmio_read mmio_read; 377 378 struct ena_rss rss; 379 u32 supported_features; 380 u32 dma_addr_bits; 381 382 struct ena_host_attribute host_attr; 383 bool adaptive_coalescing; 384 u16 intr_delay_resolution; 385 u32 intr_moder_tx_interval; 386 struct ena_intr_moder_entry *intr_moder_tbl; 387 388 struct ena_com_llq_info llq_info; 389 struct ena_extra_properties_strings extra_properties_strings; 390 }; 391 392 struct ena_com_dev_get_features_ctx { 393 struct ena_admin_queue_feature_desc max_queues; 394 struct ena_admin_queue_ext_feature_desc max_queue_ext; 395 struct ena_admin_device_attr_feature_desc dev_attr; 396 struct ena_admin_feature_aenq_desc aenq; 397 struct ena_admin_feature_offload_desc offload; 398 struct ena_admin_ena_hw_hints hw_hints; 399 struct ena_admin_feature_llq_desc llq; 400 }; 401 402 struct ena_com_create_io_ctx { 403 enum ena_admin_placement_policy_type mem_queue_type; 404 enum queue_direction direction; 405 int numa_node; 406 u32 msix_vector; 407 u16 queue_size; 408 u16 qid; 409 }; 410 411 typedef void (*ena_aenq_handler)(void *data, 412 struct ena_admin_aenq_entry *aenq_e); 413 414 /* Holds aenq handlers. Indexed by AENQ event group */ 415 struct ena_aenq_handlers { 416 ena_aenq_handler handlers[ENA_MAX_HANDLERS]; 417 ena_aenq_handler unimplemented_handler; 418 }; 419 420 /*****************************************************************************/ 421 /*****************************************************************************/ 422 423 /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism 424 * @ena_dev: ENA communication layer struct 425 * 426 * Initialize the register read mechanism. 427 * 428 * @note: This method must be the first stage in the initialization sequence. 429 * 430 * @return - 0 on success, negative value on failure. 431 */ 432 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev); 433 434 /* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism 435 * @ena_dev: ENA communication layer struct 436 * @readless_supported: readless mode (enable/disable) 437 */ 438 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, 439 bool readless_supported); 440 441 /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return 442 * value physical address. 443 * @ena_dev: ENA communication layer struct 444 */ 445 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev); 446 447 /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism 448 * @ena_dev: ENA communication layer struct 449 */ 450 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev); 451 452 /* ena_com_admin_init - Init the admin and the async queues 453 * @ena_dev: ENA communication layer struct 454 * @aenq_handlers: Those handlers to be called upon event. 455 * 456 * Initialize the admin submission and completion queues. 457 * Initialize the asynchronous events notification queues. 458 * 459 * @return - 0 on success, negative value on failure. 460 */ 461 int ena_com_admin_init(struct ena_com_dev *ena_dev, 462 struct ena_aenq_handlers *aenq_handlers); 463 464 /* ena_com_admin_destroy - Destroy the admin and the async events queues. 465 * @ena_dev: ENA communication layer struct 466 * 467 * @note: Before calling this method, the caller must validate that the device 468 * won't send any additional admin completions/aenq. 469 * To achieve that, a FLR is recommended. 470 */ 471 void ena_com_admin_destroy(struct ena_com_dev *ena_dev); 472 473 /* ena_com_dev_reset - Perform device FLR to the device. 474 * @ena_dev: ENA communication layer struct 475 * @reset_reason: Specify what is the trigger for the reset in case of an error. 476 * 477 * @return - 0 on success, negative value on failure. 478 */ 479 int ena_com_dev_reset(struct ena_com_dev *ena_dev, 480 enum ena_regs_reset_reason_types reset_reason); 481 482 /* ena_com_create_io_queue - Create io queue. 483 * @ena_dev: ENA communication layer struct 484 * @ctx - create context structure 485 * 486 * Create the submission and the completion queues. 487 * 488 * @return - 0 on success, negative value on failure. 489 */ 490 int ena_com_create_io_queue(struct ena_com_dev *ena_dev, 491 struct ena_com_create_io_ctx *ctx); 492 493 /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid. 494 * @ena_dev: ENA communication layer struct 495 * @qid - the caller virtual queue id. 496 */ 497 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid); 498 499 /* ena_com_get_io_handlers - Return the io queue handlers 500 * @ena_dev: ENA communication layer struct 501 * @qid - the caller virtual queue id. 502 * @io_sq - IO submission queue handler 503 * @io_cq - IO completion queue handler. 504 * 505 * @return - 0 on success, negative value on failure. 506 */ 507 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, 508 struct ena_com_io_sq **io_sq, 509 struct ena_com_io_cq **io_cq); 510 511 /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications 512 * @ena_dev: ENA communication layer struct 513 * 514 * After this method, aenq event can be received via AENQ. 515 */ 516 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev); 517 518 /* ena_com_set_admin_running_state - Set the state of the admin queue 519 * @ena_dev: ENA communication layer struct 520 * 521 * Change the state of the admin queue (enable/disable) 522 */ 523 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state); 524 525 /* ena_com_get_admin_running_state - Get the admin queue state 526 * @ena_dev: ENA communication layer struct 527 * 528 * Retrieve the state of the admin queue (enable/disable) 529 * 530 * @return - current polling mode (enable/disable) 531 */ 532 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev); 533 534 /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode 535 * @ena_dev: ENA communication layer struct 536 * @polling: ENAble/Disable polling mode 537 * 538 * Set the admin completion mode. 539 */ 540 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling); 541 542 /* ena_com_set_admin_polling_mode - Get the admin completion queue polling mode 543 * @ena_dev: ENA communication layer struct 544 * 545 * Get the admin completion mode. 546 * If polling mode is on, ena_com_execute_admin_command will perform a 547 * polling on the admin completion queue for the commands completion, 548 * otherwise it will wait on wait event. 549 * 550 * @return state 551 */ 552 bool ena_com_get_ena_admin_polling_mode(struct ena_com_dev *ena_dev); 553 554 /* ena_com_set_admin_auto_polling_mode - Enable autoswitch to polling mode 555 * @ena_dev: ENA communication layer struct 556 * @polling: Enable/Disable polling mode 557 * 558 * Set the autopolling mode. 559 * If autopolling is on: 560 * In case of missing interrupt when data is available switch to polling. 561 */ 562 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev, 563 bool polling); 564 565 /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler 566 * @ena_dev: ENA communication layer struct 567 * 568 * This method go over the admin completion queue and wake up all the pending 569 * threads that wait on the commands wait event. 570 * 571 * @note: Should be called after MSI-X interrupt. 572 */ 573 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev); 574 575 /* ena_com_aenq_intr_handler - AENQ interrupt handler 576 * @ena_dev: ENA communication layer struct 577 * 578 * This method go over the async event notification queue and call the proper 579 * aenq handler. 580 */ 581 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data); 582 583 /* ena_com_abort_admin_commands - Abort all the outstanding admin commands. 584 * @ena_dev: ENA communication layer struct 585 * 586 * This method aborts all the outstanding admin commands. 587 * The caller should then call ena_com_wait_for_abort_completion to make sure 588 * all the commands were completed. 589 */ 590 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev); 591 592 /* ena_com_wait_for_abort_completion - Wait for admin commands abort. 593 * @ena_dev: ENA communication layer struct 594 * 595 * This method wait until all the outstanding admin commands will be completed. 596 */ 597 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev); 598 599 /* ena_com_validate_version - Validate the device parameters 600 * @ena_dev: ENA communication layer struct 601 * 602 * This method validate the device parameters are the same as the saved 603 * parameters in ena_dev. 604 * This method is useful after device reset, to validate the device mac address 605 * and the device offloads are the same as before the reset. 606 * 607 * @return - 0 on success negative value otherwise. 608 */ 609 int ena_com_validate_version(struct ena_com_dev *ena_dev); 610 611 /* ena_com_get_link_params - Retrieve physical link parameters. 612 * @ena_dev: ENA communication layer struct 613 * @resp: Link parameters 614 * 615 * Retrieve the physical link parameters, 616 * like speed, auto-negotiation and full duplex support. 617 * 618 * @return - 0 on Success negative value otherwise. 619 */ 620 int ena_com_get_link_params(struct ena_com_dev *ena_dev, 621 struct ena_admin_get_feat_resp *resp); 622 623 /* ena_com_extra_properties_strings_init - Initialize the extra properties strings buffer. 624 * @ena_dev: ENA communication layer struct 625 * 626 * Initialize the extra properties strings buffer. 627 */ 628 int ena_com_extra_properties_strings_init(struct ena_com_dev *ena_dev); 629 630 /* ena_com_delete_extra_properties_strings - Free the extra properties strings buffer. 631 * @ena_dev: ENA communication layer struct 632 * 633 * Free the allocated extra properties strings buffer. 634 */ 635 void ena_com_delete_extra_properties_strings(struct ena_com_dev *ena_dev); 636 637 /* ena_com_get_extra_properties_flags - Retrieve extra properties flags. 638 * @ena_dev: ENA communication layer struct 639 * @resp: Extra properties flags. 640 * 641 * Retrieve the extra properties flags. 642 * 643 * @return - 0 on Success negative value otherwise. 644 */ 645 int ena_com_get_extra_properties_flags(struct ena_com_dev *ena_dev, 646 struct ena_admin_get_feat_resp *resp); 647 648 /* ena_com_get_dma_width - Retrieve physical dma address width the device 649 * supports. 650 * @ena_dev: ENA communication layer struct 651 * 652 * Retrieve the maximum physical address bits the device can handle. 653 * 654 * @return: > 0 on Success and negative value otherwise. 655 */ 656 int ena_com_get_dma_width(struct ena_com_dev *ena_dev); 657 658 /* ena_com_set_aenq_config - Set aenq groups configurations 659 * @ena_dev: ENA communication layer struct 660 * @groups flag: bit fields flags of enum ena_admin_aenq_group. 661 * 662 * Configure which aenq event group the driver would like to receive. 663 * 664 * @return: 0 on Success and negative value otherwise. 665 */ 666 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag); 667 668 /* ena_com_get_dev_attr_feat - Get device features 669 * @ena_dev: ENA communication layer struct 670 * @get_feat_ctx: returned context that contain the get features. 671 * 672 * @return: 0 on Success and negative value otherwise. 673 */ 674 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, 675 struct ena_com_dev_get_features_ctx *get_feat_ctx); 676 677 /* ena_com_get_dev_basic_stats - Get device basic statistics 678 * @ena_dev: ENA communication layer struct 679 * @stats: stats return value 680 * 681 * @return: 0 on Success and negative value otherwise. 682 */ 683 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, 684 struct ena_admin_basic_stats *stats); 685 686 /* ena_com_set_dev_mtu - Configure the device mtu. 687 * @ena_dev: ENA communication layer struct 688 * @mtu: mtu value 689 * 690 * @return: 0 on Success and negative value otherwise. 691 */ 692 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu); 693 694 /* ena_com_get_offload_settings - Retrieve the device offloads capabilities 695 * @ena_dev: ENA communication layer struct 696 * @offlad: offload return value 697 * 698 * @return: 0 on Success and negative value otherwise. 699 */ 700 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, 701 struct ena_admin_feature_offload_desc *offload); 702 703 /* ena_com_rss_init - Init RSS 704 * @ena_dev: ENA communication layer struct 705 * @log_size: indirection log size 706 * 707 * Allocate RSS/RFS resources. 708 * The caller then can configure rss using ena_com_set_hash_function, 709 * ena_com_set_hash_ctrl and ena_com_indirect_table_set. 710 * 711 * @return: 0 on Success and negative value otherwise. 712 */ 713 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size); 714 715 /* ena_com_rss_destroy - Destroy rss 716 * @ena_dev: ENA communication layer struct 717 * 718 * Free all the RSS/RFS resources. 719 */ 720 void ena_com_rss_destroy(struct ena_com_dev *ena_dev); 721 722 /* ena_com_fill_hash_function - Fill RSS hash function 723 * @ena_dev: ENA communication layer struct 724 * @func: The hash function (Toeplitz or crc) 725 * @key: Hash key (for toeplitz hash) 726 * @key_len: key length (max length 10 DW) 727 * @init_val: initial value for the hash function 728 * 729 * Fill the ena_dev resources with the desire hash function, hash key, key_len 730 * and key initial value (if needed by the hash function). 731 * To flush the key into the device the caller should call 732 * ena_com_set_hash_function. 733 * 734 * @return: 0 on Success and negative value otherwise. 735 */ 736 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, 737 enum ena_admin_hash_functions func, 738 const u8 *key, u16 key_len, u32 init_val); 739 740 /* ena_com_set_hash_function - Flush the hash function and it dependencies to 741 * the device. 742 * @ena_dev: ENA communication layer struct 743 * 744 * Flush the hash function and it dependencies (key, key length and 745 * initial value) if needed. 746 * 747 * @note: Prior to this method the caller should call ena_com_fill_hash_function 748 * 749 * @return: 0 on Success and negative value otherwise. 750 */ 751 int ena_com_set_hash_function(struct ena_com_dev *ena_dev); 752 753 /* ena_com_get_hash_function - Retrieve the hash function and the hash key 754 * from the device. 755 * @ena_dev: ENA communication layer struct 756 * @func: hash function 757 * @key: hash key 758 * 759 * Retrieve the hash function and the hash key from the device. 760 * 761 * @note: If the caller called ena_com_fill_hash_function but didn't flash 762 * it to the device, the new configuration will be lost. 763 * 764 * @return: 0 on Success and negative value otherwise. 765 */ 766 int ena_com_get_hash_function(struct ena_com_dev *ena_dev, 767 enum ena_admin_hash_functions *func, 768 u8 *key); 769 770 /* ena_com_fill_hash_ctrl - Fill RSS hash control 771 * @ena_dev: ENA communication layer struct. 772 * @proto: The protocol to configure. 773 * @hash_fields: bit mask of ena_admin_flow_hash_fields 774 * 775 * Fill the ena_dev resources with the desire hash control (the ethernet 776 * fields that take part of the hash) for a specific protocol. 777 * To flush the hash control to the device, the caller should call 778 * ena_com_set_hash_ctrl. 779 * 780 * @return: 0 on Success and negative value otherwise. 781 */ 782 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, 783 enum ena_admin_flow_hash_proto proto, 784 u16 hash_fields); 785 786 /* ena_com_set_hash_ctrl - Flush the hash control resources to the device. 787 * @ena_dev: ENA communication layer struct 788 * 789 * Flush the hash control (the ethernet fields that take part of the hash) 790 * 791 * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl. 792 * 793 * @return: 0 on Success and negative value otherwise. 794 */ 795 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev); 796 797 /* ena_com_get_hash_ctrl - Retrieve the hash control from the device. 798 * @ena_dev: ENA communication layer struct 799 * @proto: The protocol to retrieve. 800 * @fields: bit mask of ena_admin_flow_hash_fields. 801 * 802 * Retrieve the hash control from the device. 803 * 804 * @note, If the caller called ena_com_fill_hash_ctrl but didn't flash 805 * it to the device, the new configuration will be lost. 806 * 807 * @return: 0 on Success and negative value otherwise. 808 */ 809 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, 810 enum ena_admin_flow_hash_proto proto, 811 u16 *fields); 812 813 /* ena_com_set_default_hash_ctrl - Set the hash control to a default 814 * configuration. 815 * @ena_dev: ENA communication layer struct 816 * 817 * Fill the ena_dev resources with the default hash control configuration. 818 * To flush the hash control to the device, the caller should call 819 * ena_com_set_hash_ctrl. 820 * 821 * @return: 0 on Success and negative value otherwise. 822 */ 823 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev); 824 825 /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS 826 * indirection table 827 * @ena_dev: ENA communication layer struct. 828 * @entry_idx - indirection table entry. 829 * @entry_value - redirection value 830 * 831 * Fill a single entry of the RSS indirection table in the ena_dev resources. 832 * To flush the indirection table to the device, the called should call 833 * ena_com_indirect_table_set. 834 * 835 * @return: 0 on Success and negative value otherwise. 836 */ 837 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, 838 u16 entry_idx, u16 entry_value); 839 840 /* ena_com_indirect_table_set - Flush the indirection table to the device. 841 * @ena_dev: ENA communication layer struct 842 * 843 * Flush the indirection hash control to the device. 844 * Prior to this method the caller should call ena_com_indirect_table_fill_entry 845 * 846 * @return: 0 on Success and negative value otherwise. 847 */ 848 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev); 849 850 /* ena_com_indirect_table_get - Retrieve the indirection table from the device. 851 * @ena_dev: ENA communication layer struct 852 * @ind_tbl: indirection table 853 * 854 * Retrieve the RSS indirection table from the device. 855 * 856 * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash 857 * it to the device, the new configuration will be lost. 858 * 859 * @return: 0 on Success and negative value otherwise. 860 */ 861 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl); 862 863 /* ena_com_allocate_host_info - Allocate host info resources. 864 * @ena_dev: ENA communication layer struct 865 * 866 * @return: 0 on Success and negative value otherwise. 867 */ 868 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev); 869 870 /* ena_com_allocate_debug_area - Allocate debug area. 871 * @ena_dev: ENA communication layer struct 872 * @debug_area_size - debug area size. 873 * 874 * @return: 0 on Success and negative value otherwise. 875 */ 876 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, 877 u32 debug_area_size); 878 879 /* ena_com_delete_debug_area - Free the debug area resources. 880 * @ena_dev: ENA communication layer struct 881 * 882 * Free the allocate debug area. 883 */ 884 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev); 885 886 /* ena_com_delete_host_info - Free the host info resources. 887 * @ena_dev: ENA communication layer struct 888 * 889 * Free the allocate host info. 890 */ 891 void ena_com_delete_host_info(struct ena_com_dev *ena_dev); 892 893 /* ena_com_set_host_attributes - Update the device with the host 894 * attributes (debug area and host info) base address. 895 * @ena_dev: ENA communication layer struct 896 * 897 * @return: 0 on Success and negative value otherwise. 898 */ 899 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev); 900 901 /* ena_com_create_io_cq - Create io completion queue. 902 * @ena_dev: ENA communication layer struct 903 * @io_cq - io completion queue handler 904 905 * Create IO completion queue. 906 * 907 * @return - 0 on success, negative value on failure. 908 */ 909 int ena_com_create_io_cq(struct ena_com_dev *ena_dev, 910 struct ena_com_io_cq *io_cq); 911 912 /* ena_com_destroy_io_cq - Destroy io completion queue. 913 * @ena_dev: ENA communication layer struct 914 * @io_cq - io completion queue handler 915 916 * Destroy IO completion queue. 917 * 918 * @return - 0 on success, negative value on failure. 919 */ 920 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, 921 struct ena_com_io_cq *io_cq); 922 923 /* ena_com_execute_admin_command - Execute admin command 924 * @admin_queue: admin queue. 925 * @cmd: the admin command to execute. 926 * @cmd_size: the command size. 927 * @cmd_completion: command completion return value. 928 * @cmd_comp_size: command completion size. 929 930 * Submit an admin command and then wait until the device will return a 931 * completion. 932 * The completion will be copyed into cmd_comp. 933 * 934 * @return - 0 on success, negative value on failure. 935 */ 936 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, 937 struct ena_admin_aq_entry *cmd, 938 size_t cmd_size, 939 struct ena_admin_acq_entry *cmd_comp, 940 size_t cmd_comp_size); 941 942 /* ena_com_init_interrupt_moderation - Init interrupt moderation 943 * @ena_dev: ENA communication layer struct 944 * 945 * @return - 0 on success, negative value on failure. 946 */ 947 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev); 948 949 /* ena_com_destroy_interrupt_moderation - Destroy interrupt moderation resources 950 * @ena_dev: ENA communication layer struct 951 */ 952 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev); 953 954 /* ena_com_interrupt_moderation_supported - Return if interrupt moderation 955 * capability is supported by the device. 956 * 957 * @return - supported or not. 958 */ 959 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev); 960 961 /* ena_com_config_default_interrupt_moderation_table - Restore the interrupt 962 * moderation table back to the default parameters. 963 * @ena_dev: ENA communication layer struct 964 */ 965 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev); 966 967 /* ena_com_update_nonadaptive_moderation_interval_tx - Update the 968 * non-adaptive interval in Tx direction. 969 * @ena_dev: ENA communication layer struct 970 * @tx_coalesce_usecs: Interval in usec. 971 * 972 * @return - 0 on success, negative value on failure. 973 */ 974 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, 975 u32 tx_coalesce_usecs); 976 977 /* ena_com_update_nonadaptive_moderation_interval_rx - Update the 978 * non-adaptive interval in Rx direction. 979 * @ena_dev: ENA communication layer struct 980 * @rx_coalesce_usecs: Interval in usec. 981 * 982 * @return - 0 on success, negative value on failure. 983 */ 984 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, 985 u32 rx_coalesce_usecs); 986 987 /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the 988 * non-adaptive interval in Tx direction. 989 * @ena_dev: ENA communication layer struct 990 * 991 * @return - interval in usec 992 */ 993 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev); 994 995 /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the 996 * non-adaptive interval in Rx direction. 997 * @ena_dev: ENA communication layer struct 998 * 999 * @return - interval in usec 1000 */ 1001 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev); 1002 1003 /* ena_com_init_intr_moderation_entry - Update a single entry in the interrupt 1004 * moderation table. 1005 * @ena_dev: ENA communication layer struct 1006 * @level: Interrupt moderation table level 1007 * @entry: Entry value 1008 * 1009 * Update a single entry in the interrupt moderation table. 1010 */ 1011 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev, 1012 enum ena_intr_moder_level level, 1013 struct ena_intr_moder_entry *entry); 1014 1015 /* ena_com_get_intr_moderation_entry - Init ena_intr_moder_entry. 1016 * @ena_dev: ENA communication layer struct 1017 * @level: Interrupt moderation table level 1018 * @entry: Entry to fill. 1019 * 1020 * Initialize the entry according to the adaptive interrupt moderation table. 1021 */ 1022 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev, 1023 enum ena_intr_moder_level level, 1024 struct ena_intr_moder_entry *entry); 1025 1026 /* ena_com_config_dev_mode - Configure the placement policy of the device. 1027 * @ena_dev: ENA communication layer struct 1028 * @llq_features: LLQ feature descriptor, retrieve via 1029 * ena_com_get_dev_attr_feat. 1030 * @ena_llq_config: The default driver LLQ parameters configurations 1031 */ 1032 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, 1033 struct ena_admin_feature_llq_desc *llq_features, 1034 struct ena_llq_configurations *llq_default_config); 1035 1036 static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev) 1037 { 1038 return ena_dev->adaptive_coalescing; 1039 } 1040 1041 static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev) 1042 { 1043 ena_dev->adaptive_coalescing = true; 1044 } 1045 1046 static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev) 1047 { 1048 ena_dev->adaptive_coalescing = false; 1049 } 1050 1051 /* ena_com_calculate_interrupt_delay - Calculate new interrupt delay 1052 * @ena_dev: ENA communication layer struct 1053 * @pkts: Number of packets since the last update 1054 * @bytes: Number of bytes received since the last update. 1055 * @smoothed_interval: Returned interval 1056 * @moder_tbl_idx: Current table level as input update new level as return 1057 * value. 1058 */ 1059 static inline void ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev, 1060 unsigned int pkts, 1061 unsigned int bytes, 1062 unsigned int *smoothed_interval, 1063 unsigned int *moder_tbl_idx) 1064 { 1065 enum ena_intr_moder_level curr_moder_idx, new_moder_idx; 1066 struct ena_intr_moder_entry *curr_moder_entry; 1067 struct ena_intr_moder_entry *pred_moder_entry; 1068 struct ena_intr_moder_entry *new_moder_entry; 1069 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 1070 unsigned int interval; 1071 1072 /* We apply adaptive moderation on Rx path only. 1073 * Tx uses static interrupt moderation. 1074 */ 1075 if (!pkts || !bytes) 1076 /* Tx interrupt, or spurious interrupt, 1077 * in both cases we just use same delay values 1078 */ 1079 return; 1080 1081 curr_moder_idx = (enum ena_intr_moder_level)(*moder_tbl_idx); 1082 if (unlikely(curr_moder_idx >= ENA_INTR_MAX_NUM_OF_LEVELS)) { 1083 pr_err("Wrong moderation index %u\n", curr_moder_idx); 1084 return; 1085 } 1086 1087 curr_moder_entry = &intr_moder_tbl[curr_moder_idx]; 1088 new_moder_idx = curr_moder_idx; 1089 1090 if (curr_moder_idx == ENA_INTR_MODER_LOWEST) { 1091 if ((pkts > curr_moder_entry->pkts_per_interval) || 1092 (bytes > curr_moder_entry->bytes_per_interval)) 1093 new_moder_idx = 1094 (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE); 1095 } else { 1096 pred_moder_entry = &intr_moder_tbl[curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE]; 1097 1098 if ((pkts <= pred_moder_entry->pkts_per_interval) || 1099 (bytes <= pred_moder_entry->bytes_per_interval)) 1100 new_moder_idx = 1101 (enum ena_intr_moder_level)(curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE); 1102 else if ((pkts > curr_moder_entry->pkts_per_interval) || 1103 (bytes > curr_moder_entry->bytes_per_interval)) { 1104 if (curr_moder_idx != ENA_INTR_MODER_HIGHEST) 1105 new_moder_idx = 1106 (enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE); 1107 } 1108 } 1109 new_moder_entry = &intr_moder_tbl[new_moder_idx]; 1110 1111 interval = new_moder_entry->intr_moder_interval; 1112 *smoothed_interval = ( 1113 (interval * ENA_INTR_DELAY_NEW_VALUE_WEIGHT + 1114 ENA_INTR_DELAY_OLD_VALUE_WEIGHT * (*smoothed_interval)) + 5) / 1115 10; 1116 1117 *moder_tbl_idx = new_moder_idx; 1118 } 1119 1120 /* ena_com_update_intr_reg - Prepare interrupt register 1121 * @intr_reg: interrupt register to update. 1122 * @rx_delay_interval: Rx interval in usecs 1123 * @tx_delay_interval: Tx interval in usecs 1124 * @unmask: unask enable/disable 1125 * 1126 * Prepare interrupt update register with the supplied parameters. 1127 */ 1128 static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg, 1129 u32 rx_delay_interval, 1130 u32 tx_delay_interval, 1131 bool unmask) 1132 { 1133 intr_reg->intr_control = 0; 1134 intr_reg->intr_control |= rx_delay_interval & 1135 ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 1136 1137 intr_reg->intr_control |= 1138 (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) 1139 & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; 1140 1141 if (unmask) 1142 intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; 1143 } 1144 1145 static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl) 1146 { 1147 u16 size, buffers_num; 1148 u8 *buf; 1149 1150 size = bounce_buf_ctrl->buffer_size; 1151 buffers_num = bounce_buf_ctrl->buffers_num; 1152 1153 buf = bounce_buf_ctrl->base_buffer + 1154 (bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size; 1155 1156 prefetchw(bounce_buf_ctrl->base_buffer + 1157 (bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size); 1158 1159 return buf; 1160 } 1161 1162 #endif /* !(ENA_COM) */ 1163