1 /*
2  * Copyright 2015 Amazon.com, Inc. or its affiliates.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef ENA_COM
34 #define ENA_COM
35 
36 #include <linux/compiler.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/gfp.h>
40 #include <linux/sched.h>
41 #include <linux/sizes.h>
42 #include <linux/spinlock.h>
43 #include <linux/types.h>
44 #include <linux/wait.h>
45 
46 #include "ena_common_defs.h"
47 #include "ena_admin_defs.h"
48 #include "ena_eth_io_defs.h"
49 #include "ena_regs_defs.h"
50 
51 #undef pr_fmt
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
53 
54 #define ENA_MAX_NUM_IO_QUEUES		128U
55 /* We need to queues for each IO (on for Tx and one for Rx) */
56 #define ENA_TOTAL_NUM_QUEUES		(2 * (ENA_MAX_NUM_IO_QUEUES))
57 
58 #define ENA_MAX_HANDLERS 256
59 
60 #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48
61 
62 /* Unit in usec */
63 #define ENA_REG_READ_TIMEOUT 200000
64 
65 #define ADMIN_SQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_aq_entry))
66 #define ADMIN_CQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_acq_entry))
67 #define ADMIN_AENQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_aenq_entry))
68 
69 /*****************************************************************************/
70 /*****************************************************************************/
71 /* ENA adaptive interrupt moderation settings */
72 
73 #define ENA_INTR_LOWEST_USECS           (0)
74 #define ENA_INTR_LOWEST_PKTS            (3)
75 #define ENA_INTR_LOWEST_BYTES           (2 * 1524)
76 
77 #define ENA_INTR_LOW_USECS              (32)
78 #define ENA_INTR_LOW_PKTS               (12)
79 #define ENA_INTR_LOW_BYTES              (16 * 1024)
80 
81 #define ENA_INTR_MID_USECS              (80)
82 #define ENA_INTR_MID_PKTS               (48)
83 #define ENA_INTR_MID_BYTES              (64 * 1024)
84 
85 #define ENA_INTR_HIGH_USECS             (128)
86 #define ENA_INTR_HIGH_PKTS              (96)
87 #define ENA_INTR_HIGH_BYTES             (128 * 1024)
88 
89 #define ENA_INTR_HIGHEST_USECS          (192)
90 #define ENA_INTR_HIGHEST_PKTS           (128)
91 #define ENA_INTR_HIGHEST_BYTES          (192 * 1024)
92 
93 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS		196
94 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS		4
95 #define ENA_INTR_DELAY_OLD_VALUE_WEIGHT			6
96 #define ENA_INTR_DELAY_NEW_VALUE_WEIGHT			4
97 #define ENA_INTR_MODER_LEVEL_STRIDE			2
98 #define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED		0xFFFFFF
99 
100 #define ENA_HW_HINTS_NO_TIMEOUT				0xFFFF
101 
102 enum ena_intr_moder_level {
103 	ENA_INTR_MODER_LOWEST = 0,
104 	ENA_INTR_MODER_LOW,
105 	ENA_INTR_MODER_MID,
106 	ENA_INTR_MODER_HIGH,
107 	ENA_INTR_MODER_HIGHEST,
108 	ENA_INTR_MAX_NUM_OF_LEVELS,
109 };
110 
111 struct ena_intr_moder_entry {
112 	unsigned int intr_moder_interval;
113 	unsigned int pkts_per_interval;
114 	unsigned int bytes_per_interval;
115 };
116 
117 enum queue_direction {
118 	ENA_COM_IO_QUEUE_DIRECTION_TX,
119 	ENA_COM_IO_QUEUE_DIRECTION_RX
120 };
121 
122 struct ena_com_buf {
123 	dma_addr_t paddr; /**< Buffer physical address */
124 	u16 len; /**< Buffer length in bytes */
125 };
126 
127 struct ena_com_rx_buf_info {
128 	u16 len;
129 	u16 req_id;
130 };
131 
132 struct ena_com_io_desc_addr {
133 	u8 __iomem *pbuf_dev_addr; /* LLQ address */
134 	u8 *virt_addr;
135 	dma_addr_t phys_addr;
136 };
137 
138 struct ena_com_tx_meta {
139 	u16 mss;
140 	u16 l3_hdr_len;
141 	u16 l3_hdr_offset;
142 	u16 l4_hdr_len; /* In words */
143 };
144 
145 struct ena_com_io_cq {
146 	struct ena_com_io_desc_addr cdesc_addr;
147 
148 	/* Interrupt unmask register */
149 	u32 __iomem *unmask_reg;
150 
151 	/* The completion queue head doorbell register */
152 	u32 __iomem *cq_head_db_reg;
153 
154 	/* numa configuration register (for TPH) */
155 	u32 __iomem *numa_node_cfg_reg;
156 
157 	/* The value to write to the above register to unmask
158 	 * the interrupt of this queue
159 	 */
160 	u32 msix_vector;
161 
162 	enum queue_direction direction;
163 
164 	/* holds the number of cdesc of the current packet */
165 	u16 cur_rx_pkt_cdesc_count;
166 	/* save the firt cdesc idx of the current packet */
167 	u16 cur_rx_pkt_cdesc_start_idx;
168 
169 	u16 q_depth;
170 	/* Caller qid */
171 	u16 qid;
172 
173 	/* Device queue index */
174 	u16 idx;
175 	u16 head;
176 	u16 last_head_update;
177 	u8 phase;
178 	u8 cdesc_entry_size_in_bytes;
179 
180 } ____cacheline_aligned;
181 
182 struct ena_com_io_sq {
183 	struct ena_com_io_desc_addr desc_addr;
184 
185 	u32 __iomem *db_addr;
186 	u8 __iomem *header_addr;
187 
188 	enum queue_direction direction;
189 	enum ena_admin_placement_policy_type mem_queue_type;
190 
191 	u32 msix_vector;
192 	struct ena_com_tx_meta cached_tx_meta;
193 
194 	u16 q_depth;
195 	u16 qid;
196 
197 	u16 idx;
198 	u16 tail;
199 	u16 next_to_comp;
200 	u32 tx_max_header_size;
201 	u8 phase;
202 	u8 desc_entry_size;
203 	u8 dma_addr_bits;
204 } ____cacheline_aligned;
205 
206 struct ena_com_admin_cq {
207 	struct ena_admin_acq_entry *entries;
208 	dma_addr_t dma_addr;
209 
210 	u16 head;
211 	u8 phase;
212 };
213 
214 struct ena_com_admin_sq {
215 	struct ena_admin_aq_entry *entries;
216 	dma_addr_t dma_addr;
217 
218 	u32 __iomem *db_addr;
219 
220 	u16 head;
221 	u16 tail;
222 	u8 phase;
223 
224 };
225 
226 struct ena_com_stats_admin {
227 	u32 aborted_cmd;
228 	u32 submitted_cmd;
229 	u32 completed_cmd;
230 	u32 out_of_space;
231 	u32 no_completion;
232 };
233 
234 struct ena_com_admin_queue {
235 	void *q_dmadev;
236 	spinlock_t q_lock; /* spinlock for the admin queue */
237 
238 	struct ena_comp_ctx *comp_ctx;
239 	u32 completion_timeout;
240 	u16 q_depth;
241 	struct ena_com_admin_cq cq;
242 	struct ena_com_admin_sq sq;
243 
244 	/* Indicate if the admin queue should poll for completion */
245 	bool polling;
246 
247 	u16 curr_cmd_id;
248 
249 	/* Indicate that the ena was initialized and can
250 	 * process new admin commands
251 	 */
252 	bool running_state;
253 
254 	/* Count the number of outstanding admin commands */
255 	atomic_t outstanding_cmds;
256 
257 	struct ena_com_stats_admin stats;
258 };
259 
260 struct ena_aenq_handlers;
261 
262 struct ena_com_aenq {
263 	u16 head;
264 	u8 phase;
265 	struct ena_admin_aenq_entry *entries;
266 	dma_addr_t dma_addr;
267 	u16 q_depth;
268 	struct ena_aenq_handlers *aenq_handlers;
269 };
270 
271 struct ena_com_mmio_read {
272 	struct ena_admin_ena_mmio_req_read_less_resp *read_resp;
273 	dma_addr_t read_resp_dma_addr;
274 	u32 reg_read_to; /* in us */
275 	u16 seq_num;
276 	bool readless_supported;
277 	/* spin lock to ensure a single outstanding read */
278 	spinlock_t lock;
279 };
280 
281 struct ena_rss {
282 	/* Indirect table */
283 	u16 *host_rss_ind_tbl;
284 	struct ena_admin_rss_ind_table_entry *rss_ind_tbl;
285 	dma_addr_t rss_ind_tbl_dma_addr;
286 	u16 tbl_log_size;
287 
288 	/* Hash key */
289 	enum ena_admin_hash_functions hash_func;
290 	struct ena_admin_feature_rss_flow_hash_control *hash_key;
291 	dma_addr_t hash_key_dma_addr;
292 	u32 hash_init_val;
293 
294 	/* Flow Control */
295 	struct ena_admin_feature_rss_hash_control *hash_ctrl;
296 	dma_addr_t hash_ctrl_dma_addr;
297 
298 };
299 
300 struct ena_host_attribute {
301 	/* Debug area */
302 	u8 *debug_area_virt_addr;
303 	dma_addr_t debug_area_dma_addr;
304 	u32 debug_area_size;
305 
306 	/* Host information */
307 	struct ena_admin_host_info *host_info;
308 	dma_addr_t host_info_dma_addr;
309 };
310 
311 /* Each ena_dev is a PCI function. */
312 struct ena_com_dev {
313 	struct ena_com_admin_queue admin_queue;
314 	struct ena_com_aenq aenq;
315 	struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES];
316 	struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES];
317 	u8 __iomem *reg_bar;
318 	void __iomem *mem_bar;
319 	void *dmadev;
320 
321 	enum ena_admin_placement_policy_type tx_mem_queue_type;
322 	u32 tx_max_header_size;
323 	u16 stats_func; /* Selected function for extended statistic dump */
324 	u16 stats_queue; /* Selected queue for extended statistic dump */
325 
326 	struct ena_com_mmio_read mmio_read;
327 
328 	struct ena_rss rss;
329 	u32 supported_features;
330 	u32 dma_addr_bits;
331 
332 	struct ena_host_attribute host_attr;
333 	bool adaptive_coalescing;
334 	u16 intr_delay_resolution;
335 	u32 intr_moder_tx_interval;
336 	struct ena_intr_moder_entry *intr_moder_tbl;
337 };
338 
339 struct ena_com_dev_get_features_ctx {
340 	struct ena_admin_queue_feature_desc max_queues;
341 	struct ena_admin_device_attr_feature_desc dev_attr;
342 	struct ena_admin_feature_aenq_desc aenq;
343 	struct ena_admin_feature_offload_desc offload;
344 	struct ena_admin_ena_hw_hints hw_hints;
345 };
346 
347 struct ena_com_create_io_ctx {
348 	enum ena_admin_placement_policy_type mem_queue_type;
349 	enum queue_direction direction;
350 	int numa_node;
351 	u32 msix_vector;
352 	u16 queue_size;
353 	u16 qid;
354 };
355 
356 typedef void (*ena_aenq_handler)(void *data,
357 	struct ena_admin_aenq_entry *aenq_e);
358 
359 /* Holds aenq handlers. Indexed by AENQ event group */
360 struct ena_aenq_handlers {
361 	ena_aenq_handler handlers[ENA_MAX_HANDLERS];
362 	ena_aenq_handler unimplemented_handler;
363 };
364 
365 /*****************************************************************************/
366 /*****************************************************************************/
367 
368 /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism
369  * @ena_dev: ENA communication layer struct
370  *
371  * Initialize the register read mechanism.
372  *
373  * @note: This method must be the first stage in the initialization sequence.
374  *
375  * @return - 0 on success, negative value on failure.
376  */
377 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);
378 
379 /* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism
380  * @ena_dev: ENA communication layer struct
381  * @readless_supported: readless mode (enable/disable)
382  */
383 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev,
384 				bool readless_supported);
385 
386 /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return
387  * value physical address.
388  * @ena_dev: ENA communication layer struct
389  */
390 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev);
391 
392 /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism
393  * @ena_dev: ENA communication layer struct
394  */
395 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev);
396 
397 /* ena_com_admin_init - Init the admin and the async queues
398  * @ena_dev: ENA communication layer struct
399  * @aenq_handlers: Those handlers to be called upon event.
400  * @init_spinlock: Indicate if this method should init the admin spinlock or
401  * the spinlock was init before (for example, in a case of FLR).
402  *
403  * Initialize the admin submission and completion queues.
404  * Initialize the asynchronous events notification queues.
405  *
406  * @return - 0 on success, negative value on failure.
407  */
408 int ena_com_admin_init(struct ena_com_dev *ena_dev,
409 		       struct ena_aenq_handlers *aenq_handlers,
410 		       bool init_spinlock);
411 
412 /* ena_com_admin_destroy - Destroy the admin and the async events queues.
413  * @ena_dev: ENA communication layer struct
414  *
415  * @note: Before calling this method, the caller must validate that the device
416  * won't send any additional admin completions/aenq.
417  * To achieve that, a FLR is recommended.
418  */
419 void ena_com_admin_destroy(struct ena_com_dev *ena_dev);
420 
421 /* ena_com_dev_reset - Perform device FLR to the device.
422  * @ena_dev: ENA communication layer struct
423  * @reset_reason: Specify what is the trigger for the reset in case of an error.
424  *
425  * @return - 0 on success, negative value on failure.
426  */
427 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
428 		      enum ena_regs_reset_reason_types reset_reason);
429 
430 /* ena_com_create_io_queue - Create io queue.
431  * @ena_dev: ENA communication layer struct
432  * @ctx - create context structure
433  *
434  * Create the submission and the completion queues.
435  *
436  * @return - 0 on success, negative value on failure.
437  */
438 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
439 			    struct ena_com_create_io_ctx *ctx);
440 
441 /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid.
442  * @ena_dev: ENA communication layer struct
443  * @qid - the caller virtual queue id.
444  */
445 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid);
446 
447 /* ena_com_get_io_handlers - Return the io queue handlers
448  * @ena_dev: ENA communication layer struct
449  * @qid - the caller virtual queue id.
450  * @io_sq - IO submission queue handler
451  * @io_cq - IO completion queue handler.
452  *
453  * @return - 0 on success, negative value on failure.
454  */
455 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
456 			    struct ena_com_io_sq **io_sq,
457 			    struct ena_com_io_cq **io_cq);
458 
459 /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications
460  * @ena_dev: ENA communication layer struct
461  *
462  * After this method, aenq event can be received via AENQ.
463  */
464 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev);
465 
466 /* ena_com_set_admin_running_state - Set the state of the admin queue
467  * @ena_dev: ENA communication layer struct
468  *
469  * Change the state of the admin queue (enable/disable)
470  */
471 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state);
472 
473 /* ena_com_get_admin_running_state - Get the admin queue state
474  * @ena_dev: ENA communication layer struct
475  *
476  * Retrieve the state of the admin queue (enable/disable)
477  *
478  * @return - current polling mode (enable/disable)
479  */
480 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev);
481 
482 /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode
483  * @ena_dev: ENA communication layer struct
484  * @polling: ENAble/Disable polling mode
485  *
486  * Set the admin completion mode.
487  */
488 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling);
489 
490 /* ena_com_set_admin_polling_mode - Get the admin completion queue polling mode
491  * @ena_dev: ENA communication layer struct
492  *
493  * Get the admin completion mode.
494  * If polling mode is on, ena_com_execute_admin_command will perform a
495  * polling on the admin completion queue for the commands completion,
496  * otherwise it will wait on wait event.
497  *
498  * @return state
499  */
500 bool ena_com_get_ena_admin_polling_mode(struct ena_com_dev *ena_dev);
501 
502 /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler
503  * @ena_dev: ENA communication layer struct
504  *
505  * This method go over the admin completion queue and wake up all the pending
506  * threads that wait on the commands wait event.
507  *
508  * @note: Should be called after MSI-X interrupt.
509  */
510 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev);
511 
512 /* ena_com_aenq_intr_handler - AENQ interrupt handler
513  * @ena_dev: ENA communication layer struct
514  *
515  * This method go over the async event notification queue and call the proper
516  * aenq handler.
517  */
518 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data);
519 
520 /* ena_com_abort_admin_commands - Abort all the outstanding admin commands.
521  * @ena_dev: ENA communication layer struct
522  *
523  * This method aborts all the outstanding admin commands.
524  * The caller should then call ena_com_wait_for_abort_completion to make sure
525  * all the commands were completed.
526  */
527 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev);
528 
529 /* ena_com_wait_for_abort_completion - Wait for admin commands abort.
530  * @ena_dev: ENA communication layer struct
531  *
532  * This method wait until all the outstanding admin commands will be completed.
533  */
534 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev);
535 
536 /* ena_com_validate_version - Validate the device parameters
537  * @ena_dev: ENA communication layer struct
538  *
539  * This method validate the device parameters are the same as the saved
540  * parameters in ena_dev.
541  * This method is useful after device reset, to validate the device mac address
542  * and the device offloads are the same as before the reset.
543  *
544  * @return - 0 on success negative value otherwise.
545  */
546 int ena_com_validate_version(struct ena_com_dev *ena_dev);
547 
548 /* ena_com_get_link_params - Retrieve physical link parameters.
549  * @ena_dev: ENA communication layer struct
550  * @resp: Link parameters
551  *
552  * Retrieve the physical link parameters,
553  * like speed, auto-negotiation and full duplex support.
554  *
555  * @return - 0 on Success negative value otherwise.
556  */
557 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
558 			    struct ena_admin_get_feat_resp *resp);
559 
560 /* ena_com_get_dma_width - Retrieve physical dma address width the device
561  * supports.
562  * @ena_dev: ENA communication layer struct
563  *
564  * Retrieve the maximum physical address bits the device can handle.
565  *
566  * @return: > 0 on Success and negative value otherwise.
567  */
568 int ena_com_get_dma_width(struct ena_com_dev *ena_dev);
569 
570 /* ena_com_set_aenq_config - Set aenq groups configurations
571  * @ena_dev: ENA communication layer struct
572  * @groups flag: bit fields flags of enum ena_admin_aenq_group.
573  *
574  * Configure which aenq event group the driver would like to receive.
575  *
576  * @return: 0 on Success and negative value otherwise.
577  */
578 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag);
579 
580 /* ena_com_get_dev_attr_feat - Get device features
581  * @ena_dev: ENA communication layer struct
582  * @get_feat_ctx: returned context that contain the get features.
583  *
584  * @return: 0 on Success and negative value otherwise.
585  */
586 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
587 			      struct ena_com_dev_get_features_ctx *get_feat_ctx);
588 
589 /* ena_com_get_dev_basic_stats - Get device basic statistics
590  * @ena_dev: ENA communication layer struct
591  * @stats: stats return value
592  *
593  * @return: 0 on Success and negative value otherwise.
594  */
595 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
596 				struct ena_admin_basic_stats *stats);
597 
598 /* ena_com_set_dev_mtu - Configure the device mtu.
599  * @ena_dev: ENA communication layer struct
600  * @mtu: mtu value
601  *
602  * @return: 0 on Success and negative value otherwise.
603  */
604 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu);
605 
606 /* ena_com_get_offload_settings - Retrieve the device offloads capabilities
607  * @ena_dev: ENA communication layer struct
608  * @offlad: offload return value
609  *
610  * @return: 0 on Success and negative value otherwise.
611  */
612 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
613 				 struct ena_admin_feature_offload_desc *offload);
614 
615 /* ena_com_rss_init - Init RSS
616  * @ena_dev: ENA communication layer struct
617  * @log_size: indirection log size
618  *
619  * Allocate RSS/RFS resources.
620  * The caller then can configure rss using ena_com_set_hash_function,
621  * ena_com_set_hash_ctrl and ena_com_indirect_table_set.
622  *
623  * @return: 0 on Success and negative value otherwise.
624  */
625 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size);
626 
627 /* ena_com_rss_destroy - Destroy rss
628  * @ena_dev: ENA communication layer struct
629  *
630  * Free all the RSS/RFS resources.
631  */
632 void ena_com_rss_destroy(struct ena_com_dev *ena_dev);
633 
634 /* ena_com_fill_hash_function - Fill RSS hash function
635  * @ena_dev: ENA communication layer struct
636  * @func: The hash function (Toeplitz or crc)
637  * @key: Hash key (for toeplitz hash)
638  * @key_len: key length (max length 10 DW)
639  * @init_val: initial value for the hash function
640  *
641  * Fill the ena_dev resources with the desire hash function, hash key, key_len
642  * and key initial value (if needed by the hash function).
643  * To flush the key into the device the caller should call
644  * ena_com_set_hash_function.
645  *
646  * @return: 0 on Success and negative value otherwise.
647  */
648 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
649 			       enum ena_admin_hash_functions func,
650 			       const u8 *key, u16 key_len, u32 init_val);
651 
652 /* ena_com_set_hash_function - Flush the hash function and it dependencies to
653  * the device.
654  * @ena_dev: ENA communication layer struct
655  *
656  * Flush the hash function and it dependencies (key, key length and
657  * initial value) if needed.
658  *
659  * @note: Prior to this method the caller should call ena_com_fill_hash_function
660  *
661  * @return: 0 on Success and negative value otherwise.
662  */
663 int ena_com_set_hash_function(struct ena_com_dev *ena_dev);
664 
665 /* ena_com_get_hash_function - Retrieve the hash function and the hash key
666  * from the device.
667  * @ena_dev: ENA communication layer struct
668  * @func: hash function
669  * @key: hash key
670  *
671  * Retrieve the hash function and the hash key from the device.
672  *
673  * @note: If the caller called ena_com_fill_hash_function but didn't flash
674  * it to the device, the new configuration will be lost.
675  *
676  * @return: 0 on Success and negative value otherwise.
677  */
678 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
679 			      enum ena_admin_hash_functions *func,
680 			      u8 *key);
681 
682 /* ena_com_fill_hash_ctrl - Fill RSS hash control
683  * @ena_dev: ENA communication layer struct.
684  * @proto: The protocol to configure.
685  * @hash_fields: bit mask of ena_admin_flow_hash_fields
686  *
687  * Fill the ena_dev resources with the desire hash control (the ethernet
688  * fields that take part of the hash) for a specific protocol.
689  * To flush the hash control to the device, the caller should call
690  * ena_com_set_hash_ctrl.
691  *
692  * @return: 0 on Success and negative value otherwise.
693  */
694 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
695 			   enum ena_admin_flow_hash_proto proto,
696 			   u16 hash_fields);
697 
698 /* ena_com_set_hash_ctrl - Flush the hash control resources to the device.
699  * @ena_dev: ENA communication layer struct
700  *
701  * Flush the hash control (the ethernet fields that take part of the hash)
702  *
703  * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl.
704  *
705  * @return: 0 on Success and negative value otherwise.
706  */
707 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev);
708 
709 /* ena_com_get_hash_ctrl - Retrieve the hash control from the device.
710  * @ena_dev: ENA communication layer struct
711  * @proto: The protocol to retrieve.
712  * @fields: bit mask of ena_admin_flow_hash_fields.
713  *
714  * Retrieve the hash control from the device.
715  *
716  * @note, If the caller called ena_com_fill_hash_ctrl but didn't flash
717  * it to the device, the new configuration will be lost.
718  *
719  * @return: 0 on Success and negative value otherwise.
720  */
721 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
722 			  enum ena_admin_flow_hash_proto proto,
723 			  u16 *fields);
724 
725 /* ena_com_set_default_hash_ctrl - Set the hash control to a default
726  * configuration.
727  * @ena_dev: ENA communication layer struct
728  *
729  * Fill the ena_dev resources with the default hash control configuration.
730  * To flush the hash control to the device, the caller should call
731  * ena_com_set_hash_ctrl.
732  *
733  * @return: 0 on Success and negative value otherwise.
734  */
735 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev);
736 
737 /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS
738  * indirection table
739  * @ena_dev: ENA communication layer struct.
740  * @entry_idx - indirection table entry.
741  * @entry_value - redirection value
742  *
743  * Fill a single entry of the RSS indirection table in the ena_dev resources.
744  * To flush the indirection table to the device, the called should call
745  * ena_com_indirect_table_set.
746  *
747  * @return: 0 on Success and negative value otherwise.
748  */
749 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
750 				      u16 entry_idx, u16 entry_value);
751 
752 /* ena_com_indirect_table_set - Flush the indirection table to the device.
753  * @ena_dev: ENA communication layer struct
754  *
755  * Flush the indirection hash control to the device.
756  * Prior to this method the caller should call ena_com_indirect_table_fill_entry
757  *
758  * @return: 0 on Success and negative value otherwise.
759  */
760 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev);
761 
762 /* ena_com_indirect_table_get - Retrieve the indirection table from the device.
763  * @ena_dev: ENA communication layer struct
764  * @ind_tbl: indirection table
765  *
766  * Retrieve the RSS indirection table from the device.
767  *
768  * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash
769  * it to the device, the new configuration will be lost.
770  *
771  * @return: 0 on Success and negative value otherwise.
772  */
773 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl);
774 
775 /* ena_com_allocate_host_info - Allocate host info resources.
776  * @ena_dev: ENA communication layer struct
777  *
778  * @return: 0 on Success and negative value otherwise.
779  */
780 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev);
781 
782 /* ena_com_allocate_debug_area - Allocate debug area.
783  * @ena_dev: ENA communication layer struct
784  * @debug_area_size - debug area size.
785  *
786  * @return: 0 on Success and negative value otherwise.
787  */
788 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
789 				u32 debug_area_size);
790 
791 /* ena_com_delete_debug_area - Free the debug area resources.
792  * @ena_dev: ENA communication layer struct
793  *
794  * Free the allocate debug area.
795  */
796 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev);
797 
798 /* ena_com_delete_host_info - Free the host info resources.
799  * @ena_dev: ENA communication layer struct
800  *
801  * Free the allocate host info.
802  */
803 void ena_com_delete_host_info(struct ena_com_dev *ena_dev);
804 
805 /* ena_com_set_host_attributes - Update the device with the host
806  * attributes (debug area and host info) base address.
807  * @ena_dev: ENA communication layer struct
808  *
809  * @return: 0 on Success and negative value otherwise.
810  */
811 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev);
812 
813 /* ena_com_create_io_cq - Create io completion queue.
814  * @ena_dev: ENA communication layer struct
815  * @io_cq - io completion queue handler
816 
817  * Create IO completion queue.
818  *
819  * @return - 0 on success, negative value on failure.
820  */
821 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
822 			 struct ena_com_io_cq *io_cq);
823 
824 /* ena_com_destroy_io_cq - Destroy io completion queue.
825  * @ena_dev: ENA communication layer struct
826  * @io_cq - io completion queue handler
827 
828  * Destroy IO completion queue.
829  *
830  * @return - 0 on success, negative value on failure.
831  */
832 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
833 			  struct ena_com_io_cq *io_cq);
834 
835 /* ena_com_execute_admin_command - Execute admin command
836  * @admin_queue: admin queue.
837  * @cmd: the admin command to execute.
838  * @cmd_size: the command size.
839  * @cmd_completion: command completion return value.
840  * @cmd_comp_size: command completion size.
841 
842  * Submit an admin command and then wait until the device will return a
843  * completion.
844  * The completion will be copyed into cmd_comp.
845  *
846  * @return - 0 on success, negative value on failure.
847  */
848 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
849 				  struct ena_admin_aq_entry *cmd,
850 				  size_t cmd_size,
851 				  struct ena_admin_acq_entry *cmd_comp,
852 				  size_t cmd_comp_size);
853 
854 /* ena_com_init_interrupt_moderation - Init interrupt moderation
855  * @ena_dev: ENA communication layer struct
856  *
857  * @return - 0 on success, negative value on failure.
858  */
859 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev);
860 
861 /* ena_com_destroy_interrupt_moderation - Destroy interrupt moderation resources
862  * @ena_dev: ENA communication layer struct
863  */
864 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev);
865 
866 /* ena_com_interrupt_moderation_supported - Return if interrupt moderation
867  * capability is supported by the device.
868  *
869  * @return - supported or not.
870  */
871 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev);
872 
873 /* ena_com_config_default_interrupt_moderation_table - Restore the interrupt
874  * moderation table back to the default parameters.
875  * @ena_dev: ENA communication layer struct
876  */
877 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev);
878 
879 /* ena_com_update_nonadaptive_moderation_interval_tx - Update the
880  * non-adaptive interval in Tx direction.
881  * @ena_dev: ENA communication layer struct
882  * @tx_coalesce_usecs: Interval in usec.
883  *
884  * @return - 0 on success, negative value on failure.
885  */
886 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
887 						      u32 tx_coalesce_usecs);
888 
889 /* ena_com_update_nonadaptive_moderation_interval_rx - Update the
890  * non-adaptive interval in Rx direction.
891  * @ena_dev: ENA communication layer struct
892  * @rx_coalesce_usecs: Interval in usec.
893  *
894  * @return - 0 on success, negative value on failure.
895  */
896 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
897 						      u32 rx_coalesce_usecs);
898 
899 /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the
900  * non-adaptive interval in Tx direction.
901  * @ena_dev: ENA communication layer struct
902  *
903  * @return - interval in usec
904  */
905 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);
906 
907 /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the
908  * non-adaptive interval in Rx direction.
909  * @ena_dev: ENA communication layer struct
910  *
911  * @return - interval in usec
912  */
913 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev);
914 
915 /* ena_com_init_intr_moderation_entry - Update a single entry in the interrupt
916  * moderation table.
917  * @ena_dev: ENA communication layer struct
918  * @level: Interrupt moderation table level
919  * @entry: Entry value
920  *
921  * Update a single entry in the interrupt moderation table.
922  */
923 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev,
924 					enum ena_intr_moder_level level,
925 					struct ena_intr_moder_entry *entry);
926 
927 /* ena_com_get_intr_moderation_entry - Init ena_intr_moder_entry.
928  * @ena_dev: ENA communication layer struct
929  * @level: Interrupt moderation table level
930  * @entry: Entry to fill.
931  *
932  * Initialize the entry according to the adaptive interrupt moderation table.
933  */
934 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
935 				       enum ena_intr_moder_level level,
936 				       struct ena_intr_moder_entry *entry);
937 
938 static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
939 {
940 	return ena_dev->adaptive_coalescing;
941 }
942 
943 static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)
944 {
945 	ena_dev->adaptive_coalescing = true;
946 }
947 
948 static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)
949 {
950 	ena_dev->adaptive_coalescing = false;
951 }
952 
953 /* ena_com_calculate_interrupt_delay - Calculate new interrupt delay
954  * @ena_dev: ENA communication layer struct
955  * @pkts: Number of packets since the last update
956  * @bytes: Number of bytes received since the last update.
957  * @smoothed_interval: Returned interval
958  * @moder_tbl_idx: Current table level as input update new level as return
959  * value.
960  */
961 static inline void ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev,
962 						     unsigned int pkts,
963 						     unsigned int bytes,
964 						     unsigned int *smoothed_interval,
965 						     unsigned int *moder_tbl_idx)
966 {
967 	enum ena_intr_moder_level curr_moder_idx, new_moder_idx;
968 	struct ena_intr_moder_entry *curr_moder_entry;
969 	struct ena_intr_moder_entry *pred_moder_entry;
970 	struct ena_intr_moder_entry *new_moder_entry;
971 	struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl;
972 	unsigned int interval;
973 
974 	/* We apply adaptive moderation on Rx path only.
975 	 * Tx uses static interrupt moderation.
976 	 */
977 	if (!pkts || !bytes)
978 		/* Tx interrupt, or spurious interrupt,
979 		 * in both cases we just use same delay values
980 		 */
981 		return;
982 
983 	curr_moder_idx = (enum ena_intr_moder_level)(*moder_tbl_idx);
984 	if (unlikely(curr_moder_idx >= ENA_INTR_MAX_NUM_OF_LEVELS)) {
985 		pr_err("Wrong moderation index %u\n", curr_moder_idx);
986 		return;
987 	}
988 
989 	curr_moder_entry = &intr_moder_tbl[curr_moder_idx];
990 	new_moder_idx = curr_moder_idx;
991 
992 	if (curr_moder_idx == ENA_INTR_MODER_LOWEST) {
993 		if ((pkts > curr_moder_entry->pkts_per_interval) ||
994 		    (bytes > curr_moder_entry->bytes_per_interval))
995 			new_moder_idx =
996 				(enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE);
997 	} else {
998 		pred_moder_entry = &intr_moder_tbl[curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE];
999 
1000 		if ((pkts <= pred_moder_entry->pkts_per_interval) ||
1001 		    (bytes <= pred_moder_entry->bytes_per_interval))
1002 			new_moder_idx =
1003 				(enum ena_intr_moder_level)(curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE);
1004 		else if ((pkts > curr_moder_entry->pkts_per_interval) ||
1005 			 (bytes > curr_moder_entry->bytes_per_interval)) {
1006 			if (curr_moder_idx != ENA_INTR_MODER_HIGHEST)
1007 				new_moder_idx =
1008 					(enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE);
1009 		}
1010 	}
1011 	new_moder_entry = &intr_moder_tbl[new_moder_idx];
1012 
1013 	interval = new_moder_entry->intr_moder_interval;
1014 	*smoothed_interval = (
1015 		(interval * ENA_INTR_DELAY_NEW_VALUE_WEIGHT +
1016 		ENA_INTR_DELAY_OLD_VALUE_WEIGHT * (*smoothed_interval)) + 5) /
1017 		10;
1018 
1019 	*moder_tbl_idx = new_moder_idx;
1020 }
1021 
1022 /* ena_com_update_intr_reg - Prepare interrupt register
1023  * @intr_reg: interrupt register to update.
1024  * @rx_delay_interval: Rx interval in usecs
1025  * @tx_delay_interval: Tx interval in usecs
1026  * @unmask: unask enable/disable
1027  *
1028  * Prepare interrupt update register with the supplied parameters.
1029  */
1030 static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,
1031 					   u32 rx_delay_interval,
1032 					   u32 tx_delay_interval,
1033 					   bool unmask)
1034 {
1035 	intr_reg->intr_control = 0;
1036 	intr_reg->intr_control |= rx_delay_interval &
1037 		ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
1038 
1039 	intr_reg->intr_control |=
1040 		(tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
1041 		& ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
1042 
1043 	if (unmask)
1044 		intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
1045 }
1046 
1047 #endif /* !(ENA_COM) */
1048