1 /* 2 * Copyright 2015 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef ENA_COM 34 #define ENA_COM 35 36 #include <linux/compiler.h> 37 #include <linux/delay.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/gfp.h> 40 #include <linux/io.h> 41 #include <linux/prefetch.h> 42 #include <linux/sched.h> 43 #include <linux/sizes.h> 44 #include <linux/spinlock.h> 45 #include <linux/types.h> 46 #include <linux/wait.h> 47 #include <linux/netdevice.h> 48 49 #include "ena_common_defs.h" 50 #include "ena_admin_defs.h" 51 #include "ena_eth_io_defs.h" 52 #include "ena_regs_defs.h" 53 54 #undef pr_fmt 55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 56 57 #define ENA_MAX_NUM_IO_QUEUES 128U 58 /* We need to queues for each IO (on for Tx and one for Rx) */ 59 #define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES)) 60 61 #define ENA_MAX_HANDLERS 256 62 63 #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48 64 65 /* Unit in usec */ 66 #define ENA_REG_READ_TIMEOUT 200000 67 68 #define ADMIN_SQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aq_entry)) 69 #define ADMIN_CQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_acq_entry)) 70 #define ADMIN_AENQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aenq_entry)) 71 72 /*****************************************************************************/ 73 /*****************************************************************************/ 74 /* ENA adaptive interrupt moderation settings */ 75 76 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS 64 77 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 0 78 #define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1 79 80 #define ENA_HASH_KEY_SIZE 40 81 82 #define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF 83 84 #define ENA_FEATURE_MAX_QUEUE_EXT_VER 1 85 86 struct ena_llq_configurations { 87 enum ena_admin_llq_header_location llq_header_location; 88 enum ena_admin_llq_ring_entry_size llq_ring_entry_size; 89 enum ena_admin_llq_stride_ctrl llq_stride_ctrl; 90 enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header; 91 u16 llq_ring_entry_size_value; 92 }; 93 94 enum queue_direction { 95 ENA_COM_IO_QUEUE_DIRECTION_TX, 96 ENA_COM_IO_QUEUE_DIRECTION_RX 97 }; 98 99 struct ena_com_buf { 100 dma_addr_t paddr; /**< Buffer physical address */ 101 u16 len; /**< Buffer length in bytes */ 102 }; 103 104 struct ena_com_rx_buf_info { 105 u16 len; 106 u16 req_id; 107 }; 108 109 struct ena_com_io_desc_addr { 110 u8 __iomem *pbuf_dev_addr; /* LLQ address */ 111 u8 *virt_addr; 112 dma_addr_t phys_addr; 113 }; 114 115 struct ena_com_tx_meta { 116 u16 mss; 117 u16 l3_hdr_len; 118 u16 l3_hdr_offset; 119 u16 l4_hdr_len; /* In words */ 120 }; 121 122 struct ena_com_llq_info { 123 u16 header_location_ctrl; 124 u16 desc_stride_ctrl; 125 u16 desc_list_entry_size_ctrl; 126 u16 desc_list_entry_size; 127 u16 descs_num_before_header; 128 u16 descs_per_entry; 129 u16 max_entries_in_tx_burst; 130 }; 131 132 struct ena_com_io_cq { 133 struct ena_com_io_desc_addr cdesc_addr; 134 135 /* Interrupt unmask register */ 136 u32 __iomem *unmask_reg; 137 138 /* The completion queue head doorbell register */ 139 u32 __iomem *cq_head_db_reg; 140 141 /* numa configuration register (for TPH) */ 142 u32 __iomem *numa_node_cfg_reg; 143 144 /* The value to write to the above register to unmask 145 * the interrupt of this queue 146 */ 147 u32 msix_vector; 148 149 enum queue_direction direction; 150 151 /* holds the number of cdesc of the current packet */ 152 u16 cur_rx_pkt_cdesc_count; 153 /* save the firt cdesc idx of the current packet */ 154 u16 cur_rx_pkt_cdesc_start_idx; 155 156 u16 q_depth; 157 /* Caller qid */ 158 u16 qid; 159 160 /* Device queue index */ 161 u16 idx; 162 u16 head; 163 u16 last_head_update; 164 u8 phase; 165 u8 cdesc_entry_size_in_bytes; 166 167 } ____cacheline_aligned; 168 169 struct ena_com_io_bounce_buffer_control { 170 u8 *base_buffer; 171 u16 next_to_use; 172 u16 buffer_size; 173 u16 buffers_num; /* Must be a power of 2 */ 174 }; 175 176 /* This struct is to keep tracking the current location of the next llq entry */ 177 struct ena_com_llq_pkt_ctrl { 178 u8 *curr_bounce_buf; 179 u16 idx; 180 u16 descs_left_in_line; 181 }; 182 183 struct ena_com_io_sq { 184 struct ena_com_io_desc_addr desc_addr; 185 186 u32 __iomem *db_addr; 187 u8 __iomem *header_addr; 188 189 enum queue_direction direction; 190 enum ena_admin_placement_policy_type mem_queue_type; 191 192 u32 msix_vector; 193 struct ena_com_tx_meta cached_tx_meta; 194 struct ena_com_llq_info llq_info; 195 struct ena_com_llq_pkt_ctrl llq_buf_ctrl; 196 struct ena_com_io_bounce_buffer_control bounce_buf_ctrl; 197 198 u16 q_depth; 199 u16 qid; 200 201 u16 idx; 202 u16 tail; 203 u16 next_to_comp; 204 u16 llq_last_copy_tail; 205 u32 tx_max_header_size; 206 u8 phase; 207 u8 desc_entry_size; 208 u8 dma_addr_bits; 209 u16 entries_in_tx_burst_left; 210 } ____cacheline_aligned; 211 212 struct ena_com_admin_cq { 213 struct ena_admin_acq_entry *entries; 214 dma_addr_t dma_addr; 215 216 u16 head; 217 u8 phase; 218 }; 219 220 struct ena_com_admin_sq { 221 struct ena_admin_aq_entry *entries; 222 dma_addr_t dma_addr; 223 224 u32 __iomem *db_addr; 225 226 u16 head; 227 u16 tail; 228 u8 phase; 229 230 }; 231 232 struct ena_com_stats_admin { 233 u32 aborted_cmd; 234 u32 submitted_cmd; 235 u32 completed_cmd; 236 u32 out_of_space; 237 u32 no_completion; 238 }; 239 240 struct ena_com_admin_queue { 241 void *q_dmadev; 242 spinlock_t q_lock; /* spinlock for the admin queue */ 243 244 struct ena_comp_ctx *comp_ctx; 245 u32 completion_timeout; 246 u16 q_depth; 247 struct ena_com_admin_cq cq; 248 struct ena_com_admin_sq sq; 249 250 /* Indicate if the admin queue should poll for completion */ 251 bool polling; 252 253 /* Define if fallback to polling mode should occur */ 254 bool auto_polling; 255 256 u16 curr_cmd_id; 257 258 /* Indicate that the ena was initialized and can 259 * process new admin commands 260 */ 261 bool running_state; 262 263 /* Count the number of outstanding admin commands */ 264 atomic_t outstanding_cmds; 265 266 struct ena_com_stats_admin stats; 267 }; 268 269 struct ena_aenq_handlers; 270 271 struct ena_com_aenq { 272 u16 head; 273 u8 phase; 274 struct ena_admin_aenq_entry *entries; 275 dma_addr_t dma_addr; 276 u16 q_depth; 277 struct ena_aenq_handlers *aenq_handlers; 278 }; 279 280 struct ena_com_mmio_read { 281 struct ena_admin_ena_mmio_req_read_less_resp *read_resp; 282 dma_addr_t read_resp_dma_addr; 283 u32 reg_read_to; /* in us */ 284 u16 seq_num; 285 bool readless_supported; 286 /* spin lock to ensure a single outstanding read */ 287 spinlock_t lock; 288 }; 289 290 struct ena_rss { 291 /* Indirect table */ 292 u16 *host_rss_ind_tbl; 293 struct ena_admin_rss_ind_table_entry *rss_ind_tbl; 294 dma_addr_t rss_ind_tbl_dma_addr; 295 u16 tbl_log_size; 296 297 /* Hash key */ 298 enum ena_admin_hash_functions hash_func; 299 struct ena_admin_feature_rss_flow_hash_control *hash_key; 300 dma_addr_t hash_key_dma_addr; 301 u32 hash_init_val; 302 303 /* Flow Control */ 304 struct ena_admin_feature_rss_hash_control *hash_ctrl; 305 dma_addr_t hash_ctrl_dma_addr; 306 307 }; 308 309 struct ena_host_attribute { 310 /* Debug area */ 311 u8 *debug_area_virt_addr; 312 dma_addr_t debug_area_dma_addr; 313 u32 debug_area_size; 314 315 /* Host information */ 316 struct ena_admin_host_info *host_info; 317 dma_addr_t host_info_dma_addr; 318 }; 319 320 /* Each ena_dev is a PCI function. */ 321 struct ena_com_dev { 322 struct ena_com_admin_queue admin_queue; 323 struct ena_com_aenq aenq; 324 struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES]; 325 struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES]; 326 u8 __iomem *reg_bar; 327 void __iomem *mem_bar; 328 void *dmadev; 329 330 enum ena_admin_placement_policy_type tx_mem_queue_type; 331 u32 tx_max_header_size; 332 u16 stats_func; /* Selected function for extended statistic dump */ 333 u16 stats_queue; /* Selected queue for extended statistic dump */ 334 335 struct ena_com_mmio_read mmio_read; 336 337 struct ena_rss rss; 338 u32 supported_features; 339 u32 dma_addr_bits; 340 341 struct ena_host_attribute host_attr; 342 bool adaptive_coalescing; 343 u16 intr_delay_resolution; 344 345 /* interrupt moderation intervals are in usec divided by 346 * intr_delay_resolution, which is supplied by the device. 347 */ 348 u32 intr_moder_tx_interval; 349 u32 intr_moder_rx_interval; 350 351 struct ena_intr_moder_entry *intr_moder_tbl; 352 353 struct ena_com_llq_info llq_info; 354 }; 355 356 struct ena_com_dev_get_features_ctx { 357 struct ena_admin_queue_feature_desc max_queues; 358 struct ena_admin_queue_ext_feature_desc max_queue_ext; 359 struct ena_admin_device_attr_feature_desc dev_attr; 360 struct ena_admin_feature_aenq_desc aenq; 361 struct ena_admin_feature_offload_desc offload; 362 struct ena_admin_ena_hw_hints hw_hints; 363 struct ena_admin_feature_llq_desc llq; 364 }; 365 366 struct ena_com_create_io_ctx { 367 enum ena_admin_placement_policy_type mem_queue_type; 368 enum queue_direction direction; 369 int numa_node; 370 u32 msix_vector; 371 u16 queue_size; 372 u16 qid; 373 }; 374 375 typedef void (*ena_aenq_handler)(void *data, 376 struct ena_admin_aenq_entry *aenq_e); 377 378 /* Holds aenq handlers. Indexed by AENQ event group */ 379 struct ena_aenq_handlers { 380 ena_aenq_handler handlers[ENA_MAX_HANDLERS]; 381 ena_aenq_handler unimplemented_handler; 382 }; 383 384 /*****************************************************************************/ 385 /*****************************************************************************/ 386 387 /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism 388 * @ena_dev: ENA communication layer struct 389 * 390 * Initialize the register read mechanism. 391 * 392 * @note: This method must be the first stage in the initialization sequence. 393 * 394 * @return - 0 on success, negative value on failure. 395 */ 396 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev); 397 398 /* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism 399 * @ena_dev: ENA communication layer struct 400 * @readless_supported: readless mode (enable/disable) 401 */ 402 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, 403 bool readless_supported); 404 405 /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return 406 * value physical address. 407 * @ena_dev: ENA communication layer struct 408 */ 409 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev); 410 411 /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism 412 * @ena_dev: ENA communication layer struct 413 */ 414 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev); 415 416 /* ena_com_admin_init - Init the admin and the async queues 417 * @ena_dev: ENA communication layer struct 418 * @aenq_handlers: Those handlers to be called upon event. 419 * 420 * Initialize the admin submission and completion queues. 421 * Initialize the asynchronous events notification queues. 422 * 423 * @return - 0 on success, negative value on failure. 424 */ 425 int ena_com_admin_init(struct ena_com_dev *ena_dev, 426 struct ena_aenq_handlers *aenq_handlers); 427 428 /* ena_com_admin_destroy - Destroy the admin and the async events queues. 429 * @ena_dev: ENA communication layer struct 430 * 431 * @note: Before calling this method, the caller must validate that the device 432 * won't send any additional admin completions/aenq. 433 * To achieve that, a FLR is recommended. 434 */ 435 void ena_com_admin_destroy(struct ena_com_dev *ena_dev); 436 437 /* ena_com_dev_reset - Perform device FLR to the device. 438 * @ena_dev: ENA communication layer struct 439 * @reset_reason: Specify what is the trigger for the reset in case of an error. 440 * 441 * @return - 0 on success, negative value on failure. 442 */ 443 int ena_com_dev_reset(struct ena_com_dev *ena_dev, 444 enum ena_regs_reset_reason_types reset_reason); 445 446 /* ena_com_create_io_queue - Create io queue. 447 * @ena_dev: ENA communication layer struct 448 * @ctx - create context structure 449 * 450 * Create the submission and the completion queues. 451 * 452 * @return - 0 on success, negative value on failure. 453 */ 454 int ena_com_create_io_queue(struct ena_com_dev *ena_dev, 455 struct ena_com_create_io_ctx *ctx); 456 457 /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid. 458 * @ena_dev: ENA communication layer struct 459 * @qid - the caller virtual queue id. 460 */ 461 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid); 462 463 /* ena_com_get_io_handlers - Return the io queue handlers 464 * @ena_dev: ENA communication layer struct 465 * @qid - the caller virtual queue id. 466 * @io_sq - IO submission queue handler 467 * @io_cq - IO completion queue handler. 468 * 469 * @return - 0 on success, negative value on failure. 470 */ 471 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, 472 struct ena_com_io_sq **io_sq, 473 struct ena_com_io_cq **io_cq); 474 475 /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications 476 * @ena_dev: ENA communication layer struct 477 * 478 * After this method, aenq event can be received via AENQ. 479 */ 480 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev); 481 482 /* ena_com_set_admin_running_state - Set the state of the admin queue 483 * @ena_dev: ENA communication layer struct 484 * 485 * Change the state of the admin queue (enable/disable) 486 */ 487 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state); 488 489 /* ena_com_get_admin_running_state - Get the admin queue state 490 * @ena_dev: ENA communication layer struct 491 * 492 * Retrieve the state of the admin queue (enable/disable) 493 * 494 * @return - current polling mode (enable/disable) 495 */ 496 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev); 497 498 /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode 499 * @ena_dev: ENA communication layer struct 500 * @polling: ENAble/Disable polling mode 501 * 502 * Set the admin completion mode. 503 */ 504 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling); 505 506 /* ena_com_set_admin_auto_polling_mode - Enable autoswitch to polling mode 507 * @ena_dev: ENA communication layer struct 508 * @polling: Enable/Disable polling mode 509 * 510 * Set the autopolling mode. 511 * If autopolling is on: 512 * In case of missing interrupt when data is available switch to polling. 513 */ 514 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev, 515 bool polling); 516 517 /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler 518 * @ena_dev: ENA communication layer struct 519 * 520 * This method goes over the admin completion queue and wakes up all the pending 521 * threads that wait on the commands wait event. 522 * 523 * @note: Should be called after MSI-X interrupt. 524 */ 525 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev); 526 527 /* ena_com_aenq_intr_handler - AENQ interrupt handler 528 * @ena_dev: ENA communication layer struct 529 * 530 * This method goes over the async event notification queue and calls the proper 531 * aenq handler. 532 */ 533 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data); 534 535 /* ena_com_abort_admin_commands - Abort all the outstanding admin commands. 536 * @ena_dev: ENA communication layer struct 537 * 538 * This method aborts all the outstanding admin commands. 539 * The caller should then call ena_com_wait_for_abort_completion to make sure 540 * all the commands were completed. 541 */ 542 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev); 543 544 /* ena_com_wait_for_abort_completion - Wait for admin commands abort. 545 * @ena_dev: ENA communication layer struct 546 * 547 * This method waits until all the outstanding admin commands are completed. 548 */ 549 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev); 550 551 /* ena_com_validate_version - Validate the device parameters 552 * @ena_dev: ENA communication layer struct 553 * 554 * This method verifies the device parameters are the same as the saved 555 * parameters in ena_dev. 556 * This method is useful after device reset, to validate the device mac address 557 * and the device offloads are the same as before the reset. 558 * 559 * @return - 0 on success negative value otherwise. 560 */ 561 int ena_com_validate_version(struct ena_com_dev *ena_dev); 562 563 /* ena_com_get_link_params - Retrieve physical link parameters. 564 * @ena_dev: ENA communication layer struct 565 * @resp: Link parameters 566 * 567 * Retrieve the physical link parameters, 568 * like speed, auto-negotiation and full duplex support. 569 * 570 * @return - 0 on Success negative value otherwise. 571 */ 572 int ena_com_get_link_params(struct ena_com_dev *ena_dev, 573 struct ena_admin_get_feat_resp *resp); 574 575 /* ena_com_get_dma_width - Retrieve physical dma address width the device 576 * supports. 577 * @ena_dev: ENA communication layer struct 578 * 579 * Retrieve the maximum physical address bits the device can handle. 580 * 581 * @return: > 0 on Success and negative value otherwise. 582 */ 583 int ena_com_get_dma_width(struct ena_com_dev *ena_dev); 584 585 /* ena_com_set_aenq_config - Set aenq groups configurations 586 * @ena_dev: ENA communication layer struct 587 * @groups flag: bit fields flags of enum ena_admin_aenq_group. 588 * 589 * Configure which aenq event group the driver would like to receive. 590 * 591 * @return: 0 on Success and negative value otherwise. 592 */ 593 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag); 594 595 /* ena_com_get_dev_attr_feat - Get device features 596 * @ena_dev: ENA communication layer struct 597 * @get_feat_ctx: returned context that contain the get features. 598 * 599 * @return: 0 on Success and negative value otherwise. 600 */ 601 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, 602 struct ena_com_dev_get_features_ctx *get_feat_ctx); 603 604 /* ena_com_get_dev_basic_stats - Get device basic statistics 605 * @ena_dev: ENA communication layer struct 606 * @stats: stats return value 607 * 608 * @return: 0 on Success and negative value otherwise. 609 */ 610 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, 611 struct ena_admin_basic_stats *stats); 612 613 /* ena_com_set_dev_mtu - Configure the device mtu. 614 * @ena_dev: ENA communication layer struct 615 * @mtu: mtu value 616 * 617 * @return: 0 on Success and negative value otherwise. 618 */ 619 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu); 620 621 /* ena_com_get_offload_settings - Retrieve the device offloads capabilities 622 * @ena_dev: ENA communication layer struct 623 * @offlad: offload return value 624 * 625 * @return: 0 on Success and negative value otherwise. 626 */ 627 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, 628 struct ena_admin_feature_offload_desc *offload); 629 630 /* ena_com_rss_init - Init RSS 631 * @ena_dev: ENA communication layer struct 632 * @log_size: indirection log size 633 * 634 * Allocate RSS/RFS resources. 635 * The caller then can configure rss using ena_com_set_hash_function, 636 * ena_com_set_hash_ctrl and ena_com_indirect_table_set. 637 * 638 * @return: 0 on Success and negative value otherwise. 639 */ 640 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size); 641 642 /* ena_com_rss_destroy - Destroy rss 643 * @ena_dev: ENA communication layer struct 644 * 645 * Free all the RSS/RFS resources. 646 */ 647 void ena_com_rss_destroy(struct ena_com_dev *ena_dev); 648 649 /* ena_com_get_current_hash_function - Get RSS hash function 650 * @ena_dev: ENA communication layer struct 651 * 652 * Return the current hash function. 653 * @return: 0 or one of the ena_admin_hash_functions values. 654 */ 655 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev); 656 657 /* ena_com_fill_hash_function - Fill RSS hash function 658 * @ena_dev: ENA communication layer struct 659 * @func: The hash function (Toeplitz or crc) 660 * @key: Hash key (for toeplitz hash) 661 * @key_len: key length (max length 10 DW) 662 * @init_val: initial value for the hash function 663 * 664 * Fill the ena_dev resources with the desire hash function, hash key, key_len 665 * and key initial value (if needed by the hash function). 666 * To flush the key into the device the caller should call 667 * ena_com_set_hash_function. 668 * 669 * @return: 0 on Success and negative value otherwise. 670 */ 671 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, 672 enum ena_admin_hash_functions func, 673 const u8 *key, u16 key_len, u32 init_val); 674 675 /* ena_com_set_hash_function - Flush the hash function and it dependencies to 676 * the device. 677 * @ena_dev: ENA communication layer struct 678 * 679 * Flush the hash function and it dependencies (key, key length and 680 * initial value) if needed. 681 * 682 * @note: Prior to this method the caller should call ena_com_fill_hash_function 683 * 684 * @return: 0 on Success and negative value otherwise. 685 */ 686 int ena_com_set_hash_function(struct ena_com_dev *ena_dev); 687 688 /* ena_com_get_hash_function - Retrieve the hash function from the device. 689 * @ena_dev: ENA communication layer struct 690 * @func: hash function 691 * 692 * Retrieve the hash function from the device. 693 * 694 * @note: If the caller called ena_com_fill_hash_function but didn't flush 695 * it to the device, the new configuration will be lost. 696 * 697 * @return: 0 on Success and negative value otherwise. 698 */ 699 int ena_com_get_hash_function(struct ena_com_dev *ena_dev, 700 enum ena_admin_hash_functions *func); 701 702 /* ena_com_get_hash_key - Retrieve the hash key 703 * @ena_dev: ENA communication layer struct 704 * @key: hash key 705 * 706 * Retrieve the hash key. 707 * 708 * @note: If the caller called ena_com_fill_hash_key but didn't flush 709 * it to the device, the new configuration will be lost. 710 * 711 * @return: 0 on Success and negative value otherwise. 712 */ 713 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key); 714 /* ena_com_fill_hash_ctrl - Fill RSS hash control 715 * @ena_dev: ENA communication layer struct. 716 * @proto: The protocol to configure. 717 * @hash_fields: bit mask of ena_admin_flow_hash_fields 718 * 719 * Fill the ena_dev resources with the desire hash control (the ethernet 720 * fields that take part of the hash) for a specific protocol. 721 * To flush the hash control to the device, the caller should call 722 * ena_com_set_hash_ctrl. 723 * 724 * @return: 0 on Success and negative value otherwise. 725 */ 726 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, 727 enum ena_admin_flow_hash_proto proto, 728 u16 hash_fields); 729 730 /* ena_com_set_hash_ctrl - Flush the hash control resources to the device. 731 * @ena_dev: ENA communication layer struct 732 * 733 * Flush the hash control (the ethernet fields that take part of the hash) 734 * 735 * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl. 736 * 737 * @return: 0 on Success and negative value otherwise. 738 */ 739 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev); 740 741 /* ena_com_get_hash_ctrl - Retrieve the hash control from the device. 742 * @ena_dev: ENA communication layer struct 743 * @proto: The protocol to retrieve. 744 * @fields: bit mask of ena_admin_flow_hash_fields. 745 * 746 * Retrieve the hash control from the device. 747 * 748 * @note: If the caller called ena_com_fill_hash_ctrl but didn't flush 749 * it to the device, the new configuration will be lost. 750 * 751 * @return: 0 on Success and negative value otherwise. 752 */ 753 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, 754 enum ena_admin_flow_hash_proto proto, 755 u16 *fields); 756 757 /* ena_com_set_default_hash_ctrl - Set the hash control to a default 758 * configuration. 759 * @ena_dev: ENA communication layer struct 760 * 761 * Fill the ena_dev resources with the default hash control configuration. 762 * To flush the hash control to the device, the caller should call 763 * ena_com_set_hash_ctrl. 764 * 765 * @return: 0 on Success and negative value otherwise. 766 */ 767 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev); 768 769 /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS 770 * indirection table 771 * @ena_dev: ENA communication layer struct. 772 * @entry_idx - indirection table entry. 773 * @entry_value - redirection value 774 * 775 * Fill a single entry of the RSS indirection table in the ena_dev resources. 776 * To flush the indirection table to the device, the called should call 777 * ena_com_indirect_table_set. 778 * 779 * @return: 0 on Success and negative value otherwise. 780 */ 781 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, 782 u16 entry_idx, u16 entry_value); 783 784 /* ena_com_indirect_table_set - Flush the indirection table to the device. 785 * @ena_dev: ENA communication layer struct 786 * 787 * Flush the indirection hash control to the device. 788 * Prior to this method the caller should call ena_com_indirect_table_fill_entry 789 * 790 * @return: 0 on Success and negative value otherwise. 791 */ 792 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev); 793 794 /* ena_com_indirect_table_get - Retrieve the indirection table from the device. 795 * @ena_dev: ENA communication layer struct 796 * @ind_tbl: indirection table 797 * 798 * Retrieve the RSS indirection table from the device. 799 * 800 * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flush 801 * it to the device, the new configuration will be lost. 802 * 803 * @return: 0 on Success and negative value otherwise. 804 */ 805 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl); 806 807 /* ena_com_allocate_host_info - Allocate host info resources. 808 * @ena_dev: ENA communication layer struct 809 * 810 * @return: 0 on Success and negative value otherwise. 811 */ 812 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev); 813 814 /* ena_com_allocate_debug_area - Allocate debug area. 815 * @ena_dev: ENA communication layer struct 816 * @debug_area_size - debug area size. 817 * 818 * @return: 0 on Success and negative value otherwise. 819 */ 820 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, 821 u32 debug_area_size); 822 823 /* ena_com_delete_debug_area - Free the debug area resources. 824 * @ena_dev: ENA communication layer struct 825 * 826 * Free the allocated debug area. 827 */ 828 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev); 829 830 /* ena_com_delete_host_info - Free the host info resources. 831 * @ena_dev: ENA communication layer struct 832 * 833 * Free the allocated host info. 834 */ 835 void ena_com_delete_host_info(struct ena_com_dev *ena_dev); 836 837 /* ena_com_set_host_attributes - Update the device with the host 838 * attributes (debug area and host info) base address. 839 * @ena_dev: ENA communication layer struct 840 * 841 * @return: 0 on Success and negative value otherwise. 842 */ 843 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev); 844 845 /* ena_com_create_io_cq - Create io completion queue. 846 * @ena_dev: ENA communication layer struct 847 * @io_cq - io completion queue handler 848 849 * Create IO completion queue. 850 * 851 * @return - 0 on success, negative value on failure. 852 */ 853 int ena_com_create_io_cq(struct ena_com_dev *ena_dev, 854 struct ena_com_io_cq *io_cq); 855 856 /* ena_com_destroy_io_cq - Destroy io completion queue. 857 * @ena_dev: ENA communication layer struct 858 * @io_cq - io completion queue handler 859 860 * Destroy IO completion queue. 861 * 862 * @return - 0 on success, negative value on failure. 863 */ 864 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, 865 struct ena_com_io_cq *io_cq); 866 867 /* ena_com_execute_admin_command - Execute admin command 868 * @admin_queue: admin queue. 869 * @cmd: the admin command to execute. 870 * @cmd_size: the command size. 871 * @cmd_completion: command completion return value. 872 * @cmd_comp_size: command completion size. 873 874 * Submit an admin command and then wait until the device returns a 875 * completion. 876 * The completion will be copied into cmd_comp. 877 * 878 * @return - 0 on success, negative value on failure. 879 */ 880 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, 881 struct ena_admin_aq_entry *cmd, 882 size_t cmd_size, 883 struct ena_admin_acq_entry *cmd_comp, 884 size_t cmd_comp_size); 885 886 /* ena_com_init_interrupt_moderation - Init interrupt moderation 887 * @ena_dev: ENA communication layer struct 888 * 889 * @return - 0 on success, negative value on failure. 890 */ 891 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev); 892 893 /* ena_com_interrupt_moderation_supported - Return if interrupt moderation 894 * capability is supported by the device. 895 * 896 * @return - supported or not. 897 */ 898 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev); 899 900 /* ena_com_update_nonadaptive_moderation_interval_tx - Update the 901 * non-adaptive interval in Tx direction. 902 * @ena_dev: ENA communication layer struct 903 * @tx_coalesce_usecs: Interval in usec. 904 * 905 * @return - 0 on success, negative value on failure. 906 */ 907 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, 908 u32 tx_coalesce_usecs); 909 910 /* ena_com_update_nonadaptive_moderation_interval_rx - Update the 911 * non-adaptive interval in Rx direction. 912 * @ena_dev: ENA communication layer struct 913 * @rx_coalesce_usecs: Interval in usec. 914 * 915 * @return - 0 on success, negative value on failure. 916 */ 917 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, 918 u32 rx_coalesce_usecs); 919 920 /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the 921 * non-adaptive interval in Tx direction. 922 * @ena_dev: ENA communication layer struct 923 * 924 * @return - interval in usec 925 */ 926 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev); 927 928 /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the 929 * non-adaptive interval in Rx direction. 930 * @ena_dev: ENA communication layer struct 931 * 932 * @return - interval in usec 933 */ 934 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev); 935 936 /* ena_com_config_dev_mode - Configure the placement policy of the device. 937 * @ena_dev: ENA communication layer struct 938 * @llq_features: LLQ feature descriptor, retrieve via 939 * ena_com_get_dev_attr_feat. 940 * @ena_llq_config: The default driver LLQ parameters configurations 941 */ 942 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, 943 struct ena_admin_feature_llq_desc *llq_features, 944 struct ena_llq_configurations *llq_default_config); 945 946 static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev) 947 { 948 return ena_dev->adaptive_coalescing; 949 } 950 951 static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev) 952 { 953 ena_dev->adaptive_coalescing = true; 954 } 955 956 static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev) 957 { 958 ena_dev->adaptive_coalescing = false; 959 } 960 961 /* ena_com_update_intr_reg - Prepare interrupt register 962 * @intr_reg: interrupt register to update. 963 * @rx_delay_interval: Rx interval in usecs 964 * @tx_delay_interval: Tx interval in usecs 965 * @unmask: unmask enable/disable 966 * 967 * Prepare interrupt update register with the supplied parameters. 968 */ 969 static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg, 970 u32 rx_delay_interval, 971 u32 tx_delay_interval, 972 bool unmask) 973 { 974 intr_reg->intr_control = 0; 975 intr_reg->intr_control |= rx_delay_interval & 976 ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 977 978 intr_reg->intr_control |= 979 (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) 980 & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; 981 982 if (unmask) 983 intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; 984 } 985 986 static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl) 987 { 988 u16 size, buffers_num; 989 u8 *buf; 990 991 size = bounce_buf_ctrl->buffer_size; 992 buffers_num = bounce_buf_ctrl->buffers_num; 993 994 buf = bounce_buf_ctrl->base_buffer + 995 (bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size; 996 997 prefetchw(bounce_buf_ctrl->base_buffer + 998 (bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size); 999 1000 return buf; 1001 } 1002 1003 #endif /* !(ENA_COM) */ 1004