1 /*
2  * Copyright 2015 Amazon.com, Inc. or its affiliates.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef ENA_COM
34 #define ENA_COM
35 
36 #include <linux/compiler.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/gfp.h>
40 #include <linux/io.h>
41 #include <linux/prefetch.h>
42 #include <linux/sched.h>
43 #include <linux/sizes.h>
44 #include <linux/spinlock.h>
45 #include <linux/types.h>
46 #include <linux/wait.h>
47 #include <linux/netdevice.h>
48 
49 #include "ena_common_defs.h"
50 #include "ena_admin_defs.h"
51 #include "ena_eth_io_defs.h"
52 #include "ena_regs_defs.h"
53 
54 #undef pr_fmt
55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56 
57 #define ENA_MAX_NUM_IO_QUEUES 128U
58 /* We need to queues for each IO (on for Tx and one for Rx) */
59 #define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES))
60 
61 #define ENA_MAX_HANDLERS 256
62 
63 #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48
64 
65 /* Unit in usec */
66 #define ENA_REG_READ_TIMEOUT 200000
67 
68 #define ADMIN_SQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_aq_entry))
69 #define ADMIN_CQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_acq_entry))
70 #define ADMIN_AENQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_aenq_entry))
71 
72 /*****************************************************************************/
73 /*****************************************************************************/
74 /* ENA adaptive interrupt moderation settings */
75 
76 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS 64
77 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 0
78 #define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1
79 
80 #define ENA_HASH_KEY_SIZE 40
81 
82 #define ENA_HW_HINTS_NO_TIMEOUT	0xFFFF
83 
84 #define ENA_FEATURE_MAX_QUEUE_EXT_VER 1
85 
86 struct ena_llq_configurations {
87 	enum ena_admin_llq_header_location llq_header_location;
88 	enum ena_admin_llq_ring_entry_size llq_ring_entry_size;
89 	enum ena_admin_llq_stride_ctrl  llq_stride_ctrl;
90 	enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header;
91 	u16 llq_ring_entry_size_value;
92 };
93 
94 enum queue_direction {
95 	ENA_COM_IO_QUEUE_DIRECTION_TX,
96 	ENA_COM_IO_QUEUE_DIRECTION_RX
97 };
98 
99 struct ena_com_buf {
100 	dma_addr_t paddr; /**< Buffer physical address */
101 	u16 len; /**< Buffer length in bytes */
102 };
103 
104 struct ena_com_rx_buf_info {
105 	u16 len;
106 	u16 req_id;
107 };
108 
109 struct ena_com_io_desc_addr {
110 	u8 __iomem *pbuf_dev_addr; /* LLQ address */
111 	u8 *virt_addr;
112 	dma_addr_t phys_addr;
113 };
114 
115 struct ena_com_tx_meta {
116 	u16 mss;
117 	u16 l3_hdr_len;
118 	u16 l3_hdr_offset;
119 	u16 l4_hdr_len; /* In words */
120 };
121 
122 struct ena_com_llq_info {
123 	u16 header_location_ctrl;
124 	u16 desc_stride_ctrl;
125 	u16 desc_list_entry_size_ctrl;
126 	u16 desc_list_entry_size;
127 	u16 descs_num_before_header;
128 	u16 descs_per_entry;
129 	u16 max_entries_in_tx_burst;
130 };
131 
132 struct ena_com_io_cq {
133 	struct ena_com_io_desc_addr cdesc_addr;
134 
135 	/* Interrupt unmask register */
136 	u32 __iomem *unmask_reg;
137 
138 	/* The completion queue head doorbell register */
139 	u32 __iomem *cq_head_db_reg;
140 
141 	/* numa configuration register (for TPH) */
142 	u32 __iomem *numa_node_cfg_reg;
143 
144 	/* The value to write to the above register to unmask
145 	 * the interrupt of this queue
146 	 */
147 	u32 msix_vector;
148 
149 	enum queue_direction direction;
150 
151 	/* holds the number of cdesc of the current packet */
152 	u16 cur_rx_pkt_cdesc_count;
153 	/* save the firt cdesc idx of the current packet */
154 	u16 cur_rx_pkt_cdesc_start_idx;
155 
156 	u16 q_depth;
157 	/* Caller qid */
158 	u16 qid;
159 
160 	/* Device queue index */
161 	u16 idx;
162 	u16 head;
163 	u16 last_head_update;
164 	u8 phase;
165 	u8 cdesc_entry_size_in_bytes;
166 
167 } ____cacheline_aligned;
168 
169 struct ena_com_io_bounce_buffer_control {
170 	u8 *base_buffer;
171 	u16 next_to_use;
172 	u16 buffer_size;
173 	u16 buffers_num;  /* Must be a power of 2 */
174 };
175 
176 /* This struct is to keep tracking the current location of the next llq entry */
177 struct ena_com_llq_pkt_ctrl {
178 	u8 *curr_bounce_buf;
179 	u16 idx;
180 	u16 descs_left_in_line;
181 };
182 
183 struct ena_com_io_sq {
184 	struct ena_com_io_desc_addr desc_addr;
185 
186 	u32 __iomem *db_addr;
187 	u8 __iomem *header_addr;
188 
189 	enum queue_direction direction;
190 	enum ena_admin_placement_policy_type mem_queue_type;
191 
192 	u32 msix_vector;
193 	struct ena_com_tx_meta cached_tx_meta;
194 	struct ena_com_llq_info llq_info;
195 	struct ena_com_llq_pkt_ctrl llq_buf_ctrl;
196 	struct ena_com_io_bounce_buffer_control bounce_buf_ctrl;
197 
198 	u16 q_depth;
199 	u16 qid;
200 
201 	u16 idx;
202 	u16 tail;
203 	u16 next_to_comp;
204 	u16 llq_last_copy_tail;
205 	u32 tx_max_header_size;
206 	u8 phase;
207 	u8 desc_entry_size;
208 	u8 dma_addr_bits;
209 	u16 entries_in_tx_burst_left;
210 } ____cacheline_aligned;
211 
212 struct ena_com_admin_cq {
213 	struct ena_admin_acq_entry *entries;
214 	dma_addr_t dma_addr;
215 
216 	u16 head;
217 	u8 phase;
218 };
219 
220 struct ena_com_admin_sq {
221 	struct ena_admin_aq_entry *entries;
222 	dma_addr_t dma_addr;
223 
224 	u32 __iomem *db_addr;
225 
226 	u16 head;
227 	u16 tail;
228 	u8 phase;
229 
230 };
231 
232 struct ena_com_stats_admin {
233 	u32 aborted_cmd;
234 	u32 submitted_cmd;
235 	u32 completed_cmd;
236 	u32 out_of_space;
237 	u32 no_completion;
238 };
239 
240 struct ena_com_admin_queue {
241 	void *q_dmadev;
242 	struct ena_com_dev *ena_dev;
243 	spinlock_t q_lock; /* spinlock for the admin queue */
244 
245 	struct ena_comp_ctx *comp_ctx;
246 	u32 completion_timeout;
247 	u16 q_depth;
248 	struct ena_com_admin_cq cq;
249 	struct ena_com_admin_sq sq;
250 
251 	/* Indicate if the admin queue should poll for completion */
252 	bool polling;
253 
254 	/* Define if fallback to polling mode should occur */
255 	bool auto_polling;
256 
257 	u16 curr_cmd_id;
258 
259 	/* Indicate that the ena was initialized and can
260 	 * process new admin commands
261 	 */
262 	bool running_state;
263 
264 	/* Count the number of outstanding admin commands */
265 	atomic_t outstanding_cmds;
266 
267 	struct ena_com_stats_admin stats;
268 };
269 
270 struct ena_aenq_handlers;
271 
272 struct ena_com_aenq {
273 	u16 head;
274 	u8 phase;
275 	struct ena_admin_aenq_entry *entries;
276 	dma_addr_t dma_addr;
277 	u16 q_depth;
278 	struct ena_aenq_handlers *aenq_handlers;
279 };
280 
281 struct ena_com_mmio_read {
282 	struct ena_admin_ena_mmio_req_read_less_resp *read_resp;
283 	dma_addr_t read_resp_dma_addr;
284 	u32 reg_read_to; /* in us */
285 	u16 seq_num;
286 	bool readless_supported;
287 	/* spin lock to ensure a single outstanding read */
288 	spinlock_t lock;
289 };
290 
291 struct ena_rss {
292 	/* Indirect table */
293 	u16 *host_rss_ind_tbl;
294 	struct ena_admin_rss_ind_table_entry *rss_ind_tbl;
295 	dma_addr_t rss_ind_tbl_dma_addr;
296 	u16 tbl_log_size;
297 
298 	/* Hash key */
299 	enum ena_admin_hash_functions hash_func;
300 	struct ena_admin_feature_rss_flow_hash_control *hash_key;
301 	dma_addr_t hash_key_dma_addr;
302 	u32 hash_init_val;
303 
304 	/* Flow Control */
305 	struct ena_admin_feature_rss_hash_control *hash_ctrl;
306 	dma_addr_t hash_ctrl_dma_addr;
307 
308 };
309 
310 struct ena_host_attribute {
311 	/* Debug area */
312 	u8 *debug_area_virt_addr;
313 	dma_addr_t debug_area_dma_addr;
314 	u32 debug_area_size;
315 
316 	/* Host information */
317 	struct ena_admin_host_info *host_info;
318 	dma_addr_t host_info_dma_addr;
319 };
320 
321 /* Each ena_dev is a PCI function. */
322 struct ena_com_dev {
323 	struct ena_com_admin_queue admin_queue;
324 	struct ena_com_aenq aenq;
325 	struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES];
326 	struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES];
327 	u8 __iomem *reg_bar;
328 	void __iomem *mem_bar;
329 	void *dmadev;
330 
331 	enum ena_admin_placement_policy_type tx_mem_queue_type;
332 	u32 tx_max_header_size;
333 	u16 stats_func; /* Selected function for extended statistic dump */
334 	u16 stats_queue; /* Selected queue for extended statistic dump */
335 
336 	struct ena_com_mmio_read mmio_read;
337 
338 	struct ena_rss rss;
339 	u32 supported_features;
340 	u32 dma_addr_bits;
341 
342 	struct ena_host_attribute host_attr;
343 	bool adaptive_coalescing;
344 	u16 intr_delay_resolution;
345 
346 	/* interrupt moderation intervals are in usec divided by
347 	 * intr_delay_resolution, which is supplied by the device.
348 	 */
349 	u32 intr_moder_tx_interval;
350 	u32 intr_moder_rx_interval;
351 
352 	struct ena_intr_moder_entry *intr_moder_tbl;
353 
354 	struct ena_com_llq_info llq_info;
355 
356 	u32 ena_min_poll_delay_us;
357 };
358 
359 struct ena_com_dev_get_features_ctx {
360 	struct ena_admin_queue_feature_desc max_queues;
361 	struct ena_admin_queue_ext_feature_desc max_queue_ext;
362 	struct ena_admin_device_attr_feature_desc dev_attr;
363 	struct ena_admin_feature_aenq_desc aenq;
364 	struct ena_admin_feature_offload_desc offload;
365 	struct ena_admin_ena_hw_hints hw_hints;
366 	struct ena_admin_feature_llq_desc llq;
367 };
368 
369 struct ena_com_create_io_ctx {
370 	enum ena_admin_placement_policy_type mem_queue_type;
371 	enum queue_direction direction;
372 	int numa_node;
373 	u32 msix_vector;
374 	u16 queue_size;
375 	u16 qid;
376 };
377 
378 typedef void (*ena_aenq_handler)(void *data,
379 	struct ena_admin_aenq_entry *aenq_e);
380 
381 /* Holds aenq handlers. Indexed by AENQ event group */
382 struct ena_aenq_handlers {
383 	ena_aenq_handler handlers[ENA_MAX_HANDLERS];
384 	ena_aenq_handler unimplemented_handler;
385 };
386 
387 /*****************************************************************************/
388 /*****************************************************************************/
389 
390 /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism
391  * @ena_dev: ENA communication layer struct
392  *
393  * Initialize the register read mechanism.
394  *
395  * @note: This method must be the first stage in the initialization sequence.
396  *
397  * @return - 0 on success, negative value on failure.
398  */
399 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);
400 
401 /* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism
402  * @ena_dev: ENA communication layer struct
403  * @readless_supported: readless mode (enable/disable)
404  */
405 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev,
406 				bool readless_supported);
407 
408 /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return
409  * value physical address.
410  * @ena_dev: ENA communication layer struct
411  */
412 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev);
413 
414 /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism
415  * @ena_dev: ENA communication layer struct
416  */
417 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev);
418 
419 /* ena_com_admin_init - Init the admin and the async queues
420  * @ena_dev: ENA communication layer struct
421  * @aenq_handlers: Those handlers to be called upon event.
422  *
423  * Initialize the admin submission and completion queues.
424  * Initialize the asynchronous events notification queues.
425  *
426  * @return - 0 on success, negative value on failure.
427  */
428 int ena_com_admin_init(struct ena_com_dev *ena_dev,
429 		       struct ena_aenq_handlers *aenq_handlers);
430 
431 /* ena_com_admin_destroy - Destroy the admin and the async events queues.
432  * @ena_dev: ENA communication layer struct
433  *
434  * @note: Before calling this method, the caller must validate that the device
435  * won't send any additional admin completions/aenq.
436  * To achieve that, a FLR is recommended.
437  */
438 void ena_com_admin_destroy(struct ena_com_dev *ena_dev);
439 
440 /* ena_com_dev_reset - Perform device FLR to the device.
441  * @ena_dev: ENA communication layer struct
442  * @reset_reason: Specify what is the trigger for the reset in case of an error.
443  *
444  * @return - 0 on success, negative value on failure.
445  */
446 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
447 		      enum ena_regs_reset_reason_types reset_reason);
448 
449 /* ena_com_create_io_queue - Create io queue.
450  * @ena_dev: ENA communication layer struct
451  * @ctx - create context structure
452  *
453  * Create the submission and the completion queues.
454  *
455  * @return - 0 on success, negative value on failure.
456  */
457 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
458 			    struct ena_com_create_io_ctx *ctx);
459 
460 /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid.
461  * @ena_dev: ENA communication layer struct
462  * @qid - the caller virtual queue id.
463  */
464 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid);
465 
466 /* ena_com_get_io_handlers - Return the io queue handlers
467  * @ena_dev: ENA communication layer struct
468  * @qid - the caller virtual queue id.
469  * @io_sq - IO submission queue handler
470  * @io_cq - IO completion queue handler.
471  *
472  * @return - 0 on success, negative value on failure.
473  */
474 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
475 			    struct ena_com_io_sq **io_sq,
476 			    struct ena_com_io_cq **io_cq);
477 
478 /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications
479  * @ena_dev: ENA communication layer struct
480  *
481  * After this method, aenq event can be received via AENQ.
482  */
483 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev);
484 
485 /* ena_com_set_admin_running_state - Set the state of the admin queue
486  * @ena_dev: ENA communication layer struct
487  *
488  * Change the state of the admin queue (enable/disable)
489  */
490 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state);
491 
492 /* ena_com_get_admin_running_state - Get the admin queue state
493  * @ena_dev: ENA communication layer struct
494  *
495  * Retrieve the state of the admin queue (enable/disable)
496  *
497  * @return - current polling mode (enable/disable)
498  */
499 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev);
500 
501 /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode
502  * @ena_dev: ENA communication layer struct
503  * @polling: ENAble/Disable polling mode
504  *
505  * Set the admin completion mode.
506  */
507 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling);
508 
509 /* ena_com_set_admin_auto_polling_mode - Enable autoswitch to polling mode
510  * @ena_dev: ENA communication layer struct
511  * @polling: Enable/Disable polling mode
512  *
513  * Set the autopolling mode.
514  * If autopolling is on:
515  * In case of missing interrupt when data is available switch to polling.
516  */
517 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
518 					 bool polling);
519 
520 /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler
521  * @ena_dev: ENA communication layer struct
522  *
523  * This method goes over the admin completion queue and wakes up all the pending
524  * threads that wait on the commands wait event.
525  *
526  * @note: Should be called after MSI-X interrupt.
527  */
528 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev);
529 
530 /* ena_com_aenq_intr_handler - AENQ interrupt handler
531  * @ena_dev: ENA communication layer struct
532  *
533  * This method goes over the async event notification queue and calls the proper
534  * aenq handler.
535  */
536 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data);
537 
538 /* ena_com_abort_admin_commands - Abort all the outstanding admin commands.
539  * @ena_dev: ENA communication layer struct
540  *
541  * This method aborts all the outstanding admin commands.
542  * The caller should then call ena_com_wait_for_abort_completion to make sure
543  * all the commands were completed.
544  */
545 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev);
546 
547 /* ena_com_wait_for_abort_completion - Wait for admin commands abort.
548  * @ena_dev: ENA communication layer struct
549  *
550  * This method waits until all the outstanding admin commands are completed.
551  */
552 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev);
553 
554 /* ena_com_validate_version - Validate the device parameters
555  * @ena_dev: ENA communication layer struct
556  *
557  * This method verifies the device parameters are the same as the saved
558  * parameters in ena_dev.
559  * This method is useful after device reset, to validate the device mac address
560  * and the device offloads are the same as before the reset.
561  *
562  * @return - 0 on success negative value otherwise.
563  */
564 int ena_com_validate_version(struct ena_com_dev *ena_dev);
565 
566 /* ena_com_get_link_params - Retrieve physical link parameters.
567  * @ena_dev: ENA communication layer struct
568  * @resp: Link parameters
569  *
570  * Retrieve the physical link parameters,
571  * like speed, auto-negotiation and full duplex support.
572  *
573  * @return - 0 on Success negative value otherwise.
574  */
575 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
576 			    struct ena_admin_get_feat_resp *resp);
577 
578 /* ena_com_get_dma_width - Retrieve physical dma address width the device
579  * supports.
580  * @ena_dev: ENA communication layer struct
581  *
582  * Retrieve the maximum physical address bits the device can handle.
583  *
584  * @return: > 0 on Success and negative value otherwise.
585  */
586 int ena_com_get_dma_width(struct ena_com_dev *ena_dev);
587 
588 /* ena_com_set_aenq_config - Set aenq groups configurations
589  * @ena_dev: ENA communication layer struct
590  * @groups flag: bit fields flags of enum ena_admin_aenq_group.
591  *
592  * Configure which aenq event group the driver would like to receive.
593  *
594  * @return: 0 on Success and negative value otherwise.
595  */
596 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag);
597 
598 /* ena_com_get_dev_attr_feat - Get device features
599  * @ena_dev: ENA communication layer struct
600  * @get_feat_ctx: returned context that contain the get features.
601  *
602  * @return: 0 on Success and negative value otherwise.
603  */
604 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
605 			      struct ena_com_dev_get_features_ctx *get_feat_ctx);
606 
607 /* ena_com_get_dev_basic_stats - Get device basic statistics
608  * @ena_dev: ENA communication layer struct
609  * @stats: stats return value
610  *
611  * @return: 0 on Success and negative value otherwise.
612  */
613 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
614 				struct ena_admin_basic_stats *stats);
615 
616 /* ena_com_set_dev_mtu - Configure the device mtu.
617  * @ena_dev: ENA communication layer struct
618  * @mtu: mtu value
619  *
620  * @return: 0 on Success and negative value otherwise.
621  */
622 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu);
623 
624 /* ena_com_get_offload_settings - Retrieve the device offloads capabilities
625  * @ena_dev: ENA communication layer struct
626  * @offlad: offload return value
627  *
628  * @return: 0 on Success and negative value otherwise.
629  */
630 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
631 				 struct ena_admin_feature_offload_desc *offload);
632 
633 /* ena_com_rss_init - Init RSS
634  * @ena_dev: ENA communication layer struct
635  * @log_size: indirection log size
636  *
637  * Allocate RSS/RFS resources.
638  * The caller then can configure rss using ena_com_set_hash_function,
639  * ena_com_set_hash_ctrl and ena_com_indirect_table_set.
640  *
641  * @return: 0 on Success and negative value otherwise.
642  */
643 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size);
644 
645 /* ena_com_rss_destroy - Destroy rss
646  * @ena_dev: ENA communication layer struct
647  *
648  * Free all the RSS/RFS resources.
649  */
650 void ena_com_rss_destroy(struct ena_com_dev *ena_dev);
651 
652 /* ena_com_get_current_hash_function - Get RSS hash function
653  * @ena_dev: ENA communication layer struct
654  *
655  * Return the current hash function.
656  * @return: 0 or one of the ena_admin_hash_functions values.
657  */
658 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev);
659 
660 /* ena_com_fill_hash_function - Fill RSS hash function
661  * @ena_dev: ENA communication layer struct
662  * @func: The hash function (Toeplitz or crc)
663  * @key: Hash key (for toeplitz hash)
664  * @key_len: key length (max length 10 DW)
665  * @init_val: initial value for the hash function
666  *
667  * Fill the ena_dev resources with the desire hash function, hash key, key_len
668  * and key initial value (if needed by the hash function).
669  * To flush the key into the device the caller should call
670  * ena_com_set_hash_function.
671  *
672  * @return: 0 on Success and negative value otherwise.
673  */
674 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
675 			       enum ena_admin_hash_functions func,
676 			       const u8 *key, u16 key_len, u32 init_val);
677 
678 /* ena_com_set_hash_function - Flush the hash function and it dependencies to
679  * the device.
680  * @ena_dev: ENA communication layer struct
681  *
682  * Flush the hash function and it dependencies (key, key length and
683  * initial value) if needed.
684  *
685  * @note: Prior to this method the caller should call ena_com_fill_hash_function
686  *
687  * @return: 0 on Success and negative value otherwise.
688  */
689 int ena_com_set_hash_function(struct ena_com_dev *ena_dev);
690 
691 /* ena_com_get_hash_function - Retrieve the hash function from the device.
692  * @ena_dev: ENA communication layer struct
693  * @func: hash function
694  *
695  * Retrieve the hash function from the device.
696  *
697  * @note: If the caller called ena_com_fill_hash_function but didn't flush
698  * it to the device, the new configuration will be lost.
699  *
700  * @return: 0 on Success and negative value otherwise.
701  */
702 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
703 			      enum ena_admin_hash_functions *func);
704 
705 /* ena_com_get_hash_key - Retrieve the hash key
706  * @ena_dev: ENA communication layer struct
707  * @key: hash key
708  *
709  * Retrieve the hash key.
710  *
711  * @note: If the caller called ena_com_fill_hash_key but didn't flush
712  * it to the device, the new configuration will be lost.
713  *
714  * @return: 0 on Success and negative value otherwise.
715  */
716 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key);
717 /* ena_com_fill_hash_ctrl - Fill RSS hash control
718  * @ena_dev: ENA communication layer struct.
719  * @proto: The protocol to configure.
720  * @hash_fields: bit mask of ena_admin_flow_hash_fields
721  *
722  * Fill the ena_dev resources with the desire hash control (the ethernet
723  * fields that take part of the hash) for a specific protocol.
724  * To flush the hash control to the device, the caller should call
725  * ena_com_set_hash_ctrl.
726  *
727  * @return: 0 on Success and negative value otherwise.
728  */
729 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
730 			   enum ena_admin_flow_hash_proto proto,
731 			   u16 hash_fields);
732 
733 /* ena_com_set_hash_ctrl - Flush the hash control resources to the device.
734  * @ena_dev: ENA communication layer struct
735  *
736  * Flush the hash control (the ethernet fields that take part of the hash)
737  *
738  * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl.
739  *
740  * @return: 0 on Success and negative value otherwise.
741  */
742 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev);
743 
744 /* ena_com_get_hash_ctrl - Retrieve the hash control from the device.
745  * @ena_dev: ENA communication layer struct
746  * @proto: The protocol to retrieve.
747  * @fields: bit mask of ena_admin_flow_hash_fields.
748  *
749  * Retrieve the hash control from the device.
750  *
751  * @note: If the caller called ena_com_fill_hash_ctrl but didn't flush
752  * it to the device, the new configuration will be lost.
753  *
754  * @return: 0 on Success and negative value otherwise.
755  */
756 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
757 			  enum ena_admin_flow_hash_proto proto,
758 			  u16 *fields);
759 
760 /* ena_com_set_default_hash_ctrl - Set the hash control to a default
761  * configuration.
762  * @ena_dev: ENA communication layer struct
763  *
764  * Fill the ena_dev resources with the default hash control configuration.
765  * To flush the hash control to the device, the caller should call
766  * ena_com_set_hash_ctrl.
767  *
768  * @return: 0 on Success and negative value otherwise.
769  */
770 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev);
771 
772 /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS
773  * indirection table
774  * @ena_dev: ENA communication layer struct.
775  * @entry_idx - indirection table entry.
776  * @entry_value - redirection value
777  *
778  * Fill a single entry of the RSS indirection table in the ena_dev resources.
779  * To flush the indirection table to the device, the called should call
780  * ena_com_indirect_table_set.
781  *
782  * @return: 0 on Success and negative value otherwise.
783  */
784 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
785 				      u16 entry_idx, u16 entry_value);
786 
787 /* ena_com_indirect_table_set - Flush the indirection table to the device.
788  * @ena_dev: ENA communication layer struct
789  *
790  * Flush the indirection hash control to the device.
791  * Prior to this method the caller should call ena_com_indirect_table_fill_entry
792  *
793  * @return: 0 on Success and negative value otherwise.
794  */
795 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev);
796 
797 /* ena_com_indirect_table_get - Retrieve the indirection table from the device.
798  * @ena_dev: ENA communication layer struct
799  * @ind_tbl: indirection table
800  *
801  * Retrieve the RSS indirection table from the device.
802  *
803  * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flush
804  * it to the device, the new configuration will be lost.
805  *
806  * @return: 0 on Success and negative value otherwise.
807  */
808 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl);
809 
810 /* ena_com_allocate_host_info - Allocate host info resources.
811  * @ena_dev: ENA communication layer struct
812  *
813  * @return: 0 on Success and negative value otherwise.
814  */
815 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev);
816 
817 /* ena_com_allocate_debug_area - Allocate debug area.
818  * @ena_dev: ENA communication layer struct
819  * @debug_area_size - debug area size.
820  *
821  * @return: 0 on Success and negative value otherwise.
822  */
823 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
824 				u32 debug_area_size);
825 
826 /* ena_com_delete_debug_area - Free the debug area resources.
827  * @ena_dev: ENA communication layer struct
828  *
829  * Free the allocated debug area.
830  */
831 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev);
832 
833 /* ena_com_delete_host_info - Free the host info resources.
834  * @ena_dev: ENA communication layer struct
835  *
836  * Free the allocated host info.
837  */
838 void ena_com_delete_host_info(struct ena_com_dev *ena_dev);
839 
840 /* ena_com_set_host_attributes - Update the device with the host
841  * attributes (debug area and host info) base address.
842  * @ena_dev: ENA communication layer struct
843  *
844  * @return: 0 on Success and negative value otherwise.
845  */
846 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev);
847 
848 /* ena_com_create_io_cq - Create io completion queue.
849  * @ena_dev: ENA communication layer struct
850  * @io_cq - io completion queue handler
851 
852  * Create IO completion queue.
853  *
854  * @return - 0 on success, negative value on failure.
855  */
856 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
857 			 struct ena_com_io_cq *io_cq);
858 
859 /* ena_com_destroy_io_cq - Destroy io completion queue.
860  * @ena_dev: ENA communication layer struct
861  * @io_cq - io completion queue handler
862 
863  * Destroy IO completion queue.
864  *
865  * @return - 0 on success, negative value on failure.
866  */
867 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
868 			  struct ena_com_io_cq *io_cq);
869 
870 /* ena_com_execute_admin_command - Execute admin command
871  * @admin_queue: admin queue.
872  * @cmd: the admin command to execute.
873  * @cmd_size: the command size.
874  * @cmd_completion: command completion return value.
875  * @cmd_comp_size: command completion size.
876 
877  * Submit an admin command and then wait until the device returns a
878  * completion.
879  * The completion will be copied into cmd_comp.
880  *
881  * @return - 0 on success, negative value on failure.
882  */
883 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
884 				  struct ena_admin_aq_entry *cmd,
885 				  size_t cmd_size,
886 				  struct ena_admin_acq_entry *cmd_comp,
887 				  size_t cmd_comp_size);
888 
889 /* ena_com_init_interrupt_moderation - Init interrupt moderation
890  * @ena_dev: ENA communication layer struct
891  *
892  * @return - 0 on success, negative value on failure.
893  */
894 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev);
895 
896 /* ena_com_interrupt_moderation_supported - Return if interrupt moderation
897  * capability is supported by the device.
898  *
899  * @return - supported or not.
900  */
901 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev);
902 
903 /* ena_com_update_nonadaptive_moderation_interval_tx - Update the
904  * non-adaptive interval in Tx direction.
905  * @ena_dev: ENA communication layer struct
906  * @tx_coalesce_usecs: Interval in usec.
907  *
908  * @return - 0 on success, negative value on failure.
909  */
910 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
911 						      u32 tx_coalesce_usecs);
912 
913 /* ena_com_update_nonadaptive_moderation_interval_rx - Update the
914  * non-adaptive interval in Rx direction.
915  * @ena_dev: ENA communication layer struct
916  * @rx_coalesce_usecs: Interval in usec.
917  *
918  * @return - 0 on success, negative value on failure.
919  */
920 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
921 						      u32 rx_coalesce_usecs);
922 
923 /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the
924  * non-adaptive interval in Tx direction.
925  * @ena_dev: ENA communication layer struct
926  *
927  * @return - interval in usec
928  */
929 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);
930 
931 /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the
932  * non-adaptive interval in Rx direction.
933  * @ena_dev: ENA communication layer struct
934  *
935  * @return - interval in usec
936  */
937 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev);
938 
939 /* ena_com_config_dev_mode - Configure the placement policy of the device.
940  * @ena_dev: ENA communication layer struct
941  * @llq_features: LLQ feature descriptor, retrieve via
942  *		   ena_com_get_dev_attr_feat.
943  * @ena_llq_config: The default driver LLQ parameters configurations
944  */
945 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
946 			    struct ena_admin_feature_llq_desc *llq_features,
947 			    struct ena_llq_configurations *llq_default_config);
948 
949 static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
950 {
951 	return ena_dev->adaptive_coalescing;
952 }
953 
954 static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)
955 {
956 	ena_dev->adaptive_coalescing = true;
957 }
958 
959 static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)
960 {
961 	ena_dev->adaptive_coalescing = false;
962 }
963 
964 /* ena_com_update_intr_reg - Prepare interrupt register
965  * @intr_reg: interrupt register to update.
966  * @rx_delay_interval: Rx interval in usecs
967  * @tx_delay_interval: Tx interval in usecs
968  * @unmask: unmask enable/disable
969  *
970  * Prepare interrupt update register with the supplied parameters.
971  */
972 static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,
973 					   u32 rx_delay_interval,
974 					   u32 tx_delay_interval,
975 					   bool unmask)
976 {
977 	intr_reg->intr_control = 0;
978 	intr_reg->intr_control |= rx_delay_interval &
979 		ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
980 
981 	intr_reg->intr_control |=
982 		(tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
983 		& ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
984 
985 	if (unmask)
986 		intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
987 }
988 
989 static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl)
990 {
991 	u16 size, buffers_num;
992 	u8 *buf;
993 
994 	size = bounce_buf_ctrl->buffer_size;
995 	buffers_num = bounce_buf_ctrl->buffers_num;
996 
997 	buf = bounce_buf_ctrl->base_buffer +
998 		(bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size;
999 
1000 	prefetchw(bounce_buf_ctrl->base_buffer +
1001 		(bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size);
1002 
1003 	return buf;
1004 }
1005 
1006 #endif /* !(ENA_COM) */
1007