1 /*
2  * Copyright 2015 Amazon.com, Inc. or its affiliates.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef ENA_COM
34 #define ENA_COM
35 
36 #include <linux/compiler.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/gfp.h>
40 #include <linux/io.h>
41 #include <linux/prefetch.h>
42 #include <linux/sched.h>
43 #include <linux/sizes.h>
44 #include <linux/spinlock.h>
45 #include <linux/types.h>
46 #include <linux/wait.h>
47 
48 #include "ena_common_defs.h"
49 #include "ena_admin_defs.h"
50 #include "ena_eth_io_defs.h"
51 #include "ena_regs_defs.h"
52 
53 #undef pr_fmt
54 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
55 
56 #define ENA_MAX_NUM_IO_QUEUES		128U
57 /* We need to queues for each IO (on for Tx and one for Rx) */
58 #define ENA_TOTAL_NUM_QUEUES		(2 * (ENA_MAX_NUM_IO_QUEUES))
59 
60 #define ENA_MAX_HANDLERS 256
61 
62 #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48
63 
64 /* Unit in usec */
65 #define ENA_REG_READ_TIMEOUT 200000
66 
67 #define ADMIN_SQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_aq_entry))
68 #define ADMIN_CQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_acq_entry))
69 #define ADMIN_AENQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_aenq_entry))
70 
71 /*****************************************************************************/
72 /*****************************************************************************/
73 /* ENA adaptive interrupt moderation settings */
74 
75 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS		196
76 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS		0
77 #define ENA_DEFAULT_INTR_DELAY_RESOLUTION		1
78 
79 #define ENA_HW_HINTS_NO_TIMEOUT				0xFFFF
80 
81 #define ENA_FEATURE_MAX_QUEUE_EXT_VER	1
82 
83 struct ena_llq_configurations {
84 	enum ena_admin_llq_header_location llq_header_location;
85 	enum ena_admin_llq_ring_entry_size llq_ring_entry_size;
86 	enum ena_admin_llq_stride_ctrl  llq_stride_ctrl;
87 	enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header;
88 	u16 llq_ring_entry_size_value;
89 };
90 
91 enum queue_direction {
92 	ENA_COM_IO_QUEUE_DIRECTION_TX,
93 	ENA_COM_IO_QUEUE_DIRECTION_RX
94 };
95 
96 struct ena_com_buf {
97 	dma_addr_t paddr; /**< Buffer physical address */
98 	u16 len; /**< Buffer length in bytes */
99 };
100 
101 struct ena_com_rx_buf_info {
102 	u16 len;
103 	u16 req_id;
104 };
105 
106 struct ena_com_io_desc_addr {
107 	u8 __iomem *pbuf_dev_addr; /* LLQ address */
108 	u8 *virt_addr;
109 	dma_addr_t phys_addr;
110 };
111 
112 struct ena_com_tx_meta {
113 	u16 mss;
114 	u16 l3_hdr_len;
115 	u16 l3_hdr_offset;
116 	u16 l4_hdr_len; /* In words */
117 };
118 
119 struct ena_com_llq_info {
120 	u16 header_location_ctrl;
121 	u16 desc_stride_ctrl;
122 	u16 desc_list_entry_size_ctrl;
123 	u16 desc_list_entry_size;
124 	u16 descs_num_before_header;
125 	u16 descs_per_entry;
126 	u16 max_entries_in_tx_burst;
127 };
128 
129 struct ena_com_io_cq {
130 	struct ena_com_io_desc_addr cdesc_addr;
131 
132 	/* Interrupt unmask register */
133 	u32 __iomem *unmask_reg;
134 
135 	/* The completion queue head doorbell register */
136 	u32 __iomem *cq_head_db_reg;
137 
138 	/* numa configuration register (for TPH) */
139 	u32 __iomem *numa_node_cfg_reg;
140 
141 	/* The value to write to the above register to unmask
142 	 * the interrupt of this queue
143 	 */
144 	u32 msix_vector;
145 
146 	enum queue_direction direction;
147 
148 	/* holds the number of cdesc of the current packet */
149 	u16 cur_rx_pkt_cdesc_count;
150 	/* save the firt cdesc idx of the current packet */
151 	u16 cur_rx_pkt_cdesc_start_idx;
152 
153 	u16 q_depth;
154 	/* Caller qid */
155 	u16 qid;
156 
157 	/* Device queue index */
158 	u16 idx;
159 	u16 head;
160 	u16 last_head_update;
161 	u8 phase;
162 	u8 cdesc_entry_size_in_bytes;
163 
164 } ____cacheline_aligned;
165 
166 struct ena_com_io_bounce_buffer_control {
167 	u8 *base_buffer;
168 	u16 next_to_use;
169 	u16 buffer_size;
170 	u16 buffers_num;  /* Must be a power of 2 */
171 };
172 
173 /* This struct is to keep tracking the current location of the next llq entry */
174 struct ena_com_llq_pkt_ctrl {
175 	u8 *curr_bounce_buf;
176 	u16 idx;
177 	u16 descs_left_in_line;
178 };
179 
180 struct ena_com_io_sq {
181 	struct ena_com_io_desc_addr desc_addr;
182 
183 	u32 __iomem *db_addr;
184 	u8 __iomem *header_addr;
185 
186 	enum queue_direction direction;
187 	enum ena_admin_placement_policy_type mem_queue_type;
188 
189 	u32 msix_vector;
190 	struct ena_com_tx_meta cached_tx_meta;
191 	struct ena_com_llq_info llq_info;
192 	struct ena_com_llq_pkt_ctrl llq_buf_ctrl;
193 	struct ena_com_io_bounce_buffer_control bounce_buf_ctrl;
194 
195 	u16 q_depth;
196 	u16 qid;
197 
198 	u16 idx;
199 	u16 tail;
200 	u16 next_to_comp;
201 	u16 llq_last_copy_tail;
202 	u32 tx_max_header_size;
203 	u8 phase;
204 	u8 desc_entry_size;
205 	u8 dma_addr_bits;
206 	u16 entries_in_tx_burst_left;
207 } ____cacheline_aligned;
208 
209 struct ena_com_admin_cq {
210 	struct ena_admin_acq_entry *entries;
211 	dma_addr_t dma_addr;
212 
213 	u16 head;
214 	u8 phase;
215 };
216 
217 struct ena_com_admin_sq {
218 	struct ena_admin_aq_entry *entries;
219 	dma_addr_t dma_addr;
220 
221 	u32 __iomem *db_addr;
222 
223 	u16 head;
224 	u16 tail;
225 	u8 phase;
226 
227 };
228 
229 struct ena_com_stats_admin {
230 	u32 aborted_cmd;
231 	u32 submitted_cmd;
232 	u32 completed_cmd;
233 	u32 out_of_space;
234 	u32 no_completion;
235 };
236 
237 struct ena_com_admin_queue {
238 	void *q_dmadev;
239 	spinlock_t q_lock; /* spinlock for the admin queue */
240 
241 	struct ena_comp_ctx *comp_ctx;
242 	u32 completion_timeout;
243 	u16 q_depth;
244 	struct ena_com_admin_cq cq;
245 	struct ena_com_admin_sq sq;
246 
247 	/* Indicate if the admin queue should poll for completion */
248 	bool polling;
249 
250 	/* Define if fallback to polling mode should occur */
251 	bool auto_polling;
252 
253 	u16 curr_cmd_id;
254 
255 	/* Indicate that the ena was initialized and can
256 	 * process new admin commands
257 	 */
258 	bool running_state;
259 
260 	/* Count the number of outstanding admin commands */
261 	atomic_t outstanding_cmds;
262 
263 	struct ena_com_stats_admin stats;
264 };
265 
266 struct ena_aenq_handlers;
267 
268 struct ena_com_aenq {
269 	u16 head;
270 	u8 phase;
271 	struct ena_admin_aenq_entry *entries;
272 	dma_addr_t dma_addr;
273 	u16 q_depth;
274 	struct ena_aenq_handlers *aenq_handlers;
275 };
276 
277 struct ena_com_mmio_read {
278 	struct ena_admin_ena_mmio_req_read_less_resp *read_resp;
279 	dma_addr_t read_resp_dma_addr;
280 	u32 reg_read_to; /* in us */
281 	u16 seq_num;
282 	bool readless_supported;
283 	/* spin lock to ensure a single outstanding read */
284 	spinlock_t lock;
285 };
286 
287 struct ena_rss {
288 	/* Indirect table */
289 	u16 *host_rss_ind_tbl;
290 	struct ena_admin_rss_ind_table_entry *rss_ind_tbl;
291 	dma_addr_t rss_ind_tbl_dma_addr;
292 	u16 tbl_log_size;
293 
294 	/* Hash key */
295 	enum ena_admin_hash_functions hash_func;
296 	struct ena_admin_feature_rss_flow_hash_control *hash_key;
297 	dma_addr_t hash_key_dma_addr;
298 	u32 hash_init_val;
299 
300 	/* Flow Control */
301 	struct ena_admin_feature_rss_hash_control *hash_ctrl;
302 	dma_addr_t hash_ctrl_dma_addr;
303 
304 };
305 
306 struct ena_host_attribute {
307 	/* Debug area */
308 	u8 *debug_area_virt_addr;
309 	dma_addr_t debug_area_dma_addr;
310 	u32 debug_area_size;
311 
312 	/* Host information */
313 	struct ena_admin_host_info *host_info;
314 	dma_addr_t host_info_dma_addr;
315 };
316 
317 /* Each ena_dev is a PCI function. */
318 struct ena_com_dev {
319 	struct ena_com_admin_queue admin_queue;
320 	struct ena_com_aenq aenq;
321 	struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES];
322 	struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES];
323 	u8 __iomem *reg_bar;
324 	void __iomem *mem_bar;
325 	void *dmadev;
326 
327 	enum ena_admin_placement_policy_type tx_mem_queue_type;
328 	u32 tx_max_header_size;
329 	u16 stats_func; /* Selected function for extended statistic dump */
330 	u16 stats_queue; /* Selected queue for extended statistic dump */
331 
332 	struct ena_com_mmio_read mmio_read;
333 
334 	struct ena_rss rss;
335 	u32 supported_features;
336 	u32 dma_addr_bits;
337 
338 	struct ena_host_attribute host_attr;
339 	bool adaptive_coalescing;
340 	u16 intr_delay_resolution;
341 
342 	/* interrupt moderation intervals are in usec divided by
343 	 * intr_delay_resolution, which is supplied by the device.
344 	 */
345 	u32 intr_moder_tx_interval;
346 	u32 intr_moder_rx_interval;
347 
348 	struct ena_intr_moder_entry *intr_moder_tbl;
349 
350 	struct ena_com_llq_info llq_info;
351 };
352 
353 struct ena_com_dev_get_features_ctx {
354 	struct ena_admin_queue_feature_desc max_queues;
355 	struct ena_admin_queue_ext_feature_desc max_queue_ext;
356 	struct ena_admin_device_attr_feature_desc dev_attr;
357 	struct ena_admin_feature_aenq_desc aenq;
358 	struct ena_admin_feature_offload_desc offload;
359 	struct ena_admin_ena_hw_hints hw_hints;
360 	struct ena_admin_feature_llq_desc llq;
361 };
362 
363 struct ena_com_create_io_ctx {
364 	enum ena_admin_placement_policy_type mem_queue_type;
365 	enum queue_direction direction;
366 	int numa_node;
367 	u32 msix_vector;
368 	u16 queue_size;
369 	u16 qid;
370 };
371 
372 typedef void (*ena_aenq_handler)(void *data,
373 	struct ena_admin_aenq_entry *aenq_e);
374 
375 /* Holds aenq handlers. Indexed by AENQ event group */
376 struct ena_aenq_handlers {
377 	ena_aenq_handler handlers[ENA_MAX_HANDLERS];
378 	ena_aenq_handler unimplemented_handler;
379 };
380 
381 /*****************************************************************************/
382 /*****************************************************************************/
383 
384 /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism
385  * @ena_dev: ENA communication layer struct
386  *
387  * Initialize the register read mechanism.
388  *
389  * @note: This method must be the first stage in the initialization sequence.
390  *
391  * @return - 0 on success, negative value on failure.
392  */
393 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);
394 
395 /* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism
396  * @ena_dev: ENA communication layer struct
397  * @readless_supported: readless mode (enable/disable)
398  */
399 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev,
400 				bool readless_supported);
401 
402 /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return
403  * value physical address.
404  * @ena_dev: ENA communication layer struct
405  */
406 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev);
407 
408 /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism
409  * @ena_dev: ENA communication layer struct
410  */
411 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev);
412 
413 /* ena_com_admin_init - Init the admin and the async queues
414  * @ena_dev: ENA communication layer struct
415  * @aenq_handlers: Those handlers to be called upon event.
416  *
417  * Initialize the admin submission and completion queues.
418  * Initialize the asynchronous events notification queues.
419  *
420  * @return - 0 on success, negative value on failure.
421  */
422 int ena_com_admin_init(struct ena_com_dev *ena_dev,
423 		       struct ena_aenq_handlers *aenq_handlers);
424 
425 /* ena_com_admin_destroy - Destroy the admin and the async events queues.
426  * @ena_dev: ENA communication layer struct
427  *
428  * @note: Before calling this method, the caller must validate that the device
429  * won't send any additional admin completions/aenq.
430  * To achieve that, a FLR is recommended.
431  */
432 void ena_com_admin_destroy(struct ena_com_dev *ena_dev);
433 
434 /* ena_com_dev_reset - Perform device FLR to the device.
435  * @ena_dev: ENA communication layer struct
436  * @reset_reason: Specify what is the trigger for the reset in case of an error.
437  *
438  * @return - 0 on success, negative value on failure.
439  */
440 int ena_com_dev_reset(struct ena_com_dev *ena_dev,
441 		      enum ena_regs_reset_reason_types reset_reason);
442 
443 /* ena_com_create_io_queue - Create io queue.
444  * @ena_dev: ENA communication layer struct
445  * @ctx - create context structure
446  *
447  * Create the submission and the completion queues.
448  *
449  * @return - 0 on success, negative value on failure.
450  */
451 int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
452 			    struct ena_com_create_io_ctx *ctx);
453 
454 /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid.
455  * @ena_dev: ENA communication layer struct
456  * @qid - the caller virtual queue id.
457  */
458 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid);
459 
460 /* ena_com_get_io_handlers - Return the io queue handlers
461  * @ena_dev: ENA communication layer struct
462  * @qid - the caller virtual queue id.
463  * @io_sq - IO submission queue handler
464  * @io_cq - IO completion queue handler.
465  *
466  * @return - 0 on success, negative value on failure.
467  */
468 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid,
469 			    struct ena_com_io_sq **io_sq,
470 			    struct ena_com_io_cq **io_cq);
471 
472 /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications
473  * @ena_dev: ENA communication layer struct
474  *
475  * After this method, aenq event can be received via AENQ.
476  */
477 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev);
478 
479 /* ena_com_set_admin_running_state - Set the state of the admin queue
480  * @ena_dev: ENA communication layer struct
481  *
482  * Change the state of the admin queue (enable/disable)
483  */
484 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state);
485 
486 /* ena_com_get_admin_running_state - Get the admin queue state
487  * @ena_dev: ENA communication layer struct
488  *
489  * Retrieve the state of the admin queue (enable/disable)
490  *
491  * @return - current polling mode (enable/disable)
492  */
493 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev);
494 
495 /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode
496  * @ena_dev: ENA communication layer struct
497  * @polling: ENAble/Disable polling mode
498  *
499  * Set the admin completion mode.
500  */
501 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling);
502 
503 /* ena_com_set_admin_polling_mode - Get the admin completion queue polling mode
504  * @ena_dev: ENA communication layer struct
505  *
506  * Get the admin completion mode.
507  * If polling mode is on, ena_com_execute_admin_command will perform a
508  * polling on the admin completion queue for the commands completion,
509  * otherwise it will wait on wait event.
510  *
511  * @return state
512  */
513 bool ena_com_get_ena_admin_polling_mode(struct ena_com_dev *ena_dev);
514 
515 /* ena_com_set_admin_auto_polling_mode - Enable autoswitch to polling mode
516  * @ena_dev: ENA communication layer struct
517  * @polling: Enable/Disable polling mode
518  *
519  * Set the autopolling mode.
520  * If autopolling is on:
521  * In case of missing interrupt when data is available switch to polling.
522  */
523 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev,
524 					 bool polling);
525 
526 /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler
527  * @ena_dev: ENA communication layer struct
528  *
529  * This method go over the admin completion queue and wake up all the pending
530  * threads that wait on the commands wait event.
531  *
532  * @note: Should be called after MSI-X interrupt.
533  */
534 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev);
535 
536 /* ena_com_aenq_intr_handler - AENQ interrupt handler
537  * @ena_dev: ENA communication layer struct
538  *
539  * This method go over the async event notification queue and call the proper
540  * aenq handler.
541  */
542 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data);
543 
544 /* ena_com_abort_admin_commands - Abort all the outstanding admin commands.
545  * @ena_dev: ENA communication layer struct
546  *
547  * This method aborts all the outstanding admin commands.
548  * The caller should then call ena_com_wait_for_abort_completion to make sure
549  * all the commands were completed.
550  */
551 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev);
552 
553 /* ena_com_wait_for_abort_completion - Wait for admin commands abort.
554  * @ena_dev: ENA communication layer struct
555  *
556  * This method wait until all the outstanding admin commands will be completed.
557  */
558 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev);
559 
560 /* ena_com_validate_version - Validate the device parameters
561  * @ena_dev: ENA communication layer struct
562  *
563  * This method validate the device parameters are the same as the saved
564  * parameters in ena_dev.
565  * This method is useful after device reset, to validate the device mac address
566  * and the device offloads are the same as before the reset.
567  *
568  * @return - 0 on success negative value otherwise.
569  */
570 int ena_com_validate_version(struct ena_com_dev *ena_dev);
571 
572 /* ena_com_get_link_params - Retrieve physical link parameters.
573  * @ena_dev: ENA communication layer struct
574  * @resp: Link parameters
575  *
576  * Retrieve the physical link parameters,
577  * like speed, auto-negotiation and full duplex support.
578  *
579  * @return - 0 on Success negative value otherwise.
580  */
581 int ena_com_get_link_params(struct ena_com_dev *ena_dev,
582 			    struct ena_admin_get_feat_resp *resp);
583 
584 /* ena_com_get_dma_width - Retrieve physical dma address width the device
585  * supports.
586  * @ena_dev: ENA communication layer struct
587  *
588  * Retrieve the maximum physical address bits the device can handle.
589  *
590  * @return: > 0 on Success and negative value otherwise.
591  */
592 int ena_com_get_dma_width(struct ena_com_dev *ena_dev);
593 
594 /* ena_com_set_aenq_config - Set aenq groups configurations
595  * @ena_dev: ENA communication layer struct
596  * @groups flag: bit fields flags of enum ena_admin_aenq_group.
597  *
598  * Configure which aenq event group the driver would like to receive.
599  *
600  * @return: 0 on Success and negative value otherwise.
601  */
602 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag);
603 
604 /* ena_com_get_dev_attr_feat - Get device features
605  * @ena_dev: ENA communication layer struct
606  * @get_feat_ctx: returned context that contain the get features.
607  *
608  * @return: 0 on Success and negative value otherwise.
609  */
610 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
611 			      struct ena_com_dev_get_features_ctx *get_feat_ctx);
612 
613 /* ena_com_get_dev_basic_stats - Get device basic statistics
614  * @ena_dev: ENA communication layer struct
615  * @stats: stats return value
616  *
617  * @return: 0 on Success and negative value otherwise.
618  */
619 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev,
620 				struct ena_admin_basic_stats *stats);
621 
622 /* ena_com_set_dev_mtu - Configure the device mtu.
623  * @ena_dev: ENA communication layer struct
624  * @mtu: mtu value
625  *
626  * @return: 0 on Success and negative value otherwise.
627  */
628 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu);
629 
630 /* ena_com_get_offload_settings - Retrieve the device offloads capabilities
631  * @ena_dev: ENA communication layer struct
632  * @offlad: offload return value
633  *
634  * @return: 0 on Success and negative value otherwise.
635  */
636 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
637 				 struct ena_admin_feature_offload_desc *offload);
638 
639 /* ena_com_rss_init - Init RSS
640  * @ena_dev: ENA communication layer struct
641  * @log_size: indirection log size
642  *
643  * Allocate RSS/RFS resources.
644  * The caller then can configure rss using ena_com_set_hash_function,
645  * ena_com_set_hash_ctrl and ena_com_indirect_table_set.
646  *
647  * @return: 0 on Success and negative value otherwise.
648  */
649 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size);
650 
651 /* ena_com_rss_destroy - Destroy rss
652  * @ena_dev: ENA communication layer struct
653  *
654  * Free all the RSS/RFS resources.
655  */
656 void ena_com_rss_destroy(struct ena_com_dev *ena_dev);
657 
658 /* ena_com_fill_hash_function - Fill RSS hash function
659  * @ena_dev: ENA communication layer struct
660  * @func: The hash function (Toeplitz or crc)
661  * @key: Hash key (for toeplitz hash)
662  * @key_len: key length (max length 10 DW)
663  * @init_val: initial value for the hash function
664  *
665  * Fill the ena_dev resources with the desire hash function, hash key, key_len
666  * and key initial value (if needed by the hash function).
667  * To flush the key into the device the caller should call
668  * ena_com_set_hash_function.
669  *
670  * @return: 0 on Success and negative value otherwise.
671  */
672 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev,
673 			       enum ena_admin_hash_functions func,
674 			       const u8 *key, u16 key_len, u32 init_val);
675 
676 /* ena_com_set_hash_function - Flush the hash function and it dependencies to
677  * the device.
678  * @ena_dev: ENA communication layer struct
679  *
680  * Flush the hash function and it dependencies (key, key length and
681  * initial value) if needed.
682  *
683  * @note: Prior to this method the caller should call ena_com_fill_hash_function
684  *
685  * @return: 0 on Success and negative value otherwise.
686  */
687 int ena_com_set_hash_function(struct ena_com_dev *ena_dev);
688 
689 /* ena_com_get_hash_function - Retrieve the hash function and the hash key
690  * from the device.
691  * @ena_dev: ENA communication layer struct
692  * @func: hash function
693  * @key: hash key
694  *
695  * Retrieve the hash function and the hash key from the device.
696  *
697  * @note: If the caller called ena_com_fill_hash_function but didn't flash
698  * it to the device, the new configuration will be lost.
699  *
700  * @return: 0 on Success and negative value otherwise.
701  */
702 int ena_com_get_hash_function(struct ena_com_dev *ena_dev,
703 			      enum ena_admin_hash_functions *func,
704 			      u8 *key);
705 
706 /* ena_com_fill_hash_ctrl - Fill RSS hash control
707  * @ena_dev: ENA communication layer struct.
708  * @proto: The protocol to configure.
709  * @hash_fields: bit mask of ena_admin_flow_hash_fields
710  *
711  * Fill the ena_dev resources with the desire hash control (the ethernet
712  * fields that take part of the hash) for a specific protocol.
713  * To flush the hash control to the device, the caller should call
714  * ena_com_set_hash_ctrl.
715  *
716  * @return: 0 on Success and negative value otherwise.
717  */
718 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev,
719 			   enum ena_admin_flow_hash_proto proto,
720 			   u16 hash_fields);
721 
722 /* ena_com_set_hash_ctrl - Flush the hash control resources to the device.
723  * @ena_dev: ENA communication layer struct
724  *
725  * Flush the hash control (the ethernet fields that take part of the hash)
726  *
727  * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl.
728  *
729  * @return: 0 on Success and negative value otherwise.
730  */
731 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev);
732 
733 /* ena_com_get_hash_ctrl - Retrieve the hash control from the device.
734  * @ena_dev: ENA communication layer struct
735  * @proto: The protocol to retrieve.
736  * @fields: bit mask of ena_admin_flow_hash_fields.
737  *
738  * Retrieve the hash control from the device.
739  *
740  * @note, If the caller called ena_com_fill_hash_ctrl but didn't flash
741  * it to the device, the new configuration will be lost.
742  *
743  * @return: 0 on Success and negative value otherwise.
744  */
745 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev,
746 			  enum ena_admin_flow_hash_proto proto,
747 			  u16 *fields);
748 
749 /* ena_com_set_default_hash_ctrl - Set the hash control to a default
750  * configuration.
751  * @ena_dev: ENA communication layer struct
752  *
753  * Fill the ena_dev resources with the default hash control configuration.
754  * To flush the hash control to the device, the caller should call
755  * ena_com_set_hash_ctrl.
756  *
757  * @return: 0 on Success and negative value otherwise.
758  */
759 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev);
760 
761 /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS
762  * indirection table
763  * @ena_dev: ENA communication layer struct.
764  * @entry_idx - indirection table entry.
765  * @entry_value - redirection value
766  *
767  * Fill a single entry of the RSS indirection table in the ena_dev resources.
768  * To flush the indirection table to the device, the called should call
769  * ena_com_indirect_table_set.
770  *
771  * @return: 0 on Success and negative value otherwise.
772  */
773 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev,
774 				      u16 entry_idx, u16 entry_value);
775 
776 /* ena_com_indirect_table_set - Flush the indirection table to the device.
777  * @ena_dev: ENA communication layer struct
778  *
779  * Flush the indirection hash control to the device.
780  * Prior to this method the caller should call ena_com_indirect_table_fill_entry
781  *
782  * @return: 0 on Success and negative value otherwise.
783  */
784 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev);
785 
786 /* ena_com_indirect_table_get - Retrieve the indirection table from the device.
787  * @ena_dev: ENA communication layer struct
788  * @ind_tbl: indirection table
789  *
790  * Retrieve the RSS indirection table from the device.
791  *
792  * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash
793  * it to the device, the new configuration will be lost.
794  *
795  * @return: 0 on Success and negative value otherwise.
796  */
797 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl);
798 
799 /* ena_com_allocate_host_info - Allocate host info resources.
800  * @ena_dev: ENA communication layer struct
801  *
802  * @return: 0 on Success and negative value otherwise.
803  */
804 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev);
805 
806 /* ena_com_allocate_debug_area - Allocate debug area.
807  * @ena_dev: ENA communication layer struct
808  * @debug_area_size - debug area size.
809  *
810  * @return: 0 on Success and negative value otherwise.
811  */
812 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev,
813 				u32 debug_area_size);
814 
815 /* ena_com_delete_debug_area - Free the debug area resources.
816  * @ena_dev: ENA communication layer struct
817  *
818  * Free the allocate debug area.
819  */
820 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev);
821 
822 /* ena_com_delete_host_info - Free the host info resources.
823  * @ena_dev: ENA communication layer struct
824  *
825  * Free the allocate host info.
826  */
827 void ena_com_delete_host_info(struct ena_com_dev *ena_dev);
828 
829 /* ena_com_set_host_attributes - Update the device with the host
830  * attributes (debug area and host info) base address.
831  * @ena_dev: ENA communication layer struct
832  *
833  * @return: 0 on Success and negative value otherwise.
834  */
835 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev);
836 
837 /* ena_com_create_io_cq - Create io completion queue.
838  * @ena_dev: ENA communication layer struct
839  * @io_cq - io completion queue handler
840 
841  * Create IO completion queue.
842  *
843  * @return - 0 on success, negative value on failure.
844  */
845 int ena_com_create_io_cq(struct ena_com_dev *ena_dev,
846 			 struct ena_com_io_cq *io_cq);
847 
848 /* ena_com_destroy_io_cq - Destroy io completion queue.
849  * @ena_dev: ENA communication layer struct
850  * @io_cq - io completion queue handler
851 
852  * Destroy IO completion queue.
853  *
854  * @return - 0 on success, negative value on failure.
855  */
856 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev,
857 			  struct ena_com_io_cq *io_cq);
858 
859 /* ena_com_execute_admin_command - Execute admin command
860  * @admin_queue: admin queue.
861  * @cmd: the admin command to execute.
862  * @cmd_size: the command size.
863  * @cmd_completion: command completion return value.
864  * @cmd_comp_size: command completion size.
865 
866  * Submit an admin command and then wait until the device will return a
867  * completion.
868  * The completion will be copyed into cmd_comp.
869  *
870  * @return - 0 on success, negative value on failure.
871  */
872 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue,
873 				  struct ena_admin_aq_entry *cmd,
874 				  size_t cmd_size,
875 				  struct ena_admin_acq_entry *cmd_comp,
876 				  size_t cmd_comp_size);
877 
878 /* ena_com_init_interrupt_moderation - Init interrupt moderation
879  * @ena_dev: ENA communication layer struct
880  *
881  * @return - 0 on success, negative value on failure.
882  */
883 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev);
884 
885 /* ena_com_interrupt_moderation_supported - Return if interrupt moderation
886  * capability is supported by the device.
887  *
888  * @return - supported or not.
889  */
890 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev);
891 
892 /* ena_com_update_nonadaptive_moderation_interval_tx - Update the
893  * non-adaptive interval in Tx direction.
894  * @ena_dev: ENA communication layer struct
895  * @tx_coalesce_usecs: Interval in usec.
896  *
897  * @return - 0 on success, negative value on failure.
898  */
899 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
900 						      u32 tx_coalesce_usecs);
901 
902 /* ena_com_update_nonadaptive_moderation_interval_rx - Update the
903  * non-adaptive interval in Rx direction.
904  * @ena_dev: ENA communication layer struct
905  * @rx_coalesce_usecs: Interval in usec.
906  *
907  * @return - 0 on success, negative value on failure.
908  */
909 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
910 						      u32 rx_coalesce_usecs);
911 
912 /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the
913  * non-adaptive interval in Tx direction.
914  * @ena_dev: ENA communication layer struct
915  *
916  * @return - interval in usec
917  */
918 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);
919 
920 /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the
921  * non-adaptive interval in Rx direction.
922  * @ena_dev: ENA communication layer struct
923  *
924  * @return - interval in usec
925  */
926 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev);
927 
928 /* ena_com_config_dev_mode - Configure the placement policy of the device.
929  * @ena_dev: ENA communication layer struct
930  * @llq_features: LLQ feature descriptor, retrieve via
931  *                ena_com_get_dev_attr_feat.
932  * @ena_llq_config: The default driver LLQ parameters configurations
933  */
934 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
935 			    struct ena_admin_feature_llq_desc *llq_features,
936 			    struct ena_llq_configurations *llq_default_config);
937 
938 static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
939 {
940 	return ena_dev->adaptive_coalescing;
941 }
942 
943 static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)
944 {
945 	ena_dev->adaptive_coalescing = true;
946 }
947 
948 static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)
949 {
950 	ena_dev->adaptive_coalescing = false;
951 }
952 
953 /* ena_com_update_intr_reg - Prepare interrupt register
954  * @intr_reg: interrupt register to update.
955  * @rx_delay_interval: Rx interval in usecs
956  * @tx_delay_interval: Tx interval in usecs
957  * @unmask: unask enable/disable
958  *
959  * Prepare interrupt update register with the supplied parameters.
960  */
961 static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,
962 					   u32 rx_delay_interval,
963 					   u32 tx_delay_interval,
964 					   bool unmask)
965 {
966 	intr_reg->intr_control = 0;
967 	intr_reg->intr_control |= rx_delay_interval &
968 		ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
969 
970 	intr_reg->intr_control |=
971 		(tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
972 		& ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
973 
974 	if (unmask)
975 		intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
976 }
977 
978 static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl)
979 {
980 	u16 size, buffers_num;
981 	u8 *buf;
982 
983 	size = bounce_buf_ctrl->buffer_size;
984 	buffers_num = bounce_buf_ctrl->buffers_num;
985 
986 	buf = bounce_buf_ctrl->base_buffer +
987 		(bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size;
988 
989 	prefetchw(bounce_buf_ctrl->base_buffer +
990 		(bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size);
991 
992 	return buf;
993 }
994 
995 #endif /* !(ENA_COM) */
996