1 /* 2 * Copyright 2015 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include "ena_com.h" 34 35 /*****************************************************************************/ 36 /*****************************************************************************/ 37 38 /* Timeout in micro-sec */ 39 #define ADMIN_CMD_TIMEOUT_US (3000000) 40 41 #define ENA_ASYNC_QUEUE_DEPTH 16 42 #define ENA_ADMIN_QUEUE_DEPTH 32 43 44 #define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \ 45 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \ 46 | (ENA_COMMON_SPEC_VERSION_MINOR)) 47 48 #define ENA_CTRL_MAJOR 0 49 #define ENA_CTRL_MINOR 0 50 #define ENA_CTRL_SUB_MINOR 1 51 52 #define MIN_ENA_CTRL_VER \ 53 (((ENA_CTRL_MAJOR) << \ 54 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \ 55 ((ENA_CTRL_MINOR) << \ 56 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \ 57 (ENA_CTRL_SUB_MINOR)) 58 59 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x))) 60 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32)) 61 62 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF 63 64 #define ENA_REGS_ADMIN_INTR_MASK 1 65 66 /*****************************************************************************/ 67 /*****************************************************************************/ 68 /*****************************************************************************/ 69 70 enum ena_cmd_status { 71 ENA_CMD_SUBMITTED, 72 ENA_CMD_COMPLETED, 73 /* Abort - canceled by the driver */ 74 ENA_CMD_ABORTED, 75 }; 76 77 struct ena_comp_ctx { 78 struct completion wait_event; 79 struct ena_admin_acq_entry *user_cqe; 80 u32 comp_size; 81 enum ena_cmd_status status; 82 /* status from the device */ 83 u8 comp_status; 84 u8 cmd_opcode; 85 bool occupied; 86 }; 87 88 struct ena_com_stats_ctx { 89 struct ena_admin_aq_get_stats_cmd get_cmd; 90 struct ena_admin_acq_get_stats_resp get_resp; 91 }; 92 93 static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, 94 struct ena_common_mem_addr *ena_addr, 95 dma_addr_t addr) 96 { 97 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { 98 pr_err("dma address has more bits that the device supports\n"); 99 return -EINVAL; 100 } 101 102 ena_addr->mem_addr_low = (u32)addr; 103 ena_addr->mem_addr_high = (u64)addr >> 32; 104 105 return 0; 106 } 107 108 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue) 109 { 110 struct ena_com_admin_sq *sq = &queue->sq; 111 u16 size = ADMIN_SQ_SIZE(queue->q_depth); 112 113 sq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &sq->dma_addr, 114 GFP_KERNEL); 115 116 if (!sq->entries) { 117 pr_err("memory allocation failed"); 118 return -ENOMEM; 119 } 120 121 sq->head = 0; 122 sq->tail = 0; 123 sq->phase = 1; 124 125 sq->db_addr = NULL; 126 127 return 0; 128 } 129 130 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue) 131 { 132 struct ena_com_admin_cq *cq = &queue->cq; 133 u16 size = ADMIN_CQ_SIZE(queue->q_depth); 134 135 cq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &cq->dma_addr, 136 GFP_KERNEL); 137 138 if (!cq->entries) { 139 pr_err("memory allocation failed"); 140 return -ENOMEM; 141 } 142 143 cq->head = 0; 144 cq->phase = 1; 145 146 return 0; 147 } 148 149 static int ena_com_admin_init_aenq(struct ena_com_dev *dev, 150 struct ena_aenq_handlers *aenq_handlers) 151 { 152 struct ena_com_aenq *aenq = &dev->aenq; 153 u32 addr_low, addr_high, aenq_caps; 154 u16 size; 155 156 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; 157 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH); 158 aenq->entries = dma_zalloc_coherent(dev->dmadev, size, &aenq->dma_addr, 159 GFP_KERNEL); 160 161 if (!aenq->entries) { 162 pr_err("memory allocation failed"); 163 return -ENOMEM; 164 } 165 166 aenq->head = aenq->q_depth; 167 aenq->phase = 1; 168 169 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); 170 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); 171 172 writel(addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF); 173 writel(addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); 174 175 aenq_caps = 0; 176 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; 177 aenq_caps |= (sizeof(struct ena_admin_aenq_entry) 178 << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) & 179 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK; 180 writel(aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); 181 182 if (unlikely(!aenq_handlers)) { 183 pr_err("aenq handlers pointer is NULL\n"); 184 return -EINVAL; 185 } 186 187 aenq->aenq_handlers = aenq_handlers; 188 189 return 0; 190 } 191 192 static inline void comp_ctxt_release(struct ena_com_admin_queue *queue, 193 struct ena_comp_ctx *comp_ctx) 194 { 195 comp_ctx->occupied = false; 196 atomic_dec(&queue->outstanding_cmds); 197 } 198 199 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue, 200 u16 command_id, bool capture) 201 { 202 if (unlikely(command_id >= queue->q_depth)) { 203 pr_err("command id is larger than the queue size. cmd_id: %u queue size %d\n", 204 command_id, queue->q_depth); 205 return NULL; 206 } 207 208 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) { 209 pr_err("Completion context is occupied\n"); 210 return NULL; 211 } 212 213 if (capture) { 214 atomic_inc(&queue->outstanding_cmds); 215 queue->comp_ctx[command_id].occupied = true; 216 } 217 218 return &queue->comp_ctx[command_id]; 219 } 220 221 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 222 struct ena_admin_aq_entry *cmd, 223 size_t cmd_size_in_bytes, 224 struct ena_admin_acq_entry *comp, 225 size_t comp_size_in_bytes) 226 { 227 struct ena_comp_ctx *comp_ctx; 228 u16 tail_masked, cmd_id; 229 u16 queue_size_mask; 230 u16 cnt; 231 232 queue_size_mask = admin_queue->q_depth - 1; 233 234 tail_masked = admin_queue->sq.tail & queue_size_mask; 235 236 /* In case of queue FULL */ 237 cnt = atomic_read(&admin_queue->outstanding_cmds); 238 if (cnt >= admin_queue->q_depth) { 239 pr_debug("admin queue is full.\n"); 240 admin_queue->stats.out_of_space++; 241 return ERR_PTR(-ENOSPC); 242 } 243 244 cmd_id = admin_queue->curr_cmd_id; 245 246 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase & 247 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 248 249 cmd->aq_common_descriptor.command_id |= cmd_id & 250 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 251 252 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true); 253 if (unlikely(!comp_ctx)) 254 return ERR_PTR(-EINVAL); 255 256 comp_ctx->status = ENA_CMD_SUBMITTED; 257 comp_ctx->comp_size = (u32)comp_size_in_bytes; 258 comp_ctx->user_cqe = comp; 259 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode; 260 261 reinit_completion(&comp_ctx->wait_event); 262 263 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes); 264 265 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) & 266 queue_size_mask; 267 268 admin_queue->sq.tail++; 269 admin_queue->stats.submitted_cmd++; 270 271 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0)) 272 admin_queue->sq.phase = !admin_queue->sq.phase; 273 274 writel(admin_queue->sq.tail, admin_queue->sq.db_addr); 275 276 return comp_ctx; 277 } 278 279 static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue) 280 { 281 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx); 282 struct ena_comp_ctx *comp_ctx; 283 u16 i; 284 285 queue->comp_ctx = devm_kzalloc(queue->q_dmadev, size, GFP_KERNEL); 286 if (unlikely(!queue->comp_ctx)) { 287 pr_err("memory allocation failed"); 288 return -ENOMEM; 289 } 290 291 for (i = 0; i < queue->q_depth; i++) { 292 comp_ctx = get_comp_ctxt(queue, i, false); 293 if (comp_ctx) 294 init_completion(&comp_ctx->wait_event); 295 } 296 297 return 0; 298 } 299 300 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 301 struct ena_admin_aq_entry *cmd, 302 size_t cmd_size_in_bytes, 303 struct ena_admin_acq_entry *comp, 304 size_t comp_size_in_bytes) 305 { 306 unsigned long flags; 307 struct ena_comp_ctx *comp_ctx; 308 309 spin_lock_irqsave(&admin_queue->q_lock, flags); 310 if (unlikely(!admin_queue->running_state)) { 311 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 312 return ERR_PTR(-ENODEV); 313 } 314 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd, 315 cmd_size_in_bytes, 316 comp, 317 comp_size_in_bytes); 318 if (unlikely(IS_ERR(comp_ctx))) 319 admin_queue->running_state = false; 320 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 321 322 return comp_ctx; 323 } 324 325 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, 326 struct ena_com_create_io_ctx *ctx, 327 struct ena_com_io_sq *io_sq) 328 { 329 size_t size; 330 int dev_node = 0; 331 332 memset(&io_sq->desc_addr, 0x0, sizeof(struct ena_com_io_desc_addr)); 333 334 io_sq->desc_entry_size = 335 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 336 sizeof(struct ena_eth_io_tx_desc) : 337 sizeof(struct ena_eth_io_rx_desc); 338 339 size = io_sq->desc_entry_size * io_sq->q_depth; 340 341 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 342 dev_node = dev_to_node(ena_dev->dmadev); 343 set_dev_node(ena_dev->dmadev, ctx->numa_node); 344 io_sq->desc_addr.virt_addr = 345 dma_zalloc_coherent(ena_dev->dmadev, size, 346 &io_sq->desc_addr.phys_addr, 347 GFP_KERNEL); 348 set_dev_node(ena_dev->dmadev, dev_node); 349 if (!io_sq->desc_addr.virt_addr) { 350 io_sq->desc_addr.virt_addr = 351 dma_zalloc_coherent(ena_dev->dmadev, size, 352 &io_sq->desc_addr.phys_addr, 353 GFP_KERNEL); 354 } 355 } else { 356 dev_node = dev_to_node(ena_dev->dmadev); 357 set_dev_node(ena_dev->dmadev, ctx->numa_node); 358 io_sq->desc_addr.virt_addr = 359 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 360 set_dev_node(ena_dev->dmadev, dev_node); 361 if (!io_sq->desc_addr.virt_addr) { 362 io_sq->desc_addr.virt_addr = 363 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 364 } 365 } 366 367 if (!io_sq->desc_addr.virt_addr) { 368 pr_err("memory allocation failed"); 369 return -ENOMEM; 370 } 371 372 io_sq->tail = 0; 373 io_sq->next_to_comp = 0; 374 io_sq->phase = 1; 375 376 return 0; 377 } 378 379 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, 380 struct ena_com_create_io_ctx *ctx, 381 struct ena_com_io_cq *io_cq) 382 { 383 size_t size; 384 int prev_node = 0; 385 386 memset(&io_cq->cdesc_addr, 0x0, sizeof(struct ena_com_io_desc_addr)); 387 388 /* Use the basic completion descriptor for Rx */ 389 io_cq->cdesc_entry_size_in_bytes = 390 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 391 sizeof(struct ena_eth_io_tx_cdesc) : 392 sizeof(struct ena_eth_io_rx_cdesc_base); 393 394 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 395 396 prev_node = dev_to_node(ena_dev->dmadev); 397 set_dev_node(ena_dev->dmadev, ctx->numa_node); 398 io_cq->cdesc_addr.virt_addr = 399 dma_zalloc_coherent(ena_dev->dmadev, size, 400 &io_cq->cdesc_addr.phys_addr, GFP_KERNEL); 401 set_dev_node(ena_dev->dmadev, prev_node); 402 if (!io_cq->cdesc_addr.virt_addr) { 403 io_cq->cdesc_addr.virt_addr = 404 dma_zalloc_coherent(ena_dev->dmadev, size, 405 &io_cq->cdesc_addr.phys_addr, 406 GFP_KERNEL); 407 } 408 409 if (!io_cq->cdesc_addr.virt_addr) { 410 pr_err("memory allocation failed"); 411 return -ENOMEM; 412 } 413 414 io_cq->phase = 1; 415 io_cq->head = 0; 416 417 return 0; 418 } 419 420 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue, 421 struct ena_admin_acq_entry *cqe) 422 { 423 struct ena_comp_ctx *comp_ctx; 424 u16 cmd_id; 425 426 cmd_id = cqe->acq_common_descriptor.command & 427 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 428 429 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false); 430 if (unlikely(!comp_ctx)) { 431 pr_err("comp_ctx is NULL. Changing the admin queue running state\n"); 432 admin_queue->running_state = false; 433 return; 434 } 435 436 comp_ctx->status = ENA_CMD_COMPLETED; 437 comp_ctx->comp_status = cqe->acq_common_descriptor.status; 438 439 if (comp_ctx->user_cqe) 440 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size); 441 442 if (!admin_queue->polling) 443 complete(&comp_ctx->wait_event); 444 } 445 446 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue) 447 { 448 struct ena_admin_acq_entry *cqe = NULL; 449 u16 comp_num = 0; 450 u16 head_masked; 451 u8 phase; 452 453 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1); 454 phase = admin_queue->cq.phase; 455 456 cqe = &admin_queue->cq.entries[head_masked]; 457 458 /* Go over all the completions */ 459 while ((cqe->acq_common_descriptor.flags & 460 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) { 461 /* Do not read the rest of the completion entry before the 462 * phase bit was validated 463 */ 464 rmb(); 465 ena_com_handle_single_admin_completion(admin_queue, cqe); 466 467 head_masked++; 468 comp_num++; 469 if (unlikely(head_masked == admin_queue->q_depth)) { 470 head_masked = 0; 471 phase = !phase; 472 } 473 474 cqe = &admin_queue->cq.entries[head_masked]; 475 } 476 477 admin_queue->cq.head += comp_num; 478 admin_queue->cq.phase = phase; 479 admin_queue->sq.head += comp_num; 480 admin_queue->stats.completed_cmd += comp_num; 481 } 482 483 static int ena_com_comp_status_to_errno(u8 comp_status) 484 { 485 if (unlikely(comp_status != 0)) 486 pr_err("admin command failed[%u]\n", comp_status); 487 488 if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR)) 489 return -EINVAL; 490 491 switch (comp_status) { 492 case ENA_ADMIN_SUCCESS: 493 return 0; 494 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE: 495 return -ENOMEM; 496 case ENA_ADMIN_UNSUPPORTED_OPCODE: 497 return -EPERM; 498 case ENA_ADMIN_BAD_OPCODE: 499 case ENA_ADMIN_MALFORMED_REQUEST: 500 case ENA_ADMIN_ILLEGAL_PARAMETER: 501 case ENA_ADMIN_UNKNOWN_ERROR: 502 return -EINVAL; 503 } 504 505 return 0; 506 } 507 508 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx, 509 struct ena_com_admin_queue *admin_queue) 510 { 511 unsigned long flags, timeout; 512 int ret; 513 514 timeout = jiffies + ADMIN_CMD_TIMEOUT_US; 515 516 while (1) { 517 spin_lock_irqsave(&admin_queue->q_lock, flags); 518 ena_com_handle_admin_completion(admin_queue); 519 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 520 521 if (comp_ctx->status != ENA_CMD_SUBMITTED) 522 break; 523 524 if (time_is_before_jiffies(timeout)) { 525 pr_err("Wait for completion (polling) timeout\n"); 526 /* ENA didn't have any completion */ 527 spin_lock_irqsave(&admin_queue->q_lock, flags); 528 admin_queue->stats.no_completion++; 529 admin_queue->running_state = false; 530 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 531 532 ret = -ETIME; 533 goto err; 534 } 535 536 msleep(100); 537 } 538 539 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) { 540 pr_err("Command was aborted\n"); 541 spin_lock_irqsave(&admin_queue->q_lock, flags); 542 admin_queue->stats.aborted_cmd++; 543 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 544 ret = -ENODEV; 545 goto err; 546 } 547 548 WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n", 549 comp_ctx->status); 550 551 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); 552 err: 553 comp_ctxt_release(admin_queue, comp_ctx); 554 return ret; 555 } 556 557 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx, 558 struct ena_com_admin_queue *admin_queue) 559 { 560 unsigned long flags; 561 int ret; 562 563 wait_for_completion_timeout(&comp_ctx->wait_event, 564 usecs_to_jiffies(ADMIN_CMD_TIMEOUT_US)); 565 566 /* In case the command wasn't completed find out the root cause. 567 * There might be 2 kinds of errors 568 * 1) No completion (timeout reached) 569 * 2) There is completion but the device didn't get any msi-x interrupt. 570 */ 571 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) { 572 spin_lock_irqsave(&admin_queue->q_lock, flags); 573 ena_com_handle_admin_completion(admin_queue); 574 admin_queue->stats.no_completion++; 575 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 576 577 if (comp_ctx->status == ENA_CMD_COMPLETED) 578 pr_err("The ena device have completion but the driver didn't receive any MSI-X interrupt (cmd %d)\n", 579 comp_ctx->cmd_opcode); 580 else 581 pr_err("The ena device doesn't send any completion for the admin cmd %d status %d\n", 582 comp_ctx->cmd_opcode, comp_ctx->status); 583 584 admin_queue->running_state = false; 585 ret = -ETIME; 586 goto err; 587 } 588 589 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); 590 err: 591 comp_ctxt_release(admin_queue, comp_ctx); 592 return ret; 593 } 594 595 /* This method read the hardware device register through posting writes 596 * and waiting for response 597 * On timeout the function will return ENA_MMIO_READ_TIMEOUT 598 */ 599 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) 600 { 601 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 602 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp = 603 mmio_read->read_resp; 604 u32 mmio_read_reg, ret; 605 unsigned long flags; 606 int i; 607 608 might_sleep(); 609 610 /* If readless is disabled, perform regular read */ 611 if (!mmio_read->readless_supported) 612 return readl(ena_dev->reg_bar + offset); 613 614 spin_lock_irqsave(&mmio_read->lock, flags); 615 mmio_read->seq_num++; 616 617 read_resp->req_id = mmio_read->seq_num + 0xDEAD; 618 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) & 619 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK; 620 mmio_read_reg |= mmio_read->seq_num & 621 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK; 622 623 /* make sure read_resp->req_id get updated before the hw can write 624 * there 625 */ 626 wmb(); 627 628 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF); 629 630 for (i = 0; i < ENA_REG_READ_TIMEOUT; i++) { 631 if (read_resp->req_id == mmio_read->seq_num) 632 break; 633 634 udelay(1); 635 } 636 637 if (unlikely(i == ENA_REG_READ_TIMEOUT)) { 638 pr_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n", 639 mmio_read->seq_num, offset, read_resp->req_id, 640 read_resp->reg_off); 641 ret = ENA_MMIO_READ_TIMEOUT; 642 goto err; 643 } 644 645 if (read_resp->reg_off != offset) { 646 pr_err("Read failure: wrong offset provided"); 647 ret = ENA_MMIO_READ_TIMEOUT; 648 } else { 649 ret = read_resp->reg_val; 650 } 651 err: 652 spin_unlock_irqrestore(&mmio_read->lock, flags); 653 654 return ret; 655 } 656 657 /* There are two types to wait for completion. 658 * Polling mode - wait until the completion is available. 659 * Async mode - wait on wait queue until the completion is ready 660 * (or the timeout expired). 661 * It is expected that the IRQ called ena_com_handle_admin_completion 662 * to mark the completions. 663 */ 664 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx, 665 struct ena_com_admin_queue *admin_queue) 666 { 667 if (admin_queue->polling) 668 return ena_com_wait_and_process_admin_cq_polling(comp_ctx, 669 admin_queue); 670 671 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx, 672 admin_queue); 673 } 674 675 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, 676 struct ena_com_io_sq *io_sq) 677 { 678 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 679 struct ena_admin_aq_destroy_sq_cmd destroy_cmd; 680 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp; 681 u8 direction; 682 int ret; 683 684 memset(&destroy_cmd, 0x0, sizeof(struct ena_admin_aq_destroy_sq_cmd)); 685 686 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 687 direction = ENA_ADMIN_SQ_DIRECTION_TX; 688 else 689 direction = ENA_ADMIN_SQ_DIRECTION_RX; 690 691 destroy_cmd.sq.sq_identity |= (direction << 692 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & 693 ENA_ADMIN_SQ_SQ_DIRECTION_MASK; 694 695 destroy_cmd.sq.sq_idx = io_sq->idx; 696 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ; 697 698 ret = ena_com_execute_admin_command(admin_queue, 699 (struct ena_admin_aq_entry *)&destroy_cmd, 700 sizeof(destroy_cmd), 701 (struct ena_admin_acq_entry *)&destroy_resp, 702 sizeof(destroy_resp)); 703 704 if (unlikely(ret && (ret != -ENODEV))) 705 pr_err("failed to destroy io sq error: %d\n", ret); 706 707 return ret; 708 } 709 710 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev, 711 struct ena_com_io_sq *io_sq, 712 struct ena_com_io_cq *io_cq) 713 { 714 size_t size; 715 716 if (io_cq->cdesc_addr.virt_addr) { 717 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 718 719 dma_free_coherent(ena_dev->dmadev, size, 720 io_cq->cdesc_addr.virt_addr, 721 io_cq->cdesc_addr.phys_addr); 722 723 io_cq->cdesc_addr.virt_addr = NULL; 724 } 725 726 if (io_sq->desc_addr.virt_addr) { 727 size = io_sq->desc_entry_size * io_sq->q_depth; 728 729 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 730 dma_free_coherent(ena_dev->dmadev, size, 731 io_sq->desc_addr.virt_addr, 732 io_sq->desc_addr.phys_addr); 733 else 734 devm_kfree(ena_dev->dmadev, io_sq->desc_addr.virt_addr); 735 736 io_sq->desc_addr.virt_addr = NULL; 737 } 738 } 739 740 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, 741 u16 exp_state) 742 { 743 u32 val, i; 744 745 for (i = 0; i < timeout; i++) { 746 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 747 748 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) { 749 pr_err("Reg read timeout occurred\n"); 750 return -ETIME; 751 } 752 753 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) == 754 exp_state) 755 return 0; 756 757 /* The resolution of the timeout is 100ms */ 758 msleep(100); 759 } 760 761 return -ETIME; 762 } 763 764 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev, 765 enum ena_admin_aq_feature_id feature_id) 766 { 767 u32 feature_mask = 1 << feature_id; 768 769 /* Device attributes is always supported */ 770 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) && 771 !(ena_dev->supported_features & feature_mask)) 772 return false; 773 774 return true; 775 } 776 777 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, 778 struct ena_admin_get_feat_resp *get_resp, 779 enum ena_admin_aq_feature_id feature_id, 780 dma_addr_t control_buf_dma_addr, 781 u32 control_buff_size) 782 { 783 struct ena_com_admin_queue *admin_queue; 784 struct ena_admin_get_feat_cmd get_cmd; 785 int ret; 786 787 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) { 788 pr_debug("Feature %d isn't supported\n", feature_id); 789 return -EPERM; 790 } 791 792 memset(&get_cmd, 0x0, sizeof(get_cmd)); 793 admin_queue = &ena_dev->admin_queue; 794 795 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE; 796 797 if (control_buff_size) 798 get_cmd.aq_common_descriptor.flags = 799 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 800 else 801 get_cmd.aq_common_descriptor.flags = 0; 802 803 ret = ena_com_mem_addr_set(ena_dev, 804 &get_cmd.control_buffer.address, 805 control_buf_dma_addr); 806 if (unlikely(ret)) { 807 pr_err("memory address set failed\n"); 808 return ret; 809 } 810 811 get_cmd.control_buffer.length = control_buff_size; 812 813 get_cmd.feat_common.feature_id = feature_id; 814 815 ret = ena_com_execute_admin_command(admin_queue, 816 (struct ena_admin_aq_entry *) 817 &get_cmd, 818 sizeof(get_cmd), 819 (struct ena_admin_acq_entry *) 820 get_resp, 821 sizeof(*get_resp)); 822 823 if (unlikely(ret)) 824 pr_err("Failed to submit get_feature command %d error: %d\n", 825 feature_id, ret); 826 827 return ret; 828 } 829 830 static int ena_com_get_feature(struct ena_com_dev *ena_dev, 831 struct ena_admin_get_feat_resp *get_resp, 832 enum ena_admin_aq_feature_id feature_id) 833 { 834 return ena_com_get_feature_ex(ena_dev, 835 get_resp, 836 feature_id, 837 0, 838 0); 839 } 840 841 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) 842 { 843 struct ena_rss *rss = &ena_dev->rss; 844 845 rss->hash_key = 846 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), 847 &rss->hash_key_dma_addr, GFP_KERNEL); 848 849 if (unlikely(!rss->hash_key)) 850 return -ENOMEM; 851 852 return 0; 853 } 854 855 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev) 856 { 857 struct ena_rss *rss = &ena_dev->rss; 858 859 if (rss->hash_key) 860 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), 861 rss->hash_key, rss->hash_key_dma_addr); 862 rss->hash_key = NULL; 863 } 864 865 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev) 866 { 867 struct ena_rss *rss = &ena_dev->rss; 868 869 rss->hash_ctrl = 870 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), 871 &rss->hash_ctrl_dma_addr, GFP_KERNEL); 872 873 if (unlikely(!rss->hash_ctrl)) 874 return -ENOMEM; 875 876 return 0; 877 } 878 879 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev) 880 { 881 struct ena_rss *rss = &ena_dev->rss; 882 883 if (rss->hash_ctrl) 884 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), 885 rss->hash_ctrl, rss->hash_ctrl_dma_addr); 886 rss->hash_ctrl = NULL; 887 } 888 889 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, 890 u16 log_size) 891 { 892 struct ena_rss *rss = &ena_dev->rss; 893 struct ena_admin_get_feat_resp get_resp; 894 size_t tbl_size; 895 int ret; 896 897 ret = ena_com_get_feature(ena_dev, &get_resp, 898 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); 899 if (unlikely(ret)) 900 return ret; 901 902 if ((get_resp.u.ind_table.min_size > log_size) || 903 (get_resp.u.ind_table.max_size < log_size)) { 904 pr_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n", 905 1 << log_size, 1 << get_resp.u.ind_table.min_size, 906 1 << get_resp.u.ind_table.max_size); 907 return -EINVAL; 908 } 909 910 tbl_size = (1ULL << log_size) * 911 sizeof(struct ena_admin_rss_ind_table_entry); 912 913 rss->rss_ind_tbl = 914 dma_zalloc_coherent(ena_dev->dmadev, tbl_size, 915 &rss->rss_ind_tbl_dma_addr, GFP_KERNEL); 916 if (unlikely(!rss->rss_ind_tbl)) 917 goto mem_err1; 918 919 tbl_size = (1ULL << log_size) * sizeof(u16); 920 rss->host_rss_ind_tbl = 921 devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL); 922 if (unlikely(!rss->host_rss_ind_tbl)) 923 goto mem_err2; 924 925 rss->tbl_log_size = log_size; 926 927 return 0; 928 929 mem_err2: 930 tbl_size = (1ULL << log_size) * 931 sizeof(struct ena_admin_rss_ind_table_entry); 932 933 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, 934 rss->rss_ind_tbl_dma_addr); 935 rss->rss_ind_tbl = NULL; 936 mem_err1: 937 rss->tbl_log_size = 0; 938 return -ENOMEM; 939 } 940 941 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev) 942 { 943 struct ena_rss *rss = &ena_dev->rss; 944 size_t tbl_size = (1ULL << rss->tbl_log_size) * 945 sizeof(struct ena_admin_rss_ind_table_entry); 946 947 if (rss->rss_ind_tbl) 948 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, 949 rss->rss_ind_tbl_dma_addr); 950 rss->rss_ind_tbl = NULL; 951 952 if (rss->host_rss_ind_tbl) 953 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl); 954 rss->host_rss_ind_tbl = NULL; 955 } 956 957 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, 958 struct ena_com_io_sq *io_sq, u16 cq_idx) 959 { 960 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 961 struct ena_admin_aq_create_sq_cmd create_cmd; 962 struct ena_admin_acq_create_sq_resp_desc cmd_completion; 963 u8 direction; 964 int ret; 965 966 memset(&create_cmd, 0x0, sizeof(struct ena_admin_aq_create_sq_cmd)); 967 968 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ; 969 970 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 971 direction = ENA_ADMIN_SQ_DIRECTION_TX; 972 else 973 direction = ENA_ADMIN_SQ_DIRECTION_RX; 974 975 create_cmd.sq_identity |= (direction << 976 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & 977 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; 978 979 create_cmd.sq_caps_2 |= io_sq->mem_queue_type & 980 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 981 982 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC << 983 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & 984 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; 985 986 create_cmd.sq_caps_3 |= 987 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 988 989 create_cmd.cq_idx = cq_idx; 990 create_cmd.sq_depth = io_sq->q_depth; 991 992 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 993 ret = ena_com_mem_addr_set(ena_dev, 994 &create_cmd.sq_ba, 995 io_sq->desc_addr.phys_addr); 996 if (unlikely(ret)) { 997 pr_err("memory address set failed\n"); 998 return ret; 999 } 1000 } 1001 1002 ret = ena_com_execute_admin_command(admin_queue, 1003 (struct ena_admin_aq_entry *)&create_cmd, 1004 sizeof(create_cmd), 1005 (struct ena_admin_acq_entry *)&cmd_completion, 1006 sizeof(cmd_completion)); 1007 if (unlikely(ret)) { 1008 pr_err("Failed to create IO SQ. error: %d\n", ret); 1009 return ret; 1010 } 1011 1012 io_sq->idx = cmd_completion.sq_idx; 1013 1014 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1015 (uintptr_t)cmd_completion.sq_doorbell_offset); 1016 1017 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1018 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar 1019 + cmd_completion.llq_headers_offset); 1020 1021 io_sq->desc_addr.pbuf_dev_addr = 1022 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar + 1023 cmd_completion.llq_descriptors_offset); 1024 } 1025 1026 pr_debug("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth); 1027 1028 return ret; 1029 } 1030 1031 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev) 1032 { 1033 struct ena_rss *rss = &ena_dev->rss; 1034 struct ena_com_io_sq *io_sq; 1035 u16 qid; 1036 int i; 1037 1038 for (i = 0; i < 1 << rss->tbl_log_size; i++) { 1039 qid = rss->host_rss_ind_tbl[i]; 1040 if (qid >= ENA_TOTAL_NUM_QUEUES) 1041 return -EINVAL; 1042 1043 io_sq = &ena_dev->io_sq_queues[qid]; 1044 1045 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX) 1046 return -EINVAL; 1047 1048 rss->rss_ind_tbl[i].cq_idx = io_sq->idx; 1049 } 1050 1051 return 0; 1052 } 1053 1054 static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev) 1055 { 1056 u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 }; 1057 struct ena_rss *rss = &ena_dev->rss; 1058 u8 idx; 1059 u16 i; 1060 1061 for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++) 1062 dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i; 1063 1064 for (i = 0; i < 1 << rss->tbl_log_size; i++) { 1065 if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES) 1066 return -EINVAL; 1067 idx = (u8)rss->rss_ind_tbl[i].cq_idx; 1068 1069 if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES) 1070 return -EINVAL; 1071 1072 rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx]; 1073 } 1074 1075 return 0; 1076 } 1077 1078 static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev) 1079 { 1080 size_t size; 1081 1082 size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS; 1083 1084 ena_dev->intr_moder_tbl = 1085 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 1086 if (!ena_dev->intr_moder_tbl) 1087 return -ENOMEM; 1088 1089 ena_com_config_default_interrupt_moderation_table(ena_dev); 1090 1091 return 0; 1092 } 1093 1094 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, 1095 u16 intr_delay_resolution) 1096 { 1097 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 1098 unsigned int i; 1099 1100 if (!intr_delay_resolution) { 1101 pr_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); 1102 intr_delay_resolution = 1; 1103 } 1104 ena_dev->intr_delay_resolution = intr_delay_resolution; 1105 1106 /* update Rx */ 1107 for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++) 1108 intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution; 1109 1110 /* update Tx */ 1111 ena_dev->intr_moder_tx_interval /= intr_delay_resolution; 1112 } 1113 1114 /*****************************************************************************/ 1115 /******************************* API ******************************/ 1116 /*****************************************************************************/ 1117 1118 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, 1119 struct ena_admin_aq_entry *cmd, 1120 size_t cmd_size, 1121 struct ena_admin_acq_entry *comp, 1122 size_t comp_size) 1123 { 1124 struct ena_comp_ctx *comp_ctx; 1125 int ret; 1126 1127 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size, 1128 comp, comp_size); 1129 if (unlikely(IS_ERR(comp_ctx))) { 1130 if (comp_ctx == ERR_PTR(-ENODEV)) 1131 pr_debug("Failed to submit command [%ld]\n", 1132 PTR_ERR(comp_ctx)); 1133 else 1134 pr_err("Failed to submit command [%ld]\n", 1135 PTR_ERR(comp_ctx)); 1136 1137 return PTR_ERR(comp_ctx); 1138 } 1139 1140 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue); 1141 if (unlikely(ret)) { 1142 if (admin_queue->running_state) 1143 pr_err("Failed to process command. ret = %d\n", ret); 1144 else 1145 pr_debug("Failed to process command. ret = %d\n", ret); 1146 } 1147 return ret; 1148 } 1149 1150 int ena_com_create_io_cq(struct ena_com_dev *ena_dev, 1151 struct ena_com_io_cq *io_cq) 1152 { 1153 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1154 struct ena_admin_aq_create_cq_cmd create_cmd; 1155 struct ena_admin_acq_create_cq_resp_desc cmd_completion; 1156 int ret; 1157 1158 memset(&create_cmd, 0x0, sizeof(struct ena_admin_aq_create_cq_cmd)); 1159 1160 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ; 1161 1162 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) & 1163 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1164 create_cmd.cq_caps_1 |= 1165 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK; 1166 1167 create_cmd.msix_vector = io_cq->msix_vector; 1168 create_cmd.cq_depth = io_cq->q_depth; 1169 1170 ret = ena_com_mem_addr_set(ena_dev, 1171 &create_cmd.cq_ba, 1172 io_cq->cdesc_addr.phys_addr); 1173 if (unlikely(ret)) { 1174 pr_err("memory address set failed\n"); 1175 return ret; 1176 } 1177 1178 ret = ena_com_execute_admin_command(admin_queue, 1179 (struct ena_admin_aq_entry *)&create_cmd, 1180 sizeof(create_cmd), 1181 (struct ena_admin_acq_entry *)&cmd_completion, 1182 sizeof(cmd_completion)); 1183 if (unlikely(ret)) { 1184 pr_err("Failed to create IO CQ. error: %d\n", ret); 1185 return ret; 1186 } 1187 1188 io_cq->idx = cmd_completion.cq_idx; 1189 1190 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1191 cmd_completion.cq_interrupt_unmask_register_offset); 1192 1193 if (cmd_completion.cq_head_db_register_offset) 1194 io_cq->cq_head_db_reg = 1195 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1196 cmd_completion.cq_head_db_register_offset); 1197 1198 if (cmd_completion.numa_node_register_offset) 1199 io_cq->numa_node_cfg_reg = 1200 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1201 cmd_completion.numa_node_register_offset); 1202 1203 pr_debug("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth); 1204 1205 return ret; 1206 } 1207 1208 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, 1209 struct ena_com_io_sq **io_sq, 1210 struct ena_com_io_cq **io_cq) 1211 { 1212 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1213 pr_err("Invalid queue number %d but the max is %d\n", qid, 1214 ENA_TOTAL_NUM_QUEUES); 1215 return -EINVAL; 1216 } 1217 1218 *io_sq = &ena_dev->io_sq_queues[qid]; 1219 *io_cq = &ena_dev->io_cq_queues[qid]; 1220 1221 return 0; 1222 } 1223 1224 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev) 1225 { 1226 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1227 struct ena_comp_ctx *comp_ctx; 1228 u16 i; 1229 1230 if (!admin_queue->comp_ctx) 1231 return; 1232 1233 for (i = 0; i < admin_queue->q_depth; i++) { 1234 comp_ctx = get_comp_ctxt(admin_queue, i, false); 1235 if (unlikely(!comp_ctx)) 1236 break; 1237 1238 comp_ctx->status = ENA_CMD_ABORTED; 1239 1240 complete(&comp_ctx->wait_event); 1241 } 1242 } 1243 1244 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev) 1245 { 1246 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1247 unsigned long flags; 1248 1249 spin_lock_irqsave(&admin_queue->q_lock, flags); 1250 while (atomic_read(&admin_queue->outstanding_cmds) != 0) { 1251 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1252 msleep(20); 1253 spin_lock_irqsave(&admin_queue->q_lock, flags); 1254 } 1255 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1256 } 1257 1258 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, 1259 struct ena_com_io_cq *io_cq) 1260 { 1261 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1262 struct ena_admin_aq_destroy_cq_cmd destroy_cmd; 1263 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp; 1264 int ret; 1265 1266 memset(&destroy_cmd, 0x0, sizeof(struct ena_admin_aq_destroy_sq_cmd)); 1267 1268 destroy_cmd.cq_idx = io_cq->idx; 1269 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ; 1270 1271 ret = ena_com_execute_admin_command(admin_queue, 1272 (struct ena_admin_aq_entry *)&destroy_cmd, 1273 sizeof(destroy_cmd), 1274 (struct ena_admin_acq_entry *)&destroy_resp, 1275 sizeof(destroy_resp)); 1276 1277 if (unlikely(ret && (ret != -ENODEV))) 1278 pr_err("Failed to destroy IO CQ. error: %d\n", ret); 1279 1280 return ret; 1281 } 1282 1283 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev) 1284 { 1285 return ena_dev->admin_queue.running_state; 1286 } 1287 1288 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state) 1289 { 1290 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1291 unsigned long flags; 1292 1293 spin_lock_irqsave(&admin_queue->q_lock, flags); 1294 ena_dev->admin_queue.running_state = state; 1295 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1296 } 1297 1298 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev) 1299 { 1300 u16 depth = ena_dev->aenq.q_depth; 1301 1302 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); 1303 1304 /* Init head_db to mark that all entries in the queue 1305 * are initially available 1306 */ 1307 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 1308 } 1309 1310 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) 1311 { 1312 struct ena_com_admin_queue *admin_queue; 1313 struct ena_admin_set_feat_cmd cmd; 1314 struct ena_admin_set_feat_resp resp; 1315 struct ena_admin_get_feat_resp get_resp; 1316 int ret; 1317 1318 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG); 1319 if (ret) { 1320 pr_info("Can't get aenq configuration\n"); 1321 return ret; 1322 } 1323 1324 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) { 1325 pr_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n", 1326 get_resp.u.aenq.supported_groups, groups_flag); 1327 return -EPERM; 1328 } 1329 1330 memset(&cmd, 0x0, sizeof(cmd)); 1331 admin_queue = &ena_dev->admin_queue; 1332 1333 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1334 cmd.aq_common_descriptor.flags = 0; 1335 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG; 1336 cmd.u.aenq.enabled_groups = groups_flag; 1337 1338 ret = ena_com_execute_admin_command(admin_queue, 1339 (struct ena_admin_aq_entry *)&cmd, 1340 sizeof(cmd), 1341 (struct ena_admin_acq_entry *)&resp, 1342 sizeof(resp)); 1343 1344 if (unlikely(ret)) 1345 pr_err("Failed to config AENQ ret: %d\n", ret); 1346 1347 return ret; 1348 } 1349 1350 int ena_com_get_dma_width(struct ena_com_dev *ena_dev) 1351 { 1352 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 1353 int width; 1354 1355 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { 1356 pr_err("Reg read timeout occurred\n"); 1357 return -ETIME; 1358 } 1359 1360 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> 1361 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT; 1362 1363 pr_debug("ENA dma width: %d\n", width); 1364 1365 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { 1366 pr_err("DMA width illegal value: %d\n", width); 1367 return -EINVAL; 1368 } 1369 1370 ena_dev->dma_addr_bits = width; 1371 1372 return width; 1373 } 1374 1375 int ena_com_validate_version(struct ena_com_dev *ena_dev) 1376 { 1377 u32 ver; 1378 u32 ctrl_ver; 1379 u32 ctrl_ver_masked; 1380 1381 /* Make sure the ENA version and the controller version are at least 1382 * as the driver expects 1383 */ 1384 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF); 1385 ctrl_ver = ena_com_reg_bar_read32(ena_dev, 1386 ENA_REGS_CONTROLLER_VERSION_OFF); 1387 1388 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || 1389 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) { 1390 pr_err("Reg read timeout occurred\n"); 1391 return -ETIME; 1392 } 1393 1394 pr_info("ena device version: %d.%d\n", 1395 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> 1396 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT, 1397 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK); 1398 1399 if (ver < MIN_ENA_VER) { 1400 pr_err("ENA version is lower than the minimal version the driver supports\n"); 1401 return -1; 1402 } 1403 1404 pr_info("ena controller version: %d.%d.%d implementation version %d\n", 1405 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >> 1406 ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT, 1407 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >> 1408 ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT, 1409 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK), 1410 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >> 1411 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT); 1412 1413 ctrl_ver_masked = 1414 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) | 1415 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) | 1416 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK); 1417 1418 /* Validate the ctrl version without the implementation ID */ 1419 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) { 1420 pr_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n"); 1421 return -1; 1422 } 1423 1424 return 0; 1425 } 1426 1427 void ena_com_admin_destroy(struct ena_com_dev *ena_dev) 1428 { 1429 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1430 struct ena_com_admin_cq *cq = &admin_queue->cq; 1431 struct ena_com_admin_sq *sq = &admin_queue->sq; 1432 struct ena_com_aenq *aenq = &ena_dev->aenq; 1433 u16 size; 1434 1435 if (admin_queue->comp_ctx) 1436 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx); 1437 admin_queue->comp_ctx = NULL; 1438 size = ADMIN_SQ_SIZE(admin_queue->q_depth); 1439 if (sq->entries) 1440 dma_free_coherent(ena_dev->dmadev, size, sq->entries, 1441 sq->dma_addr); 1442 sq->entries = NULL; 1443 1444 size = ADMIN_CQ_SIZE(admin_queue->q_depth); 1445 if (cq->entries) 1446 dma_free_coherent(ena_dev->dmadev, size, cq->entries, 1447 cq->dma_addr); 1448 cq->entries = NULL; 1449 1450 size = ADMIN_AENQ_SIZE(aenq->q_depth); 1451 if (ena_dev->aenq.entries) 1452 dma_free_coherent(ena_dev->dmadev, size, aenq->entries, 1453 aenq->dma_addr); 1454 aenq->entries = NULL; 1455 } 1456 1457 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling) 1458 { 1459 u32 mask_value = 0; 1460 1461 if (polling) 1462 mask_value = ENA_REGS_ADMIN_INTR_MASK; 1463 1464 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF); 1465 ena_dev->admin_queue.polling = polling; 1466 } 1467 1468 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev) 1469 { 1470 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1471 1472 spin_lock_init(&mmio_read->lock); 1473 mmio_read->read_resp = 1474 dma_zalloc_coherent(ena_dev->dmadev, 1475 sizeof(*mmio_read->read_resp), 1476 &mmio_read->read_resp_dma_addr, GFP_KERNEL); 1477 if (unlikely(!mmio_read->read_resp)) 1478 return -ENOMEM; 1479 1480 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 1481 1482 mmio_read->read_resp->req_id = 0x0; 1483 mmio_read->seq_num = 0x0; 1484 mmio_read->readless_supported = true; 1485 1486 return 0; 1487 } 1488 1489 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported) 1490 { 1491 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1492 1493 mmio_read->readless_supported = readless_supported; 1494 } 1495 1496 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev) 1497 { 1498 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1499 1500 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1501 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1502 1503 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), 1504 mmio_read->read_resp, mmio_read->read_resp_dma_addr); 1505 1506 mmio_read->read_resp = NULL; 1507 } 1508 1509 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev) 1510 { 1511 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1512 u32 addr_low, addr_high; 1513 1514 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr); 1515 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr); 1516 1517 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1518 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1519 } 1520 1521 int ena_com_admin_init(struct ena_com_dev *ena_dev, 1522 struct ena_aenq_handlers *aenq_handlers, 1523 bool init_spinlock) 1524 { 1525 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1526 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high; 1527 int ret; 1528 1529 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 1530 1531 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) { 1532 pr_err("Reg read timeout occurred\n"); 1533 return -ETIME; 1534 } 1535 1536 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) { 1537 pr_err("Device isn't ready, abort com init\n"); 1538 return -ENODEV; 1539 } 1540 1541 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH; 1542 1543 admin_queue->q_dmadev = ena_dev->dmadev; 1544 admin_queue->polling = false; 1545 admin_queue->curr_cmd_id = 0; 1546 1547 atomic_set(&admin_queue->outstanding_cmds, 0); 1548 1549 if (init_spinlock) 1550 spin_lock_init(&admin_queue->q_lock); 1551 1552 ret = ena_com_init_comp_ctxt(admin_queue); 1553 if (ret) 1554 goto error; 1555 1556 ret = ena_com_admin_init_sq(admin_queue); 1557 if (ret) 1558 goto error; 1559 1560 ret = ena_com_admin_init_cq(admin_queue); 1561 if (ret) 1562 goto error; 1563 1564 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1565 ENA_REGS_AQ_DB_OFF); 1566 1567 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr); 1568 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr); 1569 1570 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF); 1571 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF); 1572 1573 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr); 1574 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr); 1575 1576 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF); 1577 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF); 1578 1579 aq_caps = 0; 1580 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK; 1581 aq_caps |= (sizeof(struct ena_admin_aq_entry) << 1582 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) & 1583 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK; 1584 1585 acq_caps = 0; 1586 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK; 1587 acq_caps |= (sizeof(struct ena_admin_acq_entry) << 1588 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) & 1589 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK; 1590 1591 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF); 1592 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF); 1593 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers); 1594 if (ret) 1595 goto error; 1596 1597 admin_queue->running_state = true; 1598 1599 return 0; 1600 error: 1601 ena_com_admin_destroy(ena_dev); 1602 1603 return ret; 1604 } 1605 1606 int ena_com_create_io_queue(struct ena_com_dev *ena_dev, 1607 struct ena_com_create_io_ctx *ctx) 1608 { 1609 struct ena_com_io_sq *io_sq; 1610 struct ena_com_io_cq *io_cq; 1611 int ret; 1612 1613 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) { 1614 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", 1615 ctx->qid, ENA_TOTAL_NUM_QUEUES); 1616 return -EINVAL; 1617 } 1618 1619 io_sq = &ena_dev->io_sq_queues[ctx->qid]; 1620 io_cq = &ena_dev->io_cq_queues[ctx->qid]; 1621 1622 memset(io_sq, 0x0, sizeof(struct ena_com_io_sq)); 1623 memset(io_cq, 0x0, sizeof(struct ena_com_io_cq)); 1624 1625 /* Init CQ */ 1626 io_cq->q_depth = ctx->queue_size; 1627 io_cq->direction = ctx->direction; 1628 io_cq->qid = ctx->qid; 1629 1630 io_cq->msix_vector = ctx->msix_vector; 1631 1632 io_sq->q_depth = ctx->queue_size; 1633 io_sq->direction = ctx->direction; 1634 io_sq->qid = ctx->qid; 1635 1636 io_sq->mem_queue_type = ctx->mem_queue_type; 1637 1638 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 1639 /* header length is limited to 8 bits */ 1640 io_sq->tx_max_header_size = 1641 min_t(u32, ena_dev->tx_max_header_size, SZ_256); 1642 1643 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq); 1644 if (ret) 1645 goto error; 1646 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq); 1647 if (ret) 1648 goto error; 1649 1650 ret = ena_com_create_io_cq(ena_dev, io_cq); 1651 if (ret) 1652 goto error; 1653 1654 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx); 1655 if (ret) 1656 goto destroy_io_cq; 1657 1658 return 0; 1659 1660 destroy_io_cq: 1661 ena_com_destroy_io_cq(ena_dev, io_cq); 1662 error: 1663 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1664 return ret; 1665 } 1666 1667 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) 1668 { 1669 struct ena_com_io_sq *io_sq; 1670 struct ena_com_io_cq *io_cq; 1671 1672 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1673 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", qid, 1674 ENA_TOTAL_NUM_QUEUES); 1675 return; 1676 } 1677 1678 io_sq = &ena_dev->io_sq_queues[qid]; 1679 io_cq = &ena_dev->io_cq_queues[qid]; 1680 1681 ena_com_destroy_io_sq(ena_dev, io_sq); 1682 ena_com_destroy_io_cq(ena_dev, io_cq); 1683 1684 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1685 } 1686 1687 int ena_com_get_link_params(struct ena_com_dev *ena_dev, 1688 struct ena_admin_get_feat_resp *resp) 1689 { 1690 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG); 1691 } 1692 1693 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, 1694 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1695 { 1696 struct ena_admin_get_feat_resp get_resp; 1697 int rc; 1698 1699 rc = ena_com_get_feature(ena_dev, &get_resp, 1700 ENA_ADMIN_DEVICE_ATTRIBUTES); 1701 if (rc) 1702 return rc; 1703 1704 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr, 1705 sizeof(get_resp.u.dev_attr)); 1706 ena_dev->supported_features = get_resp.u.dev_attr.supported_features; 1707 1708 rc = ena_com_get_feature(ena_dev, &get_resp, 1709 ENA_ADMIN_MAX_QUEUES_NUM); 1710 if (rc) 1711 return rc; 1712 1713 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue, 1714 sizeof(get_resp.u.max_queue)); 1715 ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size; 1716 1717 rc = ena_com_get_feature(ena_dev, &get_resp, 1718 ENA_ADMIN_AENQ_CONFIG); 1719 if (rc) 1720 return rc; 1721 1722 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq, 1723 sizeof(get_resp.u.aenq)); 1724 1725 rc = ena_com_get_feature(ena_dev, &get_resp, 1726 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG); 1727 if (rc) 1728 return rc; 1729 1730 memcpy(&get_feat_ctx->offload, &get_resp.u.offload, 1731 sizeof(get_resp.u.offload)); 1732 1733 return 0; 1734 } 1735 1736 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev) 1737 { 1738 ena_com_handle_admin_completion(&ena_dev->admin_queue); 1739 } 1740 1741 /* ena_handle_specific_aenq_event: 1742 * return the handler that is relevant to the specific event group 1743 */ 1744 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev, 1745 u16 group) 1746 { 1747 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers; 1748 1749 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group]) 1750 return aenq_handlers->handlers[group]; 1751 1752 return aenq_handlers->unimplemented_handler; 1753 } 1754 1755 /* ena_aenq_intr_handler: 1756 * handles the aenq incoming events. 1757 * pop events from the queue and apply the specific handler 1758 */ 1759 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) 1760 { 1761 struct ena_admin_aenq_entry *aenq_e; 1762 struct ena_admin_aenq_common_desc *aenq_common; 1763 struct ena_com_aenq *aenq = &dev->aenq; 1764 ena_aenq_handler handler_cb; 1765 u16 masked_head, processed = 0; 1766 u8 phase; 1767 1768 masked_head = aenq->head & (aenq->q_depth - 1); 1769 phase = aenq->phase; 1770 aenq_e = &aenq->entries[masked_head]; /* Get first entry */ 1771 aenq_common = &aenq_e->aenq_common_desc; 1772 1773 /* Go over all the events */ 1774 while ((aenq_common->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == 1775 phase) { 1776 pr_debug("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n", 1777 aenq_common->group, aenq_common->syndrom, 1778 (u64)aenq_common->timestamp_low + 1779 ((u64)aenq_common->timestamp_high << 32)); 1780 1781 /* Handle specific event*/ 1782 handler_cb = ena_com_get_specific_aenq_cb(dev, 1783 aenq_common->group); 1784 handler_cb(data, aenq_e); /* call the actual event handler*/ 1785 1786 /* Get next event entry */ 1787 masked_head++; 1788 processed++; 1789 1790 if (unlikely(masked_head == aenq->q_depth)) { 1791 masked_head = 0; 1792 phase = !phase; 1793 } 1794 aenq_e = &aenq->entries[masked_head]; 1795 aenq_common = &aenq_e->aenq_common_desc; 1796 } 1797 1798 aenq->head += processed; 1799 aenq->phase = phase; 1800 1801 /* Don't update aenq doorbell if there weren't any processed events */ 1802 if (!processed) 1803 return; 1804 1805 /* write the aenq doorbell after all AENQ descriptors were read */ 1806 mb(); 1807 writel((u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 1808 } 1809 1810 int ena_com_dev_reset(struct ena_com_dev *ena_dev) 1811 { 1812 u32 stat, timeout, cap, reset_val; 1813 int rc; 1814 1815 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 1816 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 1817 1818 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || 1819 (cap == ENA_MMIO_READ_TIMEOUT))) { 1820 pr_err("Reg read32 timeout occurred\n"); 1821 return -ETIME; 1822 } 1823 1824 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) { 1825 pr_err("Device isn't ready, can't reset device\n"); 1826 return -EINVAL; 1827 } 1828 1829 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >> 1830 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT; 1831 if (timeout == 0) { 1832 pr_err("Invalid timeout value\n"); 1833 return -EINVAL; 1834 } 1835 1836 /* start reset */ 1837 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; 1838 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 1839 1840 /* Write again the MMIO read request address */ 1841 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 1842 1843 rc = wait_for_reset_state(ena_dev, timeout, 1844 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK); 1845 if (rc != 0) { 1846 pr_err("Reset indication didn't turn on\n"); 1847 return rc; 1848 } 1849 1850 /* reset done */ 1851 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 1852 rc = wait_for_reset_state(ena_dev, timeout, 0); 1853 if (rc != 0) { 1854 pr_err("Reset indication didn't turn off\n"); 1855 return rc; 1856 } 1857 1858 return 0; 1859 } 1860 1861 static int ena_get_dev_stats(struct ena_com_dev *ena_dev, 1862 struct ena_com_stats_ctx *ctx, 1863 enum ena_admin_get_stats_type type) 1864 { 1865 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd; 1866 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp; 1867 struct ena_com_admin_queue *admin_queue; 1868 int ret; 1869 1870 admin_queue = &ena_dev->admin_queue; 1871 1872 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS; 1873 get_cmd->aq_common_descriptor.flags = 0; 1874 get_cmd->type = type; 1875 1876 ret = ena_com_execute_admin_command(admin_queue, 1877 (struct ena_admin_aq_entry *)get_cmd, 1878 sizeof(*get_cmd), 1879 (struct ena_admin_acq_entry *)get_resp, 1880 sizeof(*get_resp)); 1881 1882 if (unlikely(ret)) 1883 pr_err("Failed to get stats. error: %d\n", ret); 1884 1885 return ret; 1886 } 1887 1888 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, 1889 struct ena_admin_basic_stats *stats) 1890 { 1891 struct ena_com_stats_ctx ctx; 1892 int ret; 1893 1894 memset(&ctx, 0x0, sizeof(ctx)); 1895 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC); 1896 if (likely(ret == 0)) 1897 memcpy(stats, &ctx.get_resp.basic_stats, 1898 sizeof(ctx.get_resp.basic_stats)); 1899 1900 return ret; 1901 } 1902 1903 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) 1904 { 1905 struct ena_com_admin_queue *admin_queue; 1906 struct ena_admin_set_feat_cmd cmd; 1907 struct ena_admin_set_feat_resp resp; 1908 int ret; 1909 1910 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) { 1911 pr_debug("Feature %d isn't supported\n", ENA_ADMIN_MTU); 1912 return -EPERM; 1913 } 1914 1915 memset(&cmd, 0x0, sizeof(cmd)); 1916 admin_queue = &ena_dev->admin_queue; 1917 1918 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1919 cmd.aq_common_descriptor.flags = 0; 1920 cmd.feat_common.feature_id = ENA_ADMIN_MTU; 1921 cmd.u.mtu.mtu = mtu; 1922 1923 ret = ena_com_execute_admin_command(admin_queue, 1924 (struct ena_admin_aq_entry *)&cmd, 1925 sizeof(cmd), 1926 (struct ena_admin_acq_entry *)&resp, 1927 sizeof(resp)); 1928 1929 if (unlikely(ret)) 1930 pr_err("Failed to set mtu %d. error: %d\n", mtu, ret); 1931 1932 return ret; 1933 } 1934 1935 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, 1936 struct ena_admin_feature_offload_desc *offload) 1937 { 1938 int ret; 1939 struct ena_admin_get_feat_resp resp; 1940 1941 ret = ena_com_get_feature(ena_dev, &resp, 1942 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG); 1943 if (unlikely(ret)) { 1944 pr_err("Failed to get offload capabilities %d\n", ret); 1945 return ret; 1946 } 1947 1948 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload)); 1949 1950 return 0; 1951 } 1952 1953 int ena_com_set_hash_function(struct ena_com_dev *ena_dev) 1954 { 1955 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1956 struct ena_rss *rss = &ena_dev->rss; 1957 struct ena_admin_set_feat_cmd cmd; 1958 struct ena_admin_set_feat_resp resp; 1959 struct ena_admin_get_feat_resp get_resp; 1960 int ret; 1961 1962 if (!ena_com_check_supported_feature_id(ena_dev, 1963 ENA_ADMIN_RSS_HASH_FUNCTION)) { 1964 pr_debug("Feature %d isn't supported\n", 1965 ENA_ADMIN_RSS_HASH_FUNCTION); 1966 return -EPERM; 1967 } 1968 1969 /* Validate hash function is supported */ 1970 ret = ena_com_get_feature(ena_dev, &get_resp, 1971 ENA_ADMIN_RSS_HASH_FUNCTION); 1972 if (unlikely(ret)) 1973 return ret; 1974 1975 if (get_resp.u.flow_hash_func.supported_func & (1 << rss->hash_func)) { 1976 pr_err("Func hash %d isn't supported by device, abort\n", 1977 rss->hash_func); 1978 return -EPERM; 1979 } 1980 1981 memset(&cmd, 0x0, sizeof(cmd)); 1982 1983 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1984 cmd.aq_common_descriptor.flags = 1985 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 1986 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION; 1987 cmd.u.flow_hash_func.init_val = rss->hash_init_val; 1988 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func; 1989 1990 ret = ena_com_mem_addr_set(ena_dev, 1991 &cmd.control_buffer.address, 1992 rss->hash_key_dma_addr); 1993 if (unlikely(ret)) { 1994 pr_err("memory address set failed\n"); 1995 return ret; 1996 } 1997 1998 cmd.control_buffer.length = sizeof(*rss->hash_key); 1999 2000 ret = ena_com_execute_admin_command(admin_queue, 2001 (struct ena_admin_aq_entry *)&cmd, 2002 sizeof(cmd), 2003 (struct ena_admin_acq_entry *)&resp, 2004 sizeof(resp)); 2005 if (unlikely(ret)) { 2006 pr_err("Failed to set hash function %d. error: %d\n", 2007 rss->hash_func, ret); 2008 return -EINVAL; 2009 } 2010 2011 return 0; 2012 } 2013 2014 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, 2015 enum ena_admin_hash_functions func, 2016 const u8 *key, u16 key_len, u32 init_val) 2017 { 2018 struct ena_rss *rss = &ena_dev->rss; 2019 struct ena_admin_get_feat_resp get_resp; 2020 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2021 rss->hash_key; 2022 int rc; 2023 2024 /* Make sure size is a mult of DWs */ 2025 if (unlikely(key_len & 0x3)) 2026 return -EINVAL; 2027 2028 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2029 ENA_ADMIN_RSS_HASH_FUNCTION, 2030 rss->hash_key_dma_addr, 2031 sizeof(*rss->hash_key)); 2032 if (unlikely(rc)) 2033 return rc; 2034 2035 if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) { 2036 pr_err("Flow hash function %d isn't supported\n", func); 2037 return -EPERM; 2038 } 2039 2040 switch (func) { 2041 case ENA_ADMIN_TOEPLITZ: 2042 if (key_len > sizeof(hash_key->key)) { 2043 pr_err("key len (%hu) is bigger than the max supported (%zu)\n", 2044 key_len, sizeof(hash_key->key)); 2045 return -EINVAL; 2046 } 2047 2048 memcpy(hash_key->key, key, key_len); 2049 rss->hash_init_val = init_val; 2050 hash_key->keys_num = key_len >> 2; 2051 break; 2052 case ENA_ADMIN_CRC32: 2053 rss->hash_init_val = init_val; 2054 break; 2055 default: 2056 pr_err("Invalid hash function (%d)\n", func); 2057 return -EINVAL; 2058 } 2059 2060 rc = ena_com_set_hash_function(ena_dev); 2061 2062 /* Restore the old function */ 2063 if (unlikely(rc)) 2064 ena_com_get_hash_function(ena_dev, NULL, NULL); 2065 2066 return rc; 2067 } 2068 2069 int ena_com_get_hash_function(struct ena_com_dev *ena_dev, 2070 enum ena_admin_hash_functions *func, 2071 u8 *key) 2072 { 2073 struct ena_rss *rss = &ena_dev->rss; 2074 struct ena_admin_get_feat_resp get_resp; 2075 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2076 rss->hash_key; 2077 int rc; 2078 2079 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2080 ENA_ADMIN_RSS_HASH_FUNCTION, 2081 rss->hash_key_dma_addr, 2082 sizeof(*rss->hash_key)); 2083 if (unlikely(rc)) 2084 return rc; 2085 2086 rss->hash_func = get_resp.u.flow_hash_func.selected_func; 2087 if (func) 2088 *func = rss->hash_func; 2089 2090 if (key) 2091 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2); 2092 2093 return 0; 2094 } 2095 2096 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, 2097 enum ena_admin_flow_hash_proto proto, 2098 u16 *fields) 2099 { 2100 struct ena_rss *rss = &ena_dev->rss; 2101 struct ena_admin_get_feat_resp get_resp; 2102 int rc; 2103 2104 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2105 ENA_ADMIN_RSS_HASH_INPUT, 2106 rss->hash_ctrl_dma_addr, 2107 sizeof(*rss->hash_ctrl)); 2108 if (unlikely(rc)) 2109 return rc; 2110 2111 if (fields) 2112 *fields = rss->hash_ctrl->selected_fields[proto].fields; 2113 2114 return 0; 2115 } 2116 2117 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) 2118 { 2119 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2120 struct ena_rss *rss = &ena_dev->rss; 2121 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2122 struct ena_admin_set_feat_cmd cmd; 2123 struct ena_admin_set_feat_resp resp; 2124 int ret; 2125 2126 if (!ena_com_check_supported_feature_id(ena_dev, 2127 ENA_ADMIN_RSS_HASH_INPUT)) { 2128 pr_debug("Feature %d isn't supported\n", 2129 ENA_ADMIN_RSS_HASH_INPUT); 2130 return -EPERM; 2131 } 2132 2133 memset(&cmd, 0x0, sizeof(cmd)); 2134 2135 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2136 cmd.aq_common_descriptor.flags = 2137 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2138 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT; 2139 cmd.u.flow_hash_input.enabled_input_sort = 2140 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK | 2141 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; 2142 2143 ret = ena_com_mem_addr_set(ena_dev, 2144 &cmd.control_buffer.address, 2145 rss->hash_ctrl_dma_addr); 2146 if (unlikely(ret)) { 2147 pr_err("memory address set failed\n"); 2148 return ret; 2149 } 2150 cmd.control_buffer.length = sizeof(*hash_ctrl); 2151 2152 ret = ena_com_execute_admin_command(admin_queue, 2153 (struct ena_admin_aq_entry *)&cmd, 2154 sizeof(cmd), 2155 (struct ena_admin_acq_entry *)&resp, 2156 sizeof(resp)); 2157 if (unlikely(ret)) 2158 pr_err("Failed to set hash input. error: %d\n", ret); 2159 2160 return ret; 2161 } 2162 2163 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) 2164 { 2165 struct ena_rss *rss = &ena_dev->rss; 2166 struct ena_admin_feature_rss_hash_control *hash_ctrl = 2167 rss->hash_ctrl; 2168 u16 available_fields = 0; 2169 int rc, i; 2170 2171 /* Get the supported hash input */ 2172 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2173 if (unlikely(rc)) 2174 return rc; 2175 2176 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields = 2177 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2178 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2179 2180 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields = 2181 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2182 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2183 2184 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields = 2185 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2186 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2187 2188 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields = 2189 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2190 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2191 2192 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields = 2193 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2194 2195 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields = 2196 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2197 2198 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields = 2199 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2200 2201 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields = 2202 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA; 2203 2204 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) { 2205 available_fields = hash_ctrl->selected_fields[i].fields & 2206 hash_ctrl->supported_fields[i].fields; 2207 if (available_fields != hash_ctrl->selected_fields[i].fields) { 2208 pr_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n", 2209 i, hash_ctrl->supported_fields[i].fields, 2210 hash_ctrl->selected_fields[i].fields); 2211 return -EPERM; 2212 } 2213 } 2214 2215 rc = ena_com_set_hash_ctrl(ena_dev); 2216 2217 /* In case of failure, restore the old hash ctrl */ 2218 if (unlikely(rc)) 2219 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2220 2221 return rc; 2222 } 2223 2224 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, 2225 enum ena_admin_flow_hash_proto proto, 2226 u16 hash_fields) 2227 { 2228 struct ena_rss *rss = &ena_dev->rss; 2229 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2230 u16 supported_fields; 2231 int rc; 2232 2233 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) { 2234 pr_err("Invalid proto num (%u)\n", proto); 2235 return -EINVAL; 2236 } 2237 2238 /* Get the ctrl table */ 2239 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL); 2240 if (unlikely(rc)) 2241 return rc; 2242 2243 /* Make sure all the fields are supported */ 2244 supported_fields = hash_ctrl->supported_fields[proto].fields; 2245 if ((hash_fields & supported_fields) != hash_fields) { 2246 pr_err("proto %d doesn't support the required fields %x. supports only: %x\n", 2247 proto, hash_fields, supported_fields); 2248 } 2249 2250 hash_ctrl->selected_fields[proto].fields = hash_fields; 2251 2252 rc = ena_com_set_hash_ctrl(ena_dev); 2253 2254 /* In case of failure, restore the old hash ctrl */ 2255 if (unlikely(rc)) 2256 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2257 2258 return 0; 2259 } 2260 2261 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, 2262 u16 entry_idx, u16 entry_value) 2263 { 2264 struct ena_rss *rss = &ena_dev->rss; 2265 2266 if (unlikely(entry_idx >= (1 << rss->tbl_log_size))) 2267 return -EINVAL; 2268 2269 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES))) 2270 return -EINVAL; 2271 2272 rss->host_rss_ind_tbl[entry_idx] = entry_value; 2273 2274 return 0; 2275 } 2276 2277 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) 2278 { 2279 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2280 struct ena_rss *rss = &ena_dev->rss; 2281 struct ena_admin_set_feat_cmd cmd; 2282 struct ena_admin_set_feat_resp resp; 2283 int ret; 2284 2285 if (!ena_com_check_supported_feature_id( 2286 ena_dev, ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) { 2287 pr_debug("Feature %d isn't supported\n", 2288 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); 2289 return -EPERM; 2290 } 2291 2292 ret = ena_com_ind_tbl_convert_to_device(ena_dev); 2293 if (ret) { 2294 pr_err("Failed to convert host indirection table to device table\n"); 2295 return ret; 2296 } 2297 2298 memset(&cmd, 0x0, sizeof(cmd)); 2299 2300 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2301 cmd.aq_common_descriptor.flags = 2302 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2303 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG; 2304 cmd.u.ind_table.size = rss->tbl_log_size; 2305 cmd.u.ind_table.inline_index = 0xFFFFFFFF; 2306 2307 ret = ena_com_mem_addr_set(ena_dev, 2308 &cmd.control_buffer.address, 2309 rss->rss_ind_tbl_dma_addr); 2310 if (unlikely(ret)) { 2311 pr_err("memory address set failed\n"); 2312 return ret; 2313 } 2314 2315 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) * 2316 sizeof(struct ena_admin_rss_ind_table_entry); 2317 2318 ret = ena_com_execute_admin_command(admin_queue, 2319 (struct ena_admin_aq_entry *)&cmd, 2320 sizeof(cmd), 2321 (struct ena_admin_acq_entry *)&resp, 2322 sizeof(resp)); 2323 2324 if (unlikely(ret)) 2325 pr_err("Failed to set indirect table. error: %d\n", ret); 2326 2327 return ret; 2328 } 2329 2330 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) 2331 { 2332 struct ena_rss *rss = &ena_dev->rss; 2333 struct ena_admin_get_feat_resp get_resp; 2334 u32 tbl_size; 2335 int i, rc; 2336 2337 tbl_size = (1ULL << rss->tbl_log_size) * 2338 sizeof(struct ena_admin_rss_ind_table_entry); 2339 2340 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2341 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 2342 rss->rss_ind_tbl_dma_addr, 2343 tbl_size); 2344 if (unlikely(rc)) 2345 return rc; 2346 2347 if (!ind_tbl) 2348 return 0; 2349 2350 rc = ena_com_ind_tbl_convert_from_device(ena_dev); 2351 if (unlikely(rc)) 2352 return rc; 2353 2354 for (i = 0; i < (1 << rss->tbl_log_size); i++) 2355 ind_tbl[i] = rss->host_rss_ind_tbl[i]; 2356 2357 return 0; 2358 } 2359 2360 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size) 2361 { 2362 int rc; 2363 2364 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2365 2366 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size); 2367 if (unlikely(rc)) 2368 goto err_indr_tbl; 2369 2370 rc = ena_com_hash_key_allocate(ena_dev); 2371 if (unlikely(rc)) 2372 goto err_hash_key; 2373 2374 rc = ena_com_hash_ctrl_init(ena_dev); 2375 if (unlikely(rc)) 2376 goto err_hash_ctrl; 2377 2378 return 0; 2379 2380 err_hash_ctrl: 2381 ena_com_hash_key_destroy(ena_dev); 2382 err_hash_key: 2383 ena_com_indirect_table_destroy(ena_dev); 2384 err_indr_tbl: 2385 2386 return rc; 2387 } 2388 2389 void ena_com_rss_destroy(struct ena_com_dev *ena_dev) 2390 { 2391 ena_com_indirect_table_destroy(ena_dev); 2392 ena_com_hash_key_destroy(ena_dev); 2393 ena_com_hash_ctrl_destroy(ena_dev); 2394 2395 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2396 } 2397 2398 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev) 2399 { 2400 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2401 2402 host_attr->host_info = 2403 dma_zalloc_coherent(ena_dev->dmadev, SZ_4K, 2404 &host_attr->host_info_dma_addr, GFP_KERNEL); 2405 if (unlikely(!host_attr->host_info)) 2406 return -ENOMEM; 2407 2408 return 0; 2409 } 2410 2411 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, 2412 u32 debug_area_size) 2413 { 2414 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2415 2416 host_attr->debug_area_virt_addr = 2417 dma_zalloc_coherent(ena_dev->dmadev, debug_area_size, 2418 &host_attr->debug_area_dma_addr, GFP_KERNEL); 2419 if (unlikely(!host_attr->debug_area_virt_addr)) { 2420 host_attr->debug_area_size = 0; 2421 return -ENOMEM; 2422 } 2423 2424 host_attr->debug_area_size = debug_area_size; 2425 2426 return 0; 2427 } 2428 2429 void ena_com_delete_host_info(struct ena_com_dev *ena_dev) 2430 { 2431 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2432 2433 if (host_attr->host_info) { 2434 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info, 2435 host_attr->host_info_dma_addr); 2436 host_attr->host_info = NULL; 2437 } 2438 } 2439 2440 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev) 2441 { 2442 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2443 2444 if (host_attr->debug_area_virt_addr) { 2445 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size, 2446 host_attr->debug_area_virt_addr, 2447 host_attr->debug_area_dma_addr); 2448 host_attr->debug_area_virt_addr = NULL; 2449 } 2450 } 2451 2452 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) 2453 { 2454 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2455 struct ena_com_admin_queue *admin_queue; 2456 struct ena_admin_set_feat_cmd cmd; 2457 struct ena_admin_set_feat_resp resp; 2458 2459 int ret; 2460 2461 /* Host attribute config is called before ena_com_get_dev_attr_feat 2462 * so ena_com can't check if the feature is supported. 2463 */ 2464 2465 memset(&cmd, 0x0, sizeof(cmd)); 2466 admin_queue = &ena_dev->admin_queue; 2467 2468 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2469 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG; 2470 2471 ret = ena_com_mem_addr_set(ena_dev, 2472 &cmd.u.host_attr.debug_ba, 2473 host_attr->debug_area_dma_addr); 2474 if (unlikely(ret)) { 2475 pr_err("memory address set failed\n"); 2476 return ret; 2477 } 2478 2479 ret = ena_com_mem_addr_set(ena_dev, 2480 &cmd.u.host_attr.os_info_ba, 2481 host_attr->host_info_dma_addr); 2482 if (unlikely(ret)) { 2483 pr_err("memory address set failed\n"); 2484 return ret; 2485 } 2486 2487 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size; 2488 2489 ret = ena_com_execute_admin_command(admin_queue, 2490 (struct ena_admin_aq_entry *)&cmd, 2491 sizeof(cmd), 2492 (struct ena_admin_acq_entry *)&resp, 2493 sizeof(resp)); 2494 2495 if (unlikely(ret)) 2496 pr_err("Failed to set host attributes: %d\n", ret); 2497 2498 return ret; 2499 } 2500 2501 /* Interrupt moderation */ 2502 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) 2503 { 2504 return ena_com_check_supported_feature_id(ena_dev, 2505 ENA_ADMIN_INTERRUPT_MODERATION); 2506 } 2507 2508 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, 2509 u32 tx_coalesce_usecs) 2510 { 2511 if (!ena_dev->intr_delay_resolution) { 2512 pr_err("Illegal interrupt delay granularity value\n"); 2513 return -EFAULT; 2514 } 2515 2516 ena_dev->intr_moder_tx_interval = tx_coalesce_usecs / 2517 ena_dev->intr_delay_resolution; 2518 2519 return 0; 2520 } 2521 2522 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, 2523 u32 rx_coalesce_usecs) 2524 { 2525 if (!ena_dev->intr_delay_resolution) { 2526 pr_err("Illegal interrupt delay granularity value\n"); 2527 return -EFAULT; 2528 } 2529 2530 /* We use LOWEST entry of moderation table for storing 2531 * nonadaptive interrupt coalescing values 2532 */ 2533 ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval = 2534 rx_coalesce_usecs / ena_dev->intr_delay_resolution; 2535 2536 return 0; 2537 } 2538 2539 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev) 2540 { 2541 if (ena_dev->intr_moder_tbl) 2542 devm_kfree(ena_dev->dmadev, ena_dev->intr_moder_tbl); 2543 ena_dev->intr_moder_tbl = NULL; 2544 } 2545 2546 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) 2547 { 2548 struct ena_admin_get_feat_resp get_resp; 2549 u16 delay_resolution; 2550 int rc; 2551 2552 rc = ena_com_get_feature(ena_dev, &get_resp, 2553 ENA_ADMIN_INTERRUPT_MODERATION); 2554 2555 if (rc) { 2556 if (rc == -EPERM) { 2557 pr_debug("Feature %d isn't supported\n", 2558 ENA_ADMIN_INTERRUPT_MODERATION); 2559 rc = 0; 2560 } else { 2561 pr_err("Failed to get interrupt moderation admin cmd. rc: %d\n", 2562 rc); 2563 } 2564 2565 /* no moderation supported, disable adaptive support */ 2566 ena_com_disable_adaptive_moderation(ena_dev); 2567 return rc; 2568 } 2569 2570 rc = ena_com_init_interrupt_moderation_table(ena_dev); 2571 if (rc) 2572 goto err; 2573 2574 /* if moderation is supported by device we set adaptive moderation */ 2575 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution; 2576 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution); 2577 ena_com_enable_adaptive_moderation(ena_dev); 2578 2579 return 0; 2580 err: 2581 ena_com_destroy_interrupt_moderation(ena_dev); 2582 return rc; 2583 } 2584 2585 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev) 2586 { 2587 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2588 2589 if (!intr_moder_tbl) 2590 return; 2591 2592 intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval = 2593 ENA_INTR_LOWEST_USECS; 2594 intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval = 2595 ENA_INTR_LOWEST_PKTS; 2596 intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval = 2597 ENA_INTR_LOWEST_BYTES; 2598 2599 intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval = 2600 ENA_INTR_LOW_USECS; 2601 intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval = 2602 ENA_INTR_LOW_PKTS; 2603 intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval = 2604 ENA_INTR_LOW_BYTES; 2605 2606 intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval = 2607 ENA_INTR_MID_USECS; 2608 intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval = 2609 ENA_INTR_MID_PKTS; 2610 intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval = 2611 ENA_INTR_MID_BYTES; 2612 2613 intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval = 2614 ENA_INTR_HIGH_USECS; 2615 intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval = 2616 ENA_INTR_HIGH_PKTS; 2617 intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval = 2618 ENA_INTR_HIGH_BYTES; 2619 2620 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval = 2621 ENA_INTR_HIGHEST_USECS; 2622 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval = 2623 ENA_INTR_HIGHEST_PKTS; 2624 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval = 2625 ENA_INTR_HIGHEST_BYTES; 2626 } 2627 2628 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev) 2629 { 2630 return ena_dev->intr_moder_tx_interval; 2631 } 2632 2633 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev) 2634 { 2635 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2636 2637 if (intr_moder_tbl) 2638 return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval; 2639 2640 return 0; 2641 } 2642 2643 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev, 2644 enum ena_intr_moder_level level, 2645 struct ena_intr_moder_entry *entry) 2646 { 2647 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2648 2649 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS) 2650 return; 2651 2652 intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval; 2653 if (ena_dev->intr_delay_resolution) 2654 intr_moder_tbl[level].intr_moder_interval /= 2655 ena_dev->intr_delay_resolution; 2656 intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval; 2657 2658 /* use hardcoded value until ethtool supports bytecount parameter */ 2659 if (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED) 2660 intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval; 2661 } 2662 2663 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev, 2664 enum ena_intr_moder_level level, 2665 struct ena_intr_moder_entry *entry) 2666 { 2667 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2668 2669 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS) 2670 return; 2671 2672 entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval; 2673 if (ena_dev->intr_delay_resolution) 2674 entry->intr_moder_interval *= ena_dev->intr_delay_resolution; 2675 entry->pkts_per_interval = 2676 intr_moder_tbl[level].pkts_per_interval; 2677 entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval; 2678 } 2679