1 /* 2 * Copyright 2015 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include "ena_com.h" 34 35 /*****************************************************************************/ 36 /*****************************************************************************/ 37 38 /* Timeout in micro-sec */ 39 #define ADMIN_CMD_TIMEOUT_US (3000000) 40 41 #define ENA_ASYNC_QUEUE_DEPTH 16 42 #define ENA_ADMIN_QUEUE_DEPTH 32 43 44 #define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \ 45 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \ 46 | (ENA_COMMON_SPEC_VERSION_MINOR)) 47 48 #define ENA_CTRL_MAJOR 0 49 #define ENA_CTRL_MINOR 0 50 #define ENA_CTRL_SUB_MINOR 1 51 52 #define MIN_ENA_CTRL_VER \ 53 (((ENA_CTRL_MAJOR) << \ 54 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \ 55 ((ENA_CTRL_MINOR) << \ 56 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \ 57 (ENA_CTRL_SUB_MINOR)) 58 59 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x))) 60 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32)) 61 62 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF 63 64 #define ENA_REGS_ADMIN_INTR_MASK 1 65 66 #define ENA_POLL_MS 5 67 68 /*****************************************************************************/ 69 /*****************************************************************************/ 70 /*****************************************************************************/ 71 72 enum ena_cmd_status { 73 ENA_CMD_SUBMITTED, 74 ENA_CMD_COMPLETED, 75 /* Abort - canceled by the driver */ 76 ENA_CMD_ABORTED, 77 }; 78 79 struct ena_comp_ctx { 80 struct completion wait_event; 81 struct ena_admin_acq_entry *user_cqe; 82 u32 comp_size; 83 enum ena_cmd_status status; 84 /* status from the device */ 85 u8 comp_status; 86 u8 cmd_opcode; 87 bool occupied; 88 }; 89 90 struct ena_com_stats_ctx { 91 struct ena_admin_aq_get_stats_cmd get_cmd; 92 struct ena_admin_acq_get_stats_resp get_resp; 93 }; 94 95 static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, 96 struct ena_common_mem_addr *ena_addr, 97 dma_addr_t addr) 98 { 99 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { 100 pr_err("dma address has more bits that the device supports\n"); 101 return -EINVAL; 102 } 103 104 ena_addr->mem_addr_low = lower_32_bits(addr); 105 ena_addr->mem_addr_high = (u16)upper_32_bits(addr); 106 107 return 0; 108 } 109 110 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue) 111 { 112 struct ena_com_admin_sq *sq = &queue->sq; 113 u16 size = ADMIN_SQ_SIZE(queue->q_depth); 114 115 sq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &sq->dma_addr, 116 GFP_KERNEL); 117 118 if (!sq->entries) { 119 pr_err("memory allocation failed"); 120 return -ENOMEM; 121 } 122 123 sq->head = 0; 124 sq->tail = 0; 125 sq->phase = 1; 126 127 sq->db_addr = NULL; 128 129 return 0; 130 } 131 132 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue) 133 { 134 struct ena_com_admin_cq *cq = &queue->cq; 135 u16 size = ADMIN_CQ_SIZE(queue->q_depth); 136 137 cq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &cq->dma_addr, 138 GFP_KERNEL); 139 140 if (!cq->entries) { 141 pr_err("memory allocation failed"); 142 return -ENOMEM; 143 } 144 145 cq->head = 0; 146 cq->phase = 1; 147 148 return 0; 149 } 150 151 static int ena_com_admin_init_aenq(struct ena_com_dev *dev, 152 struct ena_aenq_handlers *aenq_handlers) 153 { 154 struct ena_com_aenq *aenq = &dev->aenq; 155 u32 addr_low, addr_high, aenq_caps; 156 u16 size; 157 158 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; 159 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH); 160 aenq->entries = dma_zalloc_coherent(dev->dmadev, size, &aenq->dma_addr, 161 GFP_KERNEL); 162 163 if (!aenq->entries) { 164 pr_err("memory allocation failed"); 165 return -ENOMEM; 166 } 167 168 aenq->head = aenq->q_depth; 169 aenq->phase = 1; 170 171 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); 172 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); 173 174 writel(addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF); 175 writel(addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); 176 177 aenq_caps = 0; 178 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; 179 aenq_caps |= (sizeof(struct ena_admin_aenq_entry) 180 << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) & 181 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK; 182 writel(aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); 183 184 if (unlikely(!aenq_handlers)) { 185 pr_err("aenq handlers pointer is NULL\n"); 186 return -EINVAL; 187 } 188 189 aenq->aenq_handlers = aenq_handlers; 190 191 return 0; 192 } 193 194 static inline void comp_ctxt_release(struct ena_com_admin_queue *queue, 195 struct ena_comp_ctx *comp_ctx) 196 { 197 comp_ctx->occupied = false; 198 atomic_dec(&queue->outstanding_cmds); 199 } 200 201 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue, 202 u16 command_id, bool capture) 203 { 204 if (unlikely(command_id >= queue->q_depth)) { 205 pr_err("command id is larger than the queue size. cmd_id: %u queue size %d\n", 206 command_id, queue->q_depth); 207 return NULL; 208 } 209 210 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) { 211 pr_err("Completion context is occupied\n"); 212 return NULL; 213 } 214 215 if (capture) { 216 atomic_inc(&queue->outstanding_cmds); 217 queue->comp_ctx[command_id].occupied = true; 218 } 219 220 return &queue->comp_ctx[command_id]; 221 } 222 223 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 224 struct ena_admin_aq_entry *cmd, 225 size_t cmd_size_in_bytes, 226 struct ena_admin_acq_entry *comp, 227 size_t comp_size_in_bytes) 228 { 229 struct ena_comp_ctx *comp_ctx; 230 u16 tail_masked, cmd_id; 231 u16 queue_size_mask; 232 u16 cnt; 233 234 queue_size_mask = admin_queue->q_depth - 1; 235 236 tail_masked = admin_queue->sq.tail & queue_size_mask; 237 238 /* In case of queue FULL */ 239 cnt = atomic_read(&admin_queue->outstanding_cmds); 240 if (cnt >= admin_queue->q_depth) { 241 pr_debug("admin queue is full.\n"); 242 admin_queue->stats.out_of_space++; 243 return ERR_PTR(-ENOSPC); 244 } 245 246 cmd_id = admin_queue->curr_cmd_id; 247 248 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase & 249 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 250 251 cmd->aq_common_descriptor.command_id |= cmd_id & 252 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 253 254 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true); 255 if (unlikely(!comp_ctx)) 256 return ERR_PTR(-EINVAL); 257 258 comp_ctx->status = ENA_CMD_SUBMITTED; 259 comp_ctx->comp_size = (u32)comp_size_in_bytes; 260 comp_ctx->user_cqe = comp; 261 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode; 262 263 reinit_completion(&comp_ctx->wait_event); 264 265 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes); 266 267 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) & 268 queue_size_mask; 269 270 admin_queue->sq.tail++; 271 admin_queue->stats.submitted_cmd++; 272 273 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0)) 274 admin_queue->sq.phase = !admin_queue->sq.phase; 275 276 writel(admin_queue->sq.tail, admin_queue->sq.db_addr); 277 278 return comp_ctx; 279 } 280 281 static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue) 282 { 283 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx); 284 struct ena_comp_ctx *comp_ctx; 285 u16 i; 286 287 queue->comp_ctx = devm_kzalloc(queue->q_dmadev, size, GFP_KERNEL); 288 if (unlikely(!queue->comp_ctx)) { 289 pr_err("memory allocation failed"); 290 return -ENOMEM; 291 } 292 293 for (i = 0; i < queue->q_depth; i++) { 294 comp_ctx = get_comp_ctxt(queue, i, false); 295 if (comp_ctx) 296 init_completion(&comp_ctx->wait_event); 297 } 298 299 return 0; 300 } 301 302 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 303 struct ena_admin_aq_entry *cmd, 304 size_t cmd_size_in_bytes, 305 struct ena_admin_acq_entry *comp, 306 size_t comp_size_in_bytes) 307 { 308 unsigned long flags; 309 struct ena_comp_ctx *comp_ctx; 310 311 spin_lock_irqsave(&admin_queue->q_lock, flags); 312 if (unlikely(!admin_queue->running_state)) { 313 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 314 return ERR_PTR(-ENODEV); 315 } 316 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd, 317 cmd_size_in_bytes, 318 comp, 319 comp_size_in_bytes); 320 if (IS_ERR(comp_ctx)) 321 admin_queue->running_state = false; 322 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 323 324 return comp_ctx; 325 } 326 327 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, 328 struct ena_com_create_io_ctx *ctx, 329 struct ena_com_io_sq *io_sq) 330 { 331 size_t size; 332 int dev_node = 0; 333 334 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr)); 335 336 io_sq->desc_entry_size = 337 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 338 sizeof(struct ena_eth_io_tx_desc) : 339 sizeof(struct ena_eth_io_rx_desc); 340 341 size = io_sq->desc_entry_size * io_sq->q_depth; 342 343 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 344 dev_node = dev_to_node(ena_dev->dmadev); 345 set_dev_node(ena_dev->dmadev, ctx->numa_node); 346 io_sq->desc_addr.virt_addr = 347 dma_zalloc_coherent(ena_dev->dmadev, size, 348 &io_sq->desc_addr.phys_addr, 349 GFP_KERNEL); 350 set_dev_node(ena_dev->dmadev, dev_node); 351 if (!io_sq->desc_addr.virt_addr) { 352 io_sq->desc_addr.virt_addr = 353 dma_zalloc_coherent(ena_dev->dmadev, size, 354 &io_sq->desc_addr.phys_addr, 355 GFP_KERNEL); 356 } 357 } else { 358 dev_node = dev_to_node(ena_dev->dmadev); 359 set_dev_node(ena_dev->dmadev, ctx->numa_node); 360 io_sq->desc_addr.virt_addr = 361 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 362 set_dev_node(ena_dev->dmadev, dev_node); 363 if (!io_sq->desc_addr.virt_addr) { 364 io_sq->desc_addr.virt_addr = 365 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 366 } 367 } 368 369 if (!io_sq->desc_addr.virt_addr) { 370 pr_err("memory allocation failed"); 371 return -ENOMEM; 372 } 373 374 io_sq->tail = 0; 375 io_sq->next_to_comp = 0; 376 io_sq->phase = 1; 377 378 return 0; 379 } 380 381 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, 382 struct ena_com_create_io_ctx *ctx, 383 struct ena_com_io_cq *io_cq) 384 { 385 size_t size; 386 int prev_node = 0; 387 388 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr)); 389 390 /* Use the basic completion descriptor for Rx */ 391 io_cq->cdesc_entry_size_in_bytes = 392 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 393 sizeof(struct ena_eth_io_tx_cdesc) : 394 sizeof(struct ena_eth_io_rx_cdesc_base); 395 396 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 397 398 prev_node = dev_to_node(ena_dev->dmadev); 399 set_dev_node(ena_dev->dmadev, ctx->numa_node); 400 io_cq->cdesc_addr.virt_addr = 401 dma_zalloc_coherent(ena_dev->dmadev, size, 402 &io_cq->cdesc_addr.phys_addr, GFP_KERNEL); 403 set_dev_node(ena_dev->dmadev, prev_node); 404 if (!io_cq->cdesc_addr.virt_addr) { 405 io_cq->cdesc_addr.virt_addr = 406 dma_zalloc_coherent(ena_dev->dmadev, size, 407 &io_cq->cdesc_addr.phys_addr, 408 GFP_KERNEL); 409 } 410 411 if (!io_cq->cdesc_addr.virt_addr) { 412 pr_err("memory allocation failed"); 413 return -ENOMEM; 414 } 415 416 io_cq->phase = 1; 417 io_cq->head = 0; 418 419 return 0; 420 } 421 422 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue, 423 struct ena_admin_acq_entry *cqe) 424 { 425 struct ena_comp_ctx *comp_ctx; 426 u16 cmd_id; 427 428 cmd_id = cqe->acq_common_descriptor.command & 429 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 430 431 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false); 432 if (unlikely(!comp_ctx)) { 433 pr_err("comp_ctx is NULL. Changing the admin queue running state\n"); 434 admin_queue->running_state = false; 435 return; 436 } 437 438 comp_ctx->status = ENA_CMD_COMPLETED; 439 comp_ctx->comp_status = cqe->acq_common_descriptor.status; 440 441 if (comp_ctx->user_cqe) 442 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size); 443 444 if (!admin_queue->polling) 445 complete(&comp_ctx->wait_event); 446 } 447 448 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue) 449 { 450 struct ena_admin_acq_entry *cqe = NULL; 451 u16 comp_num = 0; 452 u16 head_masked; 453 u8 phase; 454 455 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1); 456 phase = admin_queue->cq.phase; 457 458 cqe = &admin_queue->cq.entries[head_masked]; 459 460 /* Go over all the completions */ 461 while ((cqe->acq_common_descriptor.flags & 462 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) { 463 /* Do not read the rest of the completion entry before the 464 * phase bit was validated 465 */ 466 rmb(); 467 ena_com_handle_single_admin_completion(admin_queue, cqe); 468 469 head_masked++; 470 comp_num++; 471 if (unlikely(head_masked == admin_queue->q_depth)) { 472 head_masked = 0; 473 phase = !phase; 474 } 475 476 cqe = &admin_queue->cq.entries[head_masked]; 477 } 478 479 admin_queue->cq.head += comp_num; 480 admin_queue->cq.phase = phase; 481 admin_queue->sq.head += comp_num; 482 admin_queue->stats.completed_cmd += comp_num; 483 } 484 485 static int ena_com_comp_status_to_errno(u8 comp_status) 486 { 487 if (unlikely(comp_status != 0)) 488 pr_err("admin command failed[%u]\n", comp_status); 489 490 if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR)) 491 return -EINVAL; 492 493 switch (comp_status) { 494 case ENA_ADMIN_SUCCESS: 495 return 0; 496 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE: 497 return -ENOMEM; 498 case ENA_ADMIN_UNSUPPORTED_OPCODE: 499 return -EOPNOTSUPP; 500 case ENA_ADMIN_BAD_OPCODE: 501 case ENA_ADMIN_MALFORMED_REQUEST: 502 case ENA_ADMIN_ILLEGAL_PARAMETER: 503 case ENA_ADMIN_UNKNOWN_ERROR: 504 return -EINVAL; 505 } 506 507 return 0; 508 } 509 510 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx, 511 struct ena_com_admin_queue *admin_queue) 512 { 513 unsigned long flags, timeout; 514 int ret; 515 516 timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout); 517 518 while (1) { 519 spin_lock_irqsave(&admin_queue->q_lock, flags); 520 ena_com_handle_admin_completion(admin_queue); 521 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 522 523 if (comp_ctx->status != ENA_CMD_SUBMITTED) 524 break; 525 526 if (time_is_before_jiffies(timeout)) { 527 pr_err("Wait for completion (polling) timeout\n"); 528 /* ENA didn't have any completion */ 529 spin_lock_irqsave(&admin_queue->q_lock, flags); 530 admin_queue->stats.no_completion++; 531 admin_queue->running_state = false; 532 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 533 534 ret = -ETIME; 535 goto err; 536 } 537 538 msleep(ENA_POLL_MS); 539 } 540 541 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) { 542 pr_err("Command was aborted\n"); 543 spin_lock_irqsave(&admin_queue->q_lock, flags); 544 admin_queue->stats.aborted_cmd++; 545 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 546 ret = -ENODEV; 547 goto err; 548 } 549 550 WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n", 551 comp_ctx->status); 552 553 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); 554 err: 555 comp_ctxt_release(admin_queue, comp_ctx); 556 return ret; 557 } 558 559 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx, 560 struct ena_com_admin_queue *admin_queue) 561 { 562 unsigned long flags; 563 int ret; 564 565 wait_for_completion_timeout(&comp_ctx->wait_event, 566 usecs_to_jiffies( 567 admin_queue->completion_timeout)); 568 569 /* In case the command wasn't completed find out the root cause. 570 * There might be 2 kinds of errors 571 * 1) No completion (timeout reached) 572 * 2) There is completion but the device didn't get any msi-x interrupt. 573 */ 574 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) { 575 spin_lock_irqsave(&admin_queue->q_lock, flags); 576 ena_com_handle_admin_completion(admin_queue); 577 admin_queue->stats.no_completion++; 578 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 579 580 if (comp_ctx->status == ENA_CMD_COMPLETED) 581 pr_err("The ena device have completion but the driver didn't receive any MSI-X interrupt (cmd %d)\n", 582 comp_ctx->cmd_opcode); 583 else 584 pr_err("The ena device doesn't send any completion for the admin cmd %d status %d\n", 585 comp_ctx->cmd_opcode, comp_ctx->status); 586 587 admin_queue->running_state = false; 588 ret = -ETIME; 589 goto err; 590 } 591 592 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); 593 err: 594 comp_ctxt_release(admin_queue, comp_ctx); 595 return ret; 596 } 597 598 /* This method read the hardware device register through posting writes 599 * and waiting for response 600 * On timeout the function will return ENA_MMIO_READ_TIMEOUT 601 */ 602 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) 603 { 604 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 605 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp = 606 mmio_read->read_resp; 607 u32 mmio_read_reg, ret, i; 608 unsigned long flags; 609 u32 timeout = mmio_read->reg_read_to; 610 611 might_sleep(); 612 613 if (timeout == 0) 614 timeout = ENA_REG_READ_TIMEOUT; 615 616 /* If readless is disabled, perform regular read */ 617 if (!mmio_read->readless_supported) 618 return readl(ena_dev->reg_bar + offset); 619 620 spin_lock_irqsave(&mmio_read->lock, flags); 621 mmio_read->seq_num++; 622 623 read_resp->req_id = mmio_read->seq_num + 0xDEAD; 624 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) & 625 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK; 626 mmio_read_reg |= mmio_read->seq_num & 627 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK; 628 629 /* make sure read_resp->req_id get updated before the hw can write 630 * there 631 */ 632 wmb(); 633 634 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF); 635 636 for (i = 0; i < timeout; i++) { 637 if (read_resp->req_id == mmio_read->seq_num) 638 break; 639 640 udelay(1); 641 } 642 643 if (unlikely(i == timeout)) { 644 pr_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n", 645 mmio_read->seq_num, offset, read_resp->req_id, 646 read_resp->reg_off); 647 ret = ENA_MMIO_READ_TIMEOUT; 648 goto err; 649 } 650 651 if (read_resp->reg_off != offset) { 652 pr_err("Read failure: wrong offset provided"); 653 ret = ENA_MMIO_READ_TIMEOUT; 654 } else { 655 ret = read_resp->reg_val; 656 } 657 err: 658 spin_unlock_irqrestore(&mmio_read->lock, flags); 659 660 return ret; 661 } 662 663 /* There are two types to wait for completion. 664 * Polling mode - wait until the completion is available. 665 * Async mode - wait on wait queue until the completion is ready 666 * (or the timeout expired). 667 * It is expected that the IRQ called ena_com_handle_admin_completion 668 * to mark the completions. 669 */ 670 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx, 671 struct ena_com_admin_queue *admin_queue) 672 { 673 if (admin_queue->polling) 674 return ena_com_wait_and_process_admin_cq_polling(comp_ctx, 675 admin_queue); 676 677 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx, 678 admin_queue); 679 } 680 681 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, 682 struct ena_com_io_sq *io_sq) 683 { 684 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 685 struct ena_admin_aq_destroy_sq_cmd destroy_cmd; 686 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp; 687 u8 direction; 688 int ret; 689 690 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 691 692 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 693 direction = ENA_ADMIN_SQ_DIRECTION_TX; 694 else 695 direction = ENA_ADMIN_SQ_DIRECTION_RX; 696 697 destroy_cmd.sq.sq_identity |= (direction << 698 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & 699 ENA_ADMIN_SQ_SQ_DIRECTION_MASK; 700 701 destroy_cmd.sq.sq_idx = io_sq->idx; 702 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ; 703 704 ret = ena_com_execute_admin_command(admin_queue, 705 (struct ena_admin_aq_entry *)&destroy_cmd, 706 sizeof(destroy_cmd), 707 (struct ena_admin_acq_entry *)&destroy_resp, 708 sizeof(destroy_resp)); 709 710 if (unlikely(ret && (ret != -ENODEV))) 711 pr_err("failed to destroy io sq error: %d\n", ret); 712 713 return ret; 714 } 715 716 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev, 717 struct ena_com_io_sq *io_sq, 718 struct ena_com_io_cq *io_cq) 719 { 720 size_t size; 721 722 if (io_cq->cdesc_addr.virt_addr) { 723 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 724 725 dma_free_coherent(ena_dev->dmadev, size, 726 io_cq->cdesc_addr.virt_addr, 727 io_cq->cdesc_addr.phys_addr); 728 729 io_cq->cdesc_addr.virt_addr = NULL; 730 } 731 732 if (io_sq->desc_addr.virt_addr) { 733 size = io_sq->desc_entry_size * io_sq->q_depth; 734 735 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 736 dma_free_coherent(ena_dev->dmadev, size, 737 io_sq->desc_addr.virt_addr, 738 io_sq->desc_addr.phys_addr); 739 else 740 devm_kfree(ena_dev->dmadev, io_sq->desc_addr.virt_addr); 741 742 io_sq->desc_addr.virt_addr = NULL; 743 } 744 } 745 746 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, 747 u16 exp_state) 748 { 749 u32 val, i; 750 751 /* Convert timeout from resolution of 100ms to ENA_POLL_MS */ 752 timeout = (timeout * 100) / ENA_POLL_MS; 753 754 for (i = 0; i < timeout; i++) { 755 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 756 757 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) { 758 pr_err("Reg read timeout occurred\n"); 759 return -ETIME; 760 } 761 762 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) == 763 exp_state) 764 return 0; 765 766 msleep(ENA_POLL_MS); 767 } 768 769 return -ETIME; 770 } 771 772 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev, 773 enum ena_admin_aq_feature_id feature_id) 774 { 775 u32 feature_mask = 1 << feature_id; 776 777 /* Device attributes is always supported */ 778 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) && 779 !(ena_dev->supported_features & feature_mask)) 780 return false; 781 782 return true; 783 } 784 785 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, 786 struct ena_admin_get_feat_resp *get_resp, 787 enum ena_admin_aq_feature_id feature_id, 788 dma_addr_t control_buf_dma_addr, 789 u32 control_buff_size) 790 { 791 struct ena_com_admin_queue *admin_queue; 792 struct ena_admin_get_feat_cmd get_cmd; 793 int ret; 794 795 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) { 796 pr_debug("Feature %d isn't supported\n", feature_id); 797 return -EOPNOTSUPP; 798 } 799 800 memset(&get_cmd, 0x0, sizeof(get_cmd)); 801 admin_queue = &ena_dev->admin_queue; 802 803 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE; 804 805 if (control_buff_size) 806 get_cmd.aq_common_descriptor.flags = 807 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 808 else 809 get_cmd.aq_common_descriptor.flags = 0; 810 811 ret = ena_com_mem_addr_set(ena_dev, 812 &get_cmd.control_buffer.address, 813 control_buf_dma_addr); 814 if (unlikely(ret)) { 815 pr_err("memory address set failed\n"); 816 return ret; 817 } 818 819 get_cmd.control_buffer.length = control_buff_size; 820 821 get_cmd.feat_common.feature_id = feature_id; 822 823 ret = ena_com_execute_admin_command(admin_queue, 824 (struct ena_admin_aq_entry *) 825 &get_cmd, 826 sizeof(get_cmd), 827 (struct ena_admin_acq_entry *) 828 get_resp, 829 sizeof(*get_resp)); 830 831 if (unlikely(ret)) 832 pr_err("Failed to submit get_feature command %d error: %d\n", 833 feature_id, ret); 834 835 return ret; 836 } 837 838 static int ena_com_get_feature(struct ena_com_dev *ena_dev, 839 struct ena_admin_get_feat_resp *get_resp, 840 enum ena_admin_aq_feature_id feature_id) 841 { 842 return ena_com_get_feature_ex(ena_dev, 843 get_resp, 844 feature_id, 845 0, 846 0); 847 } 848 849 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) 850 { 851 struct ena_rss *rss = &ena_dev->rss; 852 853 rss->hash_key = 854 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), 855 &rss->hash_key_dma_addr, GFP_KERNEL); 856 857 if (unlikely(!rss->hash_key)) 858 return -ENOMEM; 859 860 return 0; 861 } 862 863 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev) 864 { 865 struct ena_rss *rss = &ena_dev->rss; 866 867 if (rss->hash_key) 868 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), 869 rss->hash_key, rss->hash_key_dma_addr); 870 rss->hash_key = NULL; 871 } 872 873 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev) 874 { 875 struct ena_rss *rss = &ena_dev->rss; 876 877 rss->hash_ctrl = 878 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), 879 &rss->hash_ctrl_dma_addr, GFP_KERNEL); 880 881 if (unlikely(!rss->hash_ctrl)) 882 return -ENOMEM; 883 884 return 0; 885 } 886 887 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev) 888 { 889 struct ena_rss *rss = &ena_dev->rss; 890 891 if (rss->hash_ctrl) 892 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), 893 rss->hash_ctrl, rss->hash_ctrl_dma_addr); 894 rss->hash_ctrl = NULL; 895 } 896 897 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, 898 u16 log_size) 899 { 900 struct ena_rss *rss = &ena_dev->rss; 901 struct ena_admin_get_feat_resp get_resp; 902 size_t tbl_size; 903 int ret; 904 905 ret = ena_com_get_feature(ena_dev, &get_resp, 906 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); 907 if (unlikely(ret)) 908 return ret; 909 910 if ((get_resp.u.ind_table.min_size > log_size) || 911 (get_resp.u.ind_table.max_size < log_size)) { 912 pr_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n", 913 1 << log_size, 1 << get_resp.u.ind_table.min_size, 914 1 << get_resp.u.ind_table.max_size); 915 return -EINVAL; 916 } 917 918 tbl_size = (1ULL << log_size) * 919 sizeof(struct ena_admin_rss_ind_table_entry); 920 921 rss->rss_ind_tbl = 922 dma_zalloc_coherent(ena_dev->dmadev, tbl_size, 923 &rss->rss_ind_tbl_dma_addr, GFP_KERNEL); 924 if (unlikely(!rss->rss_ind_tbl)) 925 goto mem_err1; 926 927 tbl_size = (1ULL << log_size) * sizeof(u16); 928 rss->host_rss_ind_tbl = 929 devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL); 930 if (unlikely(!rss->host_rss_ind_tbl)) 931 goto mem_err2; 932 933 rss->tbl_log_size = log_size; 934 935 return 0; 936 937 mem_err2: 938 tbl_size = (1ULL << log_size) * 939 sizeof(struct ena_admin_rss_ind_table_entry); 940 941 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, 942 rss->rss_ind_tbl_dma_addr); 943 rss->rss_ind_tbl = NULL; 944 mem_err1: 945 rss->tbl_log_size = 0; 946 return -ENOMEM; 947 } 948 949 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev) 950 { 951 struct ena_rss *rss = &ena_dev->rss; 952 size_t tbl_size = (1ULL << rss->tbl_log_size) * 953 sizeof(struct ena_admin_rss_ind_table_entry); 954 955 if (rss->rss_ind_tbl) 956 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, 957 rss->rss_ind_tbl_dma_addr); 958 rss->rss_ind_tbl = NULL; 959 960 if (rss->host_rss_ind_tbl) 961 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl); 962 rss->host_rss_ind_tbl = NULL; 963 } 964 965 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, 966 struct ena_com_io_sq *io_sq, u16 cq_idx) 967 { 968 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 969 struct ena_admin_aq_create_sq_cmd create_cmd; 970 struct ena_admin_acq_create_sq_resp_desc cmd_completion; 971 u8 direction; 972 int ret; 973 974 memset(&create_cmd, 0x0, sizeof(create_cmd)); 975 976 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ; 977 978 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 979 direction = ENA_ADMIN_SQ_DIRECTION_TX; 980 else 981 direction = ENA_ADMIN_SQ_DIRECTION_RX; 982 983 create_cmd.sq_identity |= (direction << 984 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & 985 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; 986 987 create_cmd.sq_caps_2 |= io_sq->mem_queue_type & 988 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 989 990 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC << 991 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & 992 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; 993 994 create_cmd.sq_caps_3 |= 995 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 996 997 create_cmd.cq_idx = cq_idx; 998 create_cmd.sq_depth = io_sq->q_depth; 999 1000 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 1001 ret = ena_com_mem_addr_set(ena_dev, 1002 &create_cmd.sq_ba, 1003 io_sq->desc_addr.phys_addr); 1004 if (unlikely(ret)) { 1005 pr_err("memory address set failed\n"); 1006 return ret; 1007 } 1008 } 1009 1010 ret = ena_com_execute_admin_command(admin_queue, 1011 (struct ena_admin_aq_entry *)&create_cmd, 1012 sizeof(create_cmd), 1013 (struct ena_admin_acq_entry *)&cmd_completion, 1014 sizeof(cmd_completion)); 1015 if (unlikely(ret)) { 1016 pr_err("Failed to create IO SQ. error: %d\n", ret); 1017 return ret; 1018 } 1019 1020 io_sq->idx = cmd_completion.sq_idx; 1021 1022 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1023 (uintptr_t)cmd_completion.sq_doorbell_offset); 1024 1025 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1026 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar 1027 + cmd_completion.llq_headers_offset); 1028 1029 io_sq->desc_addr.pbuf_dev_addr = 1030 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar + 1031 cmd_completion.llq_descriptors_offset); 1032 } 1033 1034 pr_debug("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth); 1035 1036 return ret; 1037 } 1038 1039 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev) 1040 { 1041 struct ena_rss *rss = &ena_dev->rss; 1042 struct ena_com_io_sq *io_sq; 1043 u16 qid; 1044 int i; 1045 1046 for (i = 0; i < 1 << rss->tbl_log_size; i++) { 1047 qid = rss->host_rss_ind_tbl[i]; 1048 if (qid >= ENA_TOTAL_NUM_QUEUES) 1049 return -EINVAL; 1050 1051 io_sq = &ena_dev->io_sq_queues[qid]; 1052 1053 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX) 1054 return -EINVAL; 1055 1056 rss->rss_ind_tbl[i].cq_idx = io_sq->idx; 1057 } 1058 1059 return 0; 1060 } 1061 1062 static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev) 1063 { 1064 u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 }; 1065 struct ena_rss *rss = &ena_dev->rss; 1066 u8 idx; 1067 u16 i; 1068 1069 for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++) 1070 dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i; 1071 1072 for (i = 0; i < 1 << rss->tbl_log_size; i++) { 1073 if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES) 1074 return -EINVAL; 1075 idx = (u8)rss->rss_ind_tbl[i].cq_idx; 1076 1077 if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES) 1078 return -EINVAL; 1079 1080 rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx]; 1081 } 1082 1083 return 0; 1084 } 1085 1086 static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev) 1087 { 1088 size_t size; 1089 1090 size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS; 1091 1092 ena_dev->intr_moder_tbl = 1093 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 1094 if (!ena_dev->intr_moder_tbl) 1095 return -ENOMEM; 1096 1097 ena_com_config_default_interrupt_moderation_table(ena_dev); 1098 1099 return 0; 1100 } 1101 1102 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, 1103 u16 intr_delay_resolution) 1104 { 1105 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 1106 unsigned int i; 1107 1108 if (!intr_delay_resolution) { 1109 pr_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); 1110 intr_delay_resolution = 1; 1111 } 1112 ena_dev->intr_delay_resolution = intr_delay_resolution; 1113 1114 /* update Rx */ 1115 for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++) 1116 intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution; 1117 1118 /* update Tx */ 1119 ena_dev->intr_moder_tx_interval /= intr_delay_resolution; 1120 } 1121 1122 /*****************************************************************************/ 1123 /******************************* API ******************************/ 1124 /*****************************************************************************/ 1125 1126 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, 1127 struct ena_admin_aq_entry *cmd, 1128 size_t cmd_size, 1129 struct ena_admin_acq_entry *comp, 1130 size_t comp_size) 1131 { 1132 struct ena_comp_ctx *comp_ctx; 1133 int ret; 1134 1135 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size, 1136 comp, comp_size); 1137 if (IS_ERR(comp_ctx)) { 1138 if (comp_ctx == ERR_PTR(-ENODEV)) 1139 pr_debug("Failed to submit command [%ld]\n", 1140 PTR_ERR(comp_ctx)); 1141 else 1142 pr_err("Failed to submit command [%ld]\n", 1143 PTR_ERR(comp_ctx)); 1144 1145 return PTR_ERR(comp_ctx); 1146 } 1147 1148 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue); 1149 if (unlikely(ret)) { 1150 if (admin_queue->running_state) 1151 pr_err("Failed to process command. ret = %d\n", ret); 1152 else 1153 pr_debug("Failed to process command. ret = %d\n", ret); 1154 } 1155 return ret; 1156 } 1157 1158 int ena_com_create_io_cq(struct ena_com_dev *ena_dev, 1159 struct ena_com_io_cq *io_cq) 1160 { 1161 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1162 struct ena_admin_aq_create_cq_cmd create_cmd; 1163 struct ena_admin_acq_create_cq_resp_desc cmd_completion; 1164 int ret; 1165 1166 memset(&create_cmd, 0x0, sizeof(create_cmd)); 1167 1168 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ; 1169 1170 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) & 1171 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1172 create_cmd.cq_caps_1 |= 1173 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK; 1174 1175 create_cmd.msix_vector = io_cq->msix_vector; 1176 create_cmd.cq_depth = io_cq->q_depth; 1177 1178 ret = ena_com_mem_addr_set(ena_dev, 1179 &create_cmd.cq_ba, 1180 io_cq->cdesc_addr.phys_addr); 1181 if (unlikely(ret)) { 1182 pr_err("memory address set failed\n"); 1183 return ret; 1184 } 1185 1186 ret = ena_com_execute_admin_command(admin_queue, 1187 (struct ena_admin_aq_entry *)&create_cmd, 1188 sizeof(create_cmd), 1189 (struct ena_admin_acq_entry *)&cmd_completion, 1190 sizeof(cmd_completion)); 1191 if (unlikely(ret)) { 1192 pr_err("Failed to create IO CQ. error: %d\n", ret); 1193 return ret; 1194 } 1195 1196 io_cq->idx = cmd_completion.cq_idx; 1197 1198 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1199 cmd_completion.cq_interrupt_unmask_register_offset); 1200 1201 if (cmd_completion.cq_head_db_register_offset) 1202 io_cq->cq_head_db_reg = 1203 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1204 cmd_completion.cq_head_db_register_offset); 1205 1206 if (cmd_completion.numa_node_register_offset) 1207 io_cq->numa_node_cfg_reg = 1208 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1209 cmd_completion.numa_node_register_offset); 1210 1211 pr_debug("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth); 1212 1213 return ret; 1214 } 1215 1216 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, 1217 struct ena_com_io_sq **io_sq, 1218 struct ena_com_io_cq **io_cq) 1219 { 1220 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1221 pr_err("Invalid queue number %d but the max is %d\n", qid, 1222 ENA_TOTAL_NUM_QUEUES); 1223 return -EINVAL; 1224 } 1225 1226 *io_sq = &ena_dev->io_sq_queues[qid]; 1227 *io_cq = &ena_dev->io_cq_queues[qid]; 1228 1229 return 0; 1230 } 1231 1232 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev) 1233 { 1234 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1235 struct ena_comp_ctx *comp_ctx; 1236 u16 i; 1237 1238 if (!admin_queue->comp_ctx) 1239 return; 1240 1241 for (i = 0; i < admin_queue->q_depth; i++) { 1242 comp_ctx = get_comp_ctxt(admin_queue, i, false); 1243 if (unlikely(!comp_ctx)) 1244 break; 1245 1246 comp_ctx->status = ENA_CMD_ABORTED; 1247 1248 complete(&comp_ctx->wait_event); 1249 } 1250 } 1251 1252 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev) 1253 { 1254 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1255 unsigned long flags; 1256 1257 spin_lock_irqsave(&admin_queue->q_lock, flags); 1258 while (atomic_read(&admin_queue->outstanding_cmds) != 0) { 1259 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1260 msleep(ENA_POLL_MS); 1261 spin_lock_irqsave(&admin_queue->q_lock, flags); 1262 } 1263 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1264 } 1265 1266 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, 1267 struct ena_com_io_cq *io_cq) 1268 { 1269 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1270 struct ena_admin_aq_destroy_cq_cmd destroy_cmd; 1271 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp; 1272 int ret; 1273 1274 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 1275 1276 destroy_cmd.cq_idx = io_cq->idx; 1277 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ; 1278 1279 ret = ena_com_execute_admin_command(admin_queue, 1280 (struct ena_admin_aq_entry *)&destroy_cmd, 1281 sizeof(destroy_cmd), 1282 (struct ena_admin_acq_entry *)&destroy_resp, 1283 sizeof(destroy_resp)); 1284 1285 if (unlikely(ret && (ret != -ENODEV))) 1286 pr_err("Failed to destroy IO CQ. error: %d\n", ret); 1287 1288 return ret; 1289 } 1290 1291 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev) 1292 { 1293 return ena_dev->admin_queue.running_state; 1294 } 1295 1296 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state) 1297 { 1298 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1299 unsigned long flags; 1300 1301 spin_lock_irqsave(&admin_queue->q_lock, flags); 1302 ena_dev->admin_queue.running_state = state; 1303 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1304 } 1305 1306 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev) 1307 { 1308 u16 depth = ena_dev->aenq.q_depth; 1309 1310 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); 1311 1312 /* Init head_db to mark that all entries in the queue 1313 * are initially available 1314 */ 1315 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 1316 } 1317 1318 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) 1319 { 1320 struct ena_com_admin_queue *admin_queue; 1321 struct ena_admin_set_feat_cmd cmd; 1322 struct ena_admin_set_feat_resp resp; 1323 struct ena_admin_get_feat_resp get_resp; 1324 int ret; 1325 1326 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG); 1327 if (ret) { 1328 pr_info("Can't get aenq configuration\n"); 1329 return ret; 1330 } 1331 1332 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) { 1333 pr_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n", 1334 get_resp.u.aenq.supported_groups, groups_flag); 1335 return -EOPNOTSUPP; 1336 } 1337 1338 memset(&cmd, 0x0, sizeof(cmd)); 1339 admin_queue = &ena_dev->admin_queue; 1340 1341 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1342 cmd.aq_common_descriptor.flags = 0; 1343 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG; 1344 cmd.u.aenq.enabled_groups = groups_flag; 1345 1346 ret = ena_com_execute_admin_command(admin_queue, 1347 (struct ena_admin_aq_entry *)&cmd, 1348 sizeof(cmd), 1349 (struct ena_admin_acq_entry *)&resp, 1350 sizeof(resp)); 1351 1352 if (unlikely(ret)) 1353 pr_err("Failed to config AENQ ret: %d\n", ret); 1354 1355 return ret; 1356 } 1357 1358 int ena_com_get_dma_width(struct ena_com_dev *ena_dev) 1359 { 1360 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 1361 int width; 1362 1363 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { 1364 pr_err("Reg read timeout occurred\n"); 1365 return -ETIME; 1366 } 1367 1368 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> 1369 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT; 1370 1371 pr_debug("ENA dma width: %d\n", width); 1372 1373 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { 1374 pr_err("DMA width illegal value: %d\n", width); 1375 return -EINVAL; 1376 } 1377 1378 ena_dev->dma_addr_bits = width; 1379 1380 return width; 1381 } 1382 1383 int ena_com_validate_version(struct ena_com_dev *ena_dev) 1384 { 1385 u32 ver; 1386 u32 ctrl_ver; 1387 u32 ctrl_ver_masked; 1388 1389 /* Make sure the ENA version and the controller version are at least 1390 * as the driver expects 1391 */ 1392 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF); 1393 ctrl_ver = ena_com_reg_bar_read32(ena_dev, 1394 ENA_REGS_CONTROLLER_VERSION_OFF); 1395 1396 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || 1397 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) { 1398 pr_err("Reg read timeout occurred\n"); 1399 return -ETIME; 1400 } 1401 1402 pr_info("ena device version: %d.%d\n", 1403 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> 1404 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT, 1405 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK); 1406 1407 if (ver < MIN_ENA_VER) { 1408 pr_err("ENA version is lower than the minimal version the driver supports\n"); 1409 return -1; 1410 } 1411 1412 pr_info("ena controller version: %d.%d.%d implementation version %d\n", 1413 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >> 1414 ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT, 1415 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >> 1416 ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT, 1417 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK), 1418 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >> 1419 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT); 1420 1421 ctrl_ver_masked = 1422 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) | 1423 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) | 1424 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK); 1425 1426 /* Validate the ctrl version without the implementation ID */ 1427 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) { 1428 pr_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n"); 1429 return -1; 1430 } 1431 1432 return 0; 1433 } 1434 1435 void ena_com_admin_destroy(struct ena_com_dev *ena_dev) 1436 { 1437 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1438 struct ena_com_admin_cq *cq = &admin_queue->cq; 1439 struct ena_com_admin_sq *sq = &admin_queue->sq; 1440 struct ena_com_aenq *aenq = &ena_dev->aenq; 1441 u16 size; 1442 1443 if (admin_queue->comp_ctx) 1444 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx); 1445 admin_queue->comp_ctx = NULL; 1446 size = ADMIN_SQ_SIZE(admin_queue->q_depth); 1447 if (sq->entries) 1448 dma_free_coherent(ena_dev->dmadev, size, sq->entries, 1449 sq->dma_addr); 1450 sq->entries = NULL; 1451 1452 size = ADMIN_CQ_SIZE(admin_queue->q_depth); 1453 if (cq->entries) 1454 dma_free_coherent(ena_dev->dmadev, size, cq->entries, 1455 cq->dma_addr); 1456 cq->entries = NULL; 1457 1458 size = ADMIN_AENQ_SIZE(aenq->q_depth); 1459 if (ena_dev->aenq.entries) 1460 dma_free_coherent(ena_dev->dmadev, size, aenq->entries, 1461 aenq->dma_addr); 1462 aenq->entries = NULL; 1463 } 1464 1465 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling) 1466 { 1467 u32 mask_value = 0; 1468 1469 if (polling) 1470 mask_value = ENA_REGS_ADMIN_INTR_MASK; 1471 1472 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF); 1473 ena_dev->admin_queue.polling = polling; 1474 } 1475 1476 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev) 1477 { 1478 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1479 1480 spin_lock_init(&mmio_read->lock); 1481 mmio_read->read_resp = 1482 dma_zalloc_coherent(ena_dev->dmadev, 1483 sizeof(*mmio_read->read_resp), 1484 &mmio_read->read_resp_dma_addr, GFP_KERNEL); 1485 if (unlikely(!mmio_read->read_resp)) 1486 return -ENOMEM; 1487 1488 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 1489 1490 mmio_read->read_resp->req_id = 0x0; 1491 mmio_read->seq_num = 0x0; 1492 mmio_read->readless_supported = true; 1493 1494 return 0; 1495 } 1496 1497 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported) 1498 { 1499 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1500 1501 mmio_read->readless_supported = readless_supported; 1502 } 1503 1504 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev) 1505 { 1506 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1507 1508 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1509 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1510 1511 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), 1512 mmio_read->read_resp, mmio_read->read_resp_dma_addr); 1513 1514 mmio_read->read_resp = NULL; 1515 } 1516 1517 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev) 1518 { 1519 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1520 u32 addr_low, addr_high; 1521 1522 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr); 1523 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr); 1524 1525 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1526 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1527 } 1528 1529 int ena_com_admin_init(struct ena_com_dev *ena_dev, 1530 struct ena_aenq_handlers *aenq_handlers, 1531 bool init_spinlock) 1532 { 1533 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1534 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high; 1535 int ret; 1536 1537 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 1538 1539 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) { 1540 pr_err("Reg read timeout occurred\n"); 1541 return -ETIME; 1542 } 1543 1544 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) { 1545 pr_err("Device isn't ready, abort com init\n"); 1546 return -ENODEV; 1547 } 1548 1549 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH; 1550 1551 admin_queue->q_dmadev = ena_dev->dmadev; 1552 admin_queue->polling = false; 1553 admin_queue->curr_cmd_id = 0; 1554 1555 atomic_set(&admin_queue->outstanding_cmds, 0); 1556 1557 if (init_spinlock) 1558 spin_lock_init(&admin_queue->q_lock); 1559 1560 ret = ena_com_init_comp_ctxt(admin_queue); 1561 if (ret) 1562 goto error; 1563 1564 ret = ena_com_admin_init_sq(admin_queue); 1565 if (ret) 1566 goto error; 1567 1568 ret = ena_com_admin_init_cq(admin_queue); 1569 if (ret) 1570 goto error; 1571 1572 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1573 ENA_REGS_AQ_DB_OFF); 1574 1575 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr); 1576 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr); 1577 1578 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF); 1579 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF); 1580 1581 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr); 1582 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr); 1583 1584 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF); 1585 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF); 1586 1587 aq_caps = 0; 1588 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK; 1589 aq_caps |= (sizeof(struct ena_admin_aq_entry) << 1590 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) & 1591 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK; 1592 1593 acq_caps = 0; 1594 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK; 1595 acq_caps |= (sizeof(struct ena_admin_acq_entry) << 1596 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) & 1597 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK; 1598 1599 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF); 1600 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF); 1601 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers); 1602 if (ret) 1603 goto error; 1604 1605 admin_queue->running_state = true; 1606 1607 return 0; 1608 error: 1609 ena_com_admin_destroy(ena_dev); 1610 1611 return ret; 1612 } 1613 1614 int ena_com_create_io_queue(struct ena_com_dev *ena_dev, 1615 struct ena_com_create_io_ctx *ctx) 1616 { 1617 struct ena_com_io_sq *io_sq; 1618 struct ena_com_io_cq *io_cq; 1619 int ret; 1620 1621 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) { 1622 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", 1623 ctx->qid, ENA_TOTAL_NUM_QUEUES); 1624 return -EINVAL; 1625 } 1626 1627 io_sq = &ena_dev->io_sq_queues[ctx->qid]; 1628 io_cq = &ena_dev->io_cq_queues[ctx->qid]; 1629 1630 memset(io_sq, 0x0, sizeof(*io_sq)); 1631 memset(io_cq, 0x0, sizeof(*io_cq)); 1632 1633 /* Init CQ */ 1634 io_cq->q_depth = ctx->queue_size; 1635 io_cq->direction = ctx->direction; 1636 io_cq->qid = ctx->qid; 1637 1638 io_cq->msix_vector = ctx->msix_vector; 1639 1640 io_sq->q_depth = ctx->queue_size; 1641 io_sq->direction = ctx->direction; 1642 io_sq->qid = ctx->qid; 1643 1644 io_sq->mem_queue_type = ctx->mem_queue_type; 1645 1646 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 1647 /* header length is limited to 8 bits */ 1648 io_sq->tx_max_header_size = 1649 min_t(u32, ena_dev->tx_max_header_size, SZ_256); 1650 1651 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq); 1652 if (ret) 1653 goto error; 1654 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq); 1655 if (ret) 1656 goto error; 1657 1658 ret = ena_com_create_io_cq(ena_dev, io_cq); 1659 if (ret) 1660 goto error; 1661 1662 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx); 1663 if (ret) 1664 goto destroy_io_cq; 1665 1666 return 0; 1667 1668 destroy_io_cq: 1669 ena_com_destroy_io_cq(ena_dev, io_cq); 1670 error: 1671 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1672 return ret; 1673 } 1674 1675 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) 1676 { 1677 struct ena_com_io_sq *io_sq; 1678 struct ena_com_io_cq *io_cq; 1679 1680 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1681 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", qid, 1682 ENA_TOTAL_NUM_QUEUES); 1683 return; 1684 } 1685 1686 io_sq = &ena_dev->io_sq_queues[qid]; 1687 io_cq = &ena_dev->io_cq_queues[qid]; 1688 1689 ena_com_destroy_io_sq(ena_dev, io_sq); 1690 ena_com_destroy_io_cq(ena_dev, io_cq); 1691 1692 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1693 } 1694 1695 int ena_com_get_link_params(struct ena_com_dev *ena_dev, 1696 struct ena_admin_get_feat_resp *resp) 1697 { 1698 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG); 1699 } 1700 1701 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, 1702 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1703 { 1704 struct ena_admin_get_feat_resp get_resp; 1705 int rc; 1706 1707 rc = ena_com_get_feature(ena_dev, &get_resp, 1708 ENA_ADMIN_DEVICE_ATTRIBUTES); 1709 if (rc) 1710 return rc; 1711 1712 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr, 1713 sizeof(get_resp.u.dev_attr)); 1714 ena_dev->supported_features = get_resp.u.dev_attr.supported_features; 1715 1716 rc = ena_com_get_feature(ena_dev, &get_resp, 1717 ENA_ADMIN_MAX_QUEUES_NUM); 1718 if (rc) 1719 return rc; 1720 1721 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue, 1722 sizeof(get_resp.u.max_queue)); 1723 ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size; 1724 1725 rc = ena_com_get_feature(ena_dev, &get_resp, 1726 ENA_ADMIN_AENQ_CONFIG); 1727 if (rc) 1728 return rc; 1729 1730 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq, 1731 sizeof(get_resp.u.aenq)); 1732 1733 rc = ena_com_get_feature(ena_dev, &get_resp, 1734 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG); 1735 if (rc) 1736 return rc; 1737 1738 memcpy(&get_feat_ctx->offload, &get_resp.u.offload, 1739 sizeof(get_resp.u.offload)); 1740 1741 /* Driver hints isn't mandatory admin command. So in case the 1742 * command isn't supported set driver hints to 0 1743 */ 1744 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS); 1745 1746 if (!rc) 1747 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints, 1748 sizeof(get_resp.u.hw_hints)); 1749 else if (rc == -EOPNOTSUPP) 1750 memset(&get_feat_ctx->hw_hints, 0x0, 1751 sizeof(get_feat_ctx->hw_hints)); 1752 else 1753 return rc; 1754 1755 return 0; 1756 } 1757 1758 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev) 1759 { 1760 ena_com_handle_admin_completion(&ena_dev->admin_queue); 1761 } 1762 1763 /* ena_handle_specific_aenq_event: 1764 * return the handler that is relevant to the specific event group 1765 */ 1766 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev, 1767 u16 group) 1768 { 1769 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers; 1770 1771 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group]) 1772 return aenq_handlers->handlers[group]; 1773 1774 return aenq_handlers->unimplemented_handler; 1775 } 1776 1777 /* ena_aenq_intr_handler: 1778 * handles the aenq incoming events. 1779 * pop events from the queue and apply the specific handler 1780 */ 1781 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) 1782 { 1783 struct ena_admin_aenq_entry *aenq_e; 1784 struct ena_admin_aenq_common_desc *aenq_common; 1785 struct ena_com_aenq *aenq = &dev->aenq; 1786 ena_aenq_handler handler_cb; 1787 u16 masked_head, processed = 0; 1788 u8 phase; 1789 1790 masked_head = aenq->head & (aenq->q_depth - 1); 1791 phase = aenq->phase; 1792 aenq_e = &aenq->entries[masked_head]; /* Get first entry */ 1793 aenq_common = &aenq_e->aenq_common_desc; 1794 1795 /* Go over all the events */ 1796 while ((aenq_common->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == 1797 phase) { 1798 pr_debug("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n", 1799 aenq_common->group, aenq_common->syndrom, 1800 (u64)aenq_common->timestamp_low + 1801 ((u64)aenq_common->timestamp_high << 32)); 1802 1803 /* Handle specific event*/ 1804 handler_cb = ena_com_get_specific_aenq_cb(dev, 1805 aenq_common->group); 1806 handler_cb(data, aenq_e); /* call the actual event handler*/ 1807 1808 /* Get next event entry */ 1809 masked_head++; 1810 processed++; 1811 1812 if (unlikely(masked_head == aenq->q_depth)) { 1813 masked_head = 0; 1814 phase = !phase; 1815 } 1816 aenq_e = &aenq->entries[masked_head]; 1817 aenq_common = &aenq_e->aenq_common_desc; 1818 } 1819 1820 aenq->head += processed; 1821 aenq->phase = phase; 1822 1823 /* Don't update aenq doorbell if there weren't any processed events */ 1824 if (!processed) 1825 return; 1826 1827 /* write the aenq doorbell after all AENQ descriptors were read */ 1828 mb(); 1829 writel((u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 1830 } 1831 1832 int ena_com_dev_reset(struct ena_com_dev *ena_dev, 1833 enum ena_regs_reset_reason_types reset_reason) 1834 { 1835 u32 stat, timeout, cap, reset_val; 1836 int rc; 1837 1838 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 1839 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 1840 1841 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || 1842 (cap == ENA_MMIO_READ_TIMEOUT))) { 1843 pr_err("Reg read32 timeout occurred\n"); 1844 return -ETIME; 1845 } 1846 1847 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) { 1848 pr_err("Device isn't ready, can't reset device\n"); 1849 return -EINVAL; 1850 } 1851 1852 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >> 1853 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT; 1854 if (timeout == 0) { 1855 pr_err("Invalid timeout value\n"); 1856 return -EINVAL; 1857 } 1858 1859 /* start reset */ 1860 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; 1861 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) & 1862 ENA_REGS_DEV_CTL_RESET_REASON_MASK; 1863 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 1864 1865 /* Write again the MMIO read request address */ 1866 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 1867 1868 rc = wait_for_reset_state(ena_dev, timeout, 1869 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK); 1870 if (rc != 0) { 1871 pr_err("Reset indication didn't turn on\n"); 1872 return rc; 1873 } 1874 1875 /* reset done */ 1876 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 1877 rc = wait_for_reset_state(ena_dev, timeout, 0); 1878 if (rc != 0) { 1879 pr_err("Reset indication didn't turn off\n"); 1880 return rc; 1881 } 1882 1883 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >> 1884 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT; 1885 if (timeout) 1886 /* the resolution of timeout reg is 100ms */ 1887 ena_dev->admin_queue.completion_timeout = timeout * 100000; 1888 else 1889 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US; 1890 1891 return 0; 1892 } 1893 1894 static int ena_get_dev_stats(struct ena_com_dev *ena_dev, 1895 struct ena_com_stats_ctx *ctx, 1896 enum ena_admin_get_stats_type type) 1897 { 1898 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd; 1899 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp; 1900 struct ena_com_admin_queue *admin_queue; 1901 int ret; 1902 1903 admin_queue = &ena_dev->admin_queue; 1904 1905 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS; 1906 get_cmd->aq_common_descriptor.flags = 0; 1907 get_cmd->type = type; 1908 1909 ret = ena_com_execute_admin_command(admin_queue, 1910 (struct ena_admin_aq_entry *)get_cmd, 1911 sizeof(*get_cmd), 1912 (struct ena_admin_acq_entry *)get_resp, 1913 sizeof(*get_resp)); 1914 1915 if (unlikely(ret)) 1916 pr_err("Failed to get stats. error: %d\n", ret); 1917 1918 return ret; 1919 } 1920 1921 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, 1922 struct ena_admin_basic_stats *stats) 1923 { 1924 struct ena_com_stats_ctx ctx; 1925 int ret; 1926 1927 memset(&ctx, 0x0, sizeof(ctx)); 1928 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC); 1929 if (likely(ret == 0)) 1930 memcpy(stats, &ctx.get_resp.basic_stats, 1931 sizeof(ctx.get_resp.basic_stats)); 1932 1933 return ret; 1934 } 1935 1936 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) 1937 { 1938 struct ena_com_admin_queue *admin_queue; 1939 struct ena_admin_set_feat_cmd cmd; 1940 struct ena_admin_set_feat_resp resp; 1941 int ret; 1942 1943 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) { 1944 pr_debug("Feature %d isn't supported\n", ENA_ADMIN_MTU); 1945 return -EOPNOTSUPP; 1946 } 1947 1948 memset(&cmd, 0x0, sizeof(cmd)); 1949 admin_queue = &ena_dev->admin_queue; 1950 1951 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1952 cmd.aq_common_descriptor.flags = 0; 1953 cmd.feat_common.feature_id = ENA_ADMIN_MTU; 1954 cmd.u.mtu.mtu = mtu; 1955 1956 ret = ena_com_execute_admin_command(admin_queue, 1957 (struct ena_admin_aq_entry *)&cmd, 1958 sizeof(cmd), 1959 (struct ena_admin_acq_entry *)&resp, 1960 sizeof(resp)); 1961 1962 if (unlikely(ret)) 1963 pr_err("Failed to set mtu %d. error: %d\n", mtu, ret); 1964 1965 return ret; 1966 } 1967 1968 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, 1969 struct ena_admin_feature_offload_desc *offload) 1970 { 1971 int ret; 1972 struct ena_admin_get_feat_resp resp; 1973 1974 ret = ena_com_get_feature(ena_dev, &resp, 1975 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG); 1976 if (unlikely(ret)) { 1977 pr_err("Failed to get offload capabilities %d\n", ret); 1978 return ret; 1979 } 1980 1981 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload)); 1982 1983 return 0; 1984 } 1985 1986 int ena_com_set_hash_function(struct ena_com_dev *ena_dev) 1987 { 1988 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1989 struct ena_rss *rss = &ena_dev->rss; 1990 struct ena_admin_set_feat_cmd cmd; 1991 struct ena_admin_set_feat_resp resp; 1992 struct ena_admin_get_feat_resp get_resp; 1993 int ret; 1994 1995 if (!ena_com_check_supported_feature_id(ena_dev, 1996 ENA_ADMIN_RSS_HASH_FUNCTION)) { 1997 pr_debug("Feature %d isn't supported\n", 1998 ENA_ADMIN_RSS_HASH_FUNCTION); 1999 return -EOPNOTSUPP; 2000 } 2001 2002 /* Validate hash function is supported */ 2003 ret = ena_com_get_feature(ena_dev, &get_resp, 2004 ENA_ADMIN_RSS_HASH_FUNCTION); 2005 if (unlikely(ret)) 2006 return ret; 2007 2008 if (get_resp.u.flow_hash_func.supported_func & (1 << rss->hash_func)) { 2009 pr_err("Func hash %d isn't supported by device, abort\n", 2010 rss->hash_func); 2011 return -EOPNOTSUPP; 2012 } 2013 2014 memset(&cmd, 0x0, sizeof(cmd)); 2015 2016 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2017 cmd.aq_common_descriptor.flags = 2018 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2019 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION; 2020 cmd.u.flow_hash_func.init_val = rss->hash_init_val; 2021 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func; 2022 2023 ret = ena_com_mem_addr_set(ena_dev, 2024 &cmd.control_buffer.address, 2025 rss->hash_key_dma_addr); 2026 if (unlikely(ret)) { 2027 pr_err("memory address set failed\n"); 2028 return ret; 2029 } 2030 2031 cmd.control_buffer.length = sizeof(*rss->hash_key); 2032 2033 ret = ena_com_execute_admin_command(admin_queue, 2034 (struct ena_admin_aq_entry *)&cmd, 2035 sizeof(cmd), 2036 (struct ena_admin_acq_entry *)&resp, 2037 sizeof(resp)); 2038 if (unlikely(ret)) { 2039 pr_err("Failed to set hash function %d. error: %d\n", 2040 rss->hash_func, ret); 2041 return -EINVAL; 2042 } 2043 2044 return 0; 2045 } 2046 2047 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, 2048 enum ena_admin_hash_functions func, 2049 const u8 *key, u16 key_len, u32 init_val) 2050 { 2051 struct ena_rss *rss = &ena_dev->rss; 2052 struct ena_admin_get_feat_resp get_resp; 2053 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2054 rss->hash_key; 2055 int rc; 2056 2057 /* Make sure size is a mult of DWs */ 2058 if (unlikely(key_len & 0x3)) 2059 return -EINVAL; 2060 2061 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2062 ENA_ADMIN_RSS_HASH_FUNCTION, 2063 rss->hash_key_dma_addr, 2064 sizeof(*rss->hash_key)); 2065 if (unlikely(rc)) 2066 return rc; 2067 2068 if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) { 2069 pr_err("Flow hash function %d isn't supported\n", func); 2070 return -EOPNOTSUPP; 2071 } 2072 2073 switch (func) { 2074 case ENA_ADMIN_TOEPLITZ: 2075 if (key_len > sizeof(hash_key->key)) { 2076 pr_err("key len (%hu) is bigger than the max supported (%zu)\n", 2077 key_len, sizeof(hash_key->key)); 2078 return -EINVAL; 2079 } 2080 2081 memcpy(hash_key->key, key, key_len); 2082 rss->hash_init_val = init_val; 2083 hash_key->keys_num = key_len >> 2; 2084 break; 2085 case ENA_ADMIN_CRC32: 2086 rss->hash_init_val = init_val; 2087 break; 2088 default: 2089 pr_err("Invalid hash function (%d)\n", func); 2090 return -EINVAL; 2091 } 2092 2093 rc = ena_com_set_hash_function(ena_dev); 2094 2095 /* Restore the old function */ 2096 if (unlikely(rc)) 2097 ena_com_get_hash_function(ena_dev, NULL, NULL); 2098 2099 return rc; 2100 } 2101 2102 int ena_com_get_hash_function(struct ena_com_dev *ena_dev, 2103 enum ena_admin_hash_functions *func, 2104 u8 *key) 2105 { 2106 struct ena_rss *rss = &ena_dev->rss; 2107 struct ena_admin_get_feat_resp get_resp; 2108 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2109 rss->hash_key; 2110 int rc; 2111 2112 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2113 ENA_ADMIN_RSS_HASH_FUNCTION, 2114 rss->hash_key_dma_addr, 2115 sizeof(*rss->hash_key)); 2116 if (unlikely(rc)) 2117 return rc; 2118 2119 rss->hash_func = get_resp.u.flow_hash_func.selected_func; 2120 if (func) 2121 *func = rss->hash_func; 2122 2123 if (key) 2124 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2); 2125 2126 return 0; 2127 } 2128 2129 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, 2130 enum ena_admin_flow_hash_proto proto, 2131 u16 *fields) 2132 { 2133 struct ena_rss *rss = &ena_dev->rss; 2134 struct ena_admin_get_feat_resp get_resp; 2135 int rc; 2136 2137 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2138 ENA_ADMIN_RSS_HASH_INPUT, 2139 rss->hash_ctrl_dma_addr, 2140 sizeof(*rss->hash_ctrl)); 2141 if (unlikely(rc)) 2142 return rc; 2143 2144 if (fields) 2145 *fields = rss->hash_ctrl->selected_fields[proto].fields; 2146 2147 return 0; 2148 } 2149 2150 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) 2151 { 2152 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2153 struct ena_rss *rss = &ena_dev->rss; 2154 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2155 struct ena_admin_set_feat_cmd cmd; 2156 struct ena_admin_set_feat_resp resp; 2157 int ret; 2158 2159 if (!ena_com_check_supported_feature_id(ena_dev, 2160 ENA_ADMIN_RSS_HASH_INPUT)) { 2161 pr_debug("Feature %d isn't supported\n", 2162 ENA_ADMIN_RSS_HASH_INPUT); 2163 return -EOPNOTSUPP; 2164 } 2165 2166 memset(&cmd, 0x0, sizeof(cmd)); 2167 2168 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2169 cmd.aq_common_descriptor.flags = 2170 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2171 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT; 2172 cmd.u.flow_hash_input.enabled_input_sort = 2173 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK | 2174 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; 2175 2176 ret = ena_com_mem_addr_set(ena_dev, 2177 &cmd.control_buffer.address, 2178 rss->hash_ctrl_dma_addr); 2179 if (unlikely(ret)) { 2180 pr_err("memory address set failed\n"); 2181 return ret; 2182 } 2183 cmd.control_buffer.length = sizeof(*hash_ctrl); 2184 2185 ret = ena_com_execute_admin_command(admin_queue, 2186 (struct ena_admin_aq_entry *)&cmd, 2187 sizeof(cmd), 2188 (struct ena_admin_acq_entry *)&resp, 2189 sizeof(resp)); 2190 if (unlikely(ret)) 2191 pr_err("Failed to set hash input. error: %d\n", ret); 2192 2193 return ret; 2194 } 2195 2196 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) 2197 { 2198 struct ena_rss *rss = &ena_dev->rss; 2199 struct ena_admin_feature_rss_hash_control *hash_ctrl = 2200 rss->hash_ctrl; 2201 u16 available_fields = 0; 2202 int rc, i; 2203 2204 /* Get the supported hash input */ 2205 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2206 if (unlikely(rc)) 2207 return rc; 2208 2209 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields = 2210 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2211 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2212 2213 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields = 2214 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2215 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2216 2217 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields = 2218 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2219 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2220 2221 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields = 2222 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2223 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2224 2225 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields = 2226 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2227 2228 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields = 2229 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2230 2231 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields = 2232 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2233 2234 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields = 2235 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA; 2236 2237 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) { 2238 available_fields = hash_ctrl->selected_fields[i].fields & 2239 hash_ctrl->supported_fields[i].fields; 2240 if (available_fields != hash_ctrl->selected_fields[i].fields) { 2241 pr_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n", 2242 i, hash_ctrl->supported_fields[i].fields, 2243 hash_ctrl->selected_fields[i].fields); 2244 return -EOPNOTSUPP; 2245 } 2246 } 2247 2248 rc = ena_com_set_hash_ctrl(ena_dev); 2249 2250 /* In case of failure, restore the old hash ctrl */ 2251 if (unlikely(rc)) 2252 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2253 2254 return rc; 2255 } 2256 2257 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, 2258 enum ena_admin_flow_hash_proto proto, 2259 u16 hash_fields) 2260 { 2261 struct ena_rss *rss = &ena_dev->rss; 2262 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2263 u16 supported_fields; 2264 int rc; 2265 2266 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) { 2267 pr_err("Invalid proto num (%u)\n", proto); 2268 return -EINVAL; 2269 } 2270 2271 /* Get the ctrl table */ 2272 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL); 2273 if (unlikely(rc)) 2274 return rc; 2275 2276 /* Make sure all the fields are supported */ 2277 supported_fields = hash_ctrl->supported_fields[proto].fields; 2278 if ((hash_fields & supported_fields) != hash_fields) { 2279 pr_err("proto %d doesn't support the required fields %x. supports only: %x\n", 2280 proto, hash_fields, supported_fields); 2281 } 2282 2283 hash_ctrl->selected_fields[proto].fields = hash_fields; 2284 2285 rc = ena_com_set_hash_ctrl(ena_dev); 2286 2287 /* In case of failure, restore the old hash ctrl */ 2288 if (unlikely(rc)) 2289 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2290 2291 return 0; 2292 } 2293 2294 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, 2295 u16 entry_idx, u16 entry_value) 2296 { 2297 struct ena_rss *rss = &ena_dev->rss; 2298 2299 if (unlikely(entry_idx >= (1 << rss->tbl_log_size))) 2300 return -EINVAL; 2301 2302 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES))) 2303 return -EINVAL; 2304 2305 rss->host_rss_ind_tbl[entry_idx] = entry_value; 2306 2307 return 0; 2308 } 2309 2310 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) 2311 { 2312 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2313 struct ena_rss *rss = &ena_dev->rss; 2314 struct ena_admin_set_feat_cmd cmd; 2315 struct ena_admin_set_feat_resp resp; 2316 int ret; 2317 2318 if (!ena_com_check_supported_feature_id( 2319 ena_dev, ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) { 2320 pr_debug("Feature %d isn't supported\n", 2321 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); 2322 return -EOPNOTSUPP; 2323 } 2324 2325 ret = ena_com_ind_tbl_convert_to_device(ena_dev); 2326 if (ret) { 2327 pr_err("Failed to convert host indirection table to device table\n"); 2328 return ret; 2329 } 2330 2331 memset(&cmd, 0x0, sizeof(cmd)); 2332 2333 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2334 cmd.aq_common_descriptor.flags = 2335 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2336 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG; 2337 cmd.u.ind_table.size = rss->tbl_log_size; 2338 cmd.u.ind_table.inline_index = 0xFFFFFFFF; 2339 2340 ret = ena_com_mem_addr_set(ena_dev, 2341 &cmd.control_buffer.address, 2342 rss->rss_ind_tbl_dma_addr); 2343 if (unlikely(ret)) { 2344 pr_err("memory address set failed\n"); 2345 return ret; 2346 } 2347 2348 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) * 2349 sizeof(struct ena_admin_rss_ind_table_entry); 2350 2351 ret = ena_com_execute_admin_command(admin_queue, 2352 (struct ena_admin_aq_entry *)&cmd, 2353 sizeof(cmd), 2354 (struct ena_admin_acq_entry *)&resp, 2355 sizeof(resp)); 2356 2357 if (unlikely(ret)) 2358 pr_err("Failed to set indirect table. error: %d\n", ret); 2359 2360 return ret; 2361 } 2362 2363 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) 2364 { 2365 struct ena_rss *rss = &ena_dev->rss; 2366 struct ena_admin_get_feat_resp get_resp; 2367 u32 tbl_size; 2368 int i, rc; 2369 2370 tbl_size = (1ULL << rss->tbl_log_size) * 2371 sizeof(struct ena_admin_rss_ind_table_entry); 2372 2373 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2374 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 2375 rss->rss_ind_tbl_dma_addr, 2376 tbl_size); 2377 if (unlikely(rc)) 2378 return rc; 2379 2380 if (!ind_tbl) 2381 return 0; 2382 2383 rc = ena_com_ind_tbl_convert_from_device(ena_dev); 2384 if (unlikely(rc)) 2385 return rc; 2386 2387 for (i = 0; i < (1 << rss->tbl_log_size); i++) 2388 ind_tbl[i] = rss->host_rss_ind_tbl[i]; 2389 2390 return 0; 2391 } 2392 2393 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size) 2394 { 2395 int rc; 2396 2397 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2398 2399 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size); 2400 if (unlikely(rc)) 2401 goto err_indr_tbl; 2402 2403 rc = ena_com_hash_key_allocate(ena_dev); 2404 if (unlikely(rc)) 2405 goto err_hash_key; 2406 2407 rc = ena_com_hash_ctrl_init(ena_dev); 2408 if (unlikely(rc)) 2409 goto err_hash_ctrl; 2410 2411 return 0; 2412 2413 err_hash_ctrl: 2414 ena_com_hash_key_destroy(ena_dev); 2415 err_hash_key: 2416 ena_com_indirect_table_destroy(ena_dev); 2417 err_indr_tbl: 2418 2419 return rc; 2420 } 2421 2422 void ena_com_rss_destroy(struct ena_com_dev *ena_dev) 2423 { 2424 ena_com_indirect_table_destroy(ena_dev); 2425 ena_com_hash_key_destroy(ena_dev); 2426 ena_com_hash_ctrl_destroy(ena_dev); 2427 2428 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2429 } 2430 2431 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev) 2432 { 2433 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2434 2435 host_attr->host_info = 2436 dma_zalloc_coherent(ena_dev->dmadev, SZ_4K, 2437 &host_attr->host_info_dma_addr, GFP_KERNEL); 2438 if (unlikely(!host_attr->host_info)) 2439 return -ENOMEM; 2440 2441 return 0; 2442 } 2443 2444 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, 2445 u32 debug_area_size) 2446 { 2447 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2448 2449 host_attr->debug_area_virt_addr = 2450 dma_zalloc_coherent(ena_dev->dmadev, debug_area_size, 2451 &host_attr->debug_area_dma_addr, GFP_KERNEL); 2452 if (unlikely(!host_attr->debug_area_virt_addr)) { 2453 host_attr->debug_area_size = 0; 2454 return -ENOMEM; 2455 } 2456 2457 host_attr->debug_area_size = debug_area_size; 2458 2459 return 0; 2460 } 2461 2462 void ena_com_delete_host_info(struct ena_com_dev *ena_dev) 2463 { 2464 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2465 2466 if (host_attr->host_info) { 2467 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info, 2468 host_attr->host_info_dma_addr); 2469 host_attr->host_info = NULL; 2470 } 2471 } 2472 2473 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev) 2474 { 2475 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2476 2477 if (host_attr->debug_area_virt_addr) { 2478 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size, 2479 host_attr->debug_area_virt_addr, 2480 host_attr->debug_area_dma_addr); 2481 host_attr->debug_area_virt_addr = NULL; 2482 } 2483 } 2484 2485 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) 2486 { 2487 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2488 struct ena_com_admin_queue *admin_queue; 2489 struct ena_admin_set_feat_cmd cmd; 2490 struct ena_admin_set_feat_resp resp; 2491 2492 int ret; 2493 2494 /* Host attribute config is called before ena_com_get_dev_attr_feat 2495 * so ena_com can't check if the feature is supported. 2496 */ 2497 2498 memset(&cmd, 0x0, sizeof(cmd)); 2499 admin_queue = &ena_dev->admin_queue; 2500 2501 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2502 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG; 2503 2504 ret = ena_com_mem_addr_set(ena_dev, 2505 &cmd.u.host_attr.debug_ba, 2506 host_attr->debug_area_dma_addr); 2507 if (unlikely(ret)) { 2508 pr_err("memory address set failed\n"); 2509 return ret; 2510 } 2511 2512 ret = ena_com_mem_addr_set(ena_dev, 2513 &cmd.u.host_attr.os_info_ba, 2514 host_attr->host_info_dma_addr); 2515 if (unlikely(ret)) { 2516 pr_err("memory address set failed\n"); 2517 return ret; 2518 } 2519 2520 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size; 2521 2522 ret = ena_com_execute_admin_command(admin_queue, 2523 (struct ena_admin_aq_entry *)&cmd, 2524 sizeof(cmd), 2525 (struct ena_admin_acq_entry *)&resp, 2526 sizeof(resp)); 2527 2528 if (unlikely(ret)) 2529 pr_err("Failed to set host attributes: %d\n", ret); 2530 2531 return ret; 2532 } 2533 2534 /* Interrupt moderation */ 2535 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) 2536 { 2537 return ena_com_check_supported_feature_id(ena_dev, 2538 ENA_ADMIN_INTERRUPT_MODERATION); 2539 } 2540 2541 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, 2542 u32 tx_coalesce_usecs) 2543 { 2544 if (!ena_dev->intr_delay_resolution) { 2545 pr_err("Illegal interrupt delay granularity value\n"); 2546 return -EFAULT; 2547 } 2548 2549 ena_dev->intr_moder_tx_interval = tx_coalesce_usecs / 2550 ena_dev->intr_delay_resolution; 2551 2552 return 0; 2553 } 2554 2555 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, 2556 u32 rx_coalesce_usecs) 2557 { 2558 if (!ena_dev->intr_delay_resolution) { 2559 pr_err("Illegal interrupt delay granularity value\n"); 2560 return -EFAULT; 2561 } 2562 2563 /* We use LOWEST entry of moderation table for storing 2564 * nonadaptive interrupt coalescing values 2565 */ 2566 ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval = 2567 rx_coalesce_usecs / ena_dev->intr_delay_resolution; 2568 2569 return 0; 2570 } 2571 2572 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev) 2573 { 2574 if (ena_dev->intr_moder_tbl) 2575 devm_kfree(ena_dev->dmadev, ena_dev->intr_moder_tbl); 2576 ena_dev->intr_moder_tbl = NULL; 2577 } 2578 2579 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) 2580 { 2581 struct ena_admin_get_feat_resp get_resp; 2582 u16 delay_resolution; 2583 int rc; 2584 2585 rc = ena_com_get_feature(ena_dev, &get_resp, 2586 ENA_ADMIN_INTERRUPT_MODERATION); 2587 2588 if (rc) { 2589 if (rc == -EOPNOTSUPP) { 2590 pr_debug("Feature %d isn't supported\n", 2591 ENA_ADMIN_INTERRUPT_MODERATION); 2592 rc = 0; 2593 } else { 2594 pr_err("Failed to get interrupt moderation admin cmd. rc: %d\n", 2595 rc); 2596 } 2597 2598 /* no moderation supported, disable adaptive support */ 2599 ena_com_disable_adaptive_moderation(ena_dev); 2600 return rc; 2601 } 2602 2603 rc = ena_com_init_interrupt_moderation_table(ena_dev); 2604 if (rc) 2605 goto err; 2606 2607 /* if moderation is supported by device we set adaptive moderation */ 2608 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution; 2609 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution); 2610 ena_com_enable_adaptive_moderation(ena_dev); 2611 2612 return 0; 2613 err: 2614 ena_com_destroy_interrupt_moderation(ena_dev); 2615 return rc; 2616 } 2617 2618 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev) 2619 { 2620 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2621 2622 if (!intr_moder_tbl) 2623 return; 2624 2625 intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval = 2626 ENA_INTR_LOWEST_USECS; 2627 intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval = 2628 ENA_INTR_LOWEST_PKTS; 2629 intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval = 2630 ENA_INTR_LOWEST_BYTES; 2631 2632 intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval = 2633 ENA_INTR_LOW_USECS; 2634 intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval = 2635 ENA_INTR_LOW_PKTS; 2636 intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval = 2637 ENA_INTR_LOW_BYTES; 2638 2639 intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval = 2640 ENA_INTR_MID_USECS; 2641 intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval = 2642 ENA_INTR_MID_PKTS; 2643 intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval = 2644 ENA_INTR_MID_BYTES; 2645 2646 intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval = 2647 ENA_INTR_HIGH_USECS; 2648 intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval = 2649 ENA_INTR_HIGH_PKTS; 2650 intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval = 2651 ENA_INTR_HIGH_BYTES; 2652 2653 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval = 2654 ENA_INTR_HIGHEST_USECS; 2655 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval = 2656 ENA_INTR_HIGHEST_PKTS; 2657 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval = 2658 ENA_INTR_HIGHEST_BYTES; 2659 } 2660 2661 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev) 2662 { 2663 return ena_dev->intr_moder_tx_interval; 2664 } 2665 2666 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev) 2667 { 2668 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2669 2670 if (intr_moder_tbl) 2671 return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval; 2672 2673 return 0; 2674 } 2675 2676 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev, 2677 enum ena_intr_moder_level level, 2678 struct ena_intr_moder_entry *entry) 2679 { 2680 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2681 2682 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS) 2683 return; 2684 2685 intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval; 2686 if (ena_dev->intr_delay_resolution) 2687 intr_moder_tbl[level].intr_moder_interval /= 2688 ena_dev->intr_delay_resolution; 2689 intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval; 2690 2691 /* use hardcoded value until ethtool supports bytecount parameter */ 2692 if (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED) 2693 intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval; 2694 } 2695 2696 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev, 2697 enum ena_intr_moder_level level, 2698 struct ena_intr_moder_entry *entry) 2699 { 2700 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2701 2702 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS) 2703 return; 2704 2705 entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval; 2706 if (ena_dev->intr_delay_resolution) 2707 entry->intr_moder_interval *= ena_dev->intr_delay_resolution; 2708 entry->pkts_per_interval = 2709 intr_moder_tbl[level].pkts_per_interval; 2710 entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval; 2711 } 2712