1 /* 2 * Copyright 2015 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include "ena_com.h" 34 35 /*****************************************************************************/ 36 /*****************************************************************************/ 37 38 /* Timeout in micro-sec */ 39 #define ADMIN_CMD_TIMEOUT_US (3000000) 40 41 #define ENA_ASYNC_QUEUE_DEPTH 16 42 #define ENA_ADMIN_QUEUE_DEPTH 32 43 44 #define MIN_ENA_VER (((ENA_COMMON_SPEC_VERSION_MAJOR) << \ 45 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT) \ 46 | (ENA_COMMON_SPEC_VERSION_MINOR)) 47 48 #define ENA_CTRL_MAJOR 0 49 #define ENA_CTRL_MINOR 0 50 #define ENA_CTRL_SUB_MINOR 1 51 52 #define MIN_ENA_CTRL_VER \ 53 (((ENA_CTRL_MAJOR) << \ 54 (ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT)) | \ 55 ((ENA_CTRL_MINOR) << \ 56 (ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT)) | \ 57 (ENA_CTRL_SUB_MINOR)) 58 59 #define ENA_DMA_ADDR_TO_UINT32_LOW(x) ((u32)((u64)(x))) 60 #define ENA_DMA_ADDR_TO_UINT32_HIGH(x) ((u32)(((u64)(x)) >> 32)) 61 62 #define ENA_MMIO_READ_TIMEOUT 0xFFFFFFFF 63 64 #define ENA_REGS_ADMIN_INTR_MASK 1 65 66 /*****************************************************************************/ 67 /*****************************************************************************/ 68 /*****************************************************************************/ 69 70 enum ena_cmd_status { 71 ENA_CMD_SUBMITTED, 72 ENA_CMD_COMPLETED, 73 /* Abort - canceled by the driver */ 74 ENA_CMD_ABORTED, 75 }; 76 77 struct ena_comp_ctx { 78 struct completion wait_event; 79 struct ena_admin_acq_entry *user_cqe; 80 u32 comp_size; 81 enum ena_cmd_status status; 82 /* status from the device */ 83 u8 comp_status; 84 u8 cmd_opcode; 85 bool occupied; 86 }; 87 88 struct ena_com_stats_ctx { 89 struct ena_admin_aq_get_stats_cmd get_cmd; 90 struct ena_admin_acq_get_stats_resp get_resp; 91 }; 92 93 static inline int ena_com_mem_addr_set(struct ena_com_dev *ena_dev, 94 struct ena_common_mem_addr *ena_addr, 95 dma_addr_t addr) 96 { 97 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { 98 pr_err("dma address has more bits that the device supports\n"); 99 return -EINVAL; 100 } 101 102 ena_addr->mem_addr_low = lower_32_bits(addr); 103 ena_addr->mem_addr_high = (u16)upper_32_bits(addr); 104 105 return 0; 106 } 107 108 static int ena_com_admin_init_sq(struct ena_com_admin_queue *queue) 109 { 110 struct ena_com_admin_sq *sq = &queue->sq; 111 u16 size = ADMIN_SQ_SIZE(queue->q_depth); 112 113 sq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &sq->dma_addr, 114 GFP_KERNEL); 115 116 if (!sq->entries) { 117 pr_err("memory allocation failed"); 118 return -ENOMEM; 119 } 120 121 sq->head = 0; 122 sq->tail = 0; 123 sq->phase = 1; 124 125 sq->db_addr = NULL; 126 127 return 0; 128 } 129 130 static int ena_com_admin_init_cq(struct ena_com_admin_queue *queue) 131 { 132 struct ena_com_admin_cq *cq = &queue->cq; 133 u16 size = ADMIN_CQ_SIZE(queue->q_depth); 134 135 cq->entries = dma_zalloc_coherent(queue->q_dmadev, size, &cq->dma_addr, 136 GFP_KERNEL); 137 138 if (!cq->entries) { 139 pr_err("memory allocation failed"); 140 return -ENOMEM; 141 } 142 143 cq->head = 0; 144 cq->phase = 1; 145 146 return 0; 147 } 148 149 static int ena_com_admin_init_aenq(struct ena_com_dev *dev, 150 struct ena_aenq_handlers *aenq_handlers) 151 { 152 struct ena_com_aenq *aenq = &dev->aenq; 153 u32 addr_low, addr_high, aenq_caps; 154 u16 size; 155 156 dev->aenq.q_depth = ENA_ASYNC_QUEUE_DEPTH; 157 size = ADMIN_AENQ_SIZE(ENA_ASYNC_QUEUE_DEPTH); 158 aenq->entries = dma_zalloc_coherent(dev->dmadev, size, &aenq->dma_addr, 159 GFP_KERNEL); 160 161 if (!aenq->entries) { 162 pr_err("memory allocation failed"); 163 return -ENOMEM; 164 } 165 166 aenq->head = aenq->q_depth; 167 aenq->phase = 1; 168 169 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(aenq->dma_addr); 170 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(aenq->dma_addr); 171 172 writel(addr_low, dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF); 173 writel(addr_high, dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF); 174 175 aenq_caps = 0; 176 aenq_caps |= dev->aenq.q_depth & ENA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK; 177 aenq_caps |= (sizeof(struct ena_admin_aenq_entry) 178 << ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_SHIFT) & 179 ENA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK; 180 writel(aenq_caps, dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF); 181 182 if (unlikely(!aenq_handlers)) { 183 pr_err("aenq handlers pointer is NULL\n"); 184 return -EINVAL; 185 } 186 187 aenq->aenq_handlers = aenq_handlers; 188 189 return 0; 190 } 191 192 static inline void comp_ctxt_release(struct ena_com_admin_queue *queue, 193 struct ena_comp_ctx *comp_ctx) 194 { 195 comp_ctx->occupied = false; 196 atomic_dec(&queue->outstanding_cmds); 197 } 198 199 static struct ena_comp_ctx *get_comp_ctxt(struct ena_com_admin_queue *queue, 200 u16 command_id, bool capture) 201 { 202 if (unlikely(command_id >= queue->q_depth)) { 203 pr_err("command id is larger than the queue size. cmd_id: %u queue size %d\n", 204 command_id, queue->q_depth); 205 return NULL; 206 } 207 208 if (unlikely(queue->comp_ctx[command_id].occupied && capture)) { 209 pr_err("Completion context is occupied\n"); 210 return NULL; 211 } 212 213 if (capture) { 214 atomic_inc(&queue->outstanding_cmds); 215 queue->comp_ctx[command_id].occupied = true; 216 } 217 218 return &queue->comp_ctx[command_id]; 219 } 220 221 static struct ena_comp_ctx *__ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 222 struct ena_admin_aq_entry *cmd, 223 size_t cmd_size_in_bytes, 224 struct ena_admin_acq_entry *comp, 225 size_t comp_size_in_bytes) 226 { 227 struct ena_comp_ctx *comp_ctx; 228 u16 tail_masked, cmd_id; 229 u16 queue_size_mask; 230 u16 cnt; 231 232 queue_size_mask = admin_queue->q_depth - 1; 233 234 tail_masked = admin_queue->sq.tail & queue_size_mask; 235 236 /* In case of queue FULL */ 237 cnt = atomic_read(&admin_queue->outstanding_cmds); 238 if (cnt >= admin_queue->q_depth) { 239 pr_debug("admin queue is full.\n"); 240 admin_queue->stats.out_of_space++; 241 return ERR_PTR(-ENOSPC); 242 } 243 244 cmd_id = admin_queue->curr_cmd_id; 245 246 cmd->aq_common_descriptor.flags |= admin_queue->sq.phase & 247 ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 248 249 cmd->aq_common_descriptor.command_id |= cmd_id & 250 ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 251 252 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, true); 253 if (unlikely(!comp_ctx)) 254 return ERR_PTR(-EINVAL); 255 256 comp_ctx->status = ENA_CMD_SUBMITTED; 257 comp_ctx->comp_size = (u32)comp_size_in_bytes; 258 comp_ctx->user_cqe = comp; 259 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode; 260 261 reinit_completion(&comp_ctx->wait_event); 262 263 memcpy(&admin_queue->sq.entries[tail_masked], cmd, cmd_size_in_bytes); 264 265 admin_queue->curr_cmd_id = (admin_queue->curr_cmd_id + 1) & 266 queue_size_mask; 267 268 admin_queue->sq.tail++; 269 admin_queue->stats.submitted_cmd++; 270 271 if (unlikely((admin_queue->sq.tail & queue_size_mask) == 0)) 272 admin_queue->sq.phase = !admin_queue->sq.phase; 273 274 writel(admin_queue->sq.tail, admin_queue->sq.db_addr); 275 276 return comp_ctx; 277 } 278 279 static inline int ena_com_init_comp_ctxt(struct ena_com_admin_queue *queue) 280 { 281 size_t size = queue->q_depth * sizeof(struct ena_comp_ctx); 282 struct ena_comp_ctx *comp_ctx; 283 u16 i; 284 285 queue->comp_ctx = devm_kzalloc(queue->q_dmadev, size, GFP_KERNEL); 286 if (unlikely(!queue->comp_ctx)) { 287 pr_err("memory allocation failed"); 288 return -ENOMEM; 289 } 290 291 for (i = 0; i < queue->q_depth; i++) { 292 comp_ctx = get_comp_ctxt(queue, i, false); 293 if (comp_ctx) 294 init_completion(&comp_ctx->wait_event); 295 } 296 297 return 0; 298 } 299 300 static struct ena_comp_ctx *ena_com_submit_admin_cmd(struct ena_com_admin_queue *admin_queue, 301 struct ena_admin_aq_entry *cmd, 302 size_t cmd_size_in_bytes, 303 struct ena_admin_acq_entry *comp, 304 size_t comp_size_in_bytes) 305 { 306 unsigned long flags; 307 struct ena_comp_ctx *comp_ctx; 308 309 spin_lock_irqsave(&admin_queue->q_lock, flags); 310 if (unlikely(!admin_queue->running_state)) { 311 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 312 return ERR_PTR(-ENODEV); 313 } 314 comp_ctx = __ena_com_submit_admin_cmd(admin_queue, cmd, 315 cmd_size_in_bytes, 316 comp, 317 comp_size_in_bytes); 318 if (unlikely(IS_ERR(comp_ctx))) 319 admin_queue->running_state = false; 320 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 321 322 return comp_ctx; 323 } 324 325 static int ena_com_init_io_sq(struct ena_com_dev *ena_dev, 326 struct ena_com_create_io_ctx *ctx, 327 struct ena_com_io_sq *io_sq) 328 { 329 size_t size; 330 int dev_node = 0; 331 332 memset(&io_sq->desc_addr, 0x0, sizeof(io_sq->desc_addr)); 333 334 io_sq->desc_entry_size = 335 (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 336 sizeof(struct ena_eth_io_tx_desc) : 337 sizeof(struct ena_eth_io_rx_desc); 338 339 size = io_sq->desc_entry_size * io_sq->q_depth; 340 341 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 342 dev_node = dev_to_node(ena_dev->dmadev); 343 set_dev_node(ena_dev->dmadev, ctx->numa_node); 344 io_sq->desc_addr.virt_addr = 345 dma_zalloc_coherent(ena_dev->dmadev, size, 346 &io_sq->desc_addr.phys_addr, 347 GFP_KERNEL); 348 set_dev_node(ena_dev->dmadev, dev_node); 349 if (!io_sq->desc_addr.virt_addr) { 350 io_sq->desc_addr.virt_addr = 351 dma_zalloc_coherent(ena_dev->dmadev, size, 352 &io_sq->desc_addr.phys_addr, 353 GFP_KERNEL); 354 } 355 } else { 356 dev_node = dev_to_node(ena_dev->dmadev); 357 set_dev_node(ena_dev->dmadev, ctx->numa_node); 358 io_sq->desc_addr.virt_addr = 359 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 360 set_dev_node(ena_dev->dmadev, dev_node); 361 if (!io_sq->desc_addr.virt_addr) { 362 io_sq->desc_addr.virt_addr = 363 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 364 } 365 } 366 367 if (!io_sq->desc_addr.virt_addr) { 368 pr_err("memory allocation failed"); 369 return -ENOMEM; 370 } 371 372 io_sq->tail = 0; 373 io_sq->next_to_comp = 0; 374 io_sq->phase = 1; 375 376 return 0; 377 } 378 379 static int ena_com_init_io_cq(struct ena_com_dev *ena_dev, 380 struct ena_com_create_io_ctx *ctx, 381 struct ena_com_io_cq *io_cq) 382 { 383 size_t size; 384 int prev_node = 0; 385 386 memset(&io_cq->cdesc_addr, 0x0, sizeof(io_cq->cdesc_addr)); 387 388 /* Use the basic completion descriptor for Rx */ 389 io_cq->cdesc_entry_size_in_bytes = 390 (io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) ? 391 sizeof(struct ena_eth_io_tx_cdesc) : 392 sizeof(struct ena_eth_io_rx_cdesc_base); 393 394 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 395 396 prev_node = dev_to_node(ena_dev->dmadev); 397 set_dev_node(ena_dev->dmadev, ctx->numa_node); 398 io_cq->cdesc_addr.virt_addr = 399 dma_zalloc_coherent(ena_dev->dmadev, size, 400 &io_cq->cdesc_addr.phys_addr, GFP_KERNEL); 401 set_dev_node(ena_dev->dmadev, prev_node); 402 if (!io_cq->cdesc_addr.virt_addr) { 403 io_cq->cdesc_addr.virt_addr = 404 dma_zalloc_coherent(ena_dev->dmadev, size, 405 &io_cq->cdesc_addr.phys_addr, 406 GFP_KERNEL); 407 } 408 409 if (!io_cq->cdesc_addr.virt_addr) { 410 pr_err("memory allocation failed"); 411 return -ENOMEM; 412 } 413 414 io_cq->phase = 1; 415 io_cq->head = 0; 416 417 return 0; 418 } 419 420 static void ena_com_handle_single_admin_completion(struct ena_com_admin_queue *admin_queue, 421 struct ena_admin_acq_entry *cqe) 422 { 423 struct ena_comp_ctx *comp_ctx; 424 u16 cmd_id; 425 426 cmd_id = cqe->acq_common_descriptor.command & 427 ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 428 429 comp_ctx = get_comp_ctxt(admin_queue, cmd_id, false); 430 if (unlikely(!comp_ctx)) { 431 pr_err("comp_ctx is NULL. Changing the admin queue running state\n"); 432 admin_queue->running_state = false; 433 return; 434 } 435 436 comp_ctx->status = ENA_CMD_COMPLETED; 437 comp_ctx->comp_status = cqe->acq_common_descriptor.status; 438 439 if (comp_ctx->user_cqe) 440 memcpy(comp_ctx->user_cqe, (void *)cqe, comp_ctx->comp_size); 441 442 if (!admin_queue->polling) 443 complete(&comp_ctx->wait_event); 444 } 445 446 static void ena_com_handle_admin_completion(struct ena_com_admin_queue *admin_queue) 447 { 448 struct ena_admin_acq_entry *cqe = NULL; 449 u16 comp_num = 0; 450 u16 head_masked; 451 u8 phase; 452 453 head_masked = admin_queue->cq.head & (admin_queue->q_depth - 1); 454 phase = admin_queue->cq.phase; 455 456 cqe = &admin_queue->cq.entries[head_masked]; 457 458 /* Go over all the completions */ 459 while ((cqe->acq_common_descriptor.flags & 460 ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK) == phase) { 461 /* Do not read the rest of the completion entry before the 462 * phase bit was validated 463 */ 464 rmb(); 465 ena_com_handle_single_admin_completion(admin_queue, cqe); 466 467 head_masked++; 468 comp_num++; 469 if (unlikely(head_masked == admin_queue->q_depth)) { 470 head_masked = 0; 471 phase = !phase; 472 } 473 474 cqe = &admin_queue->cq.entries[head_masked]; 475 } 476 477 admin_queue->cq.head += comp_num; 478 admin_queue->cq.phase = phase; 479 admin_queue->sq.head += comp_num; 480 admin_queue->stats.completed_cmd += comp_num; 481 } 482 483 static int ena_com_comp_status_to_errno(u8 comp_status) 484 { 485 if (unlikely(comp_status != 0)) 486 pr_err("admin command failed[%u]\n", comp_status); 487 488 if (unlikely(comp_status > ENA_ADMIN_UNKNOWN_ERROR)) 489 return -EINVAL; 490 491 switch (comp_status) { 492 case ENA_ADMIN_SUCCESS: 493 return 0; 494 case ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE: 495 return -ENOMEM; 496 case ENA_ADMIN_UNSUPPORTED_OPCODE: 497 return -EOPNOTSUPP; 498 case ENA_ADMIN_BAD_OPCODE: 499 case ENA_ADMIN_MALFORMED_REQUEST: 500 case ENA_ADMIN_ILLEGAL_PARAMETER: 501 case ENA_ADMIN_UNKNOWN_ERROR: 502 return -EINVAL; 503 } 504 505 return 0; 506 } 507 508 static int ena_com_wait_and_process_admin_cq_polling(struct ena_comp_ctx *comp_ctx, 509 struct ena_com_admin_queue *admin_queue) 510 { 511 unsigned long flags, timeout; 512 int ret; 513 514 timeout = jiffies + usecs_to_jiffies(admin_queue->completion_timeout); 515 516 while (1) { 517 spin_lock_irqsave(&admin_queue->q_lock, flags); 518 ena_com_handle_admin_completion(admin_queue); 519 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 520 521 if (comp_ctx->status != ENA_CMD_SUBMITTED) 522 break; 523 524 if (time_is_before_jiffies(timeout)) { 525 pr_err("Wait for completion (polling) timeout\n"); 526 /* ENA didn't have any completion */ 527 spin_lock_irqsave(&admin_queue->q_lock, flags); 528 admin_queue->stats.no_completion++; 529 admin_queue->running_state = false; 530 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 531 532 ret = -ETIME; 533 goto err; 534 } 535 536 msleep(100); 537 } 538 539 if (unlikely(comp_ctx->status == ENA_CMD_ABORTED)) { 540 pr_err("Command was aborted\n"); 541 spin_lock_irqsave(&admin_queue->q_lock, flags); 542 admin_queue->stats.aborted_cmd++; 543 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 544 ret = -ENODEV; 545 goto err; 546 } 547 548 WARN(comp_ctx->status != ENA_CMD_COMPLETED, "Invalid comp status %d\n", 549 comp_ctx->status); 550 551 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); 552 err: 553 comp_ctxt_release(admin_queue, comp_ctx); 554 return ret; 555 } 556 557 static int ena_com_wait_and_process_admin_cq_interrupts(struct ena_comp_ctx *comp_ctx, 558 struct ena_com_admin_queue *admin_queue) 559 { 560 unsigned long flags; 561 int ret; 562 563 wait_for_completion_timeout(&comp_ctx->wait_event, 564 usecs_to_jiffies( 565 admin_queue->completion_timeout)); 566 567 /* In case the command wasn't completed find out the root cause. 568 * There might be 2 kinds of errors 569 * 1) No completion (timeout reached) 570 * 2) There is completion but the device didn't get any msi-x interrupt. 571 */ 572 if (unlikely(comp_ctx->status == ENA_CMD_SUBMITTED)) { 573 spin_lock_irqsave(&admin_queue->q_lock, flags); 574 ena_com_handle_admin_completion(admin_queue); 575 admin_queue->stats.no_completion++; 576 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 577 578 if (comp_ctx->status == ENA_CMD_COMPLETED) 579 pr_err("The ena device have completion but the driver didn't receive any MSI-X interrupt (cmd %d)\n", 580 comp_ctx->cmd_opcode); 581 else 582 pr_err("The ena device doesn't send any completion for the admin cmd %d status %d\n", 583 comp_ctx->cmd_opcode, comp_ctx->status); 584 585 admin_queue->running_state = false; 586 ret = -ETIME; 587 goto err; 588 } 589 590 ret = ena_com_comp_status_to_errno(comp_ctx->comp_status); 591 err: 592 comp_ctxt_release(admin_queue, comp_ctx); 593 return ret; 594 } 595 596 /* This method read the hardware device register through posting writes 597 * and waiting for response 598 * On timeout the function will return ENA_MMIO_READ_TIMEOUT 599 */ 600 static u32 ena_com_reg_bar_read32(struct ena_com_dev *ena_dev, u16 offset) 601 { 602 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 603 volatile struct ena_admin_ena_mmio_req_read_less_resp *read_resp = 604 mmio_read->read_resp; 605 u32 mmio_read_reg, ret, i; 606 unsigned long flags; 607 u32 timeout = mmio_read->reg_read_to; 608 609 might_sleep(); 610 611 if (timeout == 0) 612 timeout = ENA_REG_READ_TIMEOUT; 613 614 /* If readless is disabled, perform regular read */ 615 if (!mmio_read->readless_supported) 616 return readl(ena_dev->reg_bar + offset); 617 618 spin_lock_irqsave(&mmio_read->lock, flags); 619 mmio_read->seq_num++; 620 621 read_resp->req_id = mmio_read->seq_num + 0xDEAD; 622 mmio_read_reg = (offset << ENA_REGS_MMIO_REG_READ_REG_OFF_SHIFT) & 623 ENA_REGS_MMIO_REG_READ_REG_OFF_MASK; 624 mmio_read_reg |= mmio_read->seq_num & 625 ENA_REGS_MMIO_REG_READ_REQ_ID_MASK; 626 627 /* make sure read_resp->req_id get updated before the hw can write 628 * there 629 */ 630 wmb(); 631 632 writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF); 633 634 for (i = 0; i < timeout; i++) { 635 if (read_resp->req_id == mmio_read->seq_num) 636 break; 637 638 udelay(1); 639 } 640 641 if (unlikely(i == timeout)) { 642 pr_err("reading reg failed for timeout. expected: req id[%hu] offset[%hu] actual: req id[%hu] offset[%hu]\n", 643 mmio_read->seq_num, offset, read_resp->req_id, 644 read_resp->reg_off); 645 ret = ENA_MMIO_READ_TIMEOUT; 646 goto err; 647 } 648 649 if (read_resp->reg_off != offset) { 650 pr_err("Read failure: wrong offset provided"); 651 ret = ENA_MMIO_READ_TIMEOUT; 652 } else { 653 ret = read_resp->reg_val; 654 } 655 err: 656 spin_unlock_irqrestore(&mmio_read->lock, flags); 657 658 return ret; 659 } 660 661 /* There are two types to wait for completion. 662 * Polling mode - wait until the completion is available. 663 * Async mode - wait on wait queue until the completion is ready 664 * (or the timeout expired). 665 * It is expected that the IRQ called ena_com_handle_admin_completion 666 * to mark the completions. 667 */ 668 static int ena_com_wait_and_process_admin_cq(struct ena_comp_ctx *comp_ctx, 669 struct ena_com_admin_queue *admin_queue) 670 { 671 if (admin_queue->polling) 672 return ena_com_wait_and_process_admin_cq_polling(comp_ctx, 673 admin_queue); 674 675 return ena_com_wait_and_process_admin_cq_interrupts(comp_ctx, 676 admin_queue); 677 } 678 679 static int ena_com_destroy_io_sq(struct ena_com_dev *ena_dev, 680 struct ena_com_io_sq *io_sq) 681 { 682 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 683 struct ena_admin_aq_destroy_sq_cmd destroy_cmd; 684 struct ena_admin_acq_destroy_sq_resp_desc destroy_resp; 685 u8 direction; 686 int ret; 687 688 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 689 690 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 691 direction = ENA_ADMIN_SQ_DIRECTION_TX; 692 else 693 direction = ENA_ADMIN_SQ_DIRECTION_RX; 694 695 destroy_cmd.sq.sq_identity |= (direction << 696 ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & 697 ENA_ADMIN_SQ_SQ_DIRECTION_MASK; 698 699 destroy_cmd.sq.sq_idx = io_sq->idx; 700 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_SQ; 701 702 ret = ena_com_execute_admin_command(admin_queue, 703 (struct ena_admin_aq_entry *)&destroy_cmd, 704 sizeof(destroy_cmd), 705 (struct ena_admin_acq_entry *)&destroy_resp, 706 sizeof(destroy_resp)); 707 708 if (unlikely(ret && (ret != -ENODEV))) 709 pr_err("failed to destroy io sq error: %d\n", ret); 710 711 return ret; 712 } 713 714 static void ena_com_io_queue_free(struct ena_com_dev *ena_dev, 715 struct ena_com_io_sq *io_sq, 716 struct ena_com_io_cq *io_cq) 717 { 718 size_t size; 719 720 if (io_cq->cdesc_addr.virt_addr) { 721 size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth; 722 723 dma_free_coherent(ena_dev->dmadev, size, 724 io_cq->cdesc_addr.virt_addr, 725 io_cq->cdesc_addr.phys_addr); 726 727 io_cq->cdesc_addr.virt_addr = NULL; 728 } 729 730 if (io_sq->desc_addr.virt_addr) { 731 size = io_sq->desc_entry_size * io_sq->q_depth; 732 733 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) 734 dma_free_coherent(ena_dev->dmadev, size, 735 io_sq->desc_addr.virt_addr, 736 io_sq->desc_addr.phys_addr); 737 else 738 devm_kfree(ena_dev->dmadev, io_sq->desc_addr.virt_addr); 739 740 io_sq->desc_addr.virt_addr = NULL; 741 } 742 } 743 744 static int wait_for_reset_state(struct ena_com_dev *ena_dev, u32 timeout, 745 u16 exp_state) 746 { 747 u32 val, i; 748 749 for (i = 0; i < timeout; i++) { 750 val = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 751 752 if (unlikely(val == ENA_MMIO_READ_TIMEOUT)) { 753 pr_err("Reg read timeout occurred\n"); 754 return -ETIME; 755 } 756 757 if ((val & ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK) == 758 exp_state) 759 return 0; 760 761 /* The resolution of the timeout is 100ms */ 762 msleep(100); 763 } 764 765 return -ETIME; 766 } 767 768 static bool ena_com_check_supported_feature_id(struct ena_com_dev *ena_dev, 769 enum ena_admin_aq_feature_id feature_id) 770 { 771 u32 feature_mask = 1 << feature_id; 772 773 /* Device attributes is always supported */ 774 if ((feature_id != ENA_ADMIN_DEVICE_ATTRIBUTES) && 775 !(ena_dev->supported_features & feature_mask)) 776 return false; 777 778 return true; 779 } 780 781 static int ena_com_get_feature_ex(struct ena_com_dev *ena_dev, 782 struct ena_admin_get_feat_resp *get_resp, 783 enum ena_admin_aq_feature_id feature_id, 784 dma_addr_t control_buf_dma_addr, 785 u32 control_buff_size) 786 { 787 struct ena_com_admin_queue *admin_queue; 788 struct ena_admin_get_feat_cmd get_cmd; 789 int ret; 790 791 if (!ena_com_check_supported_feature_id(ena_dev, feature_id)) { 792 pr_debug("Feature %d isn't supported\n", feature_id); 793 return -EOPNOTSUPP; 794 } 795 796 memset(&get_cmd, 0x0, sizeof(get_cmd)); 797 admin_queue = &ena_dev->admin_queue; 798 799 get_cmd.aq_common_descriptor.opcode = ENA_ADMIN_GET_FEATURE; 800 801 if (control_buff_size) 802 get_cmd.aq_common_descriptor.flags = 803 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 804 else 805 get_cmd.aq_common_descriptor.flags = 0; 806 807 ret = ena_com_mem_addr_set(ena_dev, 808 &get_cmd.control_buffer.address, 809 control_buf_dma_addr); 810 if (unlikely(ret)) { 811 pr_err("memory address set failed\n"); 812 return ret; 813 } 814 815 get_cmd.control_buffer.length = control_buff_size; 816 817 get_cmd.feat_common.feature_id = feature_id; 818 819 ret = ena_com_execute_admin_command(admin_queue, 820 (struct ena_admin_aq_entry *) 821 &get_cmd, 822 sizeof(get_cmd), 823 (struct ena_admin_acq_entry *) 824 get_resp, 825 sizeof(*get_resp)); 826 827 if (unlikely(ret)) 828 pr_err("Failed to submit get_feature command %d error: %d\n", 829 feature_id, ret); 830 831 return ret; 832 } 833 834 static int ena_com_get_feature(struct ena_com_dev *ena_dev, 835 struct ena_admin_get_feat_resp *get_resp, 836 enum ena_admin_aq_feature_id feature_id) 837 { 838 return ena_com_get_feature_ex(ena_dev, 839 get_resp, 840 feature_id, 841 0, 842 0); 843 } 844 845 static int ena_com_hash_key_allocate(struct ena_com_dev *ena_dev) 846 { 847 struct ena_rss *rss = &ena_dev->rss; 848 849 rss->hash_key = 850 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), 851 &rss->hash_key_dma_addr, GFP_KERNEL); 852 853 if (unlikely(!rss->hash_key)) 854 return -ENOMEM; 855 856 return 0; 857 } 858 859 static void ena_com_hash_key_destroy(struct ena_com_dev *ena_dev) 860 { 861 struct ena_rss *rss = &ena_dev->rss; 862 863 if (rss->hash_key) 864 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_key), 865 rss->hash_key, rss->hash_key_dma_addr); 866 rss->hash_key = NULL; 867 } 868 869 static int ena_com_hash_ctrl_init(struct ena_com_dev *ena_dev) 870 { 871 struct ena_rss *rss = &ena_dev->rss; 872 873 rss->hash_ctrl = 874 dma_zalloc_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), 875 &rss->hash_ctrl_dma_addr, GFP_KERNEL); 876 877 if (unlikely(!rss->hash_ctrl)) 878 return -ENOMEM; 879 880 return 0; 881 } 882 883 static void ena_com_hash_ctrl_destroy(struct ena_com_dev *ena_dev) 884 { 885 struct ena_rss *rss = &ena_dev->rss; 886 887 if (rss->hash_ctrl) 888 dma_free_coherent(ena_dev->dmadev, sizeof(*rss->hash_ctrl), 889 rss->hash_ctrl, rss->hash_ctrl_dma_addr); 890 rss->hash_ctrl = NULL; 891 } 892 893 static int ena_com_indirect_table_allocate(struct ena_com_dev *ena_dev, 894 u16 log_size) 895 { 896 struct ena_rss *rss = &ena_dev->rss; 897 struct ena_admin_get_feat_resp get_resp; 898 size_t tbl_size; 899 int ret; 900 901 ret = ena_com_get_feature(ena_dev, &get_resp, 902 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); 903 if (unlikely(ret)) 904 return ret; 905 906 if ((get_resp.u.ind_table.min_size > log_size) || 907 (get_resp.u.ind_table.max_size < log_size)) { 908 pr_err("indirect table size doesn't fit. requested size: %d while min is:%d and max %d\n", 909 1 << log_size, 1 << get_resp.u.ind_table.min_size, 910 1 << get_resp.u.ind_table.max_size); 911 return -EINVAL; 912 } 913 914 tbl_size = (1ULL << log_size) * 915 sizeof(struct ena_admin_rss_ind_table_entry); 916 917 rss->rss_ind_tbl = 918 dma_zalloc_coherent(ena_dev->dmadev, tbl_size, 919 &rss->rss_ind_tbl_dma_addr, GFP_KERNEL); 920 if (unlikely(!rss->rss_ind_tbl)) 921 goto mem_err1; 922 923 tbl_size = (1ULL << log_size) * sizeof(u16); 924 rss->host_rss_ind_tbl = 925 devm_kzalloc(ena_dev->dmadev, tbl_size, GFP_KERNEL); 926 if (unlikely(!rss->host_rss_ind_tbl)) 927 goto mem_err2; 928 929 rss->tbl_log_size = log_size; 930 931 return 0; 932 933 mem_err2: 934 tbl_size = (1ULL << log_size) * 935 sizeof(struct ena_admin_rss_ind_table_entry); 936 937 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, 938 rss->rss_ind_tbl_dma_addr); 939 rss->rss_ind_tbl = NULL; 940 mem_err1: 941 rss->tbl_log_size = 0; 942 return -ENOMEM; 943 } 944 945 static void ena_com_indirect_table_destroy(struct ena_com_dev *ena_dev) 946 { 947 struct ena_rss *rss = &ena_dev->rss; 948 size_t tbl_size = (1ULL << rss->tbl_log_size) * 949 sizeof(struct ena_admin_rss_ind_table_entry); 950 951 if (rss->rss_ind_tbl) 952 dma_free_coherent(ena_dev->dmadev, tbl_size, rss->rss_ind_tbl, 953 rss->rss_ind_tbl_dma_addr); 954 rss->rss_ind_tbl = NULL; 955 956 if (rss->host_rss_ind_tbl) 957 devm_kfree(ena_dev->dmadev, rss->host_rss_ind_tbl); 958 rss->host_rss_ind_tbl = NULL; 959 } 960 961 static int ena_com_create_io_sq(struct ena_com_dev *ena_dev, 962 struct ena_com_io_sq *io_sq, u16 cq_idx) 963 { 964 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 965 struct ena_admin_aq_create_sq_cmd create_cmd; 966 struct ena_admin_acq_create_sq_resp_desc cmd_completion; 967 u8 direction; 968 int ret; 969 970 memset(&create_cmd, 0x0, sizeof(create_cmd)); 971 972 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_SQ; 973 974 if (io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 975 direction = ENA_ADMIN_SQ_DIRECTION_TX; 976 else 977 direction = ENA_ADMIN_SQ_DIRECTION_RX; 978 979 create_cmd.sq_identity |= (direction << 980 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & 981 ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; 982 983 create_cmd.sq_caps_2 |= io_sq->mem_queue_type & 984 ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 985 986 create_cmd.sq_caps_2 |= (ENA_ADMIN_COMPLETION_POLICY_DESC << 987 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & 988 ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; 989 990 create_cmd.sq_caps_3 |= 991 ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 992 993 create_cmd.cq_idx = cq_idx; 994 create_cmd.sq_depth = io_sq->q_depth; 995 996 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST) { 997 ret = ena_com_mem_addr_set(ena_dev, 998 &create_cmd.sq_ba, 999 io_sq->desc_addr.phys_addr); 1000 if (unlikely(ret)) { 1001 pr_err("memory address set failed\n"); 1002 return ret; 1003 } 1004 } 1005 1006 ret = ena_com_execute_admin_command(admin_queue, 1007 (struct ena_admin_aq_entry *)&create_cmd, 1008 sizeof(create_cmd), 1009 (struct ena_admin_acq_entry *)&cmd_completion, 1010 sizeof(cmd_completion)); 1011 if (unlikely(ret)) { 1012 pr_err("Failed to create IO SQ. error: %d\n", ret); 1013 return ret; 1014 } 1015 1016 io_sq->idx = cmd_completion.sq_idx; 1017 1018 io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1019 (uintptr_t)cmd_completion.sq_doorbell_offset); 1020 1021 if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) { 1022 io_sq->header_addr = (u8 __iomem *)((uintptr_t)ena_dev->mem_bar 1023 + cmd_completion.llq_headers_offset); 1024 1025 io_sq->desc_addr.pbuf_dev_addr = 1026 (u8 __iomem *)((uintptr_t)ena_dev->mem_bar + 1027 cmd_completion.llq_descriptors_offset); 1028 } 1029 1030 pr_debug("created sq[%u], depth[%u]\n", io_sq->idx, io_sq->q_depth); 1031 1032 return ret; 1033 } 1034 1035 static int ena_com_ind_tbl_convert_to_device(struct ena_com_dev *ena_dev) 1036 { 1037 struct ena_rss *rss = &ena_dev->rss; 1038 struct ena_com_io_sq *io_sq; 1039 u16 qid; 1040 int i; 1041 1042 for (i = 0; i < 1 << rss->tbl_log_size; i++) { 1043 qid = rss->host_rss_ind_tbl[i]; 1044 if (qid >= ENA_TOTAL_NUM_QUEUES) 1045 return -EINVAL; 1046 1047 io_sq = &ena_dev->io_sq_queues[qid]; 1048 1049 if (io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX) 1050 return -EINVAL; 1051 1052 rss->rss_ind_tbl[i].cq_idx = io_sq->idx; 1053 } 1054 1055 return 0; 1056 } 1057 1058 static int ena_com_ind_tbl_convert_from_device(struct ena_com_dev *ena_dev) 1059 { 1060 u16 dev_idx_to_host_tbl[ENA_TOTAL_NUM_QUEUES] = { (u16)-1 }; 1061 struct ena_rss *rss = &ena_dev->rss; 1062 u8 idx; 1063 u16 i; 1064 1065 for (i = 0; i < ENA_TOTAL_NUM_QUEUES; i++) 1066 dev_idx_to_host_tbl[ena_dev->io_sq_queues[i].idx] = i; 1067 1068 for (i = 0; i < 1 << rss->tbl_log_size; i++) { 1069 if (rss->rss_ind_tbl[i].cq_idx > ENA_TOTAL_NUM_QUEUES) 1070 return -EINVAL; 1071 idx = (u8)rss->rss_ind_tbl[i].cq_idx; 1072 1073 if (dev_idx_to_host_tbl[idx] > ENA_TOTAL_NUM_QUEUES) 1074 return -EINVAL; 1075 1076 rss->host_rss_ind_tbl[i] = dev_idx_to_host_tbl[idx]; 1077 } 1078 1079 return 0; 1080 } 1081 1082 static int ena_com_init_interrupt_moderation_table(struct ena_com_dev *ena_dev) 1083 { 1084 size_t size; 1085 1086 size = sizeof(struct ena_intr_moder_entry) * ENA_INTR_MAX_NUM_OF_LEVELS; 1087 1088 ena_dev->intr_moder_tbl = 1089 devm_kzalloc(ena_dev->dmadev, size, GFP_KERNEL); 1090 if (!ena_dev->intr_moder_tbl) 1091 return -ENOMEM; 1092 1093 ena_com_config_default_interrupt_moderation_table(ena_dev); 1094 1095 return 0; 1096 } 1097 1098 static void ena_com_update_intr_delay_resolution(struct ena_com_dev *ena_dev, 1099 u16 intr_delay_resolution) 1100 { 1101 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 1102 unsigned int i; 1103 1104 if (!intr_delay_resolution) { 1105 pr_err("Illegal intr_delay_resolution provided. Going to use default 1 usec resolution\n"); 1106 intr_delay_resolution = 1; 1107 } 1108 ena_dev->intr_delay_resolution = intr_delay_resolution; 1109 1110 /* update Rx */ 1111 for (i = 0; i < ENA_INTR_MAX_NUM_OF_LEVELS; i++) 1112 intr_moder_tbl[i].intr_moder_interval /= intr_delay_resolution; 1113 1114 /* update Tx */ 1115 ena_dev->intr_moder_tx_interval /= intr_delay_resolution; 1116 } 1117 1118 /*****************************************************************************/ 1119 /******************************* API ******************************/ 1120 /*****************************************************************************/ 1121 1122 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, 1123 struct ena_admin_aq_entry *cmd, 1124 size_t cmd_size, 1125 struct ena_admin_acq_entry *comp, 1126 size_t comp_size) 1127 { 1128 struct ena_comp_ctx *comp_ctx; 1129 int ret; 1130 1131 comp_ctx = ena_com_submit_admin_cmd(admin_queue, cmd, cmd_size, 1132 comp, comp_size); 1133 if (unlikely(IS_ERR(comp_ctx))) { 1134 if (comp_ctx == ERR_PTR(-ENODEV)) 1135 pr_debug("Failed to submit command [%ld]\n", 1136 PTR_ERR(comp_ctx)); 1137 else 1138 pr_err("Failed to submit command [%ld]\n", 1139 PTR_ERR(comp_ctx)); 1140 1141 return PTR_ERR(comp_ctx); 1142 } 1143 1144 ret = ena_com_wait_and_process_admin_cq(comp_ctx, admin_queue); 1145 if (unlikely(ret)) { 1146 if (admin_queue->running_state) 1147 pr_err("Failed to process command. ret = %d\n", ret); 1148 else 1149 pr_debug("Failed to process command. ret = %d\n", ret); 1150 } 1151 return ret; 1152 } 1153 1154 int ena_com_create_io_cq(struct ena_com_dev *ena_dev, 1155 struct ena_com_io_cq *io_cq) 1156 { 1157 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1158 struct ena_admin_aq_create_cq_cmd create_cmd; 1159 struct ena_admin_acq_create_cq_resp_desc cmd_completion; 1160 int ret; 1161 1162 memset(&create_cmd, 0x0, sizeof(create_cmd)); 1163 1164 create_cmd.aq_common_descriptor.opcode = ENA_ADMIN_CREATE_CQ; 1165 1166 create_cmd.cq_caps_2 |= (io_cq->cdesc_entry_size_in_bytes / 4) & 1167 ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1168 create_cmd.cq_caps_1 |= 1169 ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK; 1170 1171 create_cmd.msix_vector = io_cq->msix_vector; 1172 create_cmd.cq_depth = io_cq->q_depth; 1173 1174 ret = ena_com_mem_addr_set(ena_dev, 1175 &create_cmd.cq_ba, 1176 io_cq->cdesc_addr.phys_addr); 1177 if (unlikely(ret)) { 1178 pr_err("memory address set failed\n"); 1179 return ret; 1180 } 1181 1182 ret = ena_com_execute_admin_command(admin_queue, 1183 (struct ena_admin_aq_entry *)&create_cmd, 1184 sizeof(create_cmd), 1185 (struct ena_admin_acq_entry *)&cmd_completion, 1186 sizeof(cmd_completion)); 1187 if (unlikely(ret)) { 1188 pr_err("Failed to create IO CQ. error: %d\n", ret); 1189 return ret; 1190 } 1191 1192 io_cq->idx = cmd_completion.cq_idx; 1193 1194 io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1195 cmd_completion.cq_interrupt_unmask_register_offset); 1196 1197 if (cmd_completion.cq_head_db_register_offset) 1198 io_cq->cq_head_db_reg = 1199 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1200 cmd_completion.cq_head_db_register_offset); 1201 1202 if (cmd_completion.numa_node_register_offset) 1203 io_cq->numa_node_cfg_reg = 1204 (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1205 cmd_completion.numa_node_register_offset); 1206 1207 pr_debug("created cq[%u], depth[%u]\n", io_cq->idx, io_cq->q_depth); 1208 1209 return ret; 1210 } 1211 1212 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, 1213 struct ena_com_io_sq **io_sq, 1214 struct ena_com_io_cq **io_cq) 1215 { 1216 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1217 pr_err("Invalid queue number %d but the max is %d\n", qid, 1218 ENA_TOTAL_NUM_QUEUES); 1219 return -EINVAL; 1220 } 1221 1222 *io_sq = &ena_dev->io_sq_queues[qid]; 1223 *io_cq = &ena_dev->io_cq_queues[qid]; 1224 1225 return 0; 1226 } 1227 1228 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev) 1229 { 1230 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1231 struct ena_comp_ctx *comp_ctx; 1232 u16 i; 1233 1234 if (!admin_queue->comp_ctx) 1235 return; 1236 1237 for (i = 0; i < admin_queue->q_depth; i++) { 1238 comp_ctx = get_comp_ctxt(admin_queue, i, false); 1239 if (unlikely(!comp_ctx)) 1240 break; 1241 1242 comp_ctx->status = ENA_CMD_ABORTED; 1243 1244 complete(&comp_ctx->wait_event); 1245 } 1246 } 1247 1248 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev) 1249 { 1250 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1251 unsigned long flags; 1252 1253 spin_lock_irqsave(&admin_queue->q_lock, flags); 1254 while (atomic_read(&admin_queue->outstanding_cmds) != 0) { 1255 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1256 msleep(20); 1257 spin_lock_irqsave(&admin_queue->q_lock, flags); 1258 } 1259 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1260 } 1261 1262 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, 1263 struct ena_com_io_cq *io_cq) 1264 { 1265 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1266 struct ena_admin_aq_destroy_cq_cmd destroy_cmd; 1267 struct ena_admin_acq_destroy_cq_resp_desc destroy_resp; 1268 int ret; 1269 1270 memset(&destroy_cmd, 0x0, sizeof(destroy_cmd)); 1271 1272 destroy_cmd.cq_idx = io_cq->idx; 1273 destroy_cmd.aq_common_descriptor.opcode = ENA_ADMIN_DESTROY_CQ; 1274 1275 ret = ena_com_execute_admin_command(admin_queue, 1276 (struct ena_admin_aq_entry *)&destroy_cmd, 1277 sizeof(destroy_cmd), 1278 (struct ena_admin_acq_entry *)&destroy_resp, 1279 sizeof(destroy_resp)); 1280 1281 if (unlikely(ret && (ret != -ENODEV))) 1282 pr_err("Failed to destroy IO CQ. error: %d\n", ret); 1283 1284 return ret; 1285 } 1286 1287 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev) 1288 { 1289 return ena_dev->admin_queue.running_state; 1290 } 1291 1292 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state) 1293 { 1294 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1295 unsigned long flags; 1296 1297 spin_lock_irqsave(&admin_queue->q_lock, flags); 1298 ena_dev->admin_queue.running_state = state; 1299 spin_unlock_irqrestore(&admin_queue->q_lock, flags); 1300 } 1301 1302 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev) 1303 { 1304 u16 depth = ena_dev->aenq.q_depth; 1305 1306 WARN(ena_dev->aenq.head != depth, "Invalid AENQ state\n"); 1307 1308 /* Init head_db to mark that all entries in the queue 1309 * are initially available 1310 */ 1311 writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 1312 } 1313 1314 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag) 1315 { 1316 struct ena_com_admin_queue *admin_queue; 1317 struct ena_admin_set_feat_cmd cmd; 1318 struct ena_admin_set_feat_resp resp; 1319 struct ena_admin_get_feat_resp get_resp; 1320 int ret; 1321 1322 ret = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_AENQ_CONFIG); 1323 if (ret) { 1324 pr_info("Can't get aenq configuration\n"); 1325 return ret; 1326 } 1327 1328 if ((get_resp.u.aenq.supported_groups & groups_flag) != groups_flag) { 1329 pr_warn("Trying to set unsupported aenq events. supported flag: %x asked flag: %x\n", 1330 get_resp.u.aenq.supported_groups, groups_flag); 1331 return -EOPNOTSUPP; 1332 } 1333 1334 memset(&cmd, 0x0, sizeof(cmd)); 1335 admin_queue = &ena_dev->admin_queue; 1336 1337 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1338 cmd.aq_common_descriptor.flags = 0; 1339 cmd.feat_common.feature_id = ENA_ADMIN_AENQ_CONFIG; 1340 cmd.u.aenq.enabled_groups = groups_flag; 1341 1342 ret = ena_com_execute_admin_command(admin_queue, 1343 (struct ena_admin_aq_entry *)&cmd, 1344 sizeof(cmd), 1345 (struct ena_admin_acq_entry *)&resp, 1346 sizeof(resp)); 1347 1348 if (unlikely(ret)) 1349 pr_err("Failed to config AENQ ret: %d\n", ret); 1350 1351 return ret; 1352 } 1353 1354 int ena_com_get_dma_width(struct ena_com_dev *ena_dev) 1355 { 1356 u32 caps = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 1357 int width; 1358 1359 if (unlikely(caps == ENA_MMIO_READ_TIMEOUT)) { 1360 pr_err("Reg read timeout occurred\n"); 1361 return -ETIME; 1362 } 1363 1364 width = (caps & ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK) >> 1365 ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT; 1366 1367 pr_debug("ENA dma width: %d\n", width); 1368 1369 if ((width < 32) || width > ENA_MAX_PHYS_ADDR_SIZE_BITS) { 1370 pr_err("DMA width illegal value: %d\n", width); 1371 return -EINVAL; 1372 } 1373 1374 ena_dev->dma_addr_bits = width; 1375 1376 return width; 1377 } 1378 1379 int ena_com_validate_version(struct ena_com_dev *ena_dev) 1380 { 1381 u32 ver; 1382 u32 ctrl_ver; 1383 u32 ctrl_ver_masked; 1384 1385 /* Make sure the ENA version and the controller version are at least 1386 * as the driver expects 1387 */ 1388 ver = ena_com_reg_bar_read32(ena_dev, ENA_REGS_VERSION_OFF); 1389 ctrl_ver = ena_com_reg_bar_read32(ena_dev, 1390 ENA_REGS_CONTROLLER_VERSION_OFF); 1391 1392 if (unlikely((ver == ENA_MMIO_READ_TIMEOUT) || 1393 (ctrl_ver == ENA_MMIO_READ_TIMEOUT))) { 1394 pr_err("Reg read timeout occurred\n"); 1395 return -ETIME; 1396 } 1397 1398 pr_info("ena device version: %d.%d\n", 1399 (ver & ENA_REGS_VERSION_MAJOR_VERSION_MASK) >> 1400 ENA_REGS_VERSION_MAJOR_VERSION_SHIFT, 1401 ver & ENA_REGS_VERSION_MINOR_VERSION_MASK); 1402 1403 if (ver < MIN_ENA_VER) { 1404 pr_err("ENA version is lower than the minimal version the driver supports\n"); 1405 return -1; 1406 } 1407 1408 pr_info("ena controller version: %d.%d.%d implementation version %d\n", 1409 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) >> 1410 ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_SHIFT, 1411 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) >> 1412 ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_SHIFT, 1413 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK), 1414 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK) >> 1415 ENA_REGS_CONTROLLER_VERSION_IMPL_ID_SHIFT); 1416 1417 ctrl_ver_masked = 1418 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK) | 1419 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK) | 1420 (ctrl_ver & ENA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK); 1421 1422 /* Validate the ctrl version without the implementation ID */ 1423 if (ctrl_ver_masked < MIN_ENA_CTRL_VER) { 1424 pr_err("ENA ctrl version is lower than the minimal ctrl version the driver supports\n"); 1425 return -1; 1426 } 1427 1428 return 0; 1429 } 1430 1431 void ena_com_admin_destroy(struct ena_com_dev *ena_dev) 1432 { 1433 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1434 struct ena_com_admin_cq *cq = &admin_queue->cq; 1435 struct ena_com_admin_sq *sq = &admin_queue->sq; 1436 struct ena_com_aenq *aenq = &ena_dev->aenq; 1437 u16 size; 1438 1439 if (admin_queue->comp_ctx) 1440 devm_kfree(ena_dev->dmadev, admin_queue->comp_ctx); 1441 admin_queue->comp_ctx = NULL; 1442 size = ADMIN_SQ_SIZE(admin_queue->q_depth); 1443 if (sq->entries) 1444 dma_free_coherent(ena_dev->dmadev, size, sq->entries, 1445 sq->dma_addr); 1446 sq->entries = NULL; 1447 1448 size = ADMIN_CQ_SIZE(admin_queue->q_depth); 1449 if (cq->entries) 1450 dma_free_coherent(ena_dev->dmadev, size, cq->entries, 1451 cq->dma_addr); 1452 cq->entries = NULL; 1453 1454 size = ADMIN_AENQ_SIZE(aenq->q_depth); 1455 if (ena_dev->aenq.entries) 1456 dma_free_coherent(ena_dev->dmadev, size, aenq->entries, 1457 aenq->dma_addr); 1458 aenq->entries = NULL; 1459 } 1460 1461 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling) 1462 { 1463 u32 mask_value = 0; 1464 1465 if (polling) 1466 mask_value = ENA_REGS_ADMIN_INTR_MASK; 1467 1468 writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF); 1469 ena_dev->admin_queue.polling = polling; 1470 } 1471 1472 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev) 1473 { 1474 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1475 1476 spin_lock_init(&mmio_read->lock); 1477 mmio_read->read_resp = 1478 dma_zalloc_coherent(ena_dev->dmadev, 1479 sizeof(*mmio_read->read_resp), 1480 &mmio_read->read_resp_dma_addr, GFP_KERNEL); 1481 if (unlikely(!mmio_read->read_resp)) 1482 return -ENOMEM; 1483 1484 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 1485 1486 mmio_read->read_resp->req_id = 0x0; 1487 mmio_read->seq_num = 0x0; 1488 mmio_read->readless_supported = true; 1489 1490 return 0; 1491 } 1492 1493 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, bool readless_supported) 1494 { 1495 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1496 1497 mmio_read->readless_supported = readless_supported; 1498 } 1499 1500 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev) 1501 { 1502 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1503 1504 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1505 writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1506 1507 dma_free_coherent(ena_dev->dmadev, sizeof(*mmio_read->read_resp), 1508 mmio_read->read_resp, mmio_read->read_resp_dma_addr); 1509 1510 mmio_read->read_resp = NULL; 1511 } 1512 1513 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev) 1514 { 1515 struct ena_com_mmio_read *mmio_read = &ena_dev->mmio_read; 1516 u32 addr_low, addr_high; 1517 1518 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(mmio_read->read_resp_dma_addr); 1519 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(mmio_read->read_resp_dma_addr); 1520 1521 writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF); 1522 writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF); 1523 } 1524 1525 int ena_com_admin_init(struct ena_com_dev *ena_dev, 1526 struct ena_aenq_handlers *aenq_handlers, 1527 bool init_spinlock) 1528 { 1529 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1530 u32 aq_caps, acq_caps, dev_sts, addr_low, addr_high; 1531 int ret; 1532 1533 dev_sts = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 1534 1535 if (unlikely(dev_sts == ENA_MMIO_READ_TIMEOUT)) { 1536 pr_err("Reg read timeout occurred\n"); 1537 return -ETIME; 1538 } 1539 1540 if (!(dev_sts & ENA_REGS_DEV_STS_READY_MASK)) { 1541 pr_err("Device isn't ready, abort com init\n"); 1542 return -ENODEV; 1543 } 1544 1545 admin_queue->q_depth = ENA_ADMIN_QUEUE_DEPTH; 1546 1547 admin_queue->q_dmadev = ena_dev->dmadev; 1548 admin_queue->polling = false; 1549 admin_queue->curr_cmd_id = 0; 1550 1551 atomic_set(&admin_queue->outstanding_cmds, 0); 1552 1553 if (init_spinlock) 1554 spin_lock_init(&admin_queue->q_lock); 1555 1556 ret = ena_com_init_comp_ctxt(admin_queue); 1557 if (ret) 1558 goto error; 1559 1560 ret = ena_com_admin_init_sq(admin_queue); 1561 if (ret) 1562 goto error; 1563 1564 ret = ena_com_admin_init_cq(admin_queue); 1565 if (ret) 1566 goto error; 1567 1568 admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar + 1569 ENA_REGS_AQ_DB_OFF); 1570 1571 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->sq.dma_addr); 1572 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->sq.dma_addr); 1573 1574 writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF); 1575 writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF); 1576 1577 addr_low = ENA_DMA_ADDR_TO_UINT32_LOW(admin_queue->cq.dma_addr); 1578 addr_high = ENA_DMA_ADDR_TO_UINT32_HIGH(admin_queue->cq.dma_addr); 1579 1580 writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF); 1581 writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF); 1582 1583 aq_caps = 0; 1584 aq_caps |= admin_queue->q_depth & ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK; 1585 aq_caps |= (sizeof(struct ena_admin_aq_entry) << 1586 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_SHIFT) & 1587 ENA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK; 1588 1589 acq_caps = 0; 1590 acq_caps |= admin_queue->q_depth & ENA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK; 1591 acq_caps |= (sizeof(struct ena_admin_acq_entry) << 1592 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_SHIFT) & 1593 ENA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK; 1594 1595 writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF); 1596 writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF); 1597 ret = ena_com_admin_init_aenq(ena_dev, aenq_handlers); 1598 if (ret) 1599 goto error; 1600 1601 admin_queue->running_state = true; 1602 1603 return 0; 1604 error: 1605 ena_com_admin_destroy(ena_dev); 1606 1607 return ret; 1608 } 1609 1610 int ena_com_create_io_queue(struct ena_com_dev *ena_dev, 1611 struct ena_com_create_io_ctx *ctx) 1612 { 1613 struct ena_com_io_sq *io_sq; 1614 struct ena_com_io_cq *io_cq; 1615 int ret; 1616 1617 if (ctx->qid >= ENA_TOTAL_NUM_QUEUES) { 1618 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", 1619 ctx->qid, ENA_TOTAL_NUM_QUEUES); 1620 return -EINVAL; 1621 } 1622 1623 io_sq = &ena_dev->io_sq_queues[ctx->qid]; 1624 io_cq = &ena_dev->io_cq_queues[ctx->qid]; 1625 1626 memset(io_sq, 0x0, sizeof(*io_sq)); 1627 memset(io_cq, 0x0, sizeof(*io_cq)); 1628 1629 /* Init CQ */ 1630 io_cq->q_depth = ctx->queue_size; 1631 io_cq->direction = ctx->direction; 1632 io_cq->qid = ctx->qid; 1633 1634 io_cq->msix_vector = ctx->msix_vector; 1635 1636 io_sq->q_depth = ctx->queue_size; 1637 io_sq->direction = ctx->direction; 1638 io_sq->qid = ctx->qid; 1639 1640 io_sq->mem_queue_type = ctx->mem_queue_type; 1641 1642 if (ctx->direction == ENA_COM_IO_QUEUE_DIRECTION_TX) 1643 /* header length is limited to 8 bits */ 1644 io_sq->tx_max_header_size = 1645 min_t(u32, ena_dev->tx_max_header_size, SZ_256); 1646 1647 ret = ena_com_init_io_sq(ena_dev, ctx, io_sq); 1648 if (ret) 1649 goto error; 1650 ret = ena_com_init_io_cq(ena_dev, ctx, io_cq); 1651 if (ret) 1652 goto error; 1653 1654 ret = ena_com_create_io_cq(ena_dev, io_cq); 1655 if (ret) 1656 goto error; 1657 1658 ret = ena_com_create_io_sq(ena_dev, io_sq, io_cq->idx); 1659 if (ret) 1660 goto destroy_io_cq; 1661 1662 return 0; 1663 1664 destroy_io_cq: 1665 ena_com_destroy_io_cq(ena_dev, io_cq); 1666 error: 1667 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1668 return ret; 1669 } 1670 1671 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid) 1672 { 1673 struct ena_com_io_sq *io_sq; 1674 struct ena_com_io_cq *io_cq; 1675 1676 if (qid >= ENA_TOTAL_NUM_QUEUES) { 1677 pr_err("Qid (%d) is bigger than max num of queues (%d)\n", qid, 1678 ENA_TOTAL_NUM_QUEUES); 1679 return; 1680 } 1681 1682 io_sq = &ena_dev->io_sq_queues[qid]; 1683 io_cq = &ena_dev->io_cq_queues[qid]; 1684 1685 ena_com_destroy_io_sq(ena_dev, io_sq); 1686 ena_com_destroy_io_cq(ena_dev, io_cq); 1687 1688 ena_com_io_queue_free(ena_dev, io_sq, io_cq); 1689 } 1690 1691 int ena_com_get_link_params(struct ena_com_dev *ena_dev, 1692 struct ena_admin_get_feat_resp *resp) 1693 { 1694 return ena_com_get_feature(ena_dev, resp, ENA_ADMIN_LINK_CONFIG); 1695 } 1696 1697 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, 1698 struct ena_com_dev_get_features_ctx *get_feat_ctx) 1699 { 1700 struct ena_admin_get_feat_resp get_resp; 1701 int rc; 1702 1703 rc = ena_com_get_feature(ena_dev, &get_resp, 1704 ENA_ADMIN_DEVICE_ATTRIBUTES); 1705 if (rc) 1706 return rc; 1707 1708 memcpy(&get_feat_ctx->dev_attr, &get_resp.u.dev_attr, 1709 sizeof(get_resp.u.dev_attr)); 1710 ena_dev->supported_features = get_resp.u.dev_attr.supported_features; 1711 1712 rc = ena_com_get_feature(ena_dev, &get_resp, 1713 ENA_ADMIN_MAX_QUEUES_NUM); 1714 if (rc) 1715 return rc; 1716 1717 memcpy(&get_feat_ctx->max_queues, &get_resp.u.max_queue, 1718 sizeof(get_resp.u.max_queue)); 1719 ena_dev->tx_max_header_size = get_resp.u.max_queue.max_header_size; 1720 1721 rc = ena_com_get_feature(ena_dev, &get_resp, 1722 ENA_ADMIN_AENQ_CONFIG); 1723 if (rc) 1724 return rc; 1725 1726 memcpy(&get_feat_ctx->aenq, &get_resp.u.aenq, 1727 sizeof(get_resp.u.aenq)); 1728 1729 rc = ena_com_get_feature(ena_dev, &get_resp, 1730 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG); 1731 if (rc) 1732 return rc; 1733 1734 memcpy(&get_feat_ctx->offload, &get_resp.u.offload, 1735 sizeof(get_resp.u.offload)); 1736 1737 /* Driver hints isn't mandatory admin command. So in case the 1738 * command isn't supported set driver hints to 0 1739 */ 1740 rc = ena_com_get_feature(ena_dev, &get_resp, ENA_ADMIN_HW_HINTS); 1741 1742 if (!rc) 1743 memcpy(&get_feat_ctx->hw_hints, &get_resp.u.hw_hints, 1744 sizeof(get_resp.u.hw_hints)); 1745 else if (rc == -EOPNOTSUPP) 1746 memset(&get_feat_ctx->hw_hints, 0x0, 1747 sizeof(get_feat_ctx->hw_hints)); 1748 else 1749 return rc; 1750 1751 return 0; 1752 } 1753 1754 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev) 1755 { 1756 ena_com_handle_admin_completion(&ena_dev->admin_queue); 1757 } 1758 1759 /* ena_handle_specific_aenq_event: 1760 * return the handler that is relevant to the specific event group 1761 */ 1762 static ena_aenq_handler ena_com_get_specific_aenq_cb(struct ena_com_dev *dev, 1763 u16 group) 1764 { 1765 struct ena_aenq_handlers *aenq_handlers = dev->aenq.aenq_handlers; 1766 1767 if ((group < ENA_MAX_HANDLERS) && aenq_handlers->handlers[group]) 1768 return aenq_handlers->handlers[group]; 1769 1770 return aenq_handlers->unimplemented_handler; 1771 } 1772 1773 /* ena_aenq_intr_handler: 1774 * handles the aenq incoming events. 1775 * pop events from the queue and apply the specific handler 1776 */ 1777 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data) 1778 { 1779 struct ena_admin_aenq_entry *aenq_e; 1780 struct ena_admin_aenq_common_desc *aenq_common; 1781 struct ena_com_aenq *aenq = &dev->aenq; 1782 ena_aenq_handler handler_cb; 1783 u16 masked_head, processed = 0; 1784 u8 phase; 1785 1786 masked_head = aenq->head & (aenq->q_depth - 1); 1787 phase = aenq->phase; 1788 aenq_e = &aenq->entries[masked_head]; /* Get first entry */ 1789 aenq_common = &aenq_e->aenq_common_desc; 1790 1791 /* Go over all the events */ 1792 while ((aenq_common->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK) == 1793 phase) { 1794 pr_debug("AENQ! Group[%x] Syndrom[%x] timestamp: [%llus]\n", 1795 aenq_common->group, aenq_common->syndrom, 1796 (u64)aenq_common->timestamp_low + 1797 ((u64)aenq_common->timestamp_high << 32)); 1798 1799 /* Handle specific event*/ 1800 handler_cb = ena_com_get_specific_aenq_cb(dev, 1801 aenq_common->group); 1802 handler_cb(data, aenq_e); /* call the actual event handler*/ 1803 1804 /* Get next event entry */ 1805 masked_head++; 1806 processed++; 1807 1808 if (unlikely(masked_head == aenq->q_depth)) { 1809 masked_head = 0; 1810 phase = !phase; 1811 } 1812 aenq_e = &aenq->entries[masked_head]; 1813 aenq_common = &aenq_e->aenq_common_desc; 1814 } 1815 1816 aenq->head += processed; 1817 aenq->phase = phase; 1818 1819 /* Don't update aenq doorbell if there weren't any processed events */ 1820 if (!processed) 1821 return; 1822 1823 /* write the aenq doorbell after all AENQ descriptors were read */ 1824 mb(); 1825 writel((u32)aenq->head, dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF); 1826 } 1827 1828 int ena_com_dev_reset(struct ena_com_dev *ena_dev, 1829 enum ena_regs_reset_reason_types reset_reason) 1830 { 1831 u32 stat, timeout, cap, reset_val; 1832 int rc; 1833 1834 stat = ena_com_reg_bar_read32(ena_dev, ENA_REGS_DEV_STS_OFF); 1835 cap = ena_com_reg_bar_read32(ena_dev, ENA_REGS_CAPS_OFF); 1836 1837 if (unlikely((stat == ENA_MMIO_READ_TIMEOUT) || 1838 (cap == ENA_MMIO_READ_TIMEOUT))) { 1839 pr_err("Reg read32 timeout occurred\n"); 1840 return -ETIME; 1841 } 1842 1843 if ((stat & ENA_REGS_DEV_STS_READY_MASK) == 0) { 1844 pr_err("Device isn't ready, can't reset device\n"); 1845 return -EINVAL; 1846 } 1847 1848 timeout = (cap & ENA_REGS_CAPS_RESET_TIMEOUT_MASK) >> 1849 ENA_REGS_CAPS_RESET_TIMEOUT_SHIFT; 1850 if (timeout == 0) { 1851 pr_err("Invalid timeout value\n"); 1852 return -EINVAL; 1853 } 1854 1855 /* start reset */ 1856 reset_val = ENA_REGS_DEV_CTL_DEV_RESET_MASK; 1857 reset_val |= (reset_reason << ENA_REGS_DEV_CTL_RESET_REASON_SHIFT) & 1858 ENA_REGS_DEV_CTL_RESET_REASON_MASK; 1859 writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 1860 1861 /* Write again the MMIO read request address */ 1862 ena_com_mmio_reg_read_request_write_dev_addr(ena_dev); 1863 1864 rc = wait_for_reset_state(ena_dev, timeout, 1865 ENA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK); 1866 if (rc != 0) { 1867 pr_err("Reset indication didn't turn on\n"); 1868 return rc; 1869 } 1870 1871 /* reset done */ 1872 writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF); 1873 rc = wait_for_reset_state(ena_dev, timeout, 0); 1874 if (rc != 0) { 1875 pr_err("Reset indication didn't turn off\n"); 1876 return rc; 1877 } 1878 1879 timeout = (cap & ENA_REGS_CAPS_ADMIN_CMD_TO_MASK) >> 1880 ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT; 1881 if (timeout) 1882 /* the resolution of timeout reg is 100ms */ 1883 ena_dev->admin_queue.completion_timeout = timeout * 100000; 1884 else 1885 ena_dev->admin_queue.completion_timeout = ADMIN_CMD_TIMEOUT_US; 1886 1887 return 0; 1888 } 1889 1890 static int ena_get_dev_stats(struct ena_com_dev *ena_dev, 1891 struct ena_com_stats_ctx *ctx, 1892 enum ena_admin_get_stats_type type) 1893 { 1894 struct ena_admin_aq_get_stats_cmd *get_cmd = &ctx->get_cmd; 1895 struct ena_admin_acq_get_stats_resp *get_resp = &ctx->get_resp; 1896 struct ena_com_admin_queue *admin_queue; 1897 int ret; 1898 1899 admin_queue = &ena_dev->admin_queue; 1900 1901 get_cmd->aq_common_descriptor.opcode = ENA_ADMIN_GET_STATS; 1902 get_cmd->aq_common_descriptor.flags = 0; 1903 get_cmd->type = type; 1904 1905 ret = ena_com_execute_admin_command(admin_queue, 1906 (struct ena_admin_aq_entry *)get_cmd, 1907 sizeof(*get_cmd), 1908 (struct ena_admin_acq_entry *)get_resp, 1909 sizeof(*get_resp)); 1910 1911 if (unlikely(ret)) 1912 pr_err("Failed to get stats. error: %d\n", ret); 1913 1914 return ret; 1915 } 1916 1917 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, 1918 struct ena_admin_basic_stats *stats) 1919 { 1920 struct ena_com_stats_ctx ctx; 1921 int ret; 1922 1923 memset(&ctx, 0x0, sizeof(ctx)); 1924 ret = ena_get_dev_stats(ena_dev, &ctx, ENA_ADMIN_GET_STATS_TYPE_BASIC); 1925 if (likely(ret == 0)) 1926 memcpy(stats, &ctx.get_resp.basic_stats, 1927 sizeof(ctx.get_resp.basic_stats)); 1928 1929 return ret; 1930 } 1931 1932 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu) 1933 { 1934 struct ena_com_admin_queue *admin_queue; 1935 struct ena_admin_set_feat_cmd cmd; 1936 struct ena_admin_set_feat_resp resp; 1937 int ret; 1938 1939 if (!ena_com_check_supported_feature_id(ena_dev, ENA_ADMIN_MTU)) { 1940 pr_debug("Feature %d isn't supported\n", ENA_ADMIN_MTU); 1941 return -EOPNOTSUPP; 1942 } 1943 1944 memset(&cmd, 0x0, sizeof(cmd)); 1945 admin_queue = &ena_dev->admin_queue; 1946 1947 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 1948 cmd.aq_common_descriptor.flags = 0; 1949 cmd.feat_common.feature_id = ENA_ADMIN_MTU; 1950 cmd.u.mtu.mtu = mtu; 1951 1952 ret = ena_com_execute_admin_command(admin_queue, 1953 (struct ena_admin_aq_entry *)&cmd, 1954 sizeof(cmd), 1955 (struct ena_admin_acq_entry *)&resp, 1956 sizeof(resp)); 1957 1958 if (unlikely(ret)) 1959 pr_err("Failed to set mtu %d. error: %d\n", mtu, ret); 1960 1961 return ret; 1962 } 1963 1964 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, 1965 struct ena_admin_feature_offload_desc *offload) 1966 { 1967 int ret; 1968 struct ena_admin_get_feat_resp resp; 1969 1970 ret = ena_com_get_feature(ena_dev, &resp, 1971 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG); 1972 if (unlikely(ret)) { 1973 pr_err("Failed to get offload capabilities %d\n", ret); 1974 return ret; 1975 } 1976 1977 memcpy(offload, &resp.u.offload, sizeof(resp.u.offload)); 1978 1979 return 0; 1980 } 1981 1982 int ena_com_set_hash_function(struct ena_com_dev *ena_dev) 1983 { 1984 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 1985 struct ena_rss *rss = &ena_dev->rss; 1986 struct ena_admin_set_feat_cmd cmd; 1987 struct ena_admin_set_feat_resp resp; 1988 struct ena_admin_get_feat_resp get_resp; 1989 int ret; 1990 1991 if (!ena_com_check_supported_feature_id(ena_dev, 1992 ENA_ADMIN_RSS_HASH_FUNCTION)) { 1993 pr_debug("Feature %d isn't supported\n", 1994 ENA_ADMIN_RSS_HASH_FUNCTION); 1995 return -EOPNOTSUPP; 1996 } 1997 1998 /* Validate hash function is supported */ 1999 ret = ena_com_get_feature(ena_dev, &get_resp, 2000 ENA_ADMIN_RSS_HASH_FUNCTION); 2001 if (unlikely(ret)) 2002 return ret; 2003 2004 if (get_resp.u.flow_hash_func.supported_func & (1 << rss->hash_func)) { 2005 pr_err("Func hash %d isn't supported by device, abort\n", 2006 rss->hash_func); 2007 return -EOPNOTSUPP; 2008 } 2009 2010 memset(&cmd, 0x0, sizeof(cmd)); 2011 2012 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2013 cmd.aq_common_descriptor.flags = 2014 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2015 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_FUNCTION; 2016 cmd.u.flow_hash_func.init_val = rss->hash_init_val; 2017 cmd.u.flow_hash_func.selected_func = 1 << rss->hash_func; 2018 2019 ret = ena_com_mem_addr_set(ena_dev, 2020 &cmd.control_buffer.address, 2021 rss->hash_key_dma_addr); 2022 if (unlikely(ret)) { 2023 pr_err("memory address set failed\n"); 2024 return ret; 2025 } 2026 2027 cmd.control_buffer.length = sizeof(*rss->hash_key); 2028 2029 ret = ena_com_execute_admin_command(admin_queue, 2030 (struct ena_admin_aq_entry *)&cmd, 2031 sizeof(cmd), 2032 (struct ena_admin_acq_entry *)&resp, 2033 sizeof(resp)); 2034 if (unlikely(ret)) { 2035 pr_err("Failed to set hash function %d. error: %d\n", 2036 rss->hash_func, ret); 2037 return -EINVAL; 2038 } 2039 2040 return 0; 2041 } 2042 2043 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, 2044 enum ena_admin_hash_functions func, 2045 const u8 *key, u16 key_len, u32 init_val) 2046 { 2047 struct ena_rss *rss = &ena_dev->rss; 2048 struct ena_admin_get_feat_resp get_resp; 2049 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2050 rss->hash_key; 2051 int rc; 2052 2053 /* Make sure size is a mult of DWs */ 2054 if (unlikely(key_len & 0x3)) 2055 return -EINVAL; 2056 2057 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2058 ENA_ADMIN_RSS_HASH_FUNCTION, 2059 rss->hash_key_dma_addr, 2060 sizeof(*rss->hash_key)); 2061 if (unlikely(rc)) 2062 return rc; 2063 2064 if (!((1 << func) & get_resp.u.flow_hash_func.supported_func)) { 2065 pr_err("Flow hash function %d isn't supported\n", func); 2066 return -EOPNOTSUPP; 2067 } 2068 2069 switch (func) { 2070 case ENA_ADMIN_TOEPLITZ: 2071 if (key_len > sizeof(hash_key->key)) { 2072 pr_err("key len (%hu) is bigger than the max supported (%zu)\n", 2073 key_len, sizeof(hash_key->key)); 2074 return -EINVAL; 2075 } 2076 2077 memcpy(hash_key->key, key, key_len); 2078 rss->hash_init_val = init_val; 2079 hash_key->keys_num = key_len >> 2; 2080 break; 2081 case ENA_ADMIN_CRC32: 2082 rss->hash_init_val = init_val; 2083 break; 2084 default: 2085 pr_err("Invalid hash function (%d)\n", func); 2086 return -EINVAL; 2087 } 2088 2089 rc = ena_com_set_hash_function(ena_dev); 2090 2091 /* Restore the old function */ 2092 if (unlikely(rc)) 2093 ena_com_get_hash_function(ena_dev, NULL, NULL); 2094 2095 return rc; 2096 } 2097 2098 int ena_com_get_hash_function(struct ena_com_dev *ena_dev, 2099 enum ena_admin_hash_functions *func, 2100 u8 *key) 2101 { 2102 struct ena_rss *rss = &ena_dev->rss; 2103 struct ena_admin_get_feat_resp get_resp; 2104 struct ena_admin_feature_rss_flow_hash_control *hash_key = 2105 rss->hash_key; 2106 int rc; 2107 2108 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2109 ENA_ADMIN_RSS_HASH_FUNCTION, 2110 rss->hash_key_dma_addr, 2111 sizeof(*rss->hash_key)); 2112 if (unlikely(rc)) 2113 return rc; 2114 2115 rss->hash_func = get_resp.u.flow_hash_func.selected_func; 2116 if (func) 2117 *func = rss->hash_func; 2118 2119 if (key) 2120 memcpy(key, hash_key->key, (size_t)(hash_key->keys_num) << 2); 2121 2122 return 0; 2123 } 2124 2125 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, 2126 enum ena_admin_flow_hash_proto proto, 2127 u16 *fields) 2128 { 2129 struct ena_rss *rss = &ena_dev->rss; 2130 struct ena_admin_get_feat_resp get_resp; 2131 int rc; 2132 2133 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2134 ENA_ADMIN_RSS_HASH_INPUT, 2135 rss->hash_ctrl_dma_addr, 2136 sizeof(*rss->hash_ctrl)); 2137 if (unlikely(rc)) 2138 return rc; 2139 2140 if (fields) 2141 *fields = rss->hash_ctrl->selected_fields[proto].fields; 2142 2143 return 0; 2144 } 2145 2146 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev) 2147 { 2148 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2149 struct ena_rss *rss = &ena_dev->rss; 2150 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2151 struct ena_admin_set_feat_cmd cmd; 2152 struct ena_admin_set_feat_resp resp; 2153 int ret; 2154 2155 if (!ena_com_check_supported_feature_id(ena_dev, 2156 ENA_ADMIN_RSS_HASH_INPUT)) { 2157 pr_debug("Feature %d isn't supported\n", 2158 ENA_ADMIN_RSS_HASH_INPUT); 2159 return -EOPNOTSUPP; 2160 } 2161 2162 memset(&cmd, 0x0, sizeof(cmd)); 2163 2164 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2165 cmd.aq_common_descriptor.flags = 2166 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2167 cmd.feat_common.feature_id = ENA_ADMIN_RSS_HASH_INPUT; 2168 cmd.u.flow_hash_input.enabled_input_sort = 2169 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK | 2170 ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; 2171 2172 ret = ena_com_mem_addr_set(ena_dev, 2173 &cmd.control_buffer.address, 2174 rss->hash_ctrl_dma_addr); 2175 if (unlikely(ret)) { 2176 pr_err("memory address set failed\n"); 2177 return ret; 2178 } 2179 cmd.control_buffer.length = sizeof(*hash_ctrl); 2180 2181 ret = ena_com_execute_admin_command(admin_queue, 2182 (struct ena_admin_aq_entry *)&cmd, 2183 sizeof(cmd), 2184 (struct ena_admin_acq_entry *)&resp, 2185 sizeof(resp)); 2186 if (unlikely(ret)) 2187 pr_err("Failed to set hash input. error: %d\n", ret); 2188 2189 return ret; 2190 } 2191 2192 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev) 2193 { 2194 struct ena_rss *rss = &ena_dev->rss; 2195 struct ena_admin_feature_rss_hash_control *hash_ctrl = 2196 rss->hash_ctrl; 2197 u16 available_fields = 0; 2198 int rc, i; 2199 2200 /* Get the supported hash input */ 2201 rc = ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2202 if (unlikely(rc)) 2203 return rc; 2204 2205 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP4].fields = 2206 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2207 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2208 2209 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP4].fields = 2210 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2211 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2212 2213 hash_ctrl->selected_fields[ENA_ADMIN_RSS_TCP6].fields = 2214 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2215 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2216 2217 hash_ctrl->selected_fields[ENA_ADMIN_RSS_UDP6].fields = 2218 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA | 2219 ENA_ADMIN_RSS_L4_DP | ENA_ADMIN_RSS_L4_SP; 2220 2221 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4].fields = 2222 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2223 2224 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP6].fields = 2225 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2226 2227 hash_ctrl->selected_fields[ENA_ADMIN_RSS_IP4_FRAG].fields = 2228 ENA_ADMIN_RSS_L3_SA | ENA_ADMIN_RSS_L3_DA; 2229 2230 hash_ctrl->selected_fields[ENA_ADMIN_RSS_NOT_IP].fields = 2231 ENA_ADMIN_RSS_L2_DA | ENA_ADMIN_RSS_L2_SA; 2232 2233 for (i = 0; i < ENA_ADMIN_RSS_PROTO_NUM; i++) { 2234 available_fields = hash_ctrl->selected_fields[i].fields & 2235 hash_ctrl->supported_fields[i].fields; 2236 if (available_fields != hash_ctrl->selected_fields[i].fields) { 2237 pr_err("hash control doesn't support all the desire configuration. proto %x supported %x selected %x\n", 2238 i, hash_ctrl->supported_fields[i].fields, 2239 hash_ctrl->selected_fields[i].fields); 2240 return -EOPNOTSUPP; 2241 } 2242 } 2243 2244 rc = ena_com_set_hash_ctrl(ena_dev); 2245 2246 /* In case of failure, restore the old hash ctrl */ 2247 if (unlikely(rc)) 2248 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2249 2250 return rc; 2251 } 2252 2253 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, 2254 enum ena_admin_flow_hash_proto proto, 2255 u16 hash_fields) 2256 { 2257 struct ena_rss *rss = &ena_dev->rss; 2258 struct ena_admin_feature_rss_hash_control *hash_ctrl = rss->hash_ctrl; 2259 u16 supported_fields; 2260 int rc; 2261 2262 if (proto >= ENA_ADMIN_RSS_PROTO_NUM) { 2263 pr_err("Invalid proto num (%u)\n", proto); 2264 return -EINVAL; 2265 } 2266 2267 /* Get the ctrl table */ 2268 rc = ena_com_get_hash_ctrl(ena_dev, proto, NULL); 2269 if (unlikely(rc)) 2270 return rc; 2271 2272 /* Make sure all the fields are supported */ 2273 supported_fields = hash_ctrl->supported_fields[proto].fields; 2274 if ((hash_fields & supported_fields) != hash_fields) { 2275 pr_err("proto %d doesn't support the required fields %x. supports only: %x\n", 2276 proto, hash_fields, supported_fields); 2277 } 2278 2279 hash_ctrl->selected_fields[proto].fields = hash_fields; 2280 2281 rc = ena_com_set_hash_ctrl(ena_dev); 2282 2283 /* In case of failure, restore the old hash ctrl */ 2284 if (unlikely(rc)) 2285 ena_com_get_hash_ctrl(ena_dev, 0, NULL); 2286 2287 return 0; 2288 } 2289 2290 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, 2291 u16 entry_idx, u16 entry_value) 2292 { 2293 struct ena_rss *rss = &ena_dev->rss; 2294 2295 if (unlikely(entry_idx >= (1 << rss->tbl_log_size))) 2296 return -EINVAL; 2297 2298 if (unlikely((entry_value > ENA_TOTAL_NUM_QUEUES))) 2299 return -EINVAL; 2300 2301 rss->host_rss_ind_tbl[entry_idx] = entry_value; 2302 2303 return 0; 2304 } 2305 2306 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev) 2307 { 2308 struct ena_com_admin_queue *admin_queue = &ena_dev->admin_queue; 2309 struct ena_rss *rss = &ena_dev->rss; 2310 struct ena_admin_set_feat_cmd cmd; 2311 struct ena_admin_set_feat_resp resp; 2312 int ret; 2313 2314 if (!ena_com_check_supported_feature_id( 2315 ena_dev, ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG)) { 2316 pr_debug("Feature %d isn't supported\n", 2317 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG); 2318 return -EOPNOTSUPP; 2319 } 2320 2321 ret = ena_com_ind_tbl_convert_to_device(ena_dev); 2322 if (ret) { 2323 pr_err("Failed to convert host indirection table to device table\n"); 2324 return ret; 2325 } 2326 2327 memset(&cmd, 0x0, sizeof(cmd)); 2328 2329 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2330 cmd.aq_common_descriptor.flags = 2331 ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 2332 cmd.feat_common.feature_id = ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG; 2333 cmd.u.ind_table.size = rss->tbl_log_size; 2334 cmd.u.ind_table.inline_index = 0xFFFFFFFF; 2335 2336 ret = ena_com_mem_addr_set(ena_dev, 2337 &cmd.control_buffer.address, 2338 rss->rss_ind_tbl_dma_addr); 2339 if (unlikely(ret)) { 2340 pr_err("memory address set failed\n"); 2341 return ret; 2342 } 2343 2344 cmd.control_buffer.length = (1ULL << rss->tbl_log_size) * 2345 sizeof(struct ena_admin_rss_ind_table_entry); 2346 2347 ret = ena_com_execute_admin_command(admin_queue, 2348 (struct ena_admin_aq_entry *)&cmd, 2349 sizeof(cmd), 2350 (struct ena_admin_acq_entry *)&resp, 2351 sizeof(resp)); 2352 2353 if (unlikely(ret)) 2354 pr_err("Failed to set indirect table. error: %d\n", ret); 2355 2356 return ret; 2357 } 2358 2359 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl) 2360 { 2361 struct ena_rss *rss = &ena_dev->rss; 2362 struct ena_admin_get_feat_resp get_resp; 2363 u32 tbl_size; 2364 int i, rc; 2365 2366 tbl_size = (1ULL << rss->tbl_log_size) * 2367 sizeof(struct ena_admin_rss_ind_table_entry); 2368 2369 rc = ena_com_get_feature_ex(ena_dev, &get_resp, 2370 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG, 2371 rss->rss_ind_tbl_dma_addr, 2372 tbl_size); 2373 if (unlikely(rc)) 2374 return rc; 2375 2376 if (!ind_tbl) 2377 return 0; 2378 2379 rc = ena_com_ind_tbl_convert_from_device(ena_dev); 2380 if (unlikely(rc)) 2381 return rc; 2382 2383 for (i = 0; i < (1 << rss->tbl_log_size); i++) 2384 ind_tbl[i] = rss->host_rss_ind_tbl[i]; 2385 2386 return 0; 2387 } 2388 2389 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 indr_tbl_log_size) 2390 { 2391 int rc; 2392 2393 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2394 2395 rc = ena_com_indirect_table_allocate(ena_dev, indr_tbl_log_size); 2396 if (unlikely(rc)) 2397 goto err_indr_tbl; 2398 2399 rc = ena_com_hash_key_allocate(ena_dev); 2400 if (unlikely(rc)) 2401 goto err_hash_key; 2402 2403 rc = ena_com_hash_ctrl_init(ena_dev); 2404 if (unlikely(rc)) 2405 goto err_hash_ctrl; 2406 2407 return 0; 2408 2409 err_hash_ctrl: 2410 ena_com_hash_key_destroy(ena_dev); 2411 err_hash_key: 2412 ena_com_indirect_table_destroy(ena_dev); 2413 err_indr_tbl: 2414 2415 return rc; 2416 } 2417 2418 void ena_com_rss_destroy(struct ena_com_dev *ena_dev) 2419 { 2420 ena_com_indirect_table_destroy(ena_dev); 2421 ena_com_hash_key_destroy(ena_dev); 2422 ena_com_hash_ctrl_destroy(ena_dev); 2423 2424 memset(&ena_dev->rss, 0x0, sizeof(ena_dev->rss)); 2425 } 2426 2427 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev) 2428 { 2429 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2430 2431 host_attr->host_info = 2432 dma_zalloc_coherent(ena_dev->dmadev, SZ_4K, 2433 &host_attr->host_info_dma_addr, GFP_KERNEL); 2434 if (unlikely(!host_attr->host_info)) 2435 return -ENOMEM; 2436 2437 return 0; 2438 } 2439 2440 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, 2441 u32 debug_area_size) 2442 { 2443 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2444 2445 host_attr->debug_area_virt_addr = 2446 dma_zalloc_coherent(ena_dev->dmadev, debug_area_size, 2447 &host_attr->debug_area_dma_addr, GFP_KERNEL); 2448 if (unlikely(!host_attr->debug_area_virt_addr)) { 2449 host_attr->debug_area_size = 0; 2450 return -ENOMEM; 2451 } 2452 2453 host_attr->debug_area_size = debug_area_size; 2454 2455 return 0; 2456 } 2457 2458 void ena_com_delete_host_info(struct ena_com_dev *ena_dev) 2459 { 2460 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2461 2462 if (host_attr->host_info) { 2463 dma_free_coherent(ena_dev->dmadev, SZ_4K, host_attr->host_info, 2464 host_attr->host_info_dma_addr); 2465 host_attr->host_info = NULL; 2466 } 2467 } 2468 2469 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev) 2470 { 2471 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2472 2473 if (host_attr->debug_area_virt_addr) { 2474 dma_free_coherent(ena_dev->dmadev, host_attr->debug_area_size, 2475 host_attr->debug_area_virt_addr, 2476 host_attr->debug_area_dma_addr); 2477 host_attr->debug_area_virt_addr = NULL; 2478 } 2479 } 2480 2481 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev) 2482 { 2483 struct ena_host_attribute *host_attr = &ena_dev->host_attr; 2484 struct ena_com_admin_queue *admin_queue; 2485 struct ena_admin_set_feat_cmd cmd; 2486 struct ena_admin_set_feat_resp resp; 2487 2488 int ret; 2489 2490 /* Host attribute config is called before ena_com_get_dev_attr_feat 2491 * so ena_com can't check if the feature is supported. 2492 */ 2493 2494 memset(&cmd, 0x0, sizeof(cmd)); 2495 admin_queue = &ena_dev->admin_queue; 2496 2497 cmd.aq_common_descriptor.opcode = ENA_ADMIN_SET_FEATURE; 2498 cmd.feat_common.feature_id = ENA_ADMIN_HOST_ATTR_CONFIG; 2499 2500 ret = ena_com_mem_addr_set(ena_dev, 2501 &cmd.u.host_attr.debug_ba, 2502 host_attr->debug_area_dma_addr); 2503 if (unlikely(ret)) { 2504 pr_err("memory address set failed\n"); 2505 return ret; 2506 } 2507 2508 ret = ena_com_mem_addr_set(ena_dev, 2509 &cmd.u.host_attr.os_info_ba, 2510 host_attr->host_info_dma_addr); 2511 if (unlikely(ret)) { 2512 pr_err("memory address set failed\n"); 2513 return ret; 2514 } 2515 2516 cmd.u.host_attr.debug_area_size = host_attr->debug_area_size; 2517 2518 ret = ena_com_execute_admin_command(admin_queue, 2519 (struct ena_admin_aq_entry *)&cmd, 2520 sizeof(cmd), 2521 (struct ena_admin_acq_entry *)&resp, 2522 sizeof(resp)); 2523 2524 if (unlikely(ret)) 2525 pr_err("Failed to set host attributes: %d\n", ret); 2526 2527 return ret; 2528 } 2529 2530 /* Interrupt moderation */ 2531 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev) 2532 { 2533 return ena_com_check_supported_feature_id(ena_dev, 2534 ENA_ADMIN_INTERRUPT_MODERATION); 2535 } 2536 2537 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, 2538 u32 tx_coalesce_usecs) 2539 { 2540 if (!ena_dev->intr_delay_resolution) { 2541 pr_err("Illegal interrupt delay granularity value\n"); 2542 return -EFAULT; 2543 } 2544 2545 ena_dev->intr_moder_tx_interval = tx_coalesce_usecs / 2546 ena_dev->intr_delay_resolution; 2547 2548 return 0; 2549 } 2550 2551 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, 2552 u32 rx_coalesce_usecs) 2553 { 2554 if (!ena_dev->intr_delay_resolution) { 2555 pr_err("Illegal interrupt delay granularity value\n"); 2556 return -EFAULT; 2557 } 2558 2559 /* We use LOWEST entry of moderation table for storing 2560 * nonadaptive interrupt coalescing values 2561 */ 2562 ena_dev->intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval = 2563 rx_coalesce_usecs / ena_dev->intr_delay_resolution; 2564 2565 return 0; 2566 } 2567 2568 void ena_com_destroy_interrupt_moderation(struct ena_com_dev *ena_dev) 2569 { 2570 if (ena_dev->intr_moder_tbl) 2571 devm_kfree(ena_dev->dmadev, ena_dev->intr_moder_tbl); 2572 ena_dev->intr_moder_tbl = NULL; 2573 } 2574 2575 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev) 2576 { 2577 struct ena_admin_get_feat_resp get_resp; 2578 u16 delay_resolution; 2579 int rc; 2580 2581 rc = ena_com_get_feature(ena_dev, &get_resp, 2582 ENA_ADMIN_INTERRUPT_MODERATION); 2583 2584 if (rc) { 2585 if (rc == -EOPNOTSUPP) { 2586 pr_debug("Feature %d isn't supported\n", 2587 ENA_ADMIN_INTERRUPT_MODERATION); 2588 rc = 0; 2589 } else { 2590 pr_err("Failed to get interrupt moderation admin cmd. rc: %d\n", 2591 rc); 2592 } 2593 2594 /* no moderation supported, disable adaptive support */ 2595 ena_com_disable_adaptive_moderation(ena_dev); 2596 return rc; 2597 } 2598 2599 rc = ena_com_init_interrupt_moderation_table(ena_dev); 2600 if (rc) 2601 goto err; 2602 2603 /* if moderation is supported by device we set adaptive moderation */ 2604 delay_resolution = get_resp.u.intr_moderation.intr_delay_resolution; 2605 ena_com_update_intr_delay_resolution(ena_dev, delay_resolution); 2606 ena_com_enable_adaptive_moderation(ena_dev); 2607 2608 return 0; 2609 err: 2610 ena_com_destroy_interrupt_moderation(ena_dev); 2611 return rc; 2612 } 2613 2614 void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev) 2615 { 2616 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2617 2618 if (!intr_moder_tbl) 2619 return; 2620 2621 intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval = 2622 ENA_INTR_LOWEST_USECS; 2623 intr_moder_tbl[ENA_INTR_MODER_LOWEST].pkts_per_interval = 2624 ENA_INTR_LOWEST_PKTS; 2625 intr_moder_tbl[ENA_INTR_MODER_LOWEST].bytes_per_interval = 2626 ENA_INTR_LOWEST_BYTES; 2627 2628 intr_moder_tbl[ENA_INTR_MODER_LOW].intr_moder_interval = 2629 ENA_INTR_LOW_USECS; 2630 intr_moder_tbl[ENA_INTR_MODER_LOW].pkts_per_interval = 2631 ENA_INTR_LOW_PKTS; 2632 intr_moder_tbl[ENA_INTR_MODER_LOW].bytes_per_interval = 2633 ENA_INTR_LOW_BYTES; 2634 2635 intr_moder_tbl[ENA_INTR_MODER_MID].intr_moder_interval = 2636 ENA_INTR_MID_USECS; 2637 intr_moder_tbl[ENA_INTR_MODER_MID].pkts_per_interval = 2638 ENA_INTR_MID_PKTS; 2639 intr_moder_tbl[ENA_INTR_MODER_MID].bytes_per_interval = 2640 ENA_INTR_MID_BYTES; 2641 2642 intr_moder_tbl[ENA_INTR_MODER_HIGH].intr_moder_interval = 2643 ENA_INTR_HIGH_USECS; 2644 intr_moder_tbl[ENA_INTR_MODER_HIGH].pkts_per_interval = 2645 ENA_INTR_HIGH_PKTS; 2646 intr_moder_tbl[ENA_INTR_MODER_HIGH].bytes_per_interval = 2647 ENA_INTR_HIGH_BYTES; 2648 2649 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].intr_moder_interval = 2650 ENA_INTR_HIGHEST_USECS; 2651 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].pkts_per_interval = 2652 ENA_INTR_HIGHEST_PKTS; 2653 intr_moder_tbl[ENA_INTR_MODER_HIGHEST].bytes_per_interval = 2654 ENA_INTR_HIGHEST_BYTES; 2655 } 2656 2657 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev) 2658 { 2659 return ena_dev->intr_moder_tx_interval; 2660 } 2661 2662 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev) 2663 { 2664 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2665 2666 if (intr_moder_tbl) 2667 return intr_moder_tbl[ENA_INTR_MODER_LOWEST].intr_moder_interval; 2668 2669 return 0; 2670 } 2671 2672 void ena_com_init_intr_moderation_entry(struct ena_com_dev *ena_dev, 2673 enum ena_intr_moder_level level, 2674 struct ena_intr_moder_entry *entry) 2675 { 2676 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2677 2678 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS) 2679 return; 2680 2681 intr_moder_tbl[level].intr_moder_interval = entry->intr_moder_interval; 2682 if (ena_dev->intr_delay_resolution) 2683 intr_moder_tbl[level].intr_moder_interval /= 2684 ena_dev->intr_delay_resolution; 2685 intr_moder_tbl[level].pkts_per_interval = entry->pkts_per_interval; 2686 2687 /* use hardcoded value until ethtool supports bytecount parameter */ 2688 if (entry->bytes_per_interval != ENA_INTR_BYTE_COUNT_NOT_SUPPORTED) 2689 intr_moder_tbl[level].bytes_per_interval = entry->bytes_per_interval; 2690 } 2691 2692 void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev, 2693 enum ena_intr_moder_level level, 2694 struct ena_intr_moder_entry *entry) 2695 { 2696 struct ena_intr_moder_entry *intr_moder_tbl = ena_dev->intr_moder_tbl; 2697 2698 if (level >= ENA_INTR_MAX_NUM_OF_LEVELS) 2699 return; 2700 2701 entry->intr_moder_interval = intr_moder_tbl[level].intr_moder_interval; 2702 if (ena_dev->intr_delay_resolution) 2703 entry->intr_moder_interval *= ena_dev->intr_delay_resolution; 2704 entry->pkts_per_interval = 2705 intr_moder_tbl[level].pkts_per_interval; 2706 entry->bytes_per_interval = intr_moder_tbl[level].bytes_per_interval; 2707 } 2708