1 /* 2 * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef _ENA_ADMIN_H_ 33 #define _ENA_ADMIN_H_ 34 35 36 enum ena_admin_aq_opcode { 37 ENA_ADMIN_CREATE_SQ = 1, 38 ENA_ADMIN_DESTROY_SQ = 2, 39 ENA_ADMIN_CREATE_CQ = 3, 40 ENA_ADMIN_DESTROY_CQ = 4, 41 ENA_ADMIN_GET_FEATURE = 8, 42 ENA_ADMIN_SET_FEATURE = 9, 43 ENA_ADMIN_GET_STATS = 11, 44 }; 45 46 enum ena_admin_aq_completion_status { 47 ENA_ADMIN_SUCCESS = 0, 48 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 49 ENA_ADMIN_BAD_OPCODE = 2, 50 ENA_ADMIN_UNSUPPORTED_OPCODE = 3, 51 ENA_ADMIN_MALFORMED_REQUEST = 4, 52 /* Additional status is provided in ACQ entry extended_status */ 53 ENA_ADMIN_ILLEGAL_PARAMETER = 5, 54 ENA_ADMIN_UNKNOWN_ERROR = 6, 55 ENA_ADMIN_RESOURCE_BUSY = 7, 56 }; 57 58 enum ena_admin_aq_feature_id { 59 ENA_ADMIN_DEVICE_ATTRIBUTES = 1, 60 ENA_ADMIN_MAX_QUEUES_NUM = 2, 61 ENA_ADMIN_HW_HINTS = 3, 62 ENA_ADMIN_LLQ = 4, 63 ENA_ADMIN_MAX_QUEUES_EXT = 7, 64 ENA_ADMIN_RSS_HASH_FUNCTION = 10, 65 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, 66 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12, 67 ENA_ADMIN_MTU = 14, 68 ENA_ADMIN_RSS_HASH_INPUT = 18, 69 ENA_ADMIN_INTERRUPT_MODERATION = 20, 70 ENA_ADMIN_AENQ_CONFIG = 26, 71 ENA_ADMIN_LINK_CONFIG = 27, 72 ENA_ADMIN_HOST_ATTR_CONFIG = 28, 73 ENA_ADMIN_FEATURES_OPCODE_NUM = 32, 74 }; 75 76 enum ena_admin_placement_policy_type { 77 /* descriptors and headers are in host memory */ 78 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, 79 /* descriptors and headers are in device memory (a.k.a Low Latency 80 * Queue) 81 */ 82 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, 83 }; 84 85 enum ena_admin_link_types { 86 ENA_ADMIN_LINK_SPEED_1G = 0x1, 87 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, 88 ENA_ADMIN_LINK_SPEED_5G = 0x4, 89 ENA_ADMIN_LINK_SPEED_10G = 0x8, 90 ENA_ADMIN_LINK_SPEED_25G = 0x10, 91 ENA_ADMIN_LINK_SPEED_40G = 0x20, 92 ENA_ADMIN_LINK_SPEED_50G = 0x40, 93 ENA_ADMIN_LINK_SPEED_100G = 0x80, 94 ENA_ADMIN_LINK_SPEED_200G = 0x100, 95 ENA_ADMIN_LINK_SPEED_400G = 0x200, 96 }; 97 98 enum ena_admin_completion_policy_type { 99 /* completion queue entry for each sq descriptor */ 100 ENA_ADMIN_COMPLETION_POLICY_DESC = 0, 101 /* completion queue entry upon request in sq descriptor */ 102 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 103 /* current queue head pointer is updated in OS memory upon sq 104 * descriptor request 105 */ 106 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 107 /* current queue head pointer is updated in OS memory for each sq 108 * descriptor 109 */ 110 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, 111 }; 112 113 /* basic stats return ena_admin_basic_stats while extanded stats return a 114 * buffer (string format) with additional statistics per queue and per 115 * device id 116 */ 117 enum ena_admin_get_stats_type { 118 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, 119 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, 120 }; 121 122 enum ena_admin_get_stats_scope { 123 ENA_ADMIN_SPECIFIC_QUEUE = 0, 124 ENA_ADMIN_ETH_TRAFFIC = 1, 125 }; 126 127 struct ena_admin_aq_common_desc { 128 /* 11:0 : command_id 129 * 15:12 : reserved12 130 */ 131 u16 command_id; 132 133 /* as appears in ena_admin_aq_opcode */ 134 u8 opcode; 135 136 /* 0 : phase 137 * 1 : ctrl_data - control buffer address valid 138 * 2 : ctrl_data_indirect - control buffer address 139 * points to list of pages with addresses of control 140 * buffers 141 * 7:3 : reserved3 142 */ 143 u8 flags; 144 }; 145 146 /* used in ena_admin_aq_entry. Can point directly to control data, or to a 147 * page list chunk. Used also at the end of indirect mode page list chunks, 148 * for chaining. 149 */ 150 struct ena_admin_ctrl_buff_info { 151 u32 length; 152 153 struct ena_common_mem_addr address; 154 }; 155 156 struct ena_admin_sq { 157 u16 sq_idx; 158 159 /* 4:0 : reserved 160 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx 161 */ 162 u8 sq_identity; 163 164 u8 reserved1; 165 }; 166 167 struct ena_admin_aq_entry { 168 struct ena_admin_aq_common_desc aq_common_descriptor; 169 170 union { 171 u32 inline_data_w1[3]; 172 173 struct ena_admin_ctrl_buff_info control_buffer; 174 } u; 175 176 u32 inline_data_w4[12]; 177 }; 178 179 struct ena_admin_acq_common_desc { 180 /* command identifier to associate it with the aq descriptor 181 * 11:0 : command_id 182 * 15:12 : reserved12 183 */ 184 u16 command; 185 186 u8 status; 187 188 /* 0 : phase 189 * 7:1 : reserved1 190 */ 191 u8 flags; 192 193 u16 extended_status; 194 195 /* indicates to the driver which AQ entry has been consumed by the 196 * device and could be reused 197 */ 198 u16 sq_head_indx; 199 }; 200 201 struct ena_admin_acq_entry { 202 struct ena_admin_acq_common_desc acq_common_descriptor; 203 204 u32 response_specific_data[14]; 205 }; 206 207 struct ena_admin_aq_create_sq_cmd { 208 struct ena_admin_aq_common_desc aq_common_descriptor; 209 210 /* 4:0 : reserved0_w1 211 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx 212 */ 213 u8 sq_identity; 214 215 u8 reserved8_w1; 216 217 /* 3:0 : placement_policy - Describing where the SQ 218 * descriptor ring and the SQ packet headers reside: 219 * 0x1 - descriptors and headers are in OS memory, 220 * 0x3 - descriptors and headers in device memory 221 * (a.k.a Low Latency Queue) 222 * 6:4 : completion_policy - Describing what policy 223 * to use for generation completion entry (cqe) in 224 * the CQ associated with this SQ: 0x0 - cqe for each 225 * sq descriptor, 0x1 - cqe upon request in sq 226 * descriptor, 0x2 - current queue head pointer is 227 * updated in OS memory upon sq descriptor request 228 * 0x3 - current queue head pointer is updated in OS 229 * memory for each sq descriptor 230 * 7 : reserved15_w1 231 */ 232 u8 sq_caps_2; 233 234 /* 0 : is_physically_contiguous - Described if the 235 * queue ring memory is allocated in physical 236 * contiguous pages or split. 237 * 7:1 : reserved17_w1 238 */ 239 u8 sq_caps_3; 240 241 /* associated completion queue id. This CQ must be created prior to 242 * SQ creation 243 */ 244 u16 cq_idx; 245 246 /* submission queue depth in entries */ 247 u16 sq_depth; 248 249 /* SQ physical base address in OS memory. This field should not be 250 * used for Low Latency queues. Has to be page aligned. 251 */ 252 struct ena_common_mem_addr sq_ba; 253 254 /* specifies queue head writeback location in OS memory. Valid if 255 * completion_policy is set to completion_policy_head_on_demand or 256 * completion_policy_head. Has to be cache aligned 257 */ 258 struct ena_common_mem_addr sq_head_writeback; 259 260 u32 reserved0_w7; 261 262 u32 reserved0_w8; 263 }; 264 265 enum ena_admin_sq_direction { 266 ENA_ADMIN_SQ_DIRECTION_TX = 1, 267 ENA_ADMIN_SQ_DIRECTION_RX = 2, 268 }; 269 270 struct ena_admin_acq_create_sq_resp_desc { 271 struct ena_admin_acq_common_desc acq_common_desc; 272 273 u16 sq_idx; 274 275 u16 reserved; 276 277 /* queue doorbell address as an offset to PCIe MMIO REG BAR */ 278 u32 sq_doorbell_offset; 279 280 /* low latency queue ring base address as an offset to PCIe MMIO 281 * LLQ_MEM BAR 282 */ 283 u32 llq_descriptors_offset; 284 285 /* low latency queue headers' memory as an offset to PCIe MMIO 286 * LLQ_MEM BAR 287 */ 288 u32 llq_headers_offset; 289 }; 290 291 struct ena_admin_aq_destroy_sq_cmd { 292 struct ena_admin_aq_common_desc aq_common_descriptor; 293 294 struct ena_admin_sq sq; 295 }; 296 297 struct ena_admin_acq_destroy_sq_resp_desc { 298 struct ena_admin_acq_common_desc acq_common_desc; 299 }; 300 301 struct ena_admin_aq_create_cq_cmd { 302 struct ena_admin_aq_common_desc aq_common_descriptor; 303 304 /* 4:0 : reserved5 305 * 5 : interrupt_mode_enabled - if set, cq operates 306 * in interrupt mode, otherwise - polling 307 * 7:6 : reserved6 308 */ 309 u8 cq_caps_1; 310 311 /* 4:0 : cq_entry_size_words - size of CQ entry in 312 * 32-bit words, valid values: 4, 8. 313 * 7:5 : reserved7 314 */ 315 u8 cq_caps_2; 316 317 /* completion queue depth in # of entries. must be power of 2 */ 318 u16 cq_depth; 319 320 /* msix vector assigned to this cq */ 321 u32 msix_vector; 322 323 /* cq physical base address in OS memory. CQ must be physically 324 * contiguous 325 */ 326 struct ena_common_mem_addr cq_ba; 327 }; 328 329 struct ena_admin_acq_create_cq_resp_desc { 330 struct ena_admin_acq_common_desc acq_common_desc; 331 332 u16 cq_idx; 333 334 /* actual cq depth in number of entries */ 335 u16 cq_actual_depth; 336 337 u32 numa_node_register_offset; 338 339 u32 cq_head_db_register_offset; 340 341 u32 cq_interrupt_unmask_register_offset; 342 }; 343 344 struct ena_admin_aq_destroy_cq_cmd { 345 struct ena_admin_aq_common_desc aq_common_descriptor; 346 347 u16 cq_idx; 348 349 u16 reserved1; 350 }; 351 352 struct ena_admin_acq_destroy_cq_resp_desc { 353 struct ena_admin_acq_common_desc acq_common_desc; 354 }; 355 356 /* ENA AQ Get Statistics command. Extended statistics are placed in control 357 * buffer pointed by AQ entry 358 */ 359 struct ena_admin_aq_get_stats_cmd { 360 struct ena_admin_aq_common_desc aq_common_descriptor; 361 362 union { 363 /* command specific inline data */ 364 u32 inline_data_w1[3]; 365 366 struct ena_admin_ctrl_buff_info control_buffer; 367 } u; 368 369 /* stats type as defined in enum ena_admin_get_stats_type */ 370 u8 type; 371 372 /* stats scope defined in enum ena_admin_get_stats_scope */ 373 u8 scope; 374 375 u16 reserved3; 376 377 /* queue id. used when scope is specific_queue */ 378 u16 queue_idx; 379 380 /* device id, value 0xFFFF means mine. only privileged device can get 381 * stats of other device 382 */ 383 u16 device_id; 384 }; 385 386 /* Basic Statistics Command. */ 387 struct ena_admin_basic_stats { 388 u32 tx_bytes_low; 389 390 u32 tx_bytes_high; 391 392 u32 tx_pkts_low; 393 394 u32 tx_pkts_high; 395 396 u32 rx_bytes_low; 397 398 u32 rx_bytes_high; 399 400 u32 rx_pkts_low; 401 402 u32 rx_pkts_high; 403 404 u32 rx_drops_low; 405 406 u32 rx_drops_high; 407 408 u32 tx_drops_low; 409 410 u32 tx_drops_high; 411 }; 412 413 struct ena_admin_acq_get_stats_resp { 414 struct ena_admin_acq_common_desc acq_common_desc; 415 416 struct ena_admin_basic_stats basic_stats; 417 }; 418 419 struct ena_admin_get_set_feature_common_desc { 420 /* 1:0 : select - 0x1 - current value; 0x3 - default 421 * value 422 * 7:3 : reserved3 423 */ 424 u8 flags; 425 426 /* as appears in ena_admin_aq_feature_id */ 427 u8 feature_id; 428 429 /* The driver specifies the max feature version it supports and the 430 * device responds with the currently supported feature version. The 431 * field is zero based 432 */ 433 u8 feature_version; 434 435 u8 reserved8; 436 }; 437 438 struct ena_admin_device_attr_feature_desc { 439 u32 impl_id; 440 441 u32 device_version; 442 443 /* bitmap of ena_admin_aq_feature_id */ 444 u32 supported_features; 445 446 u32 reserved3; 447 448 /* Indicates how many bits are used physical address access. */ 449 u32 phys_addr_width; 450 451 /* Indicates how many bits are used virtual address access. */ 452 u32 virt_addr_width; 453 454 /* unicast MAC address (in Network byte order) */ 455 u8 mac_addr[6]; 456 457 u8 reserved7[2]; 458 459 u32 max_mtu; 460 }; 461 462 enum ena_admin_llq_header_location { 463 /* header is in descriptor list */ 464 ENA_ADMIN_INLINE_HEADER = 1, 465 /* header in a separate ring, implies 16B descriptor list entry */ 466 ENA_ADMIN_HEADER_RING = 2, 467 }; 468 469 enum ena_admin_llq_ring_entry_size { 470 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1, 471 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2, 472 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4, 473 }; 474 475 enum ena_admin_llq_num_descs_before_header { 476 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0, 477 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1, 478 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2, 479 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4, 480 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8, 481 }; 482 483 /* packet descriptor list entry always starts with one or more descriptors, 484 * followed by a header. The rest of the descriptors are located in the 485 * beginning of the subsequent entry. Stride refers to how the rest of the 486 * descriptors are placed. This field is relevant only for inline header 487 * mode 488 */ 489 enum ena_admin_llq_stride_ctrl { 490 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1, 491 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, 492 }; 493 494 enum ena_admin_accel_mode_feat { 495 ENA_ADMIN_DISABLE_META_CACHING = 0, 496 ENA_ADMIN_LIMIT_TX_BURST = 1, 497 }; 498 499 struct ena_admin_accel_mode_get { 500 /* bit field of enum ena_admin_accel_mode_feat */ 501 u16 supported_flags; 502 503 /* maximum burst size between two doorbells. The size is in bytes */ 504 u16 max_tx_burst_size; 505 }; 506 507 struct ena_admin_accel_mode_set { 508 /* bit field of enum ena_admin_accel_mode_feat */ 509 u16 enabled_flags; 510 511 u16 reserved; 512 }; 513 514 struct ena_admin_accel_mode_req { 515 union { 516 u32 raw[2]; 517 518 struct ena_admin_accel_mode_get get; 519 520 struct ena_admin_accel_mode_set set; 521 } u; 522 }; 523 524 struct ena_admin_feature_llq_desc { 525 u32 max_llq_num; 526 527 u32 max_llq_depth; 528 529 /* specify the header locations the device supports. bitfield of 530 * enum ena_admin_llq_header_location. 531 */ 532 u16 header_location_ctrl_supported; 533 534 /* the header location the driver selected to use. */ 535 u16 header_location_ctrl_enabled; 536 537 /* if inline header is specified - this is the size of descriptor 538 * list entry. If header in a separate ring is specified - this is 539 * the size of header ring entry. bitfield of enum 540 * ena_admin_llq_ring_entry_size. specify the entry sizes the device 541 * supports 542 */ 543 u16 entry_size_ctrl_supported; 544 545 /* the entry size the driver selected to use. */ 546 u16 entry_size_ctrl_enabled; 547 548 /* valid only if inline header is specified. First entry associated 549 * with the packet includes descriptors and header. Rest of the 550 * entries occupied by descriptors. This parameter defines the max 551 * number of descriptors precedding the header in the first entry. 552 * The field is bitfield of enum 553 * ena_admin_llq_num_descs_before_header and specify the values the 554 * device supports 555 */ 556 u16 desc_num_before_header_supported; 557 558 /* the desire field the driver selected to use */ 559 u16 desc_num_before_header_enabled; 560 561 /* valid only if inline was chosen. bitfield of enum 562 * ena_admin_llq_stride_ctrl 563 */ 564 u16 descriptors_stride_ctrl_supported; 565 566 /* the stride control the driver selected to use */ 567 u16 descriptors_stride_ctrl_enabled; 568 569 /* reserved */ 570 u32 reserved1; 571 572 /* accelerated low latency queues requirement. driver needs to 573 * support those requirements in order to use accelerated llq 574 */ 575 struct ena_admin_accel_mode_req accel_mode; 576 }; 577 578 struct ena_admin_queue_ext_feature_fields { 579 u32 max_tx_sq_num; 580 581 u32 max_tx_cq_num; 582 583 u32 max_rx_sq_num; 584 585 u32 max_rx_cq_num; 586 587 u32 max_tx_sq_depth; 588 589 u32 max_tx_cq_depth; 590 591 u32 max_rx_sq_depth; 592 593 u32 max_rx_cq_depth; 594 595 u32 max_tx_header_size; 596 597 /* Maximum Descriptors number, including meta descriptor, allowed for 598 * a single Tx packet 599 */ 600 u16 max_per_packet_tx_descs; 601 602 /* Maximum Descriptors number allowed for a single Rx packet */ 603 u16 max_per_packet_rx_descs; 604 }; 605 606 struct ena_admin_queue_feature_desc { 607 u32 max_sq_num; 608 609 u32 max_sq_depth; 610 611 u32 max_cq_num; 612 613 u32 max_cq_depth; 614 615 u32 max_legacy_llq_num; 616 617 u32 max_legacy_llq_depth; 618 619 u32 max_header_size; 620 621 /* Maximum Descriptors number, including meta descriptor, allowed for 622 * a single Tx packet 623 */ 624 u16 max_packet_tx_descs; 625 626 /* Maximum Descriptors number allowed for a single Rx packet */ 627 u16 max_packet_rx_descs; 628 }; 629 630 struct ena_admin_set_feature_mtu_desc { 631 /* exclude L2 */ 632 u32 mtu; 633 }; 634 635 struct ena_admin_set_feature_host_attr_desc { 636 /* host OS info base address in OS memory. host info is 4KB of 637 * physically contiguous 638 */ 639 struct ena_common_mem_addr os_info_ba; 640 641 /* host debug area base address in OS memory. debug area must be 642 * physically contiguous 643 */ 644 struct ena_common_mem_addr debug_ba; 645 646 /* debug area size */ 647 u32 debug_area_size; 648 }; 649 650 struct ena_admin_feature_intr_moder_desc { 651 /* interrupt delay granularity in usec */ 652 u16 intr_delay_resolution; 653 654 u16 reserved; 655 }; 656 657 struct ena_admin_get_feature_link_desc { 658 /* Link speed in Mb */ 659 u32 speed; 660 661 /* bit field of enum ena_admin_link types */ 662 u32 supported; 663 664 /* 0 : autoneg 665 * 1 : duplex - Full Duplex 666 * 31:2 : reserved2 667 */ 668 u32 flags; 669 }; 670 671 struct ena_admin_feature_aenq_desc { 672 /* bitmask for AENQ groups the device can report */ 673 u32 supported_groups; 674 675 /* bitmask for AENQ groups to report */ 676 u32 enabled_groups; 677 }; 678 679 struct ena_admin_feature_offload_desc { 680 /* 0 : TX_L3_csum_ipv4 681 * 1 : TX_L4_ipv4_csum_part - The checksum field 682 * should be initialized with pseudo header checksum 683 * 2 : TX_L4_ipv4_csum_full 684 * 3 : TX_L4_ipv6_csum_part - The checksum field 685 * should be initialized with pseudo header checksum 686 * 4 : TX_L4_ipv6_csum_full 687 * 5 : tso_ipv4 688 * 6 : tso_ipv6 689 * 7 : tso_ecn 690 */ 691 u32 tx; 692 693 /* Receive side supported stateless offload 694 * 0 : RX_L3_csum_ipv4 - IPv4 checksum 695 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum 696 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum 697 * 3 : RX_hash - Hash calculation 698 */ 699 u32 rx_supported; 700 701 u32 rx_enabled; 702 }; 703 704 enum ena_admin_hash_functions { 705 ENA_ADMIN_TOEPLITZ = 1, 706 ENA_ADMIN_CRC32 = 2, 707 }; 708 709 struct ena_admin_feature_rss_flow_hash_control { 710 u32 keys_num; 711 712 u32 reserved; 713 714 u32 key[10]; 715 }; 716 717 struct ena_admin_feature_rss_flow_hash_function { 718 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */ 719 u32 supported_func; 720 721 /* 7:0 : selected_func - bitmask of 722 * ena_admin_hash_functions 723 */ 724 u32 selected_func; 725 726 /* initial value */ 727 u32 init_val; 728 }; 729 730 /* RSS flow hash protocols */ 731 enum ena_admin_flow_hash_proto { 732 ENA_ADMIN_RSS_TCP4 = 0, 733 ENA_ADMIN_RSS_UDP4 = 1, 734 ENA_ADMIN_RSS_TCP6 = 2, 735 ENA_ADMIN_RSS_UDP6 = 3, 736 ENA_ADMIN_RSS_IP4 = 4, 737 ENA_ADMIN_RSS_IP6 = 5, 738 ENA_ADMIN_RSS_IP4_FRAG = 6, 739 ENA_ADMIN_RSS_NOT_IP = 7, 740 /* TCPv6 with extension header */ 741 ENA_ADMIN_RSS_TCP6_EX = 8, 742 /* IPv6 with extension header */ 743 ENA_ADMIN_RSS_IP6_EX = 9, 744 ENA_ADMIN_RSS_PROTO_NUM = 16, 745 }; 746 747 /* RSS flow hash fields */ 748 enum ena_admin_flow_hash_fields { 749 /* Ethernet Dest Addr */ 750 ENA_ADMIN_RSS_L2_DA = BIT(0), 751 /* Ethernet Src Addr */ 752 ENA_ADMIN_RSS_L2_SA = BIT(1), 753 /* ipv4/6 Dest Addr */ 754 ENA_ADMIN_RSS_L3_DA = BIT(2), 755 /* ipv4/6 Src Addr */ 756 ENA_ADMIN_RSS_L3_SA = BIT(3), 757 /* tcp/udp Dest Port */ 758 ENA_ADMIN_RSS_L4_DP = BIT(4), 759 /* tcp/udp Src Port */ 760 ENA_ADMIN_RSS_L4_SP = BIT(5), 761 }; 762 763 struct ena_admin_proto_input { 764 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ 765 u16 fields; 766 767 u16 reserved2; 768 }; 769 770 struct ena_admin_feature_rss_hash_control { 771 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM]; 772 773 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM]; 774 775 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM]; 776 777 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM]; 778 }; 779 780 struct ena_admin_feature_rss_flow_hash_input { 781 /* supported hash input sorting 782 * 1 : L3_sort - support swap L3 addresses if DA is 783 * smaller than SA 784 * 2 : L4_sort - support swap L4 ports if DP smaller 785 * SP 786 */ 787 u16 supported_input_sort; 788 789 /* enabled hash input sorting 790 * 1 : enable_L3_sort - enable swap L3 addresses if 791 * DA smaller than SA 792 * 2 : enable_L4_sort - enable swap L4 ports if DP 793 * smaller than SP 794 */ 795 u16 enabled_input_sort; 796 }; 797 798 enum ena_admin_os_type { 799 ENA_ADMIN_OS_LINUX = 1, 800 ENA_ADMIN_OS_WIN = 2, 801 ENA_ADMIN_OS_DPDK = 3, 802 ENA_ADMIN_OS_FREEBSD = 4, 803 ENA_ADMIN_OS_IPXE = 5, 804 ENA_ADMIN_OS_ESXI = 6, 805 ENA_ADMIN_OS_GROUPS_NUM = 6, 806 }; 807 808 struct ena_admin_host_info { 809 /* defined in enum ena_admin_os_type */ 810 u32 os_type; 811 812 /* os distribution string format */ 813 u8 os_dist_str[128]; 814 815 /* OS distribution numeric format */ 816 u32 os_dist; 817 818 /* kernel version string format */ 819 u8 kernel_ver_str[32]; 820 821 /* Kernel version numeric format */ 822 u32 kernel_ver; 823 824 /* 7:0 : major 825 * 15:8 : minor 826 * 23:16 : sub_minor 827 * 31:24 : module_type 828 */ 829 u32 driver_version; 830 831 /* features bitmap */ 832 u32 supported_network_features[2]; 833 834 /* ENA spec version of driver */ 835 u16 ena_spec_version; 836 837 /* ENA device's Bus, Device and Function 838 * 2:0 : function 839 * 7:3 : device 840 * 15:8 : bus 841 */ 842 u16 bdf; 843 844 /* Number of CPUs */ 845 u16 num_cpus; 846 847 u16 reserved; 848 849 /* 0 : reserved 850 * 1 : rx_offset 851 * 2 : interrupt_moderation 852 * 3 : rx_buf_mirroring 853 * 4 : rss_configurable_function_key 854 * 31:5 : reserved 855 */ 856 u32 driver_supported_features; 857 }; 858 859 struct ena_admin_rss_ind_table_entry { 860 u16 cq_idx; 861 862 u16 reserved; 863 }; 864 865 struct ena_admin_feature_rss_ind_table { 866 /* min supported table size (2^min_size) */ 867 u16 min_size; 868 869 /* max supported table size (2^max_size) */ 870 u16 max_size; 871 872 /* table size (2^size) */ 873 u16 size; 874 875 u16 reserved; 876 877 /* index of the inline entry. 0xFFFFFFFF means invalid */ 878 u32 inline_index; 879 880 /* used for updating single entry, ignored when setting the entire 881 * table through the control buffer. 882 */ 883 struct ena_admin_rss_ind_table_entry inline_entry; 884 }; 885 886 /* When hint value is 0, driver should use it's own predefined value */ 887 struct ena_admin_ena_hw_hints { 888 /* value in ms */ 889 u16 mmio_read_timeout; 890 891 /* value in ms */ 892 u16 driver_watchdog_timeout; 893 894 /* Per packet tx completion timeout. value in ms */ 895 u16 missing_tx_completion_timeout; 896 897 u16 missed_tx_completion_count_threshold_to_reset; 898 899 /* value in ms */ 900 u16 admin_completion_tx_timeout; 901 902 u16 netdev_wd_timeout; 903 904 u16 max_tx_sgl_size; 905 906 u16 max_rx_sgl_size; 907 908 u16 reserved[8]; 909 }; 910 911 struct ena_admin_get_feat_cmd { 912 struct ena_admin_aq_common_desc aq_common_descriptor; 913 914 struct ena_admin_ctrl_buff_info control_buffer; 915 916 struct ena_admin_get_set_feature_common_desc feat_common; 917 918 u32 raw[11]; 919 }; 920 921 struct ena_admin_queue_ext_feature_desc { 922 /* version */ 923 u8 version; 924 925 u8 reserved1[3]; 926 927 union { 928 struct ena_admin_queue_ext_feature_fields max_queue_ext; 929 930 u32 raw[10]; 931 }; 932 }; 933 934 struct ena_admin_get_feat_resp { 935 struct ena_admin_acq_common_desc acq_common_desc; 936 937 union { 938 u32 raw[14]; 939 940 struct ena_admin_device_attr_feature_desc dev_attr; 941 942 struct ena_admin_feature_llq_desc llq; 943 944 struct ena_admin_queue_feature_desc max_queue; 945 946 struct ena_admin_queue_ext_feature_desc max_queue_ext; 947 948 struct ena_admin_feature_aenq_desc aenq; 949 950 struct ena_admin_get_feature_link_desc link; 951 952 struct ena_admin_feature_offload_desc offload; 953 954 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 955 956 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 957 958 struct ena_admin_feature_rss_ind_table ind_table; 959 960 struct ena_admin_feature_intr_moder_desc intr_moderation; 961 962 struct ena_admin_ena_hw_hints hw_hints; 963 } u; 964 }; 965 966 struct ena_admin_set_feat_cmd { 967 struct ena_admin_aq_common_desc aq_common_descriptor; 968 969 struct ena_admin_ctrl_buff_info control_buffer; 970 971 struct ena_admin_get_set_feature_common_desc feat_common; 972 973 union { 974 u32 raw[11]; 975 976 /* mtu size */ 977 struct ena_admin_set_feature_mtu_desc mtu; 978 979 /* host attributes */ 980 struct ena_admin_set_feature_host_attr_desc host_attr; 981 982 /* AENQ configuration */ 983 struct ena_admin_feature_aenq_desc aenq; 984 985 /* rss flow hash function */ 986 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 987 988 /* rss flow hash input */ 989 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 990 991 /* rss indirection table */ 992 struct ena_admin_feature_rss_ind_table ind_table; 993 994 /* LLQ configuration */ 995 struct ena_admin_feature_llq_desc llq; 996 } u; 997 }; 998 999 struct ena_admin_set_feat_resp { 1000 struct ena_admin_acq_common_desc acq_common_desc; 1001 1002 union { 1003 u32 raw[14]; 1004 } u; 1005 }; 1006 1007 struct ena_admin_aenq_common_desc { 1008 u16 group; 1009 1010 u16 syndrom; 1011 1012 /* 0 : phase 1013 * 7:1 : reserved - MBZ 1014 */ 1015 u8 flags; 1016 1017 u8 reserved1[3]; 1018 1019 u32 timestamp_low; 1020 1021 u32 timestamp_high; 1022 }; 1023 1024 /* asynchronous event notification groups */ 1025 enum ena_admin_aenq_group { 1026 ENA_ADMIN_LINK_CHANGE = 0, 1027 ENA_ADMIN_FATAL_ERROR = 1, 1028 ENA_ADMIN_WARNING = 2, 1029 ENA_ADMIN_NOTIFICATION = 3, 1030 ENA_ADMIN_KEEP_ALIVE = 4, 1031 ENA_ADMIN_AENQ_GROUPS_NUM = 5, 1032 }; 1033 1034 enum ena_admin_aenq_notification_syndrom { 1035 ENA_ADMIN_SUSPEND = 0, 1036 ENA_ADMIN_RESUME = 1, 1037 ENA_ADMIN_UPDATE_HINTS = 2, 1038 }; 1039 1040 struct ena_admin_aenq_entry { 1041 struct ena_admin_aenq_common_desc aenq_common_desc; 1042 1043 /* command specific inline data */ 1044 u32 inline_data_w4[12]; 1045 }; 1046 1047 struct ena_admin_aenq_link_change_desc { 1048 struct ena_admin_aenq_common_desc aenq_common_desc; 1049 1050 /* 0 : link_status */ 1051 u32 flags; 1052 }; 1053 1054 struct ena_admin_aenq_keep_alive_desc { 1055 struct ena_admin_aenq_common_desc aenq_common_desc; 1056 1057 u32 rx_drops_low; 1058 1059 u32 rx_drops_high; 1060 1061 u32 tx_drops_low; 1062 1063 u32 tx_drops_high; 1064 }; 1065 1066 struct ena_admin_ena_mmio_req_read_less_resp { 1067 u16 req_id; 1068 1069 u16 reg_off; 1070 1071 /* value is valid when poll is cleared */ 1072 u32 reg_val; 1073 }; 1074 1075 /* aq_common_desc */ 1076 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1077 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 1078 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 1079 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 1080 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 1081 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 1082 1083 /* sq */ 1084 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 1085 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) 1086 1087 /* acq_common_desc */ 1088 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1089 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 1090 1091 /* aq_create_sq_cmd */ 1092 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 1093 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) 1094 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) 1095 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 1096 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) 1097 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) 1098 1099 /* aq_create_cq_cmd */ 1100 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 1101 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 1102 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1103 1104 /* get_set_feature_common_desc */ 1105 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 1106 1107 /* get_feature_link_desc */ 1108 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) 1109 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 1110 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) 1111 1112 /* feature_offload_desc */ 1113 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) 1114 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 1115 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 1116 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 1117 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 1118 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 1119 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 1120 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 1121 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 1122 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 1123 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) 1124 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 1125 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) 1126 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 1127 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) 1128 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) 1129 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 1130 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) 1131 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 1132 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) 1133 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 1134 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) 1135 1136 /* feature_rss_flow_hash_function */ 1137 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) 1138 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0) 1139 1140 /* feature_rss_flow_hash_input */ 1141 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 1142 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) 1143 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 1144 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) 1145 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 1146 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) 1147 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 1148 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) 1149 1150 /* host_info */ 1151 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 1152 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 1153 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) 1154 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 1155 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 1156 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 1157 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 1158 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1159 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 1160 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1161 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 1162 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1163 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1 1164 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) 1165 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 1166 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) 1167 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3 1168 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3) 1169 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4 1170 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4) 1171 1172 /* aenq_common_desc */ 1173 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 1174 1175 /* aenq_link_change_desc */ 1176 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) 1177 1178 #endif /* _ENA_ADMIN_H_ */ 1179