1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /*
3  * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
4  */
5 #ifndef _ENA_ADMIN_H_
6 #define _ENA_ADMIN_H_
7 
8 #define ENA_ADMIN_RSS_KEY_PARTS              10
9 
10 enum ena_admin_aq_opcode {
11 	ENA_ADMIN_CREATE_SQ                         = 1,
12 	ENA_ADMIN_DESTROY_SQ                        = 2,
13 	ENA_ADMIN_CREATE_CQ                         = 3,
14 	ENA_ADMIN_DESTROY_CQ                        = 4,
15 	ENA_ADMIN_GET_FEATURE                       = 8,
16 	ENA_ADMIN_SET_FEATURE                       = 9,
17 	ENA_ADMIN_GET_STATS                         = 11,
18 };
19 
20 enum ena_admin_aq_completion_status {
21 	ENA_ADMIN_SUCCESS                           = 0,
22 	ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE       = 1,
23 	ENA_ADMIN_BAD_OPCODE                        = 2,
24 	ENA_ADMIN_UNSUPPORTED_OPCODE                = 3,
25 	ENA_ADMIN_MALFORMED_REQUEST                 = 4,
26 	/* Additional status is provided in ACQ entry extended_status */
27 	ENA_ADMIN_ILLEGAL_PARAMETER                 = 5,
28 	ENA_ADMIN_UNKNOWN_ERROR                     = 6,
29 	ENA_ADMIN_RESOURCE_BUSY                     = 7,
30 };
31 
32 /* subcommands for the set/get feature admin commands */
33 enum ena_admin_aq_feature_id {
34 	ENA_ADMIN_DEVICE_ATTRIBUTES                 = 1,
35 	ENA_ADMIN_MAX_QUEUES_NUM                    = 2,
36 	ENA_ADMIN_HW_HINTS                          = 3,
37 	ENA_ADMIN_LLQ                               = 4,
38 	ENA_ADMIN_MAX_QUEUES_EXT                    = 7,
39 	ENA_ADMIN_RSS_HASH_FUNCTION                 = 10,
40 	ENA_ADMIN_STATELESS_OFFLOAD_CONFIG          = 11,
41 	ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG      = 12,
42 	ENA_ADMIN_MTU                               = 14,
43 	ENA_ADMIN_RSS_HASH_INPUT                    = 18,
44 	ENA_ADMIN_INTERRUPT_MODERATION              = 20,
45 	ENA_ADMIN_AENQ_CONFIG                       = 26,
46 	ENA_ADMIN_LINK_CONFIG                       = 27,
47 	ENA_ADMIN_HOST_ATTR_CONFIG                  = 28,
48 	ENA_ADMIN_FEATURES_OPCODE_NUM               = 32,
49 };
50 
51 enum ena_admin_placement_policy_type {
52 	/* descriptors and headers are in host memory */
53 	ENA_ADMIN_PLACEMENT_POLICY_HOST             = 1,
54 	/* descriptors and headers are in device memory (a.k.a Low Latency
55 	 * Queue)
56 	 */
57 	ENA_ADMIN_PLACEMENT_POLICY_DEV              = 3,
58 };
59 
60 enum ena_admin_link_types {
61 	ENA_ADMIN_LINK_SPEED_1G                     = 0x1,
62 	ENA_ADMIN_LINK_SPEED_2_HALF_G               = 0x2,
63 	ENA_ADMIN_LINK_SPEED_5G                     = 0x4,
64 	ENA_ADMIN_LINK_SPEED_10G                    = 0x8,
65 	ENA_ADMIN_LINK_SPEED_25G                    = 0x10,
66 	ENA_ADMIN_LINK_SPEED_40G                    = 0x20,
67 	ENA_ADMIN_LINK_SPEED_50G                    = 0x40,
68 	ENA_ADMIN_LINK_SPEED_100G                   = 0x80,
69 	ENA_ADMIN_LINK_SPEED_200G                   = 0x100,
70 	ENA_ADMIN_LINK_SPEED_400G                   = 0x200,
71 };
72 
73 enum ena_admin_completion_policy_type {
74 	/* completion queue entry for each sq descriptor */
75 	ENA_ADMIN_COMPLETION_POLICY_DESC            = 0,
76 	/* completion queue entry upon request in sq descriptor */
77 	ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND  = 1,
78 	/* current queue head pointer is updated in OS memory upon sq
79 	 * descriptor request
80 	 */
81 	ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND  = 2,
82 	/* current queue head pointer is updated in OS memory for each sq
83 	 * descriptor
84 	 */
85 	ENA_ADMIN_COMPLETION_POLICY_HEAD            = 3,
86 };
87 
88 /* basic stats return ena_admin_basic_stats while extanded stats return a
89  * buffer (string format) with additional statistics per queue and per
90  * device id
91  */
92 enum ena_admin_get_stats_type {
93 	ENA_ADMIN_GET_STATS_TYPE_BASIC              = 0,
94 	ENA_ADMIN_GET_STATS_TYPE_EXTENDED           = 1,
95 	/* extra HW stats for specific network interface */
96 	ENA_ADMIN_GET_STATS_TYPE_ENI                = 2,
97 };
98 
99 enum ena_admin_get_stats_scope {
100 	ENA_ADMIN_SPECIFIC_QUEUE                    = 0,
101 	ENA_ADMIN_ETH_TRAFFIC                       = 1,
102 };
103 
104 struct ena_admin_aq_common_desc {
105 	/* 11:0 : command_id
106 	 * 15:12 : reserved12
107 	 */
108 	u16 command_id;
109 
110 	/* as appears in ena_admin_aq_opcode */
111 	u8 opcode;
112 
113 	/* 0 : phase
114 	 * 1 : ctrl_data - control buffer address valid
115 	 * 2 : ctrl_data_indirect - control buffer address
116 	 *    points to list of pages with addresses of control
117 	 *    buffers
118 	 * 7:3 : reserved3
119 	 */
120 	u8 flags;
121 };
122 
123 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
124  * page list chunk. Used also at the end of indirect mode page list chunks,
125  * for chaining.
126  */
127 struct ena_admin_ctrl_buff_info {
128 	u32 length;
129 
130 	struct ena_common_mem_addr address;
131 };
132 
133 struct ena_admin_sq {
134 	u16 sq_idx;
135 
136 	/* 4:0 : reserved
137 	 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
138 	 */
139 	u8 sq_identity;
140 
141 	u8 reserved1;
142 };
143 
144 struct ena_admin_aq_entry {
145 	struct ena_admin_aq_common_desc aq_common_descriptor;
146 
147 	union {
148 		u32 inline_data_w1[3];
149 
150 		struct ena_admin_ctrl_buff_info control_buffer;
151 	} u;
152 
153 	u32 inline_data_w4[12];
154 };
155 
156 struct ena_admin_acq_common_desc {
157 	/* command identifier to associate it with the aq descriptor
158 	 * 11:0 : command_id
159 	 * 15:12 : reserved12
160 	 */
161 	u16 command;
162 
163 	u8 status;
164 
165 	/* 0 : phase
166 	 * 7:1 : reserved1
167 	 */
168 	u8 flags;
169 
170 	u16 extended_status;
171 
172 	/* indicates to the driver which AQ entry has been consumed by the
173 	 * device and could be reused
174 	 */
175 	u16 sq_head_indx;
176 };
177 
178 struct ena_admin_acq_entry {
179 	struct ena_admin_acq_common_desc acq_common_descriptor;
180 
181 	u32 response_specific_data[14];
182 };
183 
184 struct ena_admin_aq_create_sq_cmd {
185 	struct ena_admin_aq_common_desc aq_common_descriptor;
186 
187 	/* 4:0 : reserved0_w1
188 	 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
189 	 */
190 	u8 sq_identity;
191 
192 	u8 reserved8_w1;
193 
194 	/* 3:0 : placement_policy - Describing where the SQ
195 	 *    descriptor ring and the SQ packet headers reside:
196 	 *    0x1 - descriptors and headers are in OS memory,
197 	 *    0x3 - descriptors and headers in device memory
198 	 *    (a.k.a Low Latency Queue)
199 	 * 6:4 : completion_policy - Describing what policy
200 	 *    to use for generation completion entry (cqe) in
201 	 *    the CQ associated with this SQ: 0x0 - cqe for each
202 	 *    sq descriptor, 0x1 - cqe upon request in sq
203 	 *    descriptor, 0x2 - current queue head pointer is
204 	 *    updated in OS memory upon sq descriptor request
205 	 *    0x3 - current queue head pointer is updated in OS
206 	 *    memory for each sq descriptor
207 	 * 7 : reserved15_w1
208 	 */
209 	u8 sq_caps_2;
210 
211 	/* 0 : is_physically_contiguous - Described if the
212 	 *    queue ring memory is allocated in physical
213 	 *    contiguous pages or split.
214 	 * 7:1 : reserved17_w1
215 	 */
216 	u8 sq_caps_3;
217 
218 	/* associated completion queue id. This CQ must be created prior to SQ
219 	 * creation
220 	 */
221 	u16 cq_idx;
222 
223 	/* submission queue depth in entries */
224 	u16 sq_depth;
225 
226 	/* SQ physical base address in OS memory. This field should not be
227 	 * used for Low Latency queues. Has to be page aligned.
228 	 */
229 	struct ena_common_mem_addr sq_ba;
230 
231 	/* specifies queue head writeback location in OS memory. Valid if
232 	 * completion_policy is set to completion_policy_head_on_demand or
233 	 * completion_policy_head. Has to be cache aligned
234 	 */
235 	struct ena_common_mem_addr sq_head_writeback;
236 
237 	u32 reserved0_w7;
238 
239 	u32 reserved0_w8;
240 };
241 
242 enum ena_admin_sq_direction {
243 	ENA_ADMIN_SQ_DIRECTION_TX                   = 1,
244 	ENA_ADMIN_SQ_DIRECTION_RX                   = 2,
245 };
246 
247 struct ena_admin_acq_create_sq_resp_desc {
248 	struct ena_admin_acq_common_desc acq_common_desc;
249 
250 	u16 sq_idx;
251 
252 	u16 reserved;
253 
254 	/* queue doorbell address as an offset to PCIe MMIO REG BAR */
255 	u32 sq_doorbell_offset;
256 
257 	/* low latency queue ring base address as an offset to PCIe MMIO
258 	 * LLQ_MEM BAR
259 	 */
260 	u32 llq_descriptors_offset;
261 
262 	/* low latency queue headers' memory as an offset to PCIe MMIO
263 	 * LLQ_MEM BAR
264 	 */
265 	u32 llq_headers_offset;
266 };
267 
268 struct ena_admin_aq_destroy_sq_cmd {
269 	struct ena_admin_aq_common_desc aq_common_descriptor;
270 
271 	struct ena_admin_sq sq;
272 };
273 
274 struct ena_admin_acq_destroy_sq_resp_desc {
275 	struct ena_admin_acq_common_desc acq_common_desc;
276 };
277 
278 struct ena_admin_aq_create_cq_cmd {
279 	struct ena_admin_aq_common_desc aq_common_descriptor;
280 
281 	/* 4:0 : reserved5
282 	 * 5 : interrupt_mode_enabled - if set, cq operates
283 	 *    in interrupt mode, otherwise - polling
284 	 * 7:6 : reserved6
285 	 */
286 	u8 cq_caps_1;
287 
288 	/* 4:0 : cq_entry_size_words - size of CQ entry in
289 	 *    32-bit words, valid values: 4, 8.
290 	 * 7:5 : reserved7
291 	 */
292 	u8 cq_caps_2;
293 
294 	/* completion queue depth in # of entries. must be power of 2 */
295 	u16 cq_depth;
296 
297 	/* msix vector assigned to this cq */
298 	u32 msix_vector;
299 
300 	/* cq physical base address in OS memory. CQ must be physically
301 	 * contiguous
302 	 */
303 	struct ena_common_mem_addr cq_ba;
304 };
305 
306 struct ena_admin_acq_create_cq_resp_desc {
307 	struct ena_admin_acq_common_desc acq_common_desc;
308 
309 	u16 cq_idx;
310 
311 	/* actual cq depth in number of entries */
312 	u16 cq_actual_depth;
313 
314 	u32 numa_node_register_offset;
315 
316 	u32 cq_head_db_register_offset;
317 
318 	u32 cq_interrupt_unmask_register_offset;
319 };
320 
321 struct ena_admin_aq_destroy_cq_cmd {
322 	struct ena_admin_aq_common_desc aq_common_descriptor;
323 
324 	u16 cq_idx;
325 
326 	u16 reserved1;
327 };
328 
329 struct ena_admin_acq_destroy_cq_resp_desc {
330 	struct ena_admin_acq_common_desc acq_common_desc;
331 };
332 
333 /* ENA AQ Get Statistics command. Extended statistics are placed in control
334  * buffer pointed by AQ entry
335  */
336 struct ena_admin_aq_get_stats_cmd {
337 	struct ena_admin_aq_common_desc aq_common_descriptor;
338 
339 	union {
340 		/* command specific inline data */
341 		u32 inline_data_w1[3];
342 
343 		struct ena_admin_ctrl_buff_info control_buffer;
344 	} u;
345 
346 	/* stats type as defined in enum ena_admin_get_stats_type */
347 	u8 type;
348 
349 	/* stats scope defined in enum ena_admin_get_stats_scope */
350 	u8 scope;
351 
352 	u16 reserved3;
353 
354 	/* queue id. used when scope is specific_queue */
355 	u16 queue_idx;
356 
357 	/* device id, value 0xFFFF means mine. only privileged device can get
358 	 * stats of other device
359 	 */
360 	u16 device_id;
361 };
362 
363 /* Basic Statistics Command. */
364 struct ena_admin_basic_stats {
365 	u32 tx_bytes_low;
366 
367 	u32 tx_bytes_high;
368 
369 	u32 tx_pkts_low;
370 
371 	u32 tx_pkts_high;
372 
373 	u32 rx_bytes_low;
374 
375 	u32 rx_bytes_high;
376 
377 	u32 rx_pkts_low;
378 
379 	u32 rx_pkts_high;
380 
381 	u32 rx_drops_low;
382 
383 	u32 rx_drops_high;
384 
385 	u32 tx_drops_low;
386 
387 	u32 tx_drops_high;
388 };
389 
390 /* ENI Statistics Command. */
391 struct ena_admin_eni_stats {
392 	/* The number of packets shaped due to inbound aggregate BW
393 	 * allowance being exceeded
394 	 */
395 	u64 bw_in_allowance_exceeded;
396 
397 	/* The number of packets shaped due to outbound aggregate BW
398 	 * allowance being exceeded
399 	 */
400 	u64 bw_out_allowance_exceeded;
401 
402 	/* The number of packets shaped due to PPS allowance being exceeded */
403 	u64 pps_allowance_exceeded;
404 
405 	/* The number of packets shaped due to connection tracking
406 	 * allowance being exceeded and leading to failure in establishment
407 	 * of new connections
408 	 */
409 	u64 conntrack_allowance_exceeded;
410 
411 	/* The number of packets shaped due to linklocal packet rate
412 	 * allowance being exceeded
413 	 */
414 	u64 linklocal_allowance_exceeded;
415 };
416 
417 struct ena_admin_acq_get_stats_resp {
418 	struct ena_admin_acq_common_desc acq_common_desc;
419 
420 	union {
421 		u64 raw[7];
422 
423 		struct ena_admin_basic_stats basic_stats;
424 
425 		struct ena_admin_eni_stats eni_stats;
426 	} u;
427 };
428 
429 struct ena_admin_get_set_feature_common_desc {
430 	/* 1:0 : select - 0x1 - current value; 0x3 - default
431 	 *    value
432 	 * 7:3 : reserved3
433 	 */
434 	u8 flags;
435 
436 	/* as appears in ena_admin_aq_feature_id */
437 	u8 feature_id;
438 
439 	/* The driver specifies the max feature version it supports and the
440 	 * device responds with the currently supported feature version. The
441 	 * field is zero based
442 	 */
443 	u8 feature_version;
444 
445 	u8 reserved8;
446 };
447 
448 struct ena_admin_device_attr_feature_desc {
449 	u32 impl_id;
450 
451 	u32 device_version;
452 
453 	/* bitmap of ena_admin_aq_feature_id, which represents supported
454 	 * subcommands for the set/get feature admin commands.
455 	 */
456 	u32 supported_features;
457 
458 	u32 reserved3;
459 
460 	/* Indicates how many bits are used physical address access. */
461 	u32 phys_addr_width;
462 
463 	/* Indicates how many bits are used virtual address access. */
464 	u32 virt_addr_width;
465 
466 	/* unicast MAC address (in Network byte order) */
467 	u8 mac_addr[6];
468 
469 	u8 reserved7[2];
470 
471 	u32 max_mtu;
472 };
473 
474 enum ena_admin_llq_header_location {
475 	/* header is in descriptor list */
476 	ENA_ADMIN_INLINE_HEADER                     = 1,
477 	/* header in a separate ring, implies 16B descriptor list entry */
478 	ENA_ADMIN_HEADER_RING                       = 2,
479 };
480 
481 enum ena_admin_llq_ring_entry_size {
482 	ENA_ADMIN_LIST_ENTRY_SIZE_128B              = 1,
483 	ENA_ADMIN_LIST_ENTRY_SIZE_192B              = 2,
484 	ENA_ADMIN_LIST_ENTRY_SIZE_256B              = 4,
485 };
486 
487 enum ena_admin_llq_num_descs_before_header {
488 	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0     = 0,
489 	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1     = 1,
490 	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2     = 2,
491 	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4     = 4,
492 	ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8     = 8,
493 };
494 
495 /* packet descriptor list entry always starts with one or more descriptors,
496  * followed by a header. The rest of the descriptors are located in the
497  * beginning of the subsequent entry. Stride refers to how the rest of the
498  * descriptors are placed. This field is relevant only for inline header
499  * mode
500  */
501 enum ena_admin_llq_stride_ctrl {
502 	ENA_ADMIN_SINGLE_DESC_PER_ENTRY             = 1,
503 	ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY          = 2,
504 };
505 
506 enum ena_admin_accel_mode_feat {
507 	ENA_ADMIN_DISABLE_META_CACHING              = 0,
508 	ENA_ADMIN_LIMIT_TX_BURST                    = 1,
509 };
510 
511 struct ena_admin_accel_mode_get {
512 	/* bit field of enum ena_admin_accel_mode_feat */
513 	u16 supported_flags;
514 
515 	/* maximum burst size between two doorbells. The size is in bytes */
516 	u16 max_tx_burst_size;
517 };
518 
519 struct ena_admin_accel_mode_set {
520 	/* bit field of enum ena_admin_accel_mode_feat */
521 	u16 enabled_flags;
522 
523 	u16 reserved;
524 };
525 
526 struct ena_admin_accel_mode_req {
527 	union {
528 		u32 raw[2];
529 
530 		struct ena_admin_accel_mode_get get;
531 
532 		struct ena_admin_accel_mode_set set;
533 	} u;
534 };
535 
536 struct ena_admin_feature_llq_desc {
537 	u32 max_llq_num;
538 
539 	u32 max_llq_depth;
540 
541 	/* specify the header locations the device supports. bitfield of enum
542 	 * ena_admin_llq_header_location.
543 	 */
544 	u16 header_location_ctrl_supported;
545 
546 	/* the header location the driver selected to use. */
547 	u16 header_location_ctrl_enabled;
548 
549 	/* if inline header is specified - this is the size of descriptor list
550 	 * entry. If header in a separate ring is specified - this is the size
551 	 * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size.
552 	 * specify the entry sizes the device supports
553 	 */
554 	u16 entry_size_ctrl_supported;
555 
556 	/* the entry size the driver selected to use. */
557 	u16 entry_size_ctrl_enabled;
558 
559 	/* valid only if inline header is specified. First entry associated with
560 	 * the packet includes descriptors and header. Rest of the entries
561 	 * occupied by descriptors. This parameter defines the max number of
562 	 * descriptors precedding the header in the first entry. The field is
563 	 * bitfield of enum ena_admin_llq_num_descs_before_header and specify
564 	 * the values the device supports
565 	 */
566 	u16 desc_num_before_header_supported;
567 
568 	/* the desire field the driver selected to use */
569 	u16 desc_num_before_header_enabled;
570 
571 	/* valid only if inline was chosen. bitfield of enum
572 	 * ena_admin_llq_stride_ctrl
573 	 */
574 	u16 descriptors_stride_ctrl_supported;
575 
576 	/* the stride control the driver selected to use */
577 	u16 descriptors_stride_ctrl_enabled;
578 
579 	/* reserved */
580 	u32 reserved1;
581 
582 	/* accelerated low latency queues requirement. driver needs to
583 	 * support those requirements in order to use accelerated llq
584 	 */
585 	struct ena_admin_accel_mode_req accel_mode;
586 };
587 
588 struct ena_admin_queue_ext_feature_fields {
589 	u32 max_tx_sq_num;
590 
591 	u32 max_tx_cq_num;
592 
593 	u32 max_rx_sq_num;
594 
595 	u32 max_rx_cq_num;
596 
597 	u32 max_tx_sq_depth;
598 
599 	u32 max_tx_cq_depth;
600 
601 	u32 max_rx_sq_depth;
602 
603 	u32 max_rx_cq_depth;
604 
605 	u32 max_tx_header_size;
606 
607 	/* Maximum Descriptors number, including meta descriptor, allowed for a
608 	 * single Tx packet
609 	 */
610 	u16 max_per_packet_tx_descs;
611 
612 	/* Maximum Descriptors number allowed for a single Rx packet */
613 	u16 max_per_packet_rx_descs;
614 };
615 
616 struct ena_admin_queue_feature_desc {
617 	u32 max_sq_num;
618 
619 	u32 max_sq_depth;
620 
621 	u32 max_cq_num;
622 
623 	u32 max_cq_depth;
624 
625 	u32 max_legacy_llq_num;
626 
627 	u32 max_legacy_llq_depth;
628 
629 	u32 max_header_size;
630 
631 	/* Maximum Descriptors number, including meta descriptor, allowed for a
632 	 * single Tx packet
633 	 */
634 	u16 max_packet_tx_descs;
635 
636 	/* Maximum Descriptors number allowed for a single Rx packet */
637 	u16 max_packet_rx_descs;
638 };
639 
640 struct ena_admin_set_feature_mtu_desc {
641 	/* exclude L2 */
642 	u32 mtu;
643 };
644 
645 struct ena_admin_set_feature_host_attr_desc {
646 	/* host OS info base address in OS memory. host info is 4KB of
647 	 * physically contiguous
648 	 */
649 	struct ena_common_mem_addr os_info_ba;
650 
651 	/* host debug area base address in OS memory. debug area must be
652 	 * physically contiguous
653 	 */
654 	struct ena_common_mem_addr debug_ba;
655 
656 	/* debug area size */
657 	u32 debug_area_size;
658 };
659 
660 struct ena_admin_feature_intr_moder_desc {
661 	/* interrupt delay granularity in usec */
662 	u16 intr_delay_resolution;
663 
664 	u16 reserved;
665 };
666 
667 struct ena_admin_get_feature_link_desc {
668 	/* Link speed in Mb */
669 	u32 speed;
670 
671 	/* bit field of enum ena_admin_link types */
672 	u32 supported;
673 
674 	/* 0 : autoneg
675 	 * 1 : duplex - Full Duplex
676 	 * 31:2 : reserved2
677 	 */
678 	u32 flags;
679 };
680 
681 struct ena_admin_feature_aenq_desc {
682 	/* bitmask for AENQ groups the device can report */
683 	u32 supported_groups;
684 
685 	/* bitmask for AENQ groups to report */
686 	u32 enabled_groups;
687 };
688 
689 struct ena_admin_feature_offload_desc {
690 	/* 0 : TX_L3_csum_ipv4
691 	 * 1 : TX_L4_ipv4_csum_part - The checksum field
692 	 *    should be initialized with pseudo header checksum
693 	 * 2 : TX_L4_ipv4_csum_full
694 	 * 3 : TX_L4_ipv6_csum_part - The checksum field
695 	 *    should be initialized with pseudo header checksum
696 	 * 4 : TX_L4_ipv6_csum_full
697 	 * 5 : tso_ipv4
698 	 * 6 : tso_ipv6
699 	 * 7 : tso_ecn
700 	 */
701 	u32 tx;
702 
703 	/* Receive side supported stateless offload
704 	 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
705 	 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
706 	 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
707 	 * 3 : RX_hash - Hash calculation
708 	 */
709 	u32 rx_supported;
710 
711 	u32 rx_enabled;
712 };
713 
714 enum ena_admin_hash_functions {
715 	ENA_ADMIN_TOEPLITZ                          = 1,
716 	ENA_ADMIN_CRC32                             = 2,
717 };
718 
719 struct ena_admin_feature_rss_flow_hash_control {
720 	u32 key_parts;
721 
722 	u32 reserved;
723 
724 	u32 key[ENA_ADMIN_RSS_KEY_PARTS];
725 };
726 
727 struct ena_admin_feature_rss_flow_hash_function {
728 	/* 7:0 : funcs - bitmask of ena_admin_hash_functions */
729 	u32 supported_func;
730 
731 	/* 7:0 : selected_func - bitmask of
732 	 *    ena_admin_hash_functions
733 	 */
734 	u32 selected_func;
735 
736 	/* initial value */
737 	u32 init_val;
738 };
739 
740 /* RSS flow hash protocols */
741 enum ena_admin_flow_hash_proto {
742 	ENA_ADMIN_RSS_TCP4                          = 0,
743 	ENA_ADMIN_RSS_UDP4                          = 1,
744 	ENA_ADMIN_RSS_TCP6                          = 2,
745 	ENA_ADMIN_RSS_UDP6                          = 3,
746 	ENA_ADMIN_RSS_IP4                           = 4,
747 	ENA_ADMIN_RSS_IP6                           = 5,
748 	ENA_ADMIN_RSS_IP4_FRAG                      = 6,
749 	ENA_ADMIN_RSS_NOT_IP                        = 7,
750 	/* TCPv6 with extension header */
751 	ENA_ADMIN_RSS_TCP6_EX                       = 8,
752 	/* IPv6 with extension header */
753 	ENA_ADMIN_RSS_IP6_EX                        = 9,
754 	ENA_ADMIN_RSS_PROTO_NUM                     = 16,
755 };
756 
757 /* RSS flow hash fields */
758 enum ena_admin_flow_hash_fields {
759 	/* Ethernet Dest Addr */
760 	ENA_ADMIN_RSS_L2_DA                         = BIT(0),
761 	/* Ethernet Src Addr */
762 	ENA_ADMIN_RSS_L2_SA                         = BIT(1),
763 	/* ipv4/6 Dest Addr */
764 	ENA_ADMIN_RSS_L3_DA                         = BIT(2),
765 	/* ipv4/6 Src Addr */
766 	ENA_ADMIN_RSS_L3_SA                         = BIT(3),
767 	/* tcp/udp Dest Port */
768 	ENA_ADMIN_RSS_L4_DP                         = BIT(4),
769 	/* tcp/udp Src Port */
770 	ENA_ADMIN_RSS_L4_SP                         = BIT(5),
771 };
772 
773 struct ena_admin_proto_input {
774 	/* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
775 	u16 fields;
776 
777 	u16 reserved2;
778 };
779 
780 struct ena_admin_feature_rss_hash_control {
781 	struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
782 
783 	struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
784 
785 	struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
786 
787 	struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
788 };
789 
790 struct ena_admin_feature_rss_flow_hash_input {
791 	/* supported hash input sorting
792 	 * 1 : L3_sort - support swap L3 addresses if DA is
793 	 *    smaller than SA
794 	 * 2 : L4_sort - support swap L4 ports if DP smaller
795 	 *    SP
796 	 */
797 	u16 supported_input_sort;
798 
799 	/* enabled hash input sorting
800 	 * 1 : enable_L3_sort - enable swap L3 addresses if
801 	 *    DA smaller than SA
802 	 * 2 : enable_L4_sort - enable swap L4 ports if DP
803 	 *    smaller than SP
804 	 */
805 	u16 enabled_input_sort;
806 };
807 
808 enum ena_admin_os_type {
809 	ENA_ADMIN_OS_LINUX                          = 1,
810 	ENA_ADMIN_OS_WIN                            = 2,
811 	ENA_ADMIN_OS_DPDK                           = 3,
812 	ENA_ADMIN_OS_FREEBSD                        = 4,
813 	ENA_ADMIN_OS_IPXE                           = 5,
814 	ENA_ADMIN_OS_ESXI                           = 6,
815 	ENA_ADMIN_OS_GROUPS_NUM                     = 6,
816 };
817 
818 struct ena_admin_host_info {
819 	/* defined in enum ena_admin_os_type */
820 	u32 os_type;
821 
822 	/* os distribution string format */
823 	u8 os_dist_str[128];
824 
825 	/* OS distribution numeric format */
826 	u32 os_dist;
827 
828 	/* kernel version string format */
829 	u8 kernel_ver_str[32];
830 
831 	/* Kernel version numeric format */
832 	u32 kernel_ver;
833 
834 	/* 7:0 : major
835 	 * 15:8 : minor
836 	 * 23:16 : sub_minor
837 	 * 31:24 : module_type
838 	 */
839 	u32 driver_version;
840 
841 	/* features bitmap */
842 	u32 supported_network_features[2];
843 
844 	/* ENA spec version of driver */
845 	u16 ena_spec_version;
846 
847 	/* ENA device's Bus, Device and Function
848 	 * 2:0 : function
849 	 * 7:3 : device
850 	 * 15:8 : bus
851 	 */
852 	u16 bdf;
853 
854 	/* Number of CPUs */
855 	u16 num_cpus;
856 
857 	u16 reserved;
858 
859 	/* 0 : reserved
860 	 * 1 : rx_offset
861 	 * 2 : interrupt_moderation
862 	 * 3 : rx_buf_mirroring
863 	 * 4 : rss_configurable_function_key
864 	 * 31:5 : reserved
865 	 */
866 	u32 driver_supported_features;
867 };
868 
869 struct ena_admin_rss_ind_table_entry {
870 	u16 cq_idx;
871 
872 	u16 reserved;
873 };
874 
875 struct ena_admin_feature_rss_ind_table {
876 	/* min supported table size (2^min_size) */
877 	u16 min_size;
878 
879 	/* max supported table size (2^max_size) */
880 	u16 max_size;
881 
882 	/* table size (2^size) */
883 	u16 size;
884 
885 	u16 reserved;
886 
887 	/* index of the inline entry. 0xFFFFFFFF means invalid */
888 	u32 inline_index;
889 
890 	/* used for updating single entry, ignored when setting the entire
891 	 * table through the control buffer.
892 	 */
893 	struct ena_admin_rss_ind_table_entry inline_entry;
894 };
895 
896 /* When hint value is 0, driver should use it's own predefined value */
897 struct ena_admin_ena_hw_hints {
898 	/* value in ms */
899 	u16 mmio_read_timeout;
900 
901 	/* value in ms */
902 	u16 driver_watchdog_timeout;
903 
904 	/* Per packet tx completion timeout. value in ms */
905 	u16 missing_tx_completion_timeout;
906 
907 	u16 missed_tx_completion_count_threshold_to_reset;
908 
909 	/* value in ms */
910 	u16 admin_completion_tx_timeout;
911 
912 	u16 netdev_wd_timeout;
913 
914 	u16 max_tx_sgl_size;
915 
916 	u16 max_rx_sgl_size;
917 
918 	u16 reserved[8];
919 };
920 
921 struct ena_admin_get_feat_cmd {
922 	struct ena_admin_aq_common_desc aq_common_descriptor;
923 
924 	struct ena_admin_ctrl_buff_info control_buffer;
925 
926 	struct ena_admin_get_set_feature_common_desc feat_common;
927 
928 	u32 raw[11];
929 };
930 
931 struct ena_admin_queue_ext_feature_desc {
932 	/* version */
933 	u8 version;
934 
935 	u8 reserved1[3];
936 
937 	union {
938 		struct ena_admin_queue_ext_feature_fields max_queue_ext;
939 
940 		u32 raw[10];
941 	};
942 };
943 
944 struct ena_admin_get_feat_resp {
945 	struct ena_admin_acq_common_desc acq_common_desc;
946 
947 	union {
948 		u32 raw[14];
949 
950 		struct ena_admin_device_attr_feature_desc dev_attr;
951 
952 		struct ena_admin_feature_llq_desc llq;
953 
954 		struct ena_admin_queue_feature_desc max_queue;
955 
956 		struct ena_admin_queue_ext_feature_desc max_queue_ext;
957 
958 		struct ena_admin_feature_aenq_desc aenq;
959 
960 		struct ena_admin_get_feature_link_desc link;
961 
962 		struct ena_admin_feature_offload_desc offload;
963 
964 		struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
965 
966 		struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
967 
968 		struct ena_admin_feature_rss_ind_table ind_table;
969 
970 		struct ena_admin_feature_intr_moder_desc intr_moderation;
971 
972 		struct ena_admin_ena_hw_hints hw_hints;
973 	} u;
974 };
975 
976 struct ena_admin_set_feat_cmd {
977 	struct ena_admin_aq_common_desc aq_common_descriptor;
978 
979 	struct ena_admin_ctrl_buff_info control_buffer;
980 
981 	struct ena_admin_get_set_feature_common_desc feat_common;
982 
983 	union {
984 		u32 raw[11];
985 
986 		/* mtu size */
987 		struct ena_admin_set_feature_mtu_desc mtu;
988 
989 		/* host attributes */
990 		struct ena_admin_set_feature_host_attr_desc host_attr;
991 
992 		/* AENQ configuration */
993 		struct ena_admin_feature_aenq_desc aenq;
994 
995 		/* rss flow hash function */
996 		struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
997 
998 		/* rss flow hash input */
999 		struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
1000 
1001 		/* rss indirection table */
1002 		struct ena_admin_feature_rss_ind_table ind_table;
1003 
1004 		/* LLQ configuration */
1005 		struct ena_admin_feature_llq_desc llq;
1006 	} u;
1007 };
1008 
1009 struct ena_admin_set_feat_resp {
1010 	struct ena_admin_acq_common_desc acq_common_desc;
1011 
1012 	union {
1013 		u32 raw[14];
1014 	} u;
1015 };
1016 
1017 struct ena_admin_aenq_common_desc {
1018 	u16 group;
1019 
1020 	u16 syndrome;
1021 
1022 	/* 0 : phase
1023 	 * 7:1 : reserved - MBZ
1024 	 */
1025 	u8 flags;
1026 
1027 	u8 reserved1[3];
1028 
1029 	u32 timestamp_low;
1030 
1031 	u32 timestamp_high;
1032 };
1033 
1034 /* asynchronous event notification groups */
1035 enum ena_admin_aenq_group {
1036 	ENA_ADMIN_LINK_CHANGE                       = 0,
1037 	ENA_ADMIN_FATAL_ERROR                       = 1,
1038 	ENA_ADMIN_WARNING                           = 2,
1039 	ENA_ADMIN_NOTIFICATION                      = 3,
1040 	ENA_ADMIN_KEEP_ALIVE                        = 4,
1041 	ENA_ADMIN_AENQ_GROUPS_NUM                   = 5,
1042 };
1043 
1044 enum ena_admin_aenq_notification_syndrome {
1045 	ENA_ADMIN_UPDATE_HINTS                      = 2,
1046 };
1047 
1048 struct ena_admin_aenq_entry {
1049 	struct ena_admin_aenq_common_desc aenq_common_desc;
1050 
1051 	/* command specific inline data */
1052 	u32 inline_data_w4[12];
1053 };
1054 
1055 struct ena_admin_aenq_link_change_desc {
1056 	struct ena_admin_aenq_common_desc aenq_common_desc;
1057 
1058 	/* 0 : link_status */
1059 	u32 flags;
1060 };
1061 
1062 struct ena_admin_aenq_keep_alive_desc {
1063 	struct ena_admin_aenq_common_desc aenq_common_desc;
1064 
1065 	u32 rx_drops_low;
1066 
1067 	u32 rx_drops_high;
1068 
1069 	u32 tx_drops_low;
1070 
1071 	u32 tx_drops_high;
1072 };
1073 
1074 struct ena_admin_ena_mmio_req_read_less_resp {
1075 	u16 req_id;
1076 
1077 	u16 reg_off;
1078 
1079 	/* value is valid when poll is cleared */
1080 	u32 reg_val;
1081 };
1082 
1083 /* aq_common_desc */
1084 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK            GENMASK(11, 0)
1085 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK                 BIT(0)
1086 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT            1
1087 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK             BIT(1)
1088 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT   2
1089 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK    BIT(2)
1090 
1091 /* sq */
1092 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT                     5
1093 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK                      GENMASK(7, 5)
1094 
1095 /* acq_common_desc */
1096 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK           GENMASK(11, 0)
1097 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK                BIT(0)
1098 
1099 /* aq_create_sq_cmd */
1100 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT       5
1101 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK        GENMASK(7, 5)
1102 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK    GENMASK(3, 0)
1103 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT  4
1104 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK   GENMASK(6, 4)
1105 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1106 
1107 /* aq_create_cq_cmd */
1108 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1109 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1110 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1111 
1112 /* get_set_feature_common_desc */
1113 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK   GENMASK(1, 0)
1114 
1115 /* get_feature_link_desc */
1116 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK        BIT(0)
1117 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT        1
1118 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK         BIT(1)
1119 
1120 /* feature_offload_desc */
1121 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1122 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1123 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1124 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1125 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1126 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1127 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1128 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1129 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1130 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT       5
1131 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK        BIT(5)
1132 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT       6
1133 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK        BIT(6)
1134 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT        7
1135 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK         BIT(7)
1136 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1137 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1138 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1139 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1140 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1141 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT        3
1142 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK         BIT(3)
1143 
1144 /* feature_rss_flow_hash_function */
1145 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1146 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1147 
1148 /* feature_rss_flow_hash_input */
1149 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1150 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK  BIT(1)
1151 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1152 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK  BIT(2)
1153 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1154 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1155 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1156 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1157 
1158 /* host_info */
1159 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK                      GENMASK(7, 0)
1160 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT                     8
1161 #define ENA_ADMIN_HOST_INFO_MINOR_MASK                      GENMASK(15, 8)
1162 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT                 16
1163 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK                  GENMASK(23, 16)
1164 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT               24
1165 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK                GENMASK(31, 24)
1166 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK                   GENMASK(2, 0)
1167 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT                    3
1168 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK                     GENMASK(7, 3)
1169 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT                       8
1170 #define ENA_ADMIN_HOST_INFO_BUS_MASK                        GENMASK(15, 8)
1171 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT                 1
1172 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK                  BIT(1)
1173 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT      2
1174 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK       BIT(2)
1175 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT          3
1176 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK           BIT(3)
1177 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4
1178 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)
1179 
1180 /* aenq_common_desc */
1181 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK               BIT(0)
1182 
1183 /* aenq_link_change_desc */
1184 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK    BIT(0)
1185 
1186 #endif /* _ENA_ADMIN_H_ */
1187