1 /* 2 * Copyright 2015 - 2016 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef _ENA_ADMIN_H_ 33 #define _ENA_ADMIN_H_ 34 35 36 enum ena_admin_aq_opcode { 37 ENA_ADMIN_CREATE_SQ = 1, 38 ENA_ADMIN_DESTROY_SQ = 2, 39 ENA_ADMIN_CREATE_CQ = 3, 40 ENA_ADMIN_DESTROY_CQ = 4, 41 ENA_ADMIN_GET_FEATURE = 8, 42 ENA_ADMIN_SET_FEATURE = 9, 43 ENA_ADMIN_GET_STATS = 11, 44 }; 45 46 enum ena_admin_aq_completion_status { 47 ENA_ADMIN_SUCCESS = 0, 48 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 49 ENA_ADMIN_BAD_OPCODE = 2, 50 ENA_ADMIN_UNSUPPORTED_OPCODE = 3, 51 ENA_ADMIN_MALFORMED_REQUEST = 4, 52 /* Additional status is provided in ACQ entry extended_status */ 53 ENA_ADMIN_ILLEGAL_PARAMETER = 5, 54 ENA_ADMIN_UNKNOWN_ERROR = 6, 55 ENA_ADMIN_RESOURCE_BUSY = 7, 56 }; 57 58 enum ena_admin_aq_feature_id { 59 ENA_ADMIN_DEVICE_ATTRIBUTES = 1, 60 ENA_ADMIN_MAX_QUEUES_NUM = 2, 61 ENA_ADMIN_HW_HINTS = 3, 62 ENA_ADMIN_LLQ = 4, 63 ENA_ADMIN_MAX_QUEUES_EXT = 7, 64 ENA_ADMIN_RSS_HASH_FUNCTION = 10, 65 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, 66 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12, 67 ENA_ADMIN_MTU = 14, 68 ENA_ADMIN_RSS_HASH_INPUT = 18, 69 ENA_ADMIN_INTERRUPT_MODERATION = 20, 70 ENA_ADMIN_AENQ_CONFIG = 26, 71 ENA_ADMIN_LINK_CONFIG = 27, 72 ENA_ADMIN_HOST_ATTR_CONFIG = 28, 73 ENA_ADMIN_FEATURES_OPCODE_NUM = 32, 74 }; 75 76 enum ena_admin_placement_policy_type { 77 /* descriptors and headers are in host memory */ 78 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, 79 /* descriptors and headers are in device memory (a.k.a Low Latency 80 * Queue) 81 */ 82 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, 83 }; 84 85 enum ena_admin_link_types { 86 ENA_ADMIN_LINK_SPEED_1G = 0x1, 87 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, 88 ENA_ADMIN_LINK_SPEED_5G = 0x4, 89 ENA_ADMIN_LINK_SPEED_10G = 0x8, 90 ENA_ADMIN_LINK_SPEED_25G = 0x10, 91 ENA_ADMIN_LINK_SPEED_40G = 0x20, 92 ENA_ADMIN_LINK_SPEED_50G = 0x40, 93 ENA_ADMIN_LINK_SPEED_100G = 0x80, 94 ENA_ADMIN_LINK_SPEED_200G = 0x100, 95 ENA_ADMIN_LINK_SPEED_400G = 0x200, 96 }; 97 98 enum ena_admin_completion_policy_type { 99 /* completion queue entry for each sq descriptor */ 100 ENA_ADMIN_COMPLETION_POLICY_DESC = 0, 101 /* completion queue entry upon request in sq descriptor */ 102 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 103 /* current queue head pointer is updated in OS memory upon sq 104 * descriptor request 105 */ 106 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 107 /* current queue head pointer is updated in OS memory for each sq 108 * descriptor 109 */ 110 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, 111 }; 112 113 /* basic stats return ena_admin_basic_stats while extanded stats return a 114 * buffer (string format) with additional statistics per queue and per 115 * device id 116 */ 117 enum ena_admin_get_stats_type { 118 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, 119 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, 120 /* extra HW stats for specific network interface */ 121 ENA_ADMIN_GET_STATS_TYPE_ENI = 2, 122 }; 123 124 enum ena_admin_get_stats_scope { 125 ENA_ADMIN_SPECIFIC_QUEUE = 0, 126 ENA_ADMIN_ETH_TRAFFIC = 1, 127 }; 128 129 struct ena_admin_aq_common_desc { 130 /* 11:0 : command_id 131 * 15:12 : reserved12 132 */ 133 u16 command_id; 134 135 /* as appears in ena_admin_aq_opcode */ 136 u8 opcode; 137 138 /* 0 : phase 139 * 1 : ctrl_data - control buffer address valid 140 * 2 : ctrl_data_indirect - control buffer address 141 * points to list of pages with addresses of control 142 * buffers 143 * 7:3 : reserved3 144 */ 145 u8 flags; 146 }; 147 148 /* used in ena_admin_aq_entry. Can point directly to control data, or to a 149 * page list chunk. Used also at the end of indirect mode page list chunks, 150 * for chaining. 151 */ 152 struct ena_admin_ctrl_buff_info { 153 u32 length; 154 155 struct ena_common_mem_addr address; 156 }; 157 158 struct ena_admin_sq { 159 u16 sq_idx; 160 161 /* 4:0 : reserved 162 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx 163 */ 164 u8 sq_identity; 165 166 u8 reserved1; 167 }; 168 169 struct ena_admin_aq_entry { 170 struct ena_admin_aq_common_desc aq_common_descriptor; 171 172 union { 173 u32 inline_data_w1[3]; 174 175 struct ena_admin_ctrl_buff_info control_buffer; 176 } u; 177 178 u32 inline_data_w4[12]; 179 }; 180 181 struct ena_admin_acq_common_desc { 182 /* command identifier to associate it with the aq descriptor 183 * 11:0 : command_id 184 * 15:12 : reserved12 185 */ 186 u16 command; 187 188 u8 status; 189 190 /* 0 : phase 191 * 7:1 : reserved1 192 */ 193 u8 flags; 194 195 u16 extended_status; 196 197 /* indicates to the driver which AQ entry has been consumed by the 198 * device and could be reused 199 */ 200 u16 sq_head_indx; 201 }; 202 203 struct ena_admin_acq_entry { 204 struct ena_admin_acq_common_desc acq_common_descriptor; 205 206 u32 response_specific_data[14]; 207 }; 208 209 struct ena_admin_aq_create_sq_cmd { 210 struct ena_admin_aq_common_desc aq_common_descriptor; 211 212 /* 4:0 : reserved0_w1 213 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx 214 */ 215 u8 sq_identity; 216 217 u8 reserved8_w1; 218 219 /* 3:0 : placement_policy - Describing where the SQ 220 * descriptor ring and the SQ packet headers reside: 221 * 0x1 - descriptors and headers are in OS memory, 222 * 0x3 - descriptors and headers in device memory 223 * (a.k.a Low Latency Queue) 224 * 6:4 : completion_policy - Describing what policy 225 * to use for generation completion entry (cqe) in 226 * the CQ associated with this SQ: 0x0 - cqe for each 227 * sq descriptor, 0x1 - cqe upon request in sq 228 * descriptor, 0x2 - current queue head pointer is 229 * updated in OS memory upon sq descriptor request 230 * 0x3 - current queue head pointer is updated in OS 231 * memory for each sq descriptor 232 * 7 : reserved15_w1 233 */ 234 u8 sq_caps_2; 235 236 /* 0 : is_physically_contiguous - Described if the 237 * queue ring memory is allocated in physical 238 * contiguous pages or split. 239 * 7:1 : reserved17_w1 240 */ 241 u8 sq_caps_3; 242 243 /* associated completion queue id. This CQ must be created prior to 244 * SQ creation 245 */ 246 u16 cq_idx; 247 248 /* submission queue depth in entries */ 249 u16 sq_depth; 250 251 /* SQ physical base address in OS memory. This field should not be 252 * used for Low Latency queues. Has to be page aligned. 253 */ 254 struct ena_common_mem_addr sq_ba; 255 256 /* specifies queue head writeback location in OS memory. Valid if 257 * completion_policy is set to completion_policy_head_on_demand or 258 * completion_policy_head. Has to be cache aligned 259 */ 260 struct ena_common_mem_addr sq_head_writeback; 261 262 u32 reserved0_w7; 263 264 u32 reserved0_w8; 265 }; 266 267 enum ena_admin_sq_direction { 268 ENA_ADMIN_SQ_DIRECTION_TX = 1, 269 ENA_ADMIN_SQ_DIRECTION_RX = 2, 270 }; 271 272 struct ena_admin_acq_create_sq_resp_desc { 273 struct ena_admin_acq_common_desc acq_common_desc; 274 275 u16 sq_idx; 276 277 u16 reserved; 278 279 /* queue doorbell address as an offset to PCIe MMIO REG BAR */ 280 u32 sq_doorbell_offset; 281 282 /* low latency queue ring base address as an offset to PCIe MMIO 283 * LLQ_MEM BAR 284 */ 285 u32 llq_descriptors_offset; 286 287 /* low latency queue headers' memory as an offset to PCIe MMIO 288 * LLQ_MEM BAR 289 */ 290 u32 llq_headers_offset; 291 }; 292 293 struct ena_admin_aq_destroy_sq_cmd { 294 struct ena_admin_aq_common_desc aq_common_descriptor; 295 296 struct ena_admin_sq sq; 297 }; 298 299 struct ena_admin_acq_destroy_sq_resp_desc { 300 struct ena_admin_acq_common_desc acq_common_desc; 301 }; 302 303 struct ena_admin_aq_create_cq_cmd { 304 struct ena_admin_aq_common_desc aq_common_descriptor; 305 306 /* 4:0 : reserved5 307 * 5 : interrupt_mode_enabled - if set, cq operates 308 * in interrupt mode, otherwise - polling 309 * 7:6 : reserved6 310 */ 311 u8 cq_caps_1; 312 313 /* 4:0 : cq_entry_size_words - size of CQ entry in 314 * 32-bit words, valid values: 4, 8. 315 * 7:5 : reserved7 316 */ 317 u8 cq_caps_2; 318 319 /* completion queue depth in # of entries. must be power of 2 */ 320 u16 cq_depth; 321 322 /* msix vector assigned to this cq */ 323 u32 msix_vector; 324 325 /* cq physical base address in OS memory. CQ must be physically 326 * contiguous 327 */ 328 struct ena_common_mem_addr cq_ba; 329 }; 330 331 struct ena_admin_acq_create_cq_resp_desc { 332 struct ena_admin_acq_common_desc acq_common_desc; 333 334 u16 cq_idx; 335 336 /* actual cq depth in number of entries */ 337 u16 cq_actual_depth; 338 339 u32 numa_node_register_offset; 340 341 u32 cq_head_db_register_offset; 342 343 u32 cq_interrupt_unmask_register_offset; 344 }; 345 346 struct ena_admin_aq_destroy_cq_cmd { 347 struct ena_admin_aq_common_desc aq_common_descriptor; 348 349 u16 cq_idx; 350 351 u16 reserved1; 352 }; 353 354 struct ena_admin_acq_destroy_cq_resp_desc { 355 struct ena_admin_acq_common_desc acq_common_desc; 356 }; 357 358 /* ENA AQ Get Statistics command. Extended statistics are placed in control 359 * buffer pointed by AQ entry 360 */ 361 struct ena_admin_aq_get_stats_cmd { 362 struct ena_admin_aq_common_desc aq_common_descriptor; 363 364 union { 365 /* command specific inline data */ 366 u32 inline_data_w1[3]; 367 368 struct ena_admin_ctrl_buff_info control_buffer; 369 } u; 370 371 /* stats type as defined in enum ena_admin_get_stats_type */ 372 u8 type; 373 374 /* stats scope defined in enum ena_admin_get_stats_scope */ 375 u8 scope; 376 377 u16 reserved3; 378 379 /* queue id. used when scope is specific_queue */ 380 u16 queue_idx; 381 382 /* device id, value 0xFFFF means mine. only privileged device can get 383 * stats of other device 384 */ 385 u16 device_id; 386 }; 387 388 /* Basic Statistics Command. */ 389 struct ena_admin_basic_stats { 390 u32 tx_bytes_low; 391 392 u32 tx_bytes_high; 393 394 u32 tx_pkts_low; 395 396 u32 tx_pkts_high; 397 398 u32 rx_bytes_low; 399 400 u32 rx_bytes_high; 401 402 u32 rx_pkts_low; 403 404 u32 rx_pkts_high; 405 406 u32 rx_drops_low; 407 408 u32 rx_drops_high; 409 410 u32 tx_drops_low; 411 412 u32 tx_drops_high; 413 }; 414 415 /* ENI Statistics Command. */ 416 struct ena_admin_eni_stats { 417 /* The number of packets shaped due to inbound aggregate BW 418 * allowance being exceeded 419 */ 420 u64 bw_in_allowance_exceeded; 421 422 /* The number of packets shaped due to outbound aggregate BW 423 * allowance being exceeded 424 */ 425 u64 bw_out_allowance_exceeded; 426 427 /* The number of packets shaped due to PPS allowance being exceeded */ 428 u64 pps_allowance_exceeded; 429 430 /* The number of packets shaped due to connection tracking 431 * allowance being exceeded and leading to failure in establishment 432 * of new connections 433 */ 434 u64 conntrack_allowance_exceeded; 435 436 /* The number of packets shaped due to linklocal packet rate 437 * allowance being exceeded 438 */ 439 u64 linklocal_allowance_exceeded; 440 }; 441 442 struct ena_admin_acq_get_stats_resp { 443 struct ena_admin_acq_common_desc acq_common_desc; 444 445 union { 446 u64 raw[7]; 447 448 struct ena_admin_basic_stats basic_stats; 449 450 struct ena_admin_eni_stats eni_stats; 451 } u; 452 }; 453 454 struct ena_admin_get_set_feature_common_desc { 455 /* 1:0 : select - 0x1 - current value; 0x3 - default 456 * value 457 * 7:3 : reserved3 458 */ 459 u8 flags; 460 461 /* as appears in ena_admin_aq_feature_id */ 462 u8 feature_id; 463 464 /* The driver specifies the max feature version it supports and the 465 * device responds with the currently supported feature version. The 466 * field is zero based 467 */ 468 u8 feature_version; 469 470 u8 reserved8; 471 }; 472 473 struct ena_admin_device_attr_feature_desc { 474 u32 impl_id; 475 476 u32 device_version; 477 478 /* bitmap of ena_admin_aq_feature_id */ 479 u32 supported_features; 480 481 u32 reserved3; 482 483 /* Indicates how many bits are used physical address access. */ 484 u32 phys_addr_width; 485 486 /* Indicates how many bits are used virtual address access. */ 487 u32 virt_addr_width; 488 489 /* unicast MAC address (in Network byte order) */ 490 u8 mac_addr[6]; 491 492 u8 reserved7[2]; 493 494 u32 max_mtu; 495 }; 496 497 enum ena_admin_llq_header_location { 498 /* header is in descriptor list */ 499 ENA_ADMIN_INLINE_HEADER = 1, 500 /* header in a separate ring, implies 16B descriptor list entry */ 501 ENA_ADMIN_HEADER_RING = 2, 502 }; 503 504 enum ena_admin_llq_ring_entry_size { 505 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1, 506 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2, 507 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4, 508 }; 509 510 enum ena_admin_llq_num_descs_before_header { 511 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0, 512 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1, 513 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2, 514 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4, 515 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8, 516 }; 517 518 /* packet descriptor list entry always starts with one or more descriptors, 519 * followed by a header. The rest of the descriptors are located in the 520 * beginning of the subsequent entry. Stride refers to how the rest of the 521 * descriptors are placed. This field is relevant only for inline header 522 * mode 523 */ 524 enum ena_admin_llq_stride_ctrl { 525 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1, 526 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, 527 }; 528 529 enum ena_admin_accel_mode_feat { 530 ENA_ADMIN_DISABLE_META_CACHING = 0, 531 ENA_ADMIN_LIMIT_TX_BURST = 1, 532 }; 533 534 struct ena_admin_accel_mode_get { 535 /* bit field of enum ena_admin_accel_mode_feat */ 536 u16 supported_flags; 537 538 /* maximum burst size between two doorbells. The size is in bytes */ 539 u16 max_tx_burst_size; 540 }; 541 542 struct ena_admin_accel_mode_set { 543 /* bit field of enum ena_admin_accel_mode_feat */ 544 u16 enabled_flags; 545 546 u16 reserved; 547 }; 548 549 struct ena_admin_accel_mode_req { 550 union { 551 u32 raw[2]; 552 553 struct ena_admin_accel_mode_get get; 554 555 struct ena_admin_accel_mode_set set; 556 } u; 557 }; 558 559 struct ena_admin_feature_llq_desc { 560 u32 max_llq_num; 561 562 u32 max_llq_depth; 563 564 /* specify the header locations the device supports. bitfield of 565 * enum ena_admin_llq_header_location. 566 */ 567 u16 header_location_ctrl_supported; 568 569 /* the header location the driver selected to use. */ 570 u16 header_location_ctrl_enabled; 571 572 /* if inline header is specified - this is the size of descriptor 573 * list entry. If header in a separate ring is specified - this is 574 * the size of header ring entry. bitfield of enum 575 * ena_admin_llq_ring_entry_size. specify the entry sizes the device 576 * supports 577 */ 578 u16 entry_size_ctrl_supported; 579 580 /* the entry size the driver selected to use. */ 581 u16 entry_size_ctrl_enabled; 582 583 /* valid only if inline header is specified. First entry associated 584 * with the packet includes descriptors and header. Rest of the 585 * entries occupied by descriptors. This parameter defines the max 586 * number of descriptors precedding the header in the first entry. 587 * The field is bitfield of enum 588 * ena_admin_llq_num_descs_before_header and specify the values the 589 * device supports 590 */ 591 u16 desc_num_before_header_supported; 592 593 /* the desire field the driver selected to use */ 594 u16 desc_num_before_header_enabled; 595 596 /* valid only if inline was chosen. bitfield of enum 597 * ena_admin_llq_stride_ctrl 598 */ 599 u16 descriptors_stride_ctrl_supported; 600 601 /* the stride control the driver selected to use */ 602 u16 descriptors_stride_ctrl_enabled; 603 604 /* reserved */ 605 u32 reserved1; 606 607 /* accelerated low latency queues requirement. driver needs to 608 * support those requirements in order to use accelerated llq 609 */ 610 struct ena_admin_accel_mode_req accel_mode; 611 }; 612 613 struct ena_admin_queue_ext_feature_fields { 614 u32 max_tx_sq_num; 615 616 u32 max_tx_cq_num; 617 618 u32 max_rx_sq_num; 619 620 u32 max_rx_cq_num; 621 622 u32 max_tx_sq_depth; 623 624 u32 max_tx_cq_depth; 625 626 u32 max_rx_sq_depth; 627 628 u32 max_rx_cq_depth; 629 630 u32 max_tx_header_size; 631 632 /* Maximum Descriptors number, including meta descriptor, allowed for 633 * a single Tx packet 634 */ 635 u16 max_per_packet_tx_descs; 636 637 /* Maximum Descriptors number allowed for a single Rx packet */ 638 u16 max_per_packet_rx_descs; 639 }; 640 641 struct ena_admin_queue_feature_desc { 642 u32 max_sq_num; 643 644 u32 max_sq_depth; 645 646 u32 max_cq_num; 647 648 u32 max_cq_depth; 649 650 u32 max_legacy_llq_num; 651 652 u32 max_legacy_llq_depth; 653 654 u32 max_header_size; 655 656 /* Maximum Descriptors number, including meta descriptor, allowed for 657 * a single Tx packet 658 */ 659 u16 max_packet_tx_descs; 660 661 /* Maximum Descriptors number allowed for a single Rx packet */ 662 u16 max_packet_rx_descs; 663 }; 664 665 struct ena_admin_set_feature_mtu_desc { 666 /* exclude L2 */ 667 u32 mtu; 668 }; 669 670 struct ena_admin_set_feature_host_attr_desc { 671 /* host OS info base address in OS memory. host info is 4KB of 672 * physically contiguous 673 */ 674 struct ena_common_mem_addr os_info_ba; 675 676 /* host debug area base address in OS memory. debug area must be 677 * physically contiguous 678 */ 679 struct ena_common_mem_addr debug_ba; 680 681 /* debug area size */ 682 u32 debug_area_size; 683 }; 684 685 struct ena_admin_feature_intr_moder_desc { 686 /* interrupt delay granularity in usec */ 687 u16 intr_delay_resolution; 688 689 u16 reserved; 690 }; 691 692 struct ena_admin_get_feature_link_desc { 693 /* Link speed in Mb */ 694 u32 speed; 695 696 /* bit field of enum ena_admin_link types */ 697 u32 supported; 698 699 /* 0 : autoneg 700 * 1 : duplex - Full Duplex 701 * 31:2 : reserved2 702 */ 703 u32 flags; 704 }; 705 706 struct ena_admin_feature_aenq_desc { 707 /* bitmask for AENQ groups the device can report */ 708 u32 supported_groups; 709 710 /* bitmask for AENQ groups to report */ 711 u32 enabled_groups; 712 }; 713 714 struct ena_admin_feature_offload_desc { 715 /* 0 : TX_L3_csum_ipv4 716 * 1 : TX_L4_ipv4_csum_part - The checksum field 717 * should be initialized with pseudo header checksum 718 * 2 : TX_L4_ipv4_csum_full 719 * 3 : TX_L4_ipv6_csum_part - The checksum field 720 * should be initialized with pseudo header checksum 721 * 4 : TX_L4_ipv6_csum_full 722 * 5 : tso_ipv4 723 * 6 : tso_ipv6 724 * 7 : tso_ecn 725 */ 726 u32 tx; 727 728 /* Receive side supported stateless offload 729 * 0 : RX_L3_csum_ipv4 - IPv4 checksum 730 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum 731 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum 732 * 3 : RX_hash - Hash calculation 733 */ 734 u32 rx_supported; 735 736 u32 rx_enabled; 737 }; 738 739 enum ena_admin_hash_functions { 740 ENA_ADMIN_TOEPLITZ = 1, 741 ENA_ADMIN_CRC32 = 2, 742 }; 743 744 struct ena_admin_feature_rss_flow_hash_control { 745 u32 keys_num; 746 747 u32 reserved; 748 749 u32 key[10]; 750 }; 751 752 struct ena_admin_feature_rss_flow_hash_function { 753 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */ 754 u32 supported_func; 755 756 /* 7:0 : selected_func - bitmask of 757 * ena_admin_hash_functions 758 */ 759 u32 selected_func; 760 761 /* initial value */ 762 u32 init_val; 763 }; 764 765 /* RSS flow hash protocols */ 766 enum ena_admin_flow_hash_proto { 767 ENA_ADMIN_RSS_TCP4 = 0, 768 ENA_ADMIN_RSS_UDP4 = 1, 769 ENA_ADMIN_RSS_TCP6 = 2, 770 ENA_ADMIN_RSS_UDP6 = 3, 771 ENA_ADMIN_RSS_IP4 = 4, 772 ENA_ADMIN_RSS_IP6 = 5, 773 ENA_ADMIN_RSS_IP4_FRAG = 6, 774 ENA_ADMIN_RSS_NOT_IP = 7, 775 /* TCPv6 with extension header */ 776 ENA_ADMIN_RSS_TCP6_EX = 8, 777 /* IPv6 with extension header */ 778 ENA_ADMIN_RSS_IP6_EX = 9, 779 ENA_ADMIN_RSS_PROTO_NUM = 16, 780 }; 781 782 /* RSS flow hash fields */ 783 enum ena_admin_flow_hash_fields { 784 /* Ethernet Dest Addr */ 785 ENA_ADMIN_RSS_L2_DA = BIT(0), 786 /* Ethernet Src Addr */ 787 ENA_ADMIN_RSS_L2_SA = BIT(1), 788 /* ipv4/6 Dest Addr */ 789 ENA_ADMIN_RSS_L3_DA = BIT(2), 790 /* ipv4/6 Src Addr */ 791 ENA_ADMIN_RSS_L3_SA = BIT(3), 792 /* tcp/udp Dest Port */ 793 ENA_ADMIN_RSS_L4_DP = BIT(4), 794 /* tcp/udp Src Port */ 795 ENA_ADMIN_RSS_L4_SP = BIT(5), 796 }; 797 798 struct ena_admin_proto_input { 799 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ 800 u16 fields; 801 802 u16 reserved2; 803 }; 804 805 struct ena_admin_feature_rss_hash_control { 806 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM]; 807 808 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM]; 809 810 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM]; 811 812 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM]; 813 }; 814 815 struct ena_admin_feature_rss_flow_hash_input { 816 /* supported hash input sorting 817 * 1 : L3_sort - support swap L3 addresses if DA is 818 * smaller than SA 819 * 2 : L4_sort - support swap L4 ports if DP smaller 820 * SP 821 */ 822 u16 supported_input_sort; 823 824 /* enabled hash input sorting 825 * 1 : enable_L3_sort - enable swap L3 addresses if 826 * DA smaller than SA 827 * 2 : enable_L4_sort - enable swap L4 ports if DP 828 * smaller than SP 829 */ 830 u16 enabled_input_sort; 831 }; 832 833 enum ena_admin_os_type { 834 ENA_ADMIN_OS_LINUX = 1, 835 ENA_ADMIN_OS_WIN = 2, 836 ENA_ADMIN_OS_DPDK = 3, 837 ENA_ADMIN_OS_FREEBSD = 4, 838 ENA_ADMIN_OS_IPXE = 5, 839 ENA_ADMIN_OS_ESXI = 6, 840 ENA_ADMIN_OS_GROUPS_NUM = 6, 841 }; 842 843 struct ena_admin_host_info { 844 /* defined in enum ena_admin_os_type */ 845 u32 os_type; 846 847 /* os distribution string format */ 848 u8 os_dist_str[128]; 849 850 /* OS distribution numeric format */ 851 u32 os_dist; 852 853 /* kernel version string format */ 854 u8 kernel_ver_str[32]; 855 856 /* Kernel version numeric format */ 857 u32 kernel_ver; 858 859 /* 7:0 : major 860 * 15:8 : minor 861 * 23:16 : sub_minor 862 * 31:24 : module_type 863 */ 864 u32 driver_version; 865 866 /* features bitmap */ 867 u32 supported_network_features[2]; 868 869 /* ENA spec version of driver */ 870 u16 ena_spec_version; 871 872 /* ENA device's Bus, Device and Function 873 * 2:0 : function 874 * 7:3 : device 875 * 15:8 : bus 876 */ 877 u16 bdf; 878 879 /* Number of CPUs */ 880 u16 num_cpus; 881 882 u16 reserved; 883 884 /* 0 : reserved 885 * 1 : rx_offset 886 * 2 : interrupt_moderation 887 * 3 : rx_buf_mirroring 888 * 4 : rss_configurable_function_key 889 * 31:5 : reserved 890 */ 891 u32 driver_supported_features; 892 }; 893 894 struct ena_admin_rss_ind_table_entry { 895 u16 cq_idx; 896 897 u16 reserved; 898 }; 899 900 struct ena_admin_feature_rss_ind_table { 901 /* min supported table size (2^min_size) */ 902 u16 min_size; 903 904 /* max supported table size (2^max_size) */ 905 u16 max_size; 906 907 /* table size (2^size) */ 908 u16 size; 909 910 u16 reserved; 911 912 /* index of the inline entry. 0xFFFFFFFF means invalid */ 913 u32 inline_index; 914 915 /* used for updating single entry, ignored when setting the entire 916 * table through the control buffer. 917 */ 918 struct ena_admin_rss_ind_table_entry inline_entry; 919 }; 920 921 /* When hint value is 0, driver should use it's own predefined value */ 922 struct ena_admin_ena_hw_hints { 923 /* value in ms */ 924 u16 mmio_read_timeout; 925 926 /* value in ms */ 927 u16 driver_watchdog_timeout; 928 929 /* Per packet tx completion timeout. value in ms */ 930 u16 missing_tx_completion_timeout; 931 932 u16 missed_tx_completion_count_threshold_to_reset; 933 934 /* value in ms */ 935 u16 admin_completion_tx_timeout; 936 937 u16 netdev_wd_timeout; 938 939 u16 max_tx_sgl_size; 940 941 u16 max_rx_sgl_size; 942 943 u16 reserved[8]; 944 }; 945 946 struct ena_admin_get_feat_cmd { 947 struct ena_admin_aq_common_desc aq_common_descriptor; 948 949 struct ena_admin_ctrl_buff_info control_buffer; 950 951 struct ena_admin_get_set_feature_common_desc feat_common; 952 953 u32 raw[11]; 954 }; 955 956 struct ena_admin_queue_ext_feature_desc { 957 /* version */ 958 u8 version; 959 960 u8 reserved1[3]; 961 962 union { 963 struct ena_admin_queue_ext_feature_fields max_queue_ext; 964 965 u32 raw[10]; 966 }; 967 }; 968 969 struct ena_admin_get_feat_resp { 970 struct ena_admin_acq_common_desc acq_common_desc; 971 972 union { 973 u32 raw[14]; 974 975 struct ena_admin_device_attr_feature_desc dev_attr; 976 977 struct ena_admin_feature_llq_desc llq; 978 979 struct ena_admin_queue_feature_desc max_queue; 980 981 struct ena_admin_queue_ext_feature_desc max_queue_ext; 982 983 struct ena_admin_feature_aenq_desc aenq; 984 985 struct ena_admin_get_feature_link_desc link; 986 987 struct ena_admin_feature_offload_desc offload; 988 989 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 990 991 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 992 993 struct ena_admin_feature_rss_ind_table ind_table; 994 995 struct ena_admin_feature_intr_moder_desc intr_moderation; 996 997 struct ena_admin_ena_hw_hints hw_hints; 998 } u; 999 }; 1000 1001 struct ena_admin_set_feat_cmd { 1002 struct ena_admin_aq_common_desc aq_common_descriptor; 1003 1004 struct ena_admin_ctrl_buff_info control_buffer; 1005 1006 struct ena_admin_get_set_feature_common_desc feat_common; 1007 1008 union { 1009 u32 raw[11]; 1010 1011 /* mtu size */ 1012 struct ena_admin_set_feature_mtu_desc mtu; 1013 1014 /* host attributes */ 1015 struct ena_admin_set_feature_host_attr_desc host_attr; 1016 1017 /* AENQ configuration */ 1018 struct ena_admin_feature_aenq_desc aenq; 1019 1020 /* rss flow hash function */ 1021 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 1022 1023 /* rss flow hash input */ 1024 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 1025 1026 /* rss indirection table */ 1027 struct ena_admin_feature_rss_ind_table ind_table; 1028 1029 /* LLQ configuration */ 1030 struct ena_admin_feature_llq_desc llq; 1031 } u; 1032 }; 1033 1034 struct ena_admin_set_feat_resp { 1035 struct ena_admin_acq_common_desc acq_common_desc; 1036 1037 union { 1038 u32 raw[14]; 1039 } u; 1040 }; 1041 1042 struct ena_admin_aenq_common_desc { 1043 u16 group; 1044 1045 u16 syndrom; 1046 1047 /* 0 : phase 1048 * 7:1 : reserved - MBZ 1049 */ 1050 u8 flags; 1051 1052 u8 reserved1[3]; 1053 1054 u32 timestamp_low; 1055 1056 u32 timestamp_high; 1057 }; 1058 1059 /* asynchronous event notification groups */ 1060 enum ena_admin_aenq_group { 1061 ENA_ADMIN_LINK_CHANGE = 0, 1062 ENA_ADMIN_FATAL_ERROR = 1, 1063 ENA_ADMIN_WARNING = 2, 1064 ENA_ADMIN_NOTIFICATION = 3, 1065 ENA_ADMIN_KEEP_ALIVE = 4, 1066 ENA_ADMIN_AENQ_GROUPS_NUM = 5, 1067 }; 1068 1069 enum ena_admin_aenq_notification_syndrom { 1070 ENA_ADMIN_SUSPEND = 0, 1071 ENA_ADMIN_RESUME = 1, 1072 ENA_ADMIN_UPDATE_HINTS = 2, 1073 }; 1074 1075 struct ena_admin_aenq_entry { 1076 struct ena_admin_aenq_common_desc aenq_common_desc; 1077 1078 /* command specific inline data */ 1079 u32 inline_data_w4[12]; 1080 }; 1081 1082 struct ena_admin_aenq_link_change_desc { 1083 struct ena_admin_aenq_common_desc aenq_common_desc; 1084 1085 /* 0 : link_status */ 1086 u32 flags; 1087 }; 1088 1089 struct ena_admin_aenq_keep_alive_desc { 1090 struct ena_admin_aenq_common_desc aenq_common_desc; 1091 1092 u32 rx_drops_low; 1093 1094 u32 rx_drops_high; 1095 1096 u32 tx_drops_low; 1097 1098 u32 tx_drops_high; 1099 }; 1100 1101 struct ena_admin_ena_mmio_req_read_less_resp { 1102 u16 req_id; 1103 1104 u16 reg_off; 1105 1106 /* value is valid when poll is cleared */ 1107 u32 reg_val; 1108 }; 1109 1110 /* aq_common_desc */ 1111 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1112 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 1113 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 1114 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 1115 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 1116 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 1117 1118 /* sq */ 1119 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 1120 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) 1121 1122 /* acq_common_desc */ 1123 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1124 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 1125 1126 /* aq_create_sq_cmd */ 1127 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 1128 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) 1129 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) 1130 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 1131 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) 1132 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) 1133 1134 /* aq_create_cq_cmd */ 1135 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 1136 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 1137 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1138 1139 /* get_set_feature_common_desc */ 1140 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 1141 1142 /* get_feature_link_desc */ 1143 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) 1144 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 1145 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) 1146 1147 /* feature_offload_desc */ 1148 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) 1149 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 1150 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 1151 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 1152 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 1153 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 1154 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 1155 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 1156 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 1157 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 1158 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) 1159 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 1160 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) 1161 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 1162 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) 1163 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) 1164 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 1165 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) 1166 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 1167 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) 1168 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 1169 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) 1170 1171 /* feature_rss_flow_hash_function */ 1172 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) 1173 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0) 1174 1175 /* feature_rss_flow_hash_input */ 1176 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 1177 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) 1178 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 1179 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) 1180 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 1181 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) 1182 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 1183 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) 1184 1185 /* host_info */ 1186 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 1187 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 1188 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) 1189 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 1190 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 1191 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 1192 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 1193 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1194 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 1195 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1196 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 1197 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1198 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1 1199 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) 1200 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 1201 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) 1202 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3 1203 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3) 1204 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4 1205 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4) 1206 1207 /* aenq_common_desc */ 1208 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 1209 1210 /* aenq_link_change_desc */ 1211 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) 1212 1213 #endif /* _ENA_ADMIN_H_ */ 1214