1 /* Altera Triple-Speed Ethernet MAC driver 2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved 3 * 4 * Contributors: 5 * Dalon Westergreen 6 * Thomas Chou 7 * Ian Abbott 8 * Yuriy Kozlov 9 * Tobias Klauser 10 * Andriy Smolskyy 11 * Roman Bulgakov 12 * Dmytro Mytarchuk 13 * Matthew Gerlach 14 * 15 * Original driver contributed by SLS. 16 * Major updates contributed by GlobalLogic 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms and conditions of the GNU General Public License, 20 * version 2, as published by the Free Software Foundation. 21 * 22 * This program is distributed in the hope it will be useful, but WITHOUT 23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25 * more details. 26 * 27 * You should have received a copy of the GNU General Public License along with 28 * this program. If not, see <http://www.gnu.org/licenses/>. 29 */ 30 31 #ifndef __ALTERA_TSE_H__ 32 #define __ALTERA_TSE_H__ 33 34 #define ALTERA_TSE_RESOURCE_NAME "altera_tse" 35 36 #include <linux/bitops.h> 37 #include <linux/if_vlan.h> 38 #include <linux/list.h> 39 #include <linux/netdevice.h> 40 #include <linux/phy.h> 41 42 #define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR 10000 43 #define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in 44 * bytes 45 */ 46 /* Rx FIFO default settings */ 47 #define ALTERA_TSE_RX_SECTION_EMPTY 16 48 #define ALTERA_TSE_RX_SECTION_FULL 0 49 #define ALTERA_TSE_RX_ALMOST_EMPTY 8 50 #define ALTERA_TSE_RX_ALMOST_FULL 8 51 52 /* Tx FIFO default settings */ 53 #define ALTERA_TSE_TX_SECTION_EMPTY 16 54 #define ALTERA_TSE_TX_SECTION_FULL 0 55 #define ALTERA_TSE_TX_ALMOST_EMPTY 8 56 #define ALTERA_TSE_TX_ALMOST_FULL 3 57 58 /* MAC function configuration default settings */ 59 #define ALTERA_TSE_TX_IPG_LENGTH 12 60 61 #define ALTERA_TSE_PAUSE_QUANTA 0xffff 62 63 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) 64 65 /* MAC Command_Config Register Bit Definitions 66 */ 67 #define MAC_CMDCFG_TX_ENA BIT(0) 68 #define MAC_CMDCFG_RX_ENA BIT(1) 69 #define MAC_CMDCFG_XON_GEN BIT(2) 70 #define MAC_CMDCFG_ETH_SPEED BIT(3) 71 #define MAC_CMDCFG_PROMIS_EN BIT(4) 72 #define MAC_CMDCFG_PAD_EN BIT(5) 73 #define MAC_CMDCFG_CRC_FWD BIT(6) 74 #define MAC_CMDCFG_PAUSE_FWD BIT(7) 75 #define MAC_CMDCFG_PAUSE_IGNORE BIT(8) 76 #define MAC_CMDCFG_TX_ADDR_INS BIT(9) 77 #define MAC_CMDCFG_HD_ENA BIT(10) 78 #define MAC_CMDCFG_EXCESS_COL BIT(11) 79 #define MAC_CMDCFG_LATE_COL BIT(12) 80 #define MAC_CMDCFG_SW_RESET BIT(13) 81 #define MAC_CMDCFG_MHASH_SEL BIT(14) 82 #define MAC_CMDCFG_LOOP_ENA BIT(15) 83 #define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16) 84 #define MAC_CMDCFG_MAGIC_ENA BIT(19) 85 #define MAC_CMDCFG_SLEEP BIT(20) 86 #define MAC_CMDCFG_WAKEUP BIT(21) 87 #define MAC_CMDCFG_XOFF_GEN BIT(22) 88 #define MAC_CMDCFG_CNTL_FRM_ENA BIT(23) 89 #define MAC_CMDCFG_NO_LGTH_CHECK BIT(24) 90 #define MAC_CMDCFG_ENA_10 BIT(25) 91 #define MAC_CMDCFG_RX_ERR_DISC BIT(26) 92 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT BIT(27) 93 #define MAC_CMDCFG_CNT_RESET BIT(31) 94 95 #define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0) 96 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1) 97 #define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2) 98 #define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3) 99 #define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4) 100 #define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5) 101 #define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6) 102 #define MAC_CMDCFG_PAUSE_FWD_GET(v) GET_BIT_VALUE(v, 7) 103 #define MAC_CMDCFG_PAUSE_IGNORE_GET(v) GET_BIT_VALUE(v, 8) 104 #define MAC_CMDCFG_TX_ADDR_INS_GET(v) GET_BIT_VALUE(v, 9) 105 #define MAC_CMDCFG_HD_ENA_GET(v) GET_BIT_VALUE(v, 10) 106 #define MAC_CMDCFG_EXCESS_COL_GET(v) GET_BIT_VALUE(v, 11) 107 #define MAC_CMDCFG_LATE_COL_GET(v) GET_BIT_VALUE(v, 12) 108 #define MAC_CMDCFG_SW_RESET_GET(v) GET_BIT_VALUE(v, 13) 109 #define MAC_CMDCFG_MHASH_SEL_GET(v) GET_BIT_VALUE(v, 14) 110 #define MAC_CMDCFG_LOOP_ENA_GET(v) GET_BIT_VALUE(v, 15) 111 #define MAC_CMDCFG_TX_ADDR_SEL_GET(v) (((v) >> 16) & 0x7) 112 #define MAC_CMDCFG_MAGIC_ENA_GET(v) GET_BIT_VALUE(v, 19) 113 #define MAC_CMDCFG_SLEEP_GET(v) GET_BIT_VALUE(v, 20) 114 #define MAC_CMDCFG_WAKEUP_GET(v) GET_BIT_VALUE(v, 21) 115 #define MAC_CMDCFG_XOFF_GEN_GET(v) GET_BIT_VALUE(v, 22) 116 #define MAC_CMDCFG_CNTL_FRM_ENA_GET(v) GET_BIT_VALUE(v, 23) 117 #define MAC_CMDCFG_NO_LGTH_CHECK_GET(v) GET_BIT_VALUE(v, 24) 118 #define MAC_CMDCFG_ENA_10_GET(v) GET_BIT_VALUE(v, 25) 119 #define MAC_CMDCFG_RX_ERR_DISC_GET(v) GET_BIT_VALUE(v, 26) 120 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v) GET_BIT_VALUE(v, 27) 121 #define MAC_CMDCFG_CNT_RESET_GET(v) GET_BIT_VALUE(v, 31) 122 123 /* SGMII PCS register addresses 124 */ 125 #define SGMII_PCS_SCRATCH 0x10 126 #define SGMII_PCS_REV 0x11 127 #define SGMII_PCS_LINK_TIMER_0 0x12 128 #define SGMII_PCS_LINK_TIMER_1 0x13 129 #define SGMII_PCS_IF_MODE 0x14 130 #define SGMII_PCS_DIS_READ_TO 0x15 131 #define SGMII_PCS_READ_TO 0x16 132 #define SGMII_PCS_SW_RESET_TIMEOUT 100 /* usecs */ 133 134 /* MDIO registers within MAC register Space 135 */ 136 struct altera_tse_mdio { 137 u32 control; /* PHY device operation control register */ 138 u32 status; /* PHY device operation status register */ 139 u32 phy_id1; /* Bits 31:16 of PHY identifier */ 140 u32 phy_id2; /* Bits 15:0 of PHY identifier */ 141 u32 auto_negotiation_advertisement; /* Auto-negotiation 142 * advertisement 143 * register 144 */ 145 u32 remote_partner_base_page_ability; 146 147 u32 reg6; 148 u32 reg7; 149 u32 reg8; 150 u32 reg9; 151 u32 rega; 152 u32 regb; 153 u32 regc; 154 u32 regd; 155 u32 rege; 156 u32 regf; 157 u32 reg10; 158 u32 reg11; 159 u32 reg12; 160 u32 reg13; 161 u32 reg14; 162 u32 reg15; 163 u32 reg16; 164 u32 reg17; 165 u32 reg18; 166 u32 reg19; 167 u32 reg1a; 168 u32 reg1b; 169 u32 reg1c; 170 u32 reg1d; 171 u32 reg1e; 172 u32 reg1f; 173 }; 174 175 /* MAC register Space. Note that some of these registers may or may not be 176 * present depending upon options chosen by the user when the core was 177 * configured and built. Please consult the Altera Triple Speed Ethernet User 178 * Guide for details. 179 */ 180 struct altera_tse_mac { 181 /* Bits 15:0: MegaCore function revision (0x0800). Bit 31:16: Customer 182 * specific revision 183 */ 184 u32 megacore_revision; 185 /* Provides a memory location for user applications to test the device 186 * memory operation. 187 */ 188 u32 scratch_pad; 189 /* The host processor uses this register to control and configure the 190 * MAC block 191 */ 192 u32 command_config; 193 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary 194 * MAC address 195 */ 196 u32 mac_addr_0; 197 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary 198 * MAC address 199 */ 200 u32 mac_addr_1; 201 /* 14-bit maximum frame length. The MAC receive logic */ 202 u32 frm_length; 203 /* The pause quanta is used in each pause frame sent to a remote 204 * Ethernet device, in increments of 512 Ethernet bit times 205 */ 206 u32 pause_quanta; 207 /* 12-bit receive FIFO section-empty threshold */ 208 u32 rx_section_empty; 209 /* 12-bit receive FIFO section-full threshold */ 210 u32 rx_section_full; 211 /* 12-bit transmit FIFO section-empty threshold */ 212 u32 tx_section_empty; 213 /* 12-bit transmit FIFO section-full threshold */ 214 u32 tx_section_full; 215 /* 12-bit receive FIFO almost-empty threshold */ 216 u32 rx_almost_empty; 217 /* 12-bit receive FIFO almost-full threshold */ 218 u32 rx_almost_full; 219 /* 12-bit transmit FIFO almost-empty threshold */ 220 u32 tx_almost_empty; 221 /* 12-bit transmit FIFO almost-full threshold */ 222 u32 tx_almost_full; 223 /* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */ 224 u32 mdio_phy0_addr; 225 /* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */ 226 u32 mdio_phy1_addr; 227 228 /* Bit[15:0]—16-bit holdoff quanta */ 229 u32 holdoff_quant; 230 231 /* only if 100/1000 BaseX PCS, reserved otherwise */ 232 u32 reserved1[5]; 233 234 /* Minimum IPG between consecutive transmit frame in terms of bytes */ 235 u32 tx_ipg_length; 236 237 /* IEEE 802.3 oEntity Managed Object Support */ 238 239 /* The MAC addresses */ 240 u32 mac_id_1; 241 u32 mac_id_2; 242 243 /* Number of frames transmitted without error including pause frames */ 244 u32 frames_transmitted_ok; 245 /* Number of frames received without error including pause frames */ 246 u32 frames_received_ok; 247 /* Number of frames received with a CRC error */ 248 u32 frames_check_sequence_errors; 249 /* Frame received with an alignment error */ 250 u32 alignment_errors; 251 /* Sum of payload and padding octets of frames transmitted without 252 * error 253 */ 254 u32 octets_transmitted_ok; 255 /* Sum of payload and padding octets of frames received without error */ 256 u32 octets_received_ok; 257 258 /* IEEE 802.3 oPausedEntity Managed Object Support */ 259 260 /* Number of transmitted pause frames */ 261 u32 tx_pause_mac_ctrl_frames; 262 /* Number of Received pause frames */ 263 u32 rx_pause_mac_ctrl_frames; 264 265 /* IETF MIB (MIB-II) Object Support */ 266 267 /* Number of frames received with error */ 268 u32 if_in_errors; 269 /* Number of frames transmitted with error */ 270 u32 if_out_errors; 271 /* Number of valid received unicast frames */ 272 u32 if_in_ucast_pkts; 273 /* Number of valid received multicasts frames (without pause) */ 274 u32 if_in_multicast_pkts; 275 /* Number of valid received broadcast frames */ 276 u32 if_in_broadcast_pkts; 277 u32 if_out_discards; 278 /* The number of valid unicast frames transmitted */ 279 u32 if_out_ucast_pkts; 280 /* The number of valid multicast frames transmitted, 281 * excluding pause frames 282 */ 283 u32 if_out_multicast_pkts; 284 u32 if_out_broadcast_pkts; 285 286 /* IETF RMON MIB Object Support */ 287 288 /* Counts the number of dropped packets due to internal errors 289 * of the MAC client. 290 */ 291 u32 ether_stats_drop_events; 292 /* Total number of bytes received. Good and bad frames. */ 293 u32 ether_stats_octets; 294 /* Total number of packets received. Counts good and bad packets. */ 295 u32 ether_stats_pkts; 296 /* Number of packets received with less than 64 bytes. */ 297 u32 ether_stats_undersize_pkts; 298 /* The number of frames received that are longer than the 299 * value configured in the frm_length register 300 */ 301 u32 ether_stats_oversize_pkts; 302 /* Number of received packet with 64 bytes */ 303 u32 ether_stats_pkts_64_octets; 304 /* Frames (good and bad) with 65 to 127 bytes */ 305 u32 ether_stats_pkts_65to127_octets; 306 /* Frames (good and bad) with 128 to 255 bytes */ 307 u32 ether_stats_pkts_128to255_octets; 308 /* Frames (good and bad) with 256 to 511 bytes */ 309 u32 ether_stats_pkts_256to511_octets; 310 /* Frames (good and bad) with 512 to 1023 bytes */ 311 u32 ether_stats_pkts_512to1023_octets; 312 /* Frames (good and bad) with 1024 to 1518 bytes */ 313 u32 ether_stats_pkts_1024to1518_octets; 314 315 /* Any frame length from 1519 to the maximum length configured in the 316 * frm_length register, if it is greater than 1518 317 */ 318 u32 ether_stats_pkts_1519tox_octets; 319 /* Too long frames with CRC error */ 320 u32 ether_stats_jabbers; 321 /* Too short frames with CRC error */ 322 u32 ether_stats_fragments; 323 324 u32 reserved2; 325 326 /* FIFO control register */ 327 u32 tx_cmd_stat; 328 u32 rx_cmd_stat; 329 330 /* Extended Statistics Counters */ 331 u32 msb_octets_transmitted_ok; 332 u32 msb_octets_received_ok; 333 u32 msb_ether_stats_octets; 334 335 u32 reserved3; 336 337 /* Multicast address resolution table, mapped in the controller address 338 * space 339 */ 340 u32 hash_table[64]; 341 342 /* Registers 0 to 31 within PHY device 0/1 connected to the MDIO PHY 343 * management interface 344 */ 345 struct altera_tse_mdio mdio_phy0; 346 struct altera_tse_mdio mdio_phy1; 347 348 /* 4 Supplemental MAC Addresses */ 349 u32 supp_mac_addr_0_0; 350 u32 supp_mac_addr_0_1; 351 u32 supp_mac_addr_1_0; 352 u32 supp_mac_addr_1_1; 353 u32 supp_mac_addr_2_0; 354 u32 supp_mac_addr_2_1; 355 u32 supp_mac_addr_3_0; 356 u32 supp_mac_addr_3_1; 357 358 u32 reserved4[8]; 359 360 /* IEEE 1588v2 Feature */ 361 u32 tx_period; 362 u32 tx_adjust_fns; 363 u32 tx_adjust_ns; 364 u32 rx_period; 365 u32 rx_adjust_fns; 366 u32 rx_adjust_ns; 367 368 u32 reserved5[42]; 369 }; 370 371 #define tse_csroffs(a) (offsetof(struct altera_tse_mac, a)) 372 373 /* Transmit and Receive Command Registers Bit Definitions 374 */ 375 #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17) 376 #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 BIT(18) 377 #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 BIT(25) 378 379 /* Wrapper around a pointer to a socket buffer, 380 * so a DMA handle can be stored along with the buffer 381 */ 382 struct tse_buffer { 383 struct list_head lh; 384 struct sk_buff *skb; 385 dma_addr_t dma_addr; 386 u32 len; 387 int mapped_as_page; 388 }; 389 390 struct altera_tse_private; 391 392 #define ALTERA_DTYPE_SGDMA 1 393 #define ALTERA_DTYPE_MSGDMA 2 394 395 /* standard DMA interface for SGDMA and MSGDMA */ 396 struct altera_dmaops { 397 int altera_dtype; 398 int dmamask; 399 void (*reset_dma)(struct altera_tse_private *); 400 void (*enable_txirq)(struct altera_tse_private *); 401 void (*enable_rxirq)(struct altera_tse_private *); 402 void (*disable_txirq)(struct altera_tse_private *); 403 void (*disable_rxirq)(struct altera_tse_private *); 404 void (*clear_txirq)(struct altera_tse_private *); 405 void (*clear_rxirq)(struct altera_tse_private *); 406 int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *); 407 u32 (*tx_completions)(struct altera_tse_private *); 408 void (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *); 409 u32 (*get_rx_status)(struct altera_tse_private *); 410 int (*init_dma)(struct altera_tse_private *); 411 void (*uninit_dma)(struct altera_tse_private *); 412 void (*start_rxdma)(struct altera_tse_private *); 413 }; 414 415 /* This structure is private to each device. 416 */ 417 struct altera_tse_private { 418 struct net_device *dev; 419 struct device *device; 420 struct napi_struct napi; 421 422 /* MAC address space */ 423 struct altera_tse_mac __iomem *mac_dev; 424 425 /* TSE Revision */ 426 u32 revision; 427 428 /* mSGDMA Rx Dispatcher address space */ 429 void __iomem *rx_dma_csr; 430 void __iomem *rx_dma_desc; 431 void __iomem *rx_dma_resp; 432 433 /* mSGDMA Tx Dispatcher address space */ 434 void __iomem *tx_dma_csr; 435 void __iomem *tx_dma_desc; 436 437 /* Rx buffers queue */ 438 struct tse_buffer *rx_ring; 439 u32 rx_cons; 440 u32 rx_prod; 441 u32 rx_ring_size; 442 u32 rx_dma_buf_sz; 443 444 /* Tx ring buffer */ 445 struct tse_buffer *tx_ring; 446 u32 tx_prod; 447 u32 tx_cons; 448 u32 tx_ring_size; 449 450 /* Interrupts */ 451 u32 tx_irq; 452 u32 rx_irq; 453 454 /* RX/TX MAC FIFO configs */ 455 u32 tx_fifo_depth; 456 u32 rx_fifo_depth; 457 458 /* Hash filter settings */ 459 u32 hash_filter; 460 u32 added_unicast; 461 462 /* Descriptor memory info for managing SGDMA */ 463 u32 txdescmem; 464 u32 rxdescmem; 465 dma_addr_t rxdescmem_busaddr; 466 dma_addr_t txdescmem_busaddr; 467 u32 txctrlreg; 468 u32 rxctrlreg; 469 dma_addr_t rxdescphys; 470 dma_addr_t txdescphys; 471 472 struct list_head txlisthd; 473 struct list_head rxlisthd; 474 475 /* MAC command_config register protection */ 476 spinlock_t mac_cfg_lock; 477 /* Tx path protection */ 478 spinlock_t tx_lock; 479 /* Rx DMA & interrupt control protection */ 480 spinlock_t rxdma_irq_lock; 481 482 /* PHY */ 483 int phy_addr; /* PHY's MDIO address, -1 for autodetection */ 484 phy_interface_t phy_iface; 485 struct mii_bus *mdio; 486 int oldspeed; 487 int oldduplex; 488 int oldlink; 489 490 /* ethtool msglvl option */ 491 u32 msg_enable; 492 493 struct altera_dmaops *dmaops; 494 }; 495 496 /* Function prototypes 497 */ 498 void altera_tse_set_ethtool_ops(struct net_device *); 499 500 static inline 501 u32 csrrd32(void __iomem *mac, size_t offs) 502 { 503 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 504 return readl(paddr); 505 } 506 507 static inline 508 u16 csrrd16(void __iomem *mac, size_t offs) 509 { 510 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 511 return readw(paddr); 512 } 513 514 static inline 515 u8 csrrd8(void __iomem *mac, size_t offs) 516 { 517 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 518 return readb(paddr); 519 } 520 521 static inline 522 void csrwr32(u32 val, void __iomem *mac, size_t offs) 523 { 524 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 525 526 writel(val, paddr); 527 } 528 529 static inline 530 void csrwr16(u16 val, void __iomem *mac, size_t offs) 531 { 532 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 533 534 writew(val, paddr); 535 } 536 537 static inline 538 void csrwr8(u8 val, void __iomem *mac, size_t offs) 539 { 540 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 541 542 writeb(val, paddr); 543 } 544 545 #endif /* __ALTERA_TSE_H__ */ 546