1 /* Altera Triple-Speed Ethernet MAC driver 2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved 3 * 4 * Contributors: 5 * Dalon Westergreen 6 * Thomas Chou 7 * Ian Abbott 8 * Yuriy Kozlov 9 * Tobias Klauser 10 * Andriy Smolskyy 11 * Roman Bulgakov 12 * Dmytro Mytarchuk 13 * Matthew Gerlach 14 * 15 * Original driver contributed by SLS. 16 * Major updates contributed by GlobalLogic 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms and conditions of the GNU General Public License, 20 * version 2, as published by the Free Software Foundation. 21 * 22 * This program is distributed in the hope it will be useful, but WITHOUT 23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25 * more details. 26 * 27 * You should have received a copy of the GNU General Public License along with 28 * this program. If not, see <http://www.gnu.org/licenses/>. 29 */ 30 31 #ifndef __ALTERA_TSE_H__ 32 #define __ALTERA_TSE_H__ 33 34 #define ALTERA_TSE_RESOURCE_NAME "altera_tse" 35 36 #include <linux/bitops.h> 37 #include <linux/if_vlan.h> 38 #include <linux/list.h> 39 #include <linux/netdevice.h> 40 #include <linux/phy.h> 41 42 #define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR 10000 43 #define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in 44 * bytes 45 */ 46 /* Rx FIFO default settings */ 47 #define ALTERA_TSE_RX_SECTION_EMPTY 16 48 #define ALTERA_TSE_RX_SECTION_FULL 0 49 #define ALTERA_TSE_RX_ALMOST_EMPTY 8 50 #define ALTERA_TSE_RX_ALMOST_FULL 8 51 52 /* Tx FIFO default settings */ 53 #define ALTERA_TSE_TX_SECTION_EMPTY 16 54 #define ALTERA_TSE_TX_SECTION_FULL 0 55 #define ALTERA_TSE_TX_ALMOST_EMPTY 8 56 #define ALTERA_TSE_TX_ALMOST_FULL 3 57 58 /* MAC function configuration default settings */ 59 #define ALTERA_TSE_TX_IPG_LENGTH 12 60 61 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) 62 63 /* MAC Command_Config Register Bit Definitions 64 */ 65 #define MAC_CMDCFG_TX_ENA BIT(0) 66 #define MAC_CMDCFG_RX_ENA BIT(1) 67 #define MAC_CMDCFG_XON_GEN BIT(2) 68 #define MAC_CMDCFG_ETH_SPEED BIT(3) 69 #define MAC_CMDCFG_PROMIS_EN BIT(4) 70 #define MAC_CMDCFG_PAD_EN BIT(5) 71 #define MAC_CMDCFG_CRC_FWD BIT(6) 72 #define MAC_CMDCFG_PAUSE_FWD BIT(7) 73 #define MAC_CMDCFG_PAUSE_IGNORE BIT(8) 74 #define MAC_CMDCFG_TX_ADDR_INS BIT(9) 75 #define MAC_CMDCFG_HD_ENA BIT(10) 76 #define MAC_CMDCFG_EXCESS_COL BIT(11) 77 #define MAC_CMDCFG_LATE_COL BIT(12) 78 #define MAC_CMDCFG_SW_RESET BIT(13) 79 #define MAC_CMDCFG_MHASH_SEL BIT(14) 80 #define MAC_CMDCFG_LOOP_ENA BIT(15) 81 #define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16) 82 #define MAC_CMDCFG_MAGIC_ENA BIT(19) 83 #define MAC_CMDCFG_SLEEP BIT(20) 84 #define MAC_CMDCFG_WAKEUP BIT(21) 85 #define MAC_CMDCFG_XOFF_GEN BIT(22) 86 #define MAC_CMDCFG_CNTL_FRM_ENA BIT(23) 87 #define MAC_CMDCFG_NO_LGTH_CHECK BIT(24) 88 #define MAC_CMDCFG_ENA_10 BIT(25) 89 #define MAC_CMDCFG_RX_ERR_DISC BIT(26) 90 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT BIT(27) 91 #define MAC_CMDCFG_CNT_RESET BIT(31) 92 93 #define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0) 94 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1) 95 #define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2) 96 #define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3) 97 #define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4) 98 #define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5) 99 #define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6) 100 #define MAC_CMDCFG_PAUSE_FWD_GET(v) GET_BIT_VALUE(v, 7) 101 #define MAC_CMDCFG_PAUSE_IGNORE_GET(v) GET_BIT_VALUE(v, 8) 102 #define MAC_CMDCFG_TX_ADDR_INS_GET(v) GET_BIT_VALUE(v, 9) 103 #define MAC_CMDCFG_HD_ENA_GET(v) GET_BIT_VALUE(v, 10) 104 #define MAC_CMDCFG_EXCESS_COL_GET(v) GET_BIT_VALUE(v, 11) 105 #define MAC_CMDCFG_LATE_COL_GET(v) GET_BIT_VALUE(v, 12) 106 #define MAC_CMDCFG_SW_RESET_GET(v) GET_BIT_VALUE(v, 13) 107 #define MAC_CMDCFG_MHASH_SEL_GET(v) GET_BIT_VALUE(v, 14) 108 #define MAC_CMDCFG_LOOP_ENA_GET(v) GET_BIT_VALUE(v, 15) 109 #define MAC_CMDCFG_TX_ADDR_SEL_GET(v) (((v) >> 16) & 0x7) 110 #define MAC_CMDCFG_MAGIC_ENA_GET(v) GET_BIT_VALUE(v, 19) 111 #define MAC_CMDCFG_SLEEP_GET(v) GET_BIT_VALUE(v, 20) 112 #define MAC_CMDCFG_WAKEUP_GET(v) GET_BIT_VALUE(v, 21) 113 #define MAC_CMDCFG_XOFF_GEN_GET(v) GET_BIT_VALUE(v, 22) 114 #define MAC_CMDCFG_CNTL_FRM_ENA_GET(v) GET_BIT_VALUE(v, 23) 115 #define MAC_CMDCFG_NO_LGTH_CHECK_GET(v) GET_BIT_VALUE(v, 24) 116 #define MAC_CMDCFG_ENA_10_GET(v) GET_BIT_VALUE(v, 25) 117 #define MAC_CMDCFG_RX_ERR_DISC_GET(v) GET_BIT_VALUE(v, 26) 118 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v) GET_BIT_VALUE(v, 27) 119 #define MAC_CMDCFG_CNT_RESET_GET(v) GET_BIT_VALUE(v, 31) 120 121 /* MDIO registers within MAC register Space 122 */ 123 struct altera_tse_mdio { 124 u32 control; /* PHY device operation control register */ 125 u32 status; /* PHY device operation status register */ 126 u32 phy_id1; /* Bits 31:16 of PHY identifier */ 127 u32 phy_id2; /* Bits 15:0 of PHY identifier */ 128 u32 auto_negotiation_advertisement; /* Auto-negotiation 129 * advertisement 130 * register 131 */ 132 u32 remote_partner_base_page_ability; 133 134 u32 reg6; 135 u32 reg7; 136 u32 reg8; 137 u32 reg9; 138 u32 rega; 139 u32 regb; 140 u32 regc; 141 u32 regd; 142 u32 rege; 143 u32 regf; 144 u32 reg10; 145 u32 reg11; 146 u32 reg12; 147 u32 reg13; 148 u32 reg14; 149 u32 reg15; 150 u32 reg16; 151 u32 reg17; 152 u32 reg18; 153 u32 reg19; 154 u32 reg1a; 155 u32 reg1b; 156 u32 reg1c; 157 u32 reg1d; 158 u32 reg1e; 159 u32 reg1f; 160 }; 161 162 /* MAC register Space. Note that some of these registers may or may not be 163 * present depending upon options chosen by the user when the core was 164 * configured and built. Please consult the Altera Triple Speed Ethernet User 165 * Guide for details. 166 */ 167 struct altera_tse_mac { 168 /* Bits 15:0: MegaCore function revision (0x0800). Bit 31:16: Customer 169 * specific revision 170 */ 171 u32 megacore_revision; 172 /* Provides a memory location for user applications to test the device 173 * memory operation. 174 */ 175 u32 scratch_pad; 176 /* The host processor uses this register to control and configure the 177 * MAC block 178 */ 179 u32 command_config; 180 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary 181 * MAC address 182 */ 183 u32 mac_addr_0; 184 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary 185 * MAC address 186 */ 187 u32 mac_addr_1; 188 /* 14-bit maximum frame length. The MAC receive logic */ 189 u32 frm_length; 190 /* The pause quanta is used in each pause frame sent to a remote 191 * Ethernet device, in increments of 512 Ethernet bit times 192 */ 193 u32 pause_quanta; 194 /* 12-bit receive FIFO section-empty threshold */ 195 u32 rx_section_empty; 196 /* 12-bit receive FIFO section-full threshold */ 197 u32 rx_section_full; 198 /* 12-bit transmit FIFO section-empty threshold */ 199 u32 tx_section_empty; 200 /* 12-bit transmit FIFO section-full threshold */ 201 u32 tx_section_full; 202 /* 12-bit receive FIFO almost-empty threshold */ 203 u32 rx_almost_empty; 204 /* 12-bit receive FIFO almost-full threshold */ 205 u32 rx_almost_full; 206 /* 12-bit transmit FIFO almost-empty threshold */ 207 u32 tx_almost_empty; 208 /* 12-bit transmit FIFO almost-full threshold */ 209 u32 tx_almost_full; 210 /* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */ 211 u32 mdio_phy0_addr; 212 /* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */ 213 u32 mdio_phy1_addr; 214 215 /* Bit[15:0]—16-bit holdoff quanta */ 216 u32 holdoff_quant; 217 218 /* only if 100/1000 BaseX PCS, reserved otherwise */ 219 u32 reserved1[5]; 220 221 /* Minimum IPG between consecutive transmit frame in terms of bytes */ 222 u32 tx_ipg_length; 223 224 /* IEEE 802.3 oEntity Managed Object Support */ 225 226 /* The MAC addresses */ 227 u32 mac_id_1; 228 u32 mac_id_2; 229 230 /* Number of frames transmitted without error including pause frames */ 231 u32 frames_transmitted_ok; 232 /* Number of frames received without error including pause frames */ 233 u32 frames_received_ok; 234 /* Number of frames received with a CRC error */ 235 u32 frames_check_sequence_errors; 236 /* Frame received with an alignment error */ 237 u32 alignment_errors; 238 /* Sum of payload and padding octets of frames transmitted without 239 * error 240 */ 241 u32 octets_transmitted_ok; 242 /* Sum of payload and padding octets of frames received without error */ 243 u32 octets_received_ok; 244 245 /* IEEE 802.3 oPausedEntity Managed Object Support */ 246 247 /* Number of transmitted pause frames */ 248 u32 tx_pause_mac_ctrl_frames; 249 /* Number of Received pause frames */ 250 u32 rx_pause_mac_ctrl_frames; 251 252 /* IETF MIB (MIB-II) Object Support */ 253 254 /* Number of frames received with error */ 255 u32 if_in_errors; 256 /* Number of frames transmitted with error */ 257 u32 if_out_errors; 258 /* Number of valid received unicast frames */ 259 u32 if_in_ucast_pkts; 260 /* Number of valid received multicasts frames (without pause) */ 261 u32 if_in_multicast_pkts; 262 /* Number of valid received broadcast frames */ 263 u32 if_in_broadcast_pkts; 264 u32 if_out_discards; 265 /* The number of valid unicast frames transmitted */ 266 u32 if_out_ucast_pkts; 267 /* The number of valid multicast frames transmitted, 268 * excluding pause frames 269 */ 270 u32 if_out_multicast_pkts; 271 u32 if_out_broadcast_pkts; 272 273 /* IETF RMON MIB Object Support */ 274 275 /* Counts the number of dropped packets due to internal errors 276 * of the MAC client. 277 */ 278 u32 ether_stats_drop_events; 279 /* Total number of bytes received. Good and bad frames. */ 280 u32 ether_stats_octets; 281 /* Total number of packets received. Counts good and bad packets. */ 282 u32 ether_stats_pkts; 283 /* Number of packets received with less than 64 bytes. */ 284 u32 ether_stats_undersize_pkts; 285 /* The number of frames received that are longer than the 286 * value configured in the frm_length register 287 */ 288 u32 ether_stats_oversize_pkts; 289 /* Number of received packet with 64 bytes */ 290 u32 ether_stats_pkts_64_octets; 291 /* Frames (good and bad) with 65 to 127 bytes */ 292 u32 ether_stats_pkts_65to127_octets; 293 /* Frames (good and bad) with 128 to 255 bytes */ 294 u32 ether_stats_pkts_128to255_octets; 295 /* Frames (good and bad) with 256 to 511 bytes */ 296 u32 ether_stats_pkts_256to511_octets; 297 /* Frames (good and bad) with 512 to 1023 bytes */ 298 u32 ether_stats_pkts_512to1023_octets; 299 /* Frames (good and bad) with 1024 to 1518 bytes */ 300 u32 ether_stats_pkts_1024to1518_octets; 301 302 /* Any frame length from 1519 to the maximum length configured in the 303 * frm_length register, if it is greater than 1518 304 */ 305 u32 ether_stats_pkts_1519tox_octets; 306 /* Too long frames with CRC error */ 307 u32 ether_stats_jabbers; 308 /* Too short frames with CRC error */ 309 u32 ether_stats_fragments; 310 311 u32 reserved2; 312 313 /* FIFO control register */ 314 u32 tx_cmd_stat; 315 u32 rx_cmd_stat; 316 317 /* Extended Statistics Counters */ 318 u32 msb_octets_transmitted_ok; 319 u32 msb_octets_received_ok; 320 u32 msb_ether_stats_octets; 321 322 u32 reserved3; 323 324 /* Multicast address resolution table, mapped in the controller address 325 * space 326 */ 327 u32 hash_table[64]; 328 329 /* Registers 0 to 31 within PHY device 0/1 connected to the MDIO PHY 330 * management interface 331 */ 332 struct altera_tse_mdio mdio_phy0; 333 struct altera_tse_mdio mdio_phy1; 334 335 /* 4 Supplemental MAC Addresses */ 336 u32 supp_mac_addr_0_0; 337 u32 supp_mac_addr_0_1; 338 u32 supp_mac_addr_1_0; 339 u32 supp_mac_addr_1_1; 340 u32 supp_mac_addr_2_0; 341 u32 supp_mac_addr_2_1; 342 u32 supp_mac_addr_3_0; 343 u32 supp_mac_addr_3_1; 344 345 u32 reserved4[8]; 346 347 /* IEEE 1588v2 Feature */ 348 u32 tx_period; 349 u32 tx_adjust_fns; 350 u32 tx_adjust_ns; 351 u32 rx_period; 352 u32 rx_adjust_fns; 353 u32 rx_adjust_ns; 354 355 u32 reserved5[42]; 356 }; 357 358 /* Transmit and Receive Command Registers Bit Definitions 359 */ 360 #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17) 361 #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 BIT(18) 362 #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 BIT(25) 363 364 /* Wrapper around a pointer to a socket buffer, 365 * so a DMA handle can be stored along with the buffer 366 */ 367 struct tse_buffer { 368 struct list_head lh; 369 struct sk_buff *skb; 370 dma_addr_t dma_addr; 371 u32 len; 372 int mapped_as_page; 373 }; 374 375 struct altera_tse_private; 376 377 #define ALTERA_DTYPE_SGDMA 1 378 #define ALTERA_DTYPE_MSGDMA 2 379 380 /* standard DMA interface for SGDMA and MSGDMA */ 381 struct altera_dmaops { 382 int altera_dtype; 383 int dmamask; 384 void (*reset_dma)(struct altera_tse_private *); 385 void (*enable_txirq)(struct altera_tse_private *); 386 void (*enable_rxirq)(struct altera_tse_private *); 387 void (*disable_txirq)(struct altera_tse_private *); 388 void (*disable_rxirq)(struct altera_tse_private *); 389 void (*clear_txirq)(struct altera_tse_private *); 390 void (*clear_rxirq)(struct altera_tse_private *); 391 int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *); 392 u32 (*tx_completions)(struct altera_tse_private *); 393 int (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *); 394 u32 (*get_rx_status)(struct altera_tse_private *); 395 int (*init_dma)(struct altera_tse_private *); 396 void (*uninit_dma)(struct altera_tse_private *); 397 }; 398 399 /* This structure is private to each device. 400 */ 401 struct altera_tse_private { 402 struct net_device *dev; 403 struct device *device; 404 struct napi_struct napi; 405 406 /* MAC address space */ 407 struct altera_tse_mac __iomem *mac_dev; 408 409 /* TSE Revision */ 410 u32 revision; 411 412 /* mSGDMA Rx Dispatcher address space */ 413 void __iomem *rx_dma_csr; 414 void __iomem *rx_dma_desc; 415 void __iomem *rx_dma_resp; 416 417 /* mSGDMA Tx Dispatcher address space */ 418 void __iomem *tx_dma_csr; 419 void __iomem *tx_dma_desc; 420 421 /* Rx buffers queue */ 422 struct tse_buffer *rx_ring; 423 u32 rx_cons; 424 u32 rx_prod; 425 u32 rx_ring_size; 426 u32 rx_dma_buf_sz; 427 428 /* Tx ring buffer */ 429 struct tse_buffer *tx_ring; 430 u32 tx_prod; 431 u32 tx_cons; 432 u32 tx_ring_size; 433 434 /* Interrupts */ 435 u32 tx_irq; 436 u32 rx_irq; 437 438 /* RX/TX MAC FIFO configs */ 439 u32 tx_fifo_depth; 440 u32 rx_fifo_depth; 441 u32 max_mtu; 442 443 /* Hash filter settings */ 444 u32 hash_filter; 445 u32 added_unicast; 446 447 /* Descriptor memory info for managing SGDMA */ 448 u32 txdescmem; 449 u32 rxdescmem; 450 dma_addr_t rxdescmem_busaddr; 451 dma_addr_t txdescmem_busaddr; 452 u32 txctrlreg; 453 u32 rxctrlreg; 454 dma_addr_t rxdescphys; 455 dma_addr_t txdescphys; 456 457 struct list_head txlisthd; 458 struct list_head rxlisthd; 459 460 /* MAC command_config register protection */ 461 spinlock_t mac_cfg_lock; 462 /* Tx path protection */ 463 spinlock_t tx_lock; 464 /* Rx DMA & interrupt control protection */ 465 spinlock_t rxdma_irq_lock; 466 467 /* PHY */ 468 int phy_addr; /* PHY's MDIO address, -1 for autodetection */ 469 phy_interface_t phy_iface; 470 struct mii_bus *mdio; 471 struct phy_device *phydev; 472 int oldspeed; 473 int oldduplex; 474 int oldlink; 475 476 /* ethtool msglvl option */ 477 u32 msg_enable; 478 479 struct altera_dmaops *dmaops; 480 }; 481 482 /* Function prototypes 483 */ 484 void altera_tse_set_ethtool_ops(struct net_device *); 485 486 #endif /* __ALTERA_TSE_H__ */ 487