1 /* Altera Triple-Speed Ethernet MAC driver 2 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved 3 * 4 * Contributors: 5 * Dalon Westergreen 6 * Thomas Chou 7 * Ian Abbott 8 * Yuriy Kozlov 9 * Tobias Klauser 10 * Andriy Smolskyy 11 * Roman Bulgakov 12 * Dmytro Mytarchuk 13 * Matthew Gerlach 14 * 15 * Original driver contributed by SLS. 16 * Major updates contributed by GlobalLogic 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms and conditions of the GNU General Public License, 20 * version 2, as published by the Free Software Foundation. 21 * 22 * This program is distributed in the hope it will be useful, but WITHOUT 23 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 24 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 25 * more details. 26 * 27 * You should have received a copy of the GNU General Public License along with 28 * this program. If not, see <http://www.gnu.org/licenses/>. 29 */ 30 31 #ifndef __ALTERA_TSE_H__ 32 #define __ALTERA_TSE_H__ 33 34 #define ALTERA_TSE_RESOURCE_NAME "altera_tse" 35 36 #include <linux/bitops.h> 37 #include <linux/if_vlan.h> 38 #include <linux/list.h> 39 #include <linux/netdevice.h> 40 #include <linux/phy.h> 41 42 #define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR 10000 43 #define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in 44 * bytes 45 */ 46 /* Rx FIFO default settings */ 47 #define ALTERA_TSE_RX_SECTION_EMPTY 16 48 #define ALTERA_TSE_RX_SECTION_FULL 0 49 #define ALTERA_TSE_RX_ALMOST_EMPTY 8 50 #define ALTERA_TSE_RX_ALMOST_FULL 8 51 52 /* Tx FIFO default settings */ 53 #define ALTERA_TSE_TX_SECTION_EMPTY 16 54 #define ALTERA_TSE_TX_SECTION_FULL 0 55 #define ALTERA_TSE_TX_ALMOST_EMPTY 8 56 #define ALTERA_TSE_TX_ALMOST_FULL 3 57 58 /* MAC function configuration default settings */ 59 #define ALTERA_TSE_TX_IPG_LENGTH 12 60 61 #define ALTERA_TSE_PAUSE_QUANTA 0xffff 62 63 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) 64 65 /* MAC Command_Config Register Bit Definitions 66 */ 67 #define MAC_CMDCFG_TX_ENA BIT(0) 68 #define MAC_CMDCFG_RX_ENA BIT(1) 69 #define MAC_CMDCFG_XON_GEN BIT(2) 70 #define MAC_CMDCFG_ETH_SPEED BIT(3) 71 #define MAC_CMDCFG_PROMIS_EN BIT(4) 72 #define MAC_CMDCFG_PAD_EN BIT(5) 73 #define MAC_CMDCFG_CRC_FWD BIT(6) 74 #define MAC_CMDCFG_PAUSE_FWD BIT(7) 75 #define MAC_CMDCFG_PAUSE_IGNORE BIT(8) 76 #define MAC_CMDCFG_TX_ADDR_INS BIT(9) 77 #define MAC_CMDCFG_HD_ENA BIT(10) 78 #define MAC_CMDCFG_EXCESS_COL BIT(11) 79 #define MAC_CMDCFG_LATE_COL BIT(12) 80 #define MAC_CMDCFG_SW_RESET BIT(13) 81 #define MAC_CMDCFG_MHASH_SEL BIT(14) 82 #define MAC_CMDCFG_LOOP_ENA BIT(15) 83 #define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16) 84 #define MAC_CMDCFG_MAGIC_ENA BIT(19) 85 #define MAC_CMDCFG_SLEEP BIT(20) 86 #define MAC_CMDCFG_WAKEUP BIT(21) 87 #define MAC_CMDCFG_XOFF_GEN BIT(22) 88 #define MAC_CMDCFG_CNTL_FRM_ENA BIT(23) 89 #define MAC_CMDCFG_NO_LGTH_CHECK BIT(24) 90 #define MAC_CMDCFG_ENA_10 BIT(25) 91 #define MAC_CMDCFG_RX_ERR_DISC BIT(26) 92 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT BIT(27) 93 #define MAC_CMDCFG_CNT_RESET BIT(31) 94 95 #define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0) 96 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1) 97 #define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2) 98 #define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3) 99 #define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4) 100 #define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5) 101 #define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6) 102 #define MAC_CMDCFG_PAUSE_FWD_GET(v) GET_BIT_VALUE(v, 7) 103 #define MAC_CMDCFG_PAUSE_IGNORE_GET(v) GET_BIT_VALUE(v, 8) 104 #define MAC_CMDCFG_TX_ADDR_INS_GET(v) GET_BIT_VALUE(v, 9) 105 #define MAC_CMDCFG_HD_ENA_GET(v) GET_BIT_VALUE(v, 10) 106 #define MAC_CMDCFG_EXCESS_COL_GET(v) GET_BIT_VALUE(v, 11) 107 #define MAC_CMDCFG_LATE_COL_GET(v) GET_BIT_VALUE(v, 12) 108 #define MAC_CMDCFG_SW_RESET_GET(v) GET_BIT_VALUE(v, 13) 109 #define MAC_CMDCFG_MHASH_SEL_GET(v) GET_BIT_VALUE(v, 14) 110 #define MAC_CMDCFG_LOOP_ENA_GET(v) GET_BIT_VALUE(v, 15) 111 #define MAC_CMDCFG_TX_ADDR_SEL_GET(v) (((v) >> 16) & 0x7) 112 #define MAC_CMDCFG_MAGIC_ENA_GET(v) GET_BIT_VALUE(v, 19) 113 #define MAC_CMDCFG_SLEEP_GET(v) GET_BIT_VALUE(v, 20) 114 #define MAC_CMDCFG_WAKEUP_GET(v) GET_BIT_VALUE(v, 21) 115 #define MAC_CMDCFG_XOFF_GEN_GET(v) GET_BIT_VALUE(v, 22) 116 #define MAC_CMDCFG_CNTL_FRM_ENA_GET(v) GET_BIT_VALUE(v, 23) 117 #define MAC_CMDCFG_NO_LGTH_CHECK_GET(v) GET_BIT_VALUE(v, 24) 118 #define MAC_CMDCFG_ENA_10_GET(v) GET_BIT_VALUE(v, 25) 119 #define MAC_CMDCFG_RX_ERR_DISC_GET(v) GET_BIT_VALUE(v, 26) 120 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v) GET_BIT_VALUE(v, 27) 121 #define MAC_CMDCFG_CNT_RESET_GET(v) GET_BIT_VALUE(v, 31) 122 123 /* MDIO registers within MAC register Space 124 */ 125 struct altera_tse_mdio { 126 u32 control; /* PHY device operation control register */ 127 u32 status; /* PHY device operation status register */ 128 u32 phy_id1; /* Bits 31:16 of PHY identifier */ 129 u32 phy_id2; /* Bits 15:0 of PHY identifier */ 130 u32 auto_negotiation_advertisement; /* Auto-negotiation 131 * advertisement 132 * register 133 */ 134 u32 remote_partner_base_page_ability; 135 136 u32 reg6; 137 u32 reg7; 138 u32 reg8; 139 u32 reg9; 140 u32 rega; 141 u32 regb; 142 u32 regc; 143 u32 regd; 144 u32 rege; 145 u32 regf; 146 u32 reg10; 147 u32 reg11; 148 u32 reg12; 149 u32 reg13; 150 u32 reg14; 151 u32 reg15; 152 u32 reg16; 153 u32 reg17; 154 u32 reg18; 155 u32 reg19; 156 u32 reg1a; 157 u32 reg1b; 158 u32 reg1c; 159 u32 reg1d; 160 u32 reg1e; 161 u32 reg1f; 162 }; 163 164 /* MAC register Space. Note that some of these registers may or may not be 165 * present depending upon options chosen by the user when the core was 166 * configured and built. Please consult the Altera Triple Speed Ethernet User 167 * Guide for details. 168 */ 169 struct altera_tse_mac { 170 /* Bits 15:0: MegaCore function revision (0x0800). Bit 31:16: Customer 171 * specific revision 172 */ 173 u32 megacore_revision; 174 /* Provides a memory location for user applications to test the device 175 * memory operation. 176 */ 177 u32 scratch_pad; 178 /* The host processor uses this register to control and configure the 179 * MAC block 180 */ 181 u32 command_config; 182 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary 183 * MAC address 184 */ 185 u32 mac_addr_0; 186 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary 187 * MAC address 188 */ 189 u32 mac_addr_1; 190 /* 14-bit maximum frame length. The MAC receive logic */ 191 u32 frm_length; 192 /* The pause quanta is used in each pause frame sent to a remote 193 * Ethernet device, in increments of 512 Ethernet bit times 194 */ 195 u32 pause_quanta; 196 /* 12-bit receive FIFO section-empty threshold */ 197 u32 rx_section_empty; 198 /* 12-bit receive FIFO section-full threshold */ 199 u32 rx_section_full; 200 /* 12-bit transmit FIFO section-empty threshold */ 201 u32 tx_section_empty; 202 /* 12-bit transmit FIFO section-full threshold */ 203 u32 tx_section_full; 204 /* 12-bit receive FIFO almost-empty threshold */ 205 u32 rx_almost_empty; 206 /* 12-bit receive FIFO almost-full threshold */ 207 u32 rx_almost_full; 208 /* 12-bit transmit FIFO almost-empty threshold */ 209 u32 tx_almost_empty; 210 /* 12-bit transmit FIFO almost-full threshold */ 211 u32 tx_almost_full; 212 /* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */ 213 u32 mdio_phy0_addr; 214 /* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */ 215 u32 mdio_phy1_addr; 216 217 /* Bit[15:0]—16-bit holdoff quanta */ 218 u32 holdoff_quant; 219 220 /* only if 100/1000 BaseX PCS, reserved otherwise */ 221 u32 reserved1[5]; 222 223 /* Minimum IPG between consecutive transmit frame in terms of bytes */ 224 u32 tx_ipg_length; 225 226 /* IEEE 802.3 oEntity Managed Object Support */ 227 228 /* The MAC addresses */ 229 u32 mac_id_1; 230 u32 mac_id_2; 231 232 /* Number of frames transmitted without error including pause frames */ 233 u32 frames_transmitted_ok; 234 /* Number of frames received without error including pause frames */ 235 u32 frames_received_ok; 236 /* Number of frames received with a CRC error */ 237 u32 frames_check_sequence_errors; 238 /* Frame received with an alignment error */ 239 u32 alignment_errors; 240 /* Sum of payload and padding octets of frames transmitted without 241 * error 242 */ 243 u32 octets_transmitted_ok; 244 /* Sum of payload and padding octets of frames received without error */ 245 u32 octets_received_ok; 246 247 /* IEEE 802.3 oPausedEntity Managed Object Support */ 248 249 /* Number of transmitted pause frames */ 250 u32 tx_pause_mac_ctrl_frames; 251 /* Number of Received pause frames */ 252 u32 rx_pause_mac_ctrl_frames; 253 254 /* IETF MIB (MIB-II) Object Support */ 255 256 /* Number of frames received with error */ 257 u32 if_in_errors; 258 /* Number of frames transmitted with error */ 259 u32 if_out_errors; 260 /* Number of valid received unicast frames */ 261 u32 if_in_ucast_pkts; 262 /* Number of valid received multicasts frames (without pause) */ 263 u32 if_in_multicast_pkts; 264 /* Number of valid received broadcast frames */ 265 u32 if_in_broadcast_pkts; 266 u32 if_out_discards; 267 /* The number of valid unicast frames transmitted */ 268 u32 if_out_ucast_pkts; 269 /* The number of valid multicast frames transmitted, 270 * excluding pause frames 271 */ 272 u32 if_out_multicast_pkts; 273 u32 if_out_broadcast_pkts; 274 275 /* IETF RMON MIB Object Support */ 276 277 /* Counts the number of dropped packets due to internal errors 278 * of the MAC client. 279 */ 280 u32 ether_stats_drop_events; 281 /* Total number of bytes received. Good and bad frames. */ 282 u32 ether_stats_octets; 283 /* Total number of packets received. Counts good and bad packets. */ 284 u32 ether_stats_pkts; 285 /* Number of packets received with less than 64 bytes. */ 286 u32 ether_stats_undersize_pkts; 287 /* The number of frames received that are longer than the 288 * value configured in the frm_length register 289 */ 290 u32 ether_stats_oversize_pkts; 291 /* Number of received packet with 64 bytes */ 292 u32 ether_stats_pkts_64_octets; 293 /* Frames (good and bad) with 65 to 127 bytes */ 294 u32 ether_stats_pkts_65to127_octets; 295 /* Frames (good and bad) with 128 to 255 bytes */ 296 u32 ether_stats_pkts_128to255_octets; 297 /* Frames (good and bad) with 256 to 511 bytes */ 298 u32 ether_stats_pkts_256to511_octets; 299 /* Frames (good and bad) with 512 to 1023 bytes */ 300 u32 ether_stats_pkts_512to1023_octets; 301 /* Frames (good and bad) with 1024 to 1518 bytes */ 302 u32 ether_stats_pkts_1024to1518_octets; 303 304 /* Any frame length from 1519 to the maximum length configured in the 305 * frm_length register, if it is greater than 1518 306 */ 307 u32 ether_stats_pkts_1519tox_octets; 308 /* Too long frames with CRC error */ 309 u32 ether_stats_jabbers; 310 /* Too short frames with CRC error */ 311 u32 ether_stats_fragments; 312 313 u32 reserved2; 314 315 /* FIFO control register */ 316 u32 tx_cmd_stat; 317 u32 rx_cmd_stat; 318 319 /* Extended Statistics Counters */ 320 u32 msb_octets_transmitted_ok; 321 u32 msb_octets_received_ok; 322 u32 msb_ether_stats_octets; 323 324 u32 reserved3; 325 326 /* Multicast address resolution table, mapped in the controller address 327 * space 328 */ 329 u32 hash_table[64]; 330 331 /* Registers 0 to 31 within PHY device 0/1 connected to the MDIO PHY 332 * management interface 333 */ 334 struct altera_tse_mdio mdio_phy0; 335 struct altera_tse_mdio mdio_phy1; 336 337 /* 4 Supplemental MAC Addresses */ 338 u32 supp_mac_addr_0_0; 339 u32 supp_mac_addr_0_1; 340 u32 supp_mac_addr_1_0; 341 u32 supp_mac_addr_1_1; 342 u32 supp_mac_addr_2_0; 343 u32 supp_mac_addr_2_1; 344 u32 supp_mac_addr_3_0; 345 u32 supp_mac_addr_3_1; 346 347 u32 reserved4[8]; 348 349 /* IEEE 1588v2 Feature */ 350 u32 tx_period; 351 u32 tx_adjust_fns; 352 u32 tx_adjust_ns; 353 u32 rx_period; 354 u32 rx_adjust_fns; 355 u32 rx_adjust_ns; 356 357 u32 reserved5[42]; 358 }; 359 360 #define tse_csroffs(a) (offsetof(struct altera_tse_mac, a)) 361 362 /* Transmit and Receive Command Registers Bit Definitions 363 */ 364 #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17) 365 #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 BIT(18) 366 #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 BIT(25) 367 368 /* Wrapper around a pointer to a socket buffer, 369 * so a DMA handle can be stored along with the buffer 370 */ 371 struct tse_buffer { 372 struct list_head lh; 373 struct sk_buff *skb; 374 dma_addr_t dma_addr; 375 u32 len; 376 int mapped_as_page; 377 }; 378 379 struct altera_tse_private; 380 381 #define ALTERA_DTYPE_SGDMA 1 382 #define ALTERA_DTYPE_MSGDMA 2 383 384 /* standard DMA interface for SGDMA and MSGDMA */ 385 struct altera_dmaops { 386 int altera_dtype; 387 int dmamask; 388 void (*reset_dma)(struct altera_tse_private *); 389 void (*enable_txirq)(struct altera_tse_private *); 390 void (*enable_rxirq)(struct altera_tse_private *); 391 void (*disable_txirq)(struct altera_tse_private *); 392 void (*disable_rxirq)(struct altera_tse_private *); 393 void (*clear_txirq)(struct altera_tse_private *); 394 void (*clear_rxirq)(struct altera_tse_private *); 395 int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *); 396 u32 (*tx_completions)(struct altera_tse_private *); 397 void (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *); 398 u32 (*get_rx_status)(struct altera_tse_private *); 399 int (*init_dma)(struct altera_tse_private *); 400 void (*uninit_dma)(struct altera_tse_private *); 401 void (*start_rxdma)(struct altera_tse_private *); 402 }; 403 404 /* This structure is private to each device. 405 */ 406 struct altera_tse_private { 407 struct net_device *dev; 408 struct device *device; 409 struct napi_struct napi; 410 411 /* MAC address space */ 412 struct altera_tse_mac __iomem *mac_dev; 413 414 /* TSE Revision */ 415 u32 revision; 416 417 /* mSGDMA Rx Dispatcher address space */ 418 void __iomem *rx_dma_csr; 419 void __iomem *rx_dma_desc; 420 void __iomem *rx_dma_resp; 421 422 /* mSGDMA Tx Dispatcher address space */ 423 void __iomem *tx_dma_csr; 424 void __iomem *tx_dma_desc; 425 426 /* Rx buffers queue */ 427 struct tse_buffer *rx_ring; 428 u32 rx_cons; 429 u32 rx_prod; 430 u32 rx_ring_size; 431 u32 rx_dma_buf_sz; 432 433 /* Tx ring buffer */ 434 struct tse_buffer *tx_ring; 435 u32 tx_prod; 436 u32 tx_cons; 437 u32 tx_ring_size; 438 439 /* Interrupts */ 440 u32 tx_irq; 441 u32 rx_irq; 442 443 /* RX/TX MAC FIFO configs */ 444 u32 tx_fifo_depth; 445 u32 rx_fifo_depth; 446 u32 max_mtu; 447 448 /* Hash filter settings */ 449 u32 hash_filter; 450 u32 added_unicast; 451 452 /* Descriptor memory info for managing SGDMA */ 453 u32 txdescmem; 454 u32 rxdescmem; 455 dma_addr_t rxdescmem_busaddr; 456 dma_addr_t txdescmem_busaddr; 457 u32 txctrlreg; 458 u32 rxctrlreg; 459 dma_addr_t rxdescphys; 460 dma_addr_t txdescphys; 461 462 struct list_head txlisthd; 463 struct list_head rxlisthd; 464 465 /* MAC command_config register protection */ 466 spinlock_t mac_cfg_lock; 467 /* Tx path protection */ 468 spinlock_t tx_lock; 469 /* Rx DMA & interrupt control protection */ 470 spinlock_t rxdma_irq_lock; 471 472 /* PHY */ 473 int phy_addr; /* PHY's MDIO address, -1 for autodetection */ 474 phy_interface_t phy_iface; 475 struct mii_bus *mdio; 476 struct phy_device *phydev; 477 int oldspeed; 478 int oldduplex; 479 int oldlink; 480 481 /* ethtool msglvl option */ 482 u32 msg_enable; 483 484 struct altera_dmaops *dmaops; 485 }; 486 487 /* Function prototypes 488 */ 489 void altera_tse_set_ethtool_ops(struct net_device *); 490 491 static inline 492 u32 csrrd32(void __iomem *mac, size_t offs) 493 { 494 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 495 return readl(paddr); 496 } 497 498 static inline 499 u16 csrrd16(void __iomem *mac, size_t offs) 500 { 501 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 502 return readw(paddr); 503 } 504 505 static inline 506 u8 csrrd8(void __iomem *mac, size_t offs) 507 { 508 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 509 return readb(paddr); 510 } 511 512 static inline 513 void csrwr32(u32 val, void __iomem *mac, size_t offs) 514 { 515 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 516 517 writel(val, paddr); 518 } 519 520 static inline 521 void csrwr16(u16 val, void __iomem *mac, size_t offs) 522 { 523 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 524 525 writew(val, paddr); 526 } 527 528 static inline 529 void csrwr8(u8 val, void __iomem *mac, size_t offs) 530 { 531 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 532 533 writeb(val, paddr); 534 } 535 536 #endif /* __ALTERA_TSE_H__ */ 537