1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Altera Triple-Speed Ethernet MAC driver 3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved 4 * 5 * Contributors: 6 * Dalon Westergreen 7 * Thomas Chou 8 * Ian Abbott 9 * Yuriy Kozlov 10 * Tobias Klauser 11 * Andriy Smolskyy 12 * Roman Bulgakov 13 * Dmytro Mytarchuk 14 * Matthew Gerlach 15 * 16 * Original driver contributed by SLS. 17 * Major updates contributed by GlobalLogic 18 */ 19 20 #ifndef __ALTERA_TSE_H__ 21 #define __ALTERA_TSE_H__ 22 23 #define ALTERA_TSE_RESOURCE_NAME "altera_tse" 24 25 #include <linux/bitops.h> 26 #include <linux/if_vlan.h> 27 #include <linux/list.h> 28 #include <linux/netdevice.h> 29 #include <linux/phy.h> 30 31 #define ALTERA_TSE_SW_RESET_WATCHDOG_CNTR 10000 32 #define ALTERA_TSE_MAC_FIFO_WIDTH 4 /* TX/RX FIFO width in 33 * bytes 34 */ 35 /* Rx FIFO default settings */ 36 #define ALTERA_TSE_RX_SECTION_EMPTY 16 37 #define ALTERA_TSE_RX_SECTION_FULL 0 38 #define ALTERA_TSE_RX_ALMOST_EMPTY 8 39 #define ALTERA_TSE_RX_ALMOST_FULL 8 40 41 /* Tx FIFO default settings */ 42 #define ALTERA_TSE_TX_SECTION_EMPTY 16 43 #define ALTERA_TSE_TX_SECTION_FULL 0 44 #define ALTERA_TSE_TX_ALMOST_EMPTY 8 45 #define ALTERA_TSE_TX_ALMOST_FULL 3 46 47 /* MAC function configuration default settings */ 48 #define ALTERA_TSE_TX_IPG_LENGTH 12 49 50 #define ALTERA_TSE_PAUSE_QUANTA 0xffff 51 52 #define GET_BIT_VALUE(v, bit) (((v) >> (bit)) & 0x1) 53 54 /* MAC Command_Config Register Bit Definitions 55 */ 56 #define MAC_CMDCFG_TX_ENA BIT(0) 57 #define MAC_CMDCFG_RX_ENA BIT(1) 58 #define MAC_CMDCFG_XON_GEN BIT(2) 59 #define MAC_CMDCFG_ETH_SPEED BIT(3) 60 #define MAC_CMDCFG_PROMIS_EN BIT(4) 61 #define MAC_CMDCFG_PAD_EN BIT(5) 62 #define MAC_CMDCFG_CRC_FWD BIT(6) 63 #define MAC_CMDCFG_PAUSE_FWD BIT(7) 64 #define MAC_CMDCFG_PAUSE_IGNORE BIT(8) 65 #define MAC_CMDCFG_TX_ADDR_INS BIT(9) 66 #define MAC_CMDCFG_HD_ENA BIT(10) 67 #define MAC_CMDCFG_EXCESS_COL BIT(11) 68 #define MAC_CMDCFG_LATE_COL BIT(12) 69 #define MAC_CMDCFG_SW_RESET BIT(13) 70 #define MAC_CMDCFG_MHASH_SEL BIT(14) 71 #define MAC_CMDCFG_LOOP_ENA BIT(15) 72 #define MAC_CMDCFG_TX_ADDR_SEL(v) (((v) & 0x7) << 16) 73 #define MAC_CMDCFG_MAGIC_ENA BIT(19) 74 #define MAC_CMDCFG_SLEEP BIT(20) 75 #define MAC_CMDCFG_WAKEUP BIT(21) 76 #define MAC_CMDCFG_XOFF_GEN BIT(22) 77 #define MAC_CMDCFG_CNTL_FRM_ENA BIT(23) 78 #define MAC_CMDCFG_NO_LGTH_CHECK BIT(24) 79 #define MAC_CMDCFG_ENA_10 BIT(25) 80 #define MAC_CMDCFG_RX_ERR_DISC BIT(26) 81 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT BIT(27) 82 #define MAC_CMDCFG_CNT_RESET BIT(31) 83 84 #define MAC_CMDCFG_TX_ENA_GET(v) GET_BIT_VALUE(v, 0) 85 #define MAC_CMDCFG_RX_ENA_GET(v) GET_BIT_VALUE(v, 1) 86 #define MAC_CMDCFG_XON_GEN_GET(v) GET_BIT_VALUE(v, 2) 87 #define MAC_CMDCFG_ETH_SPEED_GET(v) GET_BIT_VALUE(v, 3) 88 #define MAC_CMDCFG_PROMIS_EN_GET(v) GET_BIT_VALUE(v, 4) 89 #define MAC_CMDCFG_PAD_EN_GET(v) GET_BIT_VALUE(v, 5) 90 #define MAC_CMDCFG_CRC_FWD_GET(v) GET_BIT_VALUE(v, 6) 91 #define MAC_CMDCFG_PAUSE_FWD_GET(v) GET_BIT_VALUE(v, 7) 92 #define MAC_CMDCFG_PAUSE_IGNORE_GET(v) GET_BIT_VALUE(v, 8) 93 #define MAC_CMDCFG_TX_ADDR_INS_GET(v) GET_BIT_VALUE(v, 9) 94 #define MAC_CMDCFG_HD_ENA_GET(v) GET_BIT_VALUE(v, 10) 95 #define MAC_CMDCFG_EXCESS_COL_GET(v) GET_BIT_VALUE(v, 11) 96 #define MAC_CMDCFG_LATE_COL_GET(v) GET_BIT_VALUE(v, 12) 97 #define MAC_CMDCFG_SW_RESET_GET(v) GET_BIT_VALUE(v, 13) 98 #define MAC_CMDCFG_MHASH_SEL_GET(v) GET_BIT_VALUE(v, 14) 99 #define MAC_CMDCFG_LOOP_ENA_GET(v) GET_BIT_VALUE(v, 15) 100 #define MAC_CMDCFG_TX_ADDR_SEL_GET(v) (((v) >> 16) & 0x7) 101 #define MAC_CMDCFG_MAGIC_ENA_GET(v) GET_BIT_VALUE(v, 19) 102 #define MAC_CMDCFG_SLEEP_GET(v) GET_BIT_VALUE(v, 20) 103 #define MAC_CMDCFG_WAKEUP_GET(v) GET_BIT_VALUE(v, 21) 104 #define MAC_CMDCFG_XOFF_GEN_GET(v) GET_BIT_VALUE(v, 22) 105 #define MAC_CMDCFG_CNTL_FRM_ENA_GET(v) GET_BIT_VALUE(v, 23) 106 #define MAC_CMDCFG_NO_LGTH_CHECK_GET(v) GET_BIT_VALUE(v, 24) 107 #define MAC_CMDCFG_ENA_10_GET(v) GET_BIT_VALUE(v, 25) 108 #define MAC_CMDCFG_RX_ERR_DISC_GET(v) GET_BIT_VALUE(v, 26) 109 #define MAC_CMDCFG_DISABLE_READ_TIMEOUT_GET(v) GET_BIT_VALUE(v, 27) 110 #define MAC_CMDCFG_CNT_RESET_GET(v) GET_BIT_VALUE(v, 31) 111 112 /* SGMII PCS register addresses 113 */ 114 #define SGMII_PCS_SCRATCH 0x10 115 #define SGMII_PCS_REV 0x11 116 #define SGMII_PCS_LINK_TIMER_0 0x12 117 #define SGMII_PCS_LINK_TIMER_1 0x13 118 #define SGMII_PCS_IF_MODE 0x14 119 #define SGMII_PCS_DIS_READ_TO 0x15 120 #define SGMII_PCS_READ_TO 0x16 121 #define SGMII_PCS_SW_RESET_TIMEOUT 100 /* usecs */ 122 123 /* MDIO registers within MAC register Space 124 */ 125 struct altera_tse_mdio { 126 u32 control; /* PHY device operation control register */ 127 u32 status; /* PHY device operation status register */ 128 u32 phy_id1; /* Bits 31:16 of PHY identifier */ 129 u32 phy_id2; /* Bits 15:0 of PHY identifier */ 130 u32 auto_negotiation_advertisement; /* Auto-negotiation 131 * advertisement 132 * register 133 */ 134 u32 remote_partner_base_page_ability; 135 136 u32 reg6; 137 u32 reg7; 138 u32 reg8; 139 u32 reg9; 140 u32 rega; 141 u32 regb; 142 u32 regc; 143 u32 regd; 144 u32 rege; 145 u32 regf; 146 u32 reg10; 147 u32 reg11; 148 u32 reg12; 149 u32 reg13; 150 u32 reg14; 151 u32 reg15; 152 u32 reg16; 153 u32 reg17; 154 u32 reg18; 155 u32 reg19; 156 u32 reg1a; 157 u32 reg1b; 158 u32 reg1c; 159 u32 reg1d; 160 u32 reg1e; 161 u32 reg1f; 162 }; 163 164 /* MAC register Space. Note that some of these registers may or may not be 165 * present depending upon options chosen by the user when the core was 166 * configured and built. Please consult the Altera Triple Speed Ethernet User 167 * Guide for details. 168 */ 169 struct altera_tse_mac { 170 /* Bits 15:0: MegaCore function revision (0x0800). Bit 31:16: Customer 171 * specific revision 172 */ 173 u32 megacore_revision; 174 /* Provides a memory location for user applications to test the device 175 * memory operation. 176 */ 177 u32 scratch_pad; 178 /* The host processor uses this register to control and configure the 179 * MAC block 180 */ 181 u32 command_config; 182 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary 183 * MAC address 184 */ 185 u32 mac_addr_0; 186 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary 187 * MAC address 188 */ 189 u32 mac_addr_1; 190 /* 14-bit maximum frame length. The MAC receive logic */ 191 u32 frm_length; 192 /* The pause quanta is used in each pause frame sent to a remote 193 * Ethernet device, in increments of 512 Ethernet bit times 194 */ 195 u32 pause_quanta; 196 /* 12-bit receive FIFO section-empty threshold */ 197 u32 rx_section_empty; 198 /* 12-bit receive FIFO section-full threshold */ 199 u32 rx_section_full; 200 /* 12-bit transmit FIFO section-empty threshold */ 201 u32 tx_section_empty; 202 /* 12-bit transmit FIFO section-full threshold */ 203 u32 tx_section_full; 204 /* 12-bit receive FIFO almost-empty threshold */ 205 u32 rx_almost_empty; 206 /* 12-bit receive FIFO almost-full threshold */ 207 u32 rx_almost_full; 208 /* 12-bit transmit FIFO almost-empty threshold */ 209 u32 tx_almost_empty; 210 /* 12-bit transmit FIFO almost-full threshold */ 211 u32 tx_almost_full; 212 /* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */ 213 u32 mdio_phy0_addr; 214 /* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */ 215 u32 mdio_phy1_addr; 216 217 /* Bit[15:0]—16-bit holdoff quanta */ 218 u32 holdoff_quant; 219 220 /* only if 100/1000 BaseX PCS, reserved otherwise */ 221 u32 reserved1[5]; 222 223 /* Minimum IPG between consecutive transmit frame in terms of bytes */ 224 u32 tx_ipg_length; 225 226 /* IEEE 802.3 oEntity Managed Object Support */ 227 228 /* The MAC addresses */ 229 u32 mac_id_1; 230 u32 mac_id_2; 231 232 /* Number of frames transmitted without error including pause frames */ 233 u32 frames_transmitted_ok; 234 /* Number of frames received without error including pause frames */ 235 u32 frames_received_ok; 236 /* Number of frames received with a CRC error */ 237 u32 frames_check_sequence_errors; 238 /* Frame received with an alignment error */ 239 u32 alignment_errors; 240 /* Sum of payload and padding octets of frames transmitted without 241 * error 242 */ 243 u32 octets_transmitted_ok; 244 /* Sum of payload and padding octets of frames received without error */ 245 u32 octets_received_ok; 246 247 /* IEEE 802.3 oPausedEntity Managed Object Support */ 248 249 /* Number of transmitted pause frames */ 250 u32 tx_pause_mac_ctrl_frames; 251 /* Number of Received pause frames */ 252 u32 rx_pause_mac_ctrl_frames; 253 254 /* IETF MIB (MIB-II) Object Support */ 255 256 /* Number of frames received with error */ 257 u32 if_in_errors; 258 /* Number of frames transmitted with error */ 259 u32 if_out_errors; 260 /* Number of valid received unicast frames */ 261 u32 if_in_ucast_pkts; 262 /* Number of valid received multicasts frames (without pause) */ 263 u32 if_in_multicast_pkts; 264 /* Number of valid received broadcast frames */ 265 u32 if_in_broadcast_pkts; 266 u32 if_out_discards; 267 /* The number of valid unicast frames transmitted */ 268 u32 if_out_ucast_pkts; 269 /* The number of valid multicast frames transmitted, 270 * excluding pause frames 271 */ 272 u32 if_out_multicast_pkts; 273 u32 if_out_broadcast_pkts; 274 275 /* IETF RMON MIB Object Support */ 276 277 /* Counts the number of dropped packets due to internal errors 278 * of the MAC client. 279 */ 280 u32 ether_stats_drop_events; 281 /* Total number of bytes received. Good and bad frames. */ 282 u32 ether_stats_octets; 283 /* Total number of packets received. Counts good and bad packets. */ 284 u32 ether_stats_pkts; 285 /* Number of packets received with less than 64 bytes. */ 286 u32 ether_stats_undersize_pkts; 287 /* The number of frames received that are longer than the 288 * value configured in the frm_length register 289 */ 290 u32 ether_stats_oversize_pkts; 291 /* Number of received packet with 64 bytes */ 292 u32 ether_stats_pkts_64_octets; 293 /* Frames (good and bad) with 65 to 127 bytes */ 294 u32 ether_stats_pkts_65to127_octets; 295 /* Frames (good and bad) with 128 to 255 bytes */ 296 u32 ether_stats_pkts_128to255_octets; 297 /* Frames (good and bad) with 256 to 511 bytes */ 298 u32 ether_stats_pkts_256to511_octets; 299 /* Frames (good and bad) with 512 to 1023 bytes */ 300 u32 ether_stats_pkts_512to1023_octets; 301 /* Frames (good and bad) with 1024 to 1518 bytes */ 302 u32 ether_stats_pkts_1024to1518_octets; 303 304 /* Any frame length from 1519 to the maximum length configured in the 305 * frm_length register, if it is greater than 1518 306 */ 307 u32 ether_stats_pkts_1519tox_octets; 308 /* Too long frames with CRC error */ 309 u32 ether_stats_jabbers; 310 /* Too short frames with CRC error */ 311 u32 ether_stats_fragments; 312 313 u32 reserved2; 314 315 /* FIFO control register */ 316 u32 tx_cmd_stat; 317 u32 rx_cmd_stat; 318 319 /* Extended Statistics Counters */ 320 u32 msb_octets_transmitted_ok; 321 u32 msb_octets_received_ok; 322 u32 msb_ether_stats_octets; 323 324 u32 reserved3; 325 326 /* Multicast address resolution table, mapped in the controller address 327 * space 328 */ 329 u32 hash_table[64]; 330 331 /* Registers 0 to 31 within PHY device 0/1 connected to the MDIO PHY 332 * management interface 333 */ 334 struct altera_tse_mdio mdio_phy0; 335 struct altera_tse_mdio mdio_phy1; 336 337 /* 4 Supplemental MAC Addresses */ 338 u32 supp_mac_addr_0_0; 339 u32 supp_mac_addr_0_1; 340 u32 supp_mac_addr_1_0; 341 u32 supp_mac_addr_1_1; 342 u32 supp_mac_addr_2_0; 343 u32 supp_mac_addr_2_1; 344 u32 supp_mac_addr_3_0; 345 u32 supp_mac_addr_3_1; 346 347 u32 reserved4[8]; 348 349 /* IEEE 1588v2 Feature */ 350 u32 tx_period; 351 u32 tx_adjust_fns; 352 u32 tx_adjust_ns; 353 u32 rx_period; 354 u32 rx_adjust_fns; 355 u32 rx_adjust_ns; 356 357 u32 reserved5[42]; 358 }; 359 360 #define tse_csroffs(a) (offsetof(struct altera_tse_mac, a)) 361 362 /* Transmit and Receive Command Registers Bit Definitions 363 */ 364 #define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC BIT(17) 365 #define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 BIT(18) 366 #define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 BIT(25) 367 368 /* Wrapper around a pointer to a socket buffer, 369 * so a DMA handle can be stored along with the buffer 370 */ 371 struct tse_buffer { 372 struct list_head lh; 373 struct sk_buff *skb; 374 dma_addr_t dma_addr; 375 u32 len; 376 int mapped_as_page; 377 }; 378 379 struct altera_tse_private; 380 381 #define ALTERA_DTYPE_SGDMA 1 382 #define ALTERA_DTYPE_MSGDMA 2 383 384 /* standard DMA interface for SGDMA and MSGDMA */ 385 struct altera_dmaops { 386 int altera_dtype; 387 int dmamask; 388 void (*reset_dma)(struct altera_tse_private *); 389 void (*enable_txirq)(struct altera_tse_private *); 390 void (*enable_rxirq)(struct altera_tse_private *); 391 void (*disable_txirq)(struct altera_tse_private *); 392 void (*disable_rxirq)(struct altera_tse_private *); 393 void (*clear_txirq)(struct altera_tse_private *); 394 void (*clear_rxirq)(struct altera_tse_private *); 395 int (*tx_buffer)(struct altera_tse_private *, struct tse_buffer *); 396 u32 (*tx_completions)(struct altera_tse_private *); 397 void (*add_rx_desc)(struct altera_tse_private *, struct tse_buffer *); 398 u32 (*get_rx_status)(struct altera_tse_private *); 399 int (*init_dma)(struct altera_tse_private *); 400 void (*uninit_dma)(struct altera_tse_private *); 401 void (*start_rxdma)(struct altera_tse_private *); 402 }; 403 404 /* This structure is private to each device. 405 */ 406 struct altera_tse_private { 407 struct net_device *dev; 408 struct device *device; 409 struct napi_struct napi; 410 411 /* MAC address space */ 412 struct altera_tse_mac __iomem *mac_dev; 413 414 /* TSE Revision */ 415 u32 revision; 416 417 /* mSGDMA Rx Dispatcher address space */ 418 void __iomem *rx_dma_csr; 419 void __iomem *rx_dma_desc; 420 void __iomem *rx_dma_resp; 421 422 /* mSGDMA Tx Dispatcher address space */ 423 void __iomem *tx_dma_csr; 424 void __iomem *tx_dma_desc; 425 426 /* Rx buffers queue */ 427 struct tse_buffer *rx_ring; 428 u32 rx_cons; 429 u32 rx_prod; 430 u32 rx_ring_size; 431 u32 rx_dma_buf_sz; 432 433 /* Tx ring buffer */ 434 struct tse_buffer *tx_ring; 435 u32 tx_prod; 436 u32 tx_cons; 437 u32 tx_ring_size; 438 439 /* Interrupts */ 440 u32 tx_irq; 441 u32 rx_irq; 442 443 /* RX/TX MAC FIFO configs */ 444 u32 tx_fifo_depth; 445 u32 rx_fifo_depth; 446 447 /* Hash filter settings */ 448 u32 hash_filter; 449 u32 added_unicast; 450 451 /* Descriptor memory info for managing SGDMA */ 452 u32 txdescmem; 453 u32 rxdescmem; 454 dma_addr_t rxdescmem_busaddr; 455 dma_addr_t txdescmem_busaddr; 456 u32 txctrlreg; 457 u32 rxctrlreg; 458 dma_addr_t rxdescphys; 459 dma_addr_t txdescphys; 460 461 struct list_head txlisthd; 462 struct list_head rxlisthd; 463 464 /* MAC command_config register protection */ 465 spinlock_t mac_cfg_lock; 466 /* Tx path protection */ 467 spinlock_t tx_lock; 468 /* Rx DMA & interrupt control protection */ 469 spinlock_t rxdma_irq_lock; 470 471 /* PHY */ 472 int phy_addr; /* PHY's MDIO address, -1 for autodetection */ 473 phy_interface_t phy_iface; 474 struct mii_bus *mdio; 475 int oldspeed; 476 int oldduplex; 477 int oldlink; 478 479 /* ethtool msglvl option */ 480 u32 msg_enable; 481 482 struct altera_dmaops *dmaops; 483 }; 484 485 /* Function prototypes 486 */ 487 void altera_tse_set_ethtool_ops(struct net_device *); 488 489 static inline 490 u32 csrrd32(void __iomem *mac, size_t offs) 491 { 492 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 493 return readl(paddr); 494 } 495 496 static inline 497 u16 csrrd16(void __iomem *mac, size_t offs) 498 { 499 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 500 return readw(paddr); 501 } 502 503 static inline 504 u8 csrrd8(void __iomem *mac, size_t offs) 505 { 506 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 507 return readb(paddr); 508 } 509 510 static inline 511 void csrwr32(u32 val, void __iomem *mac, size_t offs) 512 { 513 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 514 515 writel(val, paddr); 516 } 517 518 static inline 519 void csrwr16(u16 val, void __iomem *mac, size_t offs) 520 { 521 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 522 523 writew(val, paddr); 524 } 525 526 static inline 527 void csrwr8(u8 val, void __iomem *mac, size_t offs) 528 { 529 void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs); 530 531 writeb(val, paddr); 532 } 533 534 #endif /* __ALTERA_TSE_H__ */ 535