1 /* Altera TSE SGDMA and MSGDMA Linux driver 2 * Copyright (C) 2014 Altera Corporation. All rights reserved 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __ALTERA_MSGDMAHW_H__ 18 #define __ALTERA_MSGDMAHW_H__ 19 20 /* mSGDMA standard descriptor format 21 */ 22 struct msgdma_desc { 23 u32 read_addr; /* data buffer source address */ 24 u32 write_addr; /* data buffer destination address */ 25 u32 len; /* the number of bytes to transfer per descriptor */ 26 u32 control; /* characteristics of the transfer */ 27 }; 28 29 /* mSGDMA extended descriptor format 30 */ 31 struct msgdma_extended_desc { 32 u32 read_addr_lo; /* data buffer source address low bits */ 33 u32 write_addr_lo; /* data buffer destination address low bits */ 34 u32 len; /* the number of bytes to transfer 35 * per descriptor 36 */ 37 u32 burst_seq_num; /* bit 31:24 write burst 38 * bit 23:16 read burst 39 * bit 15:0 sequence number 40 */ 41 u32 stride; /* bit 31:16 write stride 42 * bit 15:0 read stride 43 */ 44 u32 read_addr_hi; /* data buffer source address high bits */ 45 u32 write_addr_hi; /* data buffer destination address high bits */ 46 u32 control; /* characteristics of the transfer */ 47 }; 48 49 /* mSGDMA descriptor control field bit definitions 50 */ 51 #define MSGDMA_DESC_CTL_SET_CH(x) ((x) & 0xff) 52 #define MSGDMA_DESC_CTL_GEN_SOP BIT(8) 53 #define MSGDMA_DESC_CTL_GEN_EOP BIT(9) 54 #define MSGDMA_DESC_CTL_PARK_READS BIT(10) 55 #define MSGDMA_DESC_CTL_PARK_WRITES BIT(11) 56 #define MSGDMA_DESC_CTL_END_ON_EOP BIT(12) 57 #define MSGDMA_DESC_CTL_END_ON_LEN BIT(13) 58 #define MSGDMA_DESC_CTL_TR_COMP_IRQ BIT(14) 59 #define MSGDMA_DESC_CTL_EARLY_IRQ BIT(15) 60 #define MSGDMA_DESC_CTL_TR_ERR_IRQ (0xff << 16) 61 #define MSGDMA_DESC_CTL_EARLY_DONE BIT(24) 62 /* Writing ‘1’ to the ‘go’ bit commits the entire descriptor into the 63 * descriptor FIFO(s) 64 */ 65 #define MSGDMA_DESC_CTL_GO BIT(31) 66 67 /* Tx buffer control flags 68 */ 69 #define MSGDMA_DESC_CTL_TX_FIRST (MSGDMA_DESC_CTL_GEN_SOP | \ 70 MSGDMA_DESC_CTL_TR_ERR_IRQ | \ 71 MSGDMA_DESC_CTL_GO) 72 73 #define MSGDMA_DESC_CTL_TX_MIDDLE (MSGDMA_DESC_CTL_TR_ERR_IRQ | \ 74 MSGDMA_DESC_CTL_GO) 75 76 #define MSGDMA_DESC_CTL_TX_LAST (MSGDMA_DESC_CTL_GEN_EOP | \ 77 MSGDMA_DESC_CTL_TR_COMP_IRQ | \ 78 MSGDMA_DESC_CTL_TR_ERR_IRQ | \ 79 MSGDMA_DESC_CTL_GO) 80 81 #define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \ 82 MSGDMA_DESC_CTL_GEN_EOP | \ 83 MSGDMA_DESC_CTL_TR_COMP_IRQ | \ 84 MSGDMA_DESC_CTL_TR_ERR_IRQ | \ 85 MSGDMA_DESC_CTL_GO) 86 87 #define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \ 88 MSGDMA_DESC_CTL_END_ON_LEN | \ 89 MSGDMA_DESC_CTL_TR_COMP_IRQ | \ 90 MSGDMA_DESC_CTL_EARLY_IRQ | \ 91 MSGDMA_DESC_CTL_TR_ERR_IRQ | \ 92 MSGDMA_DESC_CTL_GO) 93 94 /* mSGDMA extended descriptor stride definitions 95 */ 96 #define MSGDMA_DESC_TX_STRIDE (0x00010001) 97 #define MSGDMA_DESC_RX_STRIDE (0x00010001) 98 99 /* mSGDMA dispatcher control and status register map 100 */ 101 struct msgdma_csr { 102 u32 status; /* Read/Clear */ 103 u32 control; /* Read/Write */ 104 u32 rw_fill_level; /* bit 31:16 - write fill level 105 * bit 15:0 - read fill level 106 */ 107 u32 resp_fill_level; /* bit 15:0 */ 108 u32 rw_seq_num; /* bit 31:16 - write sequence number 109 * bit 15:0 - read sequence number 110 */ 111 u32 pad[3]; /* reserved */ 112 }; 113 114 /* mSGDMA CSR status register bit definitions 115 */ 116 #define MSGDMA_CSR_STAT_BUSY BIT(0) 117 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY BIT(1) 118 #define MSGDMA_CSR_STAT_DESC_BUF_FULL BIT(2) 119 #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY BIT(3) 120 #define MSGDMA_CSR_STAT_RESP_BUF_FULL BIT(4) 121 #define MSGDMA_CSR_STAT_STOPPED BIT(5) 122 #define MSGDMA_CSR_STAT_RESETTING BIT(6) 123 #define MSGDMA_CSR_STAT_STOPPED_ON_ERR BIT(7) 124 #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY BIT(8) 125 #define MSGDMA_CSR_STAT_IRQ BIT(9) 126 #define MSGDMA_CSR_STAT_MASK 0x3FF 127 #define MSGDMA_CSR_STAT_MASK_WITHOUT_IRQ 0x1FF 128 129 #define MSGDMA_CSR_STAT_BUSY_GET(v) GET_BIT_VALUE(v, 0) 130 #define MSGDMA_CSR_STAT_DESC_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 1) 131 #define MSGDMA_CSR_STAT_DESC_BUF_FULL_GET(v) GET_BIT_VALUE(v, 2) 132 #define MSGDMA_CSR_STAT_RESP_BUF_EMPTY_GET(v) GET_BIT_VALUE(v, 3) 133 #define MSGDMA_CSR_STAT_RESP_BUF_FULL_GET(v) GET_BIT_VALUE(v, 4) 134 #define MSGDMA_CSR_STAT_STOPPED_GET(v) GET_BIT_VALUE(v, 5) 135 #define MSGDMA_CSR_STAT_RESETTING_GET(v) GET_BIT_VALUE(v, 6) 136 #define MSGDMA_CSR_STAT_STOPPED_ON_ERR_GET(v) GET_BIT_VALUE(v, 7) 137 #define MSGDMA_CSR_STAT_STOPPED_ON_EARLY_GET(v) GET_BIT_VALUE(v, 8) 138 #define MSGDMA_CSR_STAT_IRQ_GET(v) GET_BIT_VALUE(v, 9) 139 140 /* mSGDMA CSR control register bit definitions 141 */ 142 #define MSGDMA_CSR_CTL_STOP BIT(0) 143 #define MSGDMA_CSR_CTL_RESET BIT(1) 144 #define MSGDMA_CSR_CTL_STOP_ON_ERR BIT(2) 145 #define MSGDMA_CSR_CTL_STOP_ON_EARLY BIT(3) 146 #define MSGDMA_CSR_CTL_GLOBAL_INTR BIT(4) 147 #define MSGDMA_CSR_CTL_STOP_DESCS BIT(5) 148 149 /* mSGDMA CSR fill level bits 150 */ 151 #define MSGDMA_CSR_WR_FILL_LEVEL_GET(v) (((v) & 0xffff0000) >> 16) 152 #define MSGDMA_CSR_RD_FILL_LEVEL_GET(v) ((v) & 0x0000ffff) 153 #define MSGDMA_CSR_RESP_FILL_LEVEL_GET(v) ((v) & 0x0000ffff) 154 155 /* mSGDMA response register map 156 */ 157 struct msgdma_response { 158 u32 bytes_transferred; 159 u32 status; 160 }; 161 162 /* mSGDMA response register bit definitions 163 */ 164 #define MSGDMA_RESP_EARLY_TERM BIT(8) 165 #define MSGDMA_RESP_ERR_MASK 0xFF 166 167 #endif /* __ALTERA_MSGDMA_H__*/ 168