1 /* 2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card 3 * and other Tigon based cards. 4 * 5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>. 6 * 7 * Thanks to Alteon and 3Com for providing hardware and documentation 8 * enabling me to write this driver. 9 * 10 * A mailing list for discussing the use of this driver has been 11 * setup, please subscribe to the lists if you have any questions 12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to 13 * see how to subscribe. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * Additional credits: 21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace 22 * dump support. The trace dump support has not been 23 * integrated yet however. 24 * Troy Benjegerdes: Big Endian (PPC) patches. 25 * Nate Stahl: Better out of memory handling and stats support. 26 * Aman Singla: Nasty race between interrupt handler and tx code dealing 27 * with 'testing the tx_ret_csm and setting tx_full' 28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping 29 * infrastructure and Sparc support 30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the 31 * driver under Linux/Sparc64 32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards 33 * ETHTOOL_GDRVINFO support 34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx 35 * handler and close() cleanup. 36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether 37 * memory mapped IO is enabled to 38 * make the driver work on RS/6000. 39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem 40 * where the driver would disable 41 * bus master mode if it had to disable 42 * write and invalidate. 43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little 44 * endian systems. 45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and 46 * rx producer index when 47 * flushing the Jumbo ring. 48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the 49 * driver init path. 50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes. 51 */ 52 53 #include <linux/module.h> 54 #include <linux/moduleparam.h> 55 #include <linux/types.h> 56 #include <linux/errno.h> 57 #include <linux/ioport.h> 58 #include <linux/pci.h> 59 #include <linux/dma-mapping.h> 60 #include <linux/kernel.h> 61 #include <linux/netdevice.h> 62 #include <linux/etherdevice.h> 63 #include <linux/skbuff.h> 64 #include <linux/delay.h> 65 #include <linux/mm.h> 66 #include <linux/highmem.h> 67 #include <linux/sockios.h> 68 #include <linux/firmware.h> 69 #include <linux/slab.h> 70 #include <linux/prefetch.h> 71 #include <linux/if_vlan.h> 72 73 #ifdef SIOCETHTOOL 74 #include <linux/ethtool.h> 75 #endif 76 77 #include <net/sock.h> 78 #include <net/ip.h> 79 80 #include <asm/io.h> 81 #include <asm/irq.h> 82 #include <asm/byteorder.h> 83 #include <linux/uaccess.h> 84 85 86 #define DRV_NAME "acenic" 87 88 #undef INDEX_DEBUG 89 90 #ifdef CONFIG_ACENIC_OMIT_TIGON_I 91 #define ACE_IS_TIGON_I(ap) 0 92 #define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES 93 #else 94 #define ACE_IS_TIGON_I(ap) (ap->version == 1) 95 #define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries 96 #endif 97 98 #ifndef PCI_VENDOR_ID_ALTEON 99 #define PCI_VENDOR_ID_ALTEON 0x12ae 100 #endif 101 #ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 102 #define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001 103 #define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002 104 #endif 105 #ifndef PCI_DEVICE_ID_3COM_3C985 106 #define PCI_DEVICE_ID_3COM_3C985 0x0001 107 #endif 108 #ifndef PCI_VENDOR_ID_NETGEAR 109 #define PCI_VENDOR_ID_NETGEAR 0x1385 110 #define PCI_DEVICE_ID_NETGEAR_GA620 0x620a 111 #endif 112 #ifndef PCI_DEVICE_ID_NETGEAR_GA620T 113 #define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a 114 #endif 115 116 117 /* 118 * Farallon used the DEC vendor ID by mistake and they seem not 119 * to care - stinky! 120 */ 121 #ifndef PCI_DEVICE_ID_FARALLON_PN9000SX 122 #define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a 123 #endif 124 #ifndef PCI_DEVICE_ID_FARALLON_PN9100T 125 #define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa 126 #endif 127 #ifndef PCI_VENDOR_ID_SGI 128 #define PCI_VENDOR_ID_SGI 0x10a9 129 #endif 130 #ifndef PCI_DEVICE_ID_SGI_ACENIC 131 #define PCI_DEVICE_ID_SGI_ACENIC 0x0009 132 #endif 133 134 static const struct pci_device_id acenic_pci_tbl[] = { 135 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE, 136 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 137 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER, 138 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 139 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985, 140 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 141 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620, 142 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 143 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T, 144 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 145 /* 146 * Farallon used the DEC vendor ID on their cards incorrectly, 147 * then later Alteon's ID. 148 */ 149 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX, 150 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 151 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T, 152 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 153 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC, 154 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 155 { } 156 }; 157 MODULE_DEVICE_TABLE(pci, acenic_pci_tbl); 158 159 #define ace_sync_irq(irq) synchronize_irq(irq) 160 161 #ifndef offset_in_page 162 #define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK) 163 #endif 164 165 #define ACE_MAX_MOD_PARMS 8 166 #define BOARD_IDX_STATIC 0 167 #define BOARD_IDX_OVERFLOW -1 168 169 #include "acenic.h" 170 171 /* 172 * These must be defined before the firmware is included. 173 */ 174 #define MAX_TEXT_LEN 96*1024 175 #define MAX_RODATA_LEN 8*1024 176 #define MAX_DATA_LEN 2*1024 177 178 #ifndef tigon2FwReleaseLocal 179 #define tigon2FwReleaseLocal 0 180 #endif 181 182 /* 183 * This driver currently supports Tigon I and Tigon II based cards 184 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear 185 * GA620. The driver should also work on the SGI, DEC and Farallon 186 * versions of the card, however I have not been able to test that 187 * myself. 188 * 189 * This card is really neat, it supports receive hardware checksumming 190 * and jumbo frames (up to 9000 bytes) and does a lot of work in the 191 * firmware. Also the programming interface is quite neat, except for 192 * the parts dealing with the i2c eeprom on the card ;-) 193 * 194 * Using jumbo frames: 195 * 196 * To enable jumbo frames, simply specify an mtu between 1500 and 9000 197 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time 198 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet 199 * interface number and <MTU> being the MTU value. 200 * 201 * Module parameters: 202 * 203 * When compiled as a loadable module, the driver allows for a number 204 * of module parameters to be specified. The driver supports the 205 * following module parameters: 206 * 207 * trace=<val> - Firmware trace level. This requires special traced 208 * firmware to replace the firmware supplied with 209 * the driver - for debugging purposes only. 210 * 211 * link=<val> - Link state. Normally you want to use the default link 212 * parameters set by the driver. This can be used to 213 * override these in case your switch doesn't negotiate 214 * the link properly. Valid values are: 215 * 0x0001 - Force half duplex link. 216 * 0x0002 - Do not negotiate line speed with the other end. 217 * 0x0010 - 10Mbit/sec link. 218 * 0x0020 - 100Mbit/sec link. 219 * 0x0040 - 1000Mbit/sec link. 220 * 0x0100 - Do not negotiate flow control. 221 * 0x0200 - Enable RX flow control Y 222 * 0x0400 - Enable TX flow control Y (Tigon II NICs only). 223 * Default value is 0x0270, ie. enable link+flow 224 * control negotiation. Negotiating the highest 225 * possible link speed with RX flow control enabled. 226 * 227 * When disabling link speed negotiation, only one link 228 * speed is allowed to be specified! 229 * 230 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed 231 * to wait for more packets to arive before 232 * interrupting the host, from the time the first 233 * packet arrives. 234 * 235 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed 236 * to wait for more packets to arive in the transmit ring, 237 * before interrupting the host, after transmitting the 238 * first packet in the ring. 239 * 240 * max_tx_desc=<val> - maximum number of transmit descriptors 241 * (packets) transmitted before interrupting the host. 242 * 243 * max_rx_desc=<val> - maximum number of receive descriptors 244 * (packets) received before interrupting the host. 245 * 246 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th 247 * increments of the NIC's on board memory to be used for 248 * transmit and receive buffers. For the 1MB NIC app. 800KB 249 * is available, on the 1/2MB NIC app. 300KB is available. 250 * 68KB will always be available as a minimum for both 251 * directions. The default value is a 50/50 split. 252 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate 253 * operations, default (1) is to always disable this as 254 * that is what Alteon does on NT. I have not been able 255 * to measure any real performance differences with 256 * this on my systems. Set <val>=0 if you want to 257 * enable these operations. 258 * 259 * If you use more than one NIC, specify the parameters for the 260 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to 261 * run tracing on NIC #2 but not on NIC #1 and #3. 262 * 263 * TODO: 264 * 265 * - Proper multicast support. 266 * - NIC dump support. 267 * - More tuning parameters. 268 * 269 * The mini ring is not used under Linux and I am not sure it makes sense 270 * to actually use it. 271 * 272 * New interrupt handler strategy: 273 * 274 * The old interrupt handler worked using the traditional method of 275 * replacing an skbuff with a new one when a packet arrives. However 276 * the rx rings do not need to contain a static number of buffer 277 * descriptors, thus it makes sense to move the memory allocation out 278 * of the main interrupt handler and do it in a bottom half handler 279 * and only allocate new buffers when the number of buffers in the 280 * ring is below a certain threshold. In order to avoid starving the 281 * NIC under heavy load it is however necessary to force allocation 282 * when hitting a minimum threshold. The strategy for alloction is as 283 * follows: 284 * 285 * RX_LOW_BUF_THRES - allocate buffers in the bottom half 286 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate 287 * the buffers in the interrupt handler 288 * RX_RING_THRES - maximum number of buffers in the rx ring 289 * RX_MINI_THRES - maximum number of buffers in the mini ring 290 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring 291 * 292 * One advantagous side effect of this allocation approach is that the 293 * entire rx processing can be done without holding any spin lock 294 * since the rx rings and registers are totally independent of the tx 295 * ring and its registers. This of course includes the kmalloc's of 296 * new skb's. Thus start_xmit can run in parallel with rx processing 297 * and the memory allocation on SMP systems. 298 * 299 * Note that running the skb reallocation in a bottom half opens up 300 * another can of races which needs to be handled properly. In 301 * particular it can happen that the interrupt handler tries to run 302 * the reallocation while the bottom half is either running on another 303 * CPU or was interrupted on the same CPU. To get around this the 304 * driver uses bitops to prevent the reallocation routines from being 305 * reentered. 306 * 307 * TX handling can also be done without holding any spin lock, wheee 308 * this is fun! since tx_ret_csm is only written to by the interrupt 309 * handler. The case to be aware of is when shutting down the device 310 * and cleaning up where it is necessary to make sure that 311 * start_xmit() is not running while this is happening. Well DaveM 312 * informs me that this case is already protected against ... bye bye 313 * Mr. Spin Lock, it was nice to know you. 314 * 315 * TX interrupts are now partly disabled so the NIC will only generate 316 * TX interrupts for the number of coal ticks, not for the number of 317 * TX packets in the queue. This should reduce the number of TX only, 318 * ie. when no RX processing is done, interrupts seen. 319 */ 320 321 /* 322 * Threshold values for RX buffer allocation - the low water marks for 323 * when to start refilling the rings are set to 75% of the ring 324 * sizes. It seems to make sense to refill the rings entirely from the 325 * intrrupt handler once it gets below the panic threshold, that way 326 * we don't risk that the refilling is moved to another CPU when the 327 * one running the interrupt handler just got the slab code hot in its 328 * cache. 329 */ 330 #define RX_RING_SIZE 72 331 #define RX_MINI_SIZE 64 332 #define RX_JUMBO_SIZE 48 333 334 #define RX_PANIC_STD_THRES 16 335 #define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2 336 #define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4 337 #define RX_PANIC_MINI_THRES 12 338 #define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2 339 #define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4 340 #define RX_PANIC_JUMBO_THRES 6 341 #define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2 342 #define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4 343 344 345 /* 346 * Size of the mini ring entries, basically these just should be big 347 * enough to take TCP ACKs 348 */ 349 #define ACE_MINI_SIZE 100 350 351 #define ACE_MINI_BUFSIZE ACE_MINI_SIZE 352 #define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4) 353 #define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4) 354 355 /* 356 * There seems to be a magic difference in the effect between 995 and 996 357 * but little difference between 900 and 995 ... no idea why. 358 * 359 * There is now a default set of tuning parameters which is set, depending 360 * on whether or not the user enables Jumbo frames. It's assumed that if 361 * Jumbo frames are enabled, the user wants optimal tuning for that case. 362 */ 363 #define DEF_TX_COAL 400 /* 996 */ 364 #define DEF_TX_MAX_DESC 60 /* was 40 */ 365 #define DEF_RX_COAL 120 /* 1000 */ 366 #define DEF_RX_MAX_DESC 25 367 #define DEF_TX_RATIO 21 /* 24 */ 368 369 #define DEF_JUMBO_TX_COAL 20 370 #define DEF_JUMBO_TX_MAX_DESC 60 371 #define DEF_JUMBO_RX_COAL 30 372 #define DEF_JUMBO_RX_MAX_DESC 6 373 #define DEF_JUMBO_TX_RATIO 21 374 375 #if tigon2FwReleaseLocal < 20001118 376 /* 377 * Standard firmware and early modifications duplicate 378 * IRQ load without this flag (coal timer is never reset). 379 * Note that with this flag tx_coal should be less than 380 * time to xmit full tx ring. 381 * 400usec is not so bad for tx ring size of 128. 382 */ 383 #define TX_COAL_INTS_ONLY 1 /* worth it */ 384 #else 385 /* 386 * With modified firmware, this is not necessary, but still useful. 387 */ 388 #define TX_COAL_INTS_ONLY 1 389 #endif 390 391 #define DEF_TRACE 0 392 #define DEF_STAT (2 * TICKS_PER_SEC) 393 394 395 static int link_state[ACE_MAX_MOD_PARMS]; 396 static int trace[ACE_MAX_MOD_PARMS]; 397 static int tx_coal_tick[ACE_MAX_MOD_PARMS]; 398 static int rx_coal_tick[ACE_MAX_MOD_PARMS]; 399 static int max_tx_desc[ACE_MAX_MOD_PARMS]; 400 static int max_rx_desc[ACE_MAX_MOD_PARMS]; 401 static int tx_ratio[ACE_MAX_MOD_PARMS]; 402 static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1}; 403 404 MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>"); 405 MODULE_LICENSE("GPL"); 406 MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver"); 407 #ifndef CONFIG_ACENIC_OMIT_TIGON_I 408 MODULE_FIRMWARE("acenic/tg1.bin"); 409 #endif 410 MODULE_FIRMWARE("acenic/tg2.bin"); 411 412 module_param_array_named(link, link_state, int, NULL, 0); 413 module_param_array(trace, int, NULL, 0); 414 module_param_array(tx_coal_tick, int, NULL, 0); 415 module_param_array(max_tx_desc, int, NULL, 0); 416 module_param_array(rx_coal_tick, int, NULL, 0); 417 module_param_array(max_rx_desc, int, NULL, 0); 418 module_param_array(tx_ratio, int, NULL, 0); 419 MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state"); 420 MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level"); 421 MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives"); 422 MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait"); 423 MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives"); 424 MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait"); 425 MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)"); 426 427 428 static const char version[] = 429 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n" 430 " http://home.cern.ch/~jes/gige/acenic.html\n"; 431 432 static int ace_get_link_ksettings(struct net_device *, 433 struct ethtool_link_ksettings *); 434 static int ace_set_link_ksettings(struct net_device *, 435 const struct ethtool_link_ksettings *); 436 static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *); 437 438 static const struct ethtool_ops ace_ethtool_ops = { 439 .get_drvinfo = ace_get_drvinfo, 440 .get_link_ksettings = ace_get_link_ksettings, 441 .set_link_ksettings = ace_set_link_ksettings, 442 }; 443 444 static void ace_watchdog(struct net_device *dev); 445 446 static const struct net_device_ops ace_netdev_ops = { 447 .ndo_open = ace_open, 448 .ndo_stop = ace_close, 449 .ndo_tx_timeout = ace_watchdog, 450 .ndo_get_stats = ace_get_stats, 451 .ndo_start_xmit = ace_start_xmit, 452 .ndo_set_rx_mode = ace_set_multicast_list, 453 .ndo_validate_addr = eth_validate_addr, 454 .ndo_set_mac_address = ace_set_mac_addr, 455 .ndo_change_mtu = ace_change_mtu, 456 }; 457 458 static int acenic_probe_one(struct pci_dev *pdev, 459 const struct pci_device_id *id) 460 { 461 struct net_device *dev; 462 struct ace_private *ap; 463 static int boards_found; 464 465 dev = alloc_etherdev(sizeof(struct ace_private)); 466 if (dev == NULL) 467 return -ENOMEM; 468 469 SET_NETDEV_DEV(dev, &pdev->dev); 470 471 ap = netdev_priv(dev); 472 ap->pdev = pdev; 473 ap->name = pci_name(pdev); 474 475 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; 476 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 477 478 dev->watchdog_timeo = 5*HZ; 479 dev->min_mtu = 0; 480 dev->max_mtu = ACE_JUMBO_MTU; 481 482 dev->netdev_ops = &ace_netdev_ops; 483 dev->ethtool_ops = &ace_ethtool_ops; 484 485 /* we only display this string ONCE */ 486 if (!boards_found) 487 printk(version); 488 489 if (pci_enable_device(pdev)) 490 goto fail_free_netdev; 491 492 /* 493 * Enable master mode before we start playing with the 494 * pci_command word since pci_set_master() will modify 495 * it. 496 */ 497 pci_set_master(pdev); 498 499 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command); 500 501 /* OpenFirmware on Mac's does not set this - DOH.. */ 502 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) { 503 printk(KERN_INFO "%s: Enabling PCI Memory Mapped " 504 "access - was not enabled by BIOS/Firmware\n", 505 ap->name); 506 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY; 507 pci_write_config_word(ap->pdev, PCI_COMMAND, 508 ap->pci_command); 509 wmb(); 510 } 511 512 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency); 513 if (ap->pci_latency <= 0x40) { 514 ap->pci_latency = 0x40; 515 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency); 516 } 517 518 /* 519 * Remap the regs into kernel space - this is abuse of 520 * dev->base_addr since it was means for I/O port 521 * addresses but who gives a damn. 522 */ 523 dev->base_addr = pci_resource_start(pdev, 0); 524 ap->regs = ioremap(dev->base_addr, 0x4000); 525 if (!ap->regs) { 526 printk(KERN_ERR "%s: Unable to map I/O register, " 527 "AceNIC %i will be disabled.\n", 528 ap->name, boards_found); 529 goto fail_free_netdev; 530 } 531 532 switch(pdev->vendor) { 533 case PCI_VENDOR_ID_ALTEON: 534 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) { 535 printk(KERN_INFO "%s: Farallon PN9100-T ", 536 ap->name); 537 } else { 538 printk(KERN_INFO "%s: Alteon AceNIC ", 539 ap->name); 540 } 541 break; 542 case PCI_VENDOR_ID_3COM: 543 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name); 544 break; 545 case PCI_VENDOR_ID_NETGEAR: 546 printk(KERN_INFO "%s: NetGear GA620 ", ap->name); 547 break; 548 case PCI_VENDOR_ID_DEC: 549 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) { 550 printk(KERN_INFO "%s: Farallon PN9000-SX ", 551 ap->name); 552 break; 553 } 554 case PCI_VENDOR_ID_SGI: 555 printk(KERN_INFO "%s: SGI AceNIC ", ap->name); 556 break; 557 default: 558 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name); 559 break; 560 } 561 562 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr); 563 printk("irq %d\n", pdev->irq); 564 565 #ifdef CONFIG_ACENIC_OMIT_TIGON_I 566 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) { 567 printk(KERN_ERR "%s: Driver compiled without Tigon I" 568 " support - NIC disabled\n", dev->name); 569 goto fail_uninit; 570 } 571 #endif 572 573 if (ace_allocate_descriptors(dev)) 574 goto fail_free_netdev; 575 576 #ifdef MODULE 577 if (boards_found >= ACE_MAX_MOD_PARMS) 578 ap->board_idx = BOARD_IDX_OVERFLOW; 579 else 580 ap->board_idx = boards_found; 581 #else 582 ap->board_idx = BOARD_IDX_STATIC; 583 #endif 584 585 if (ace_init(dev)) 586 goto fail_free_netdev; 587 588 if (register_netdev(dev)) { 589 printk(KERN_ERR "acenic: device registration failed\n"); 590 goto fail_uninit; 591 } 592 ap->name = dev->name; 593 594 if (ap->pci_using_dac) 595 dev->features |= NETIF_F_HIGHDMA; 596 597 pci_set_drvdata(pdev, dev); 598 599 boards_found++; 600 return 0; 601 602 fail_uninit: 603 ace_init_cleanup(dev); 604 fail_free_netdev: 605 free_netdev(dev); 606 return -ENODEV; 607 } 608 609 static void acenic_remove_one(struct pci_dev *pdev) 610 { 611 struct net_device *dev = pci_get_drvdata(pdev); 612 struct ace_private *ap = netdev_priv(dev); 613 struct ace_regs __iomem *regs = ap->regs; 614 short i; 615 616 unregister_netdev(dev); 617 618 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); 619 if (ap->version >= 2) 620 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl); 621 622 /* 623 * This clears any pending interrupts 624 */ 625 writel(1, ®s->Mb0Lo); 626 readl(®s->CpuCtrl); /* flush */ 627 628 /* 629 * Make sure no other CPUs are processing interrupts 630 * on the card before the buffers are being released. 631 * Otherwise one might experience some `interesting' 632 * effects. 633 * 634 * Then release the RX buffers - jumbo buffers were 635 * already released in ace_close(). 636 */ 637 ace_sync_irq(dev->irq); 638 639 for (i = 0; i < RX_STD_RING_ENTRIES; i++) { 640 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb; 641 642 if (skb) { 643 struct ring_info *ringp; 644 dma_addr_t mapping; 645 646 ringp = &ap->skb->rx_std_skbuff[i]; 647 mapping = dma_unmap_addr(ringp, mapping); 648 pci_unmap_page(ap->pdev, mapping, 649 ACE_STD_BUFSIZE, 650 PCI_DMA_FROMDEVICE); 651 652 ap->rx_std_ring[i].size = 0; 653 ap->skb->rx_std_skbuff[i].skb = NULL; 654 dev_kfree_skb(skb); 655 } 656 } 657 658 if (ap->version >= 2) { 659 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) { 660 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb; 661 662 if (skb) { 663 struct ring_info *ringp; 664 dma_addr_t mapping; 665 666 ringp = &ap->skb->rx_mini_skbuff[i]; 667 mapping = dma_unmap_addr(ringp,mapping); 668 pci_unmap_page(ap->pdev, mapping, 669 ACE_MINI_BUFSIZE, 670 PCI_DMA_FROMDEVICE); 671 672 ap->rx_mini_ring[i].size = 0; 673 ap->skb->rx_mini_skbuff[i].skb = NULL; 674 dev_kfree_skb(skb); 675 } 676 } 677 } 678 679 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) { 680 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb; 681 if (skb) { 682 struct ring_info *ringp; 683 dma_addr_t mapping; 684 685 ringp = &ap->skb->rx_jumbo_skbuff[i]; 686 mapping = dma_unmap_addr(ringp, mapping); 687 pci_unmap_page(ap->pdev, mapping, 688 ACE_JUMBO_BUFSIZE, 689 PCI_DMA_FROMDEVICE); 690 691 ap->rx_jumbo_ring[i].size = 0; 692 ap->skb->rx_jumbo_skbuff[i].skb = NULL; 693 dev_kfree_skb(skb); 694 } 695 } 696 697 ace_init_cleanup(dev); 698 free_netdev(dev); 699 } 700 701 static struct pci_driver acenic_pci_driver = { 702 .name = "acenic", 703 .id_table = acenic_pci_tbl, 704 .probe = acenic_probe_one, 705 .remove = acenic_remove_one, 706 }; 707 708 static void ace_free_descriptors(struct net_device *dev) 709 { 710 struct ace_private *ap = netdev_priv(dev); 711 int size; 712 713 if (ap->rx_std_ring != NULL) { 714 size = (sizeof(struct rx_desc) * 715 (RX_STD_RING_ENTRIES + 716 RX_JUMBO_RING_ENTRIES + 717 RX_MINI_RING_ENTRIES + 718 RX_RETURN_RING_ENTRIES)); 719 pci_free_consistent(ap->pdev, size, ap->rx_std_ring, 720 ap->rx_ring_base_dma); 721 ap->rx_std_ring = NULL; 722 ap->rx_jumbo_ring = NULL; 723 ap->rx_mini_ring = NULL; 724 ap->rx_return_ring = NULL; 725 } 726 if (ap->evt_ring != NULL) { 727 size = (sizeof(struct event) * EVT_RING_ENTRIES); 728 pci_free_consistent(ap->pdev, size, ap->evt_ring, 729 ap->evt_ring_dma); 730 ap->evt_ring = NULL; 731 } 732 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) { 733 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES); 734 pci_free_consistent(ap->pdev, size, ap->tx_ring, 735 ap->tx_ring_dma); 736 } 737 ap->tx_ring = NULL; 738 739 if (ap->evt_prd != NULL) { 740 pci_free_consistent(ap->pdev, sizeof(u32), 741 (void *)ap->evt_prd, ap->evt_prd_dma); 742 ap->evt_prd = NULL; 743 } 744 if (ap->rx_ret_prd != NULL) { 745 pci_free_consistent(ap->pdev, sizeof(u32), 746 (void *)ap->rx_ret_prd, 747 ap->rx_ret_prd_dma); 748 ap->rx_ret_prd = NULL; 749 } 750 if (ap->tx_csm != NULL) { 751 pci_free_consistent(ap->pdev, sizeof(u32), 752 (void *)ap->tx_csm, ap->tx_csm_dma); 753 ap->tx_csm = NULL; 754 } 755 } 756 757 758 static int ace_allocate_descriptors(struct net_device *dev) 759 { 760 struct ace_private *ap = netdev_priv(dev); 761 int size; 762 763 size = (sizeof(struct rx_desc) * 764 (RX_STD_RING_ENTRIES + 765 RX_JUMBO_RING_ENTRIES + 766 RX_MINI_RING_ENTRIES + 767 RX_RETURN_RING_ENTRIES)); 768 769 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size, 770 &ap->rx_ring_base_dma); 771 if (ap->rx_std_ring == NULL) 772 goto fail; 773 774 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES; 775 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES; 776 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES; 777 778 size = (sizeof(struct event) * EVT_RING_ENTRIES); 779 780 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma); 781 782 if (ap->evt_ring == NULL) 783 goto fail; 784 785 /* 786 * Only allocate a host TX ring for the Tigon II, the Tigon I 787 * has to use PCI registers for this ;-( 788 */ 789 if (!ACE_IS_TIGON_I(ap)) { 790 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES); 791 792 ap->tx_ring = pci_alloc_consistent(ap->pdev, size, 793 &ap->tx_ring_dma); 794 795 if (ap->tx_ring == NULL) 796 goto fail; 797 } 798 799 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32), 800 &ap->evt_prd_dma); 801 if (ap->evt_prd == NULL) 802 goto fail; 803 804 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32), 805 &ap->rx_ret_prd_dma); 806 if (ap->rx_ret_prd == NULL) 807 goto fail; 808 809 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32), 810 &ap->tx_csm_dma); 811 if (ap->tx_csm == NULL) 812 goto fail; 813 814 return 0; 815 816 fail: 817 /* Clean up. */ 818 ace_init_cleanup(dev); 819 return 1; 820 } 821 822 823 /* 824 * Generic cleanup handling data allocated during init. Used when the 825 * module is unloaded or if an error occurs during initialization 826 */ 827 static void ace_init_cleanup(struct net_device *dev) 828 { 829 struct ace_private *ap; 830 831 ap = netdev_priv(dev); 832 833 ace_free_descriptors(dev); 834 835 if (ap->info) 836 pci_free_consistent(ap->pdev, sizeof(struct ace_info), 837 ap->info, ap->info_dma); 838 kfree(ap->skb); 839 kfree(ap->trace_buf); 840 841 if (dev->irq) 842 free_irq(dev->irq, dev); 843 844 iounmap(ap->regs); 845 } 846 847 848 /* 849 * Commands are considered to be slow. 850 */ 851 static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd) 852 { 853 u32 idx; 854 855 idx = readl(®s->CmdPrd); 856 857 writel(*(u32 *)(cmd), ®s->CmdRng[idx]); 858 idx = (idx + 1) % CMD_RING_ENTRIES; 859 860 writel(idx, ®s->CmdPrd); 861 } 862 863 864 static int ace_init(struct net_device *dev) 865 { 866 struct ace_private *ap; 867 struct ace_regs __iomem *regs; 868 struct ace_info *info = NULL; 869 struct pci_dev *pdev; 870 unsigned long myjif; 871 u64 tmp_ptr; 872 u32 tig_ver, mac1, mac2, tmp, pci_state; 873 int board_idx, ecode = 0; 874 short i; 875 unsigned char cache_size; 876 877 ap = netdev_priv(dev); 878 regs = ap->regs; 879 880 board_idx = ap->board_idx; 881 882 /* 883 * aman@sgi.com - its useful to do a NIC reset here to 884 * address the `Firmware not running' problem subsequent 885 * to any crashes involving the NIC 886 */ 887 writel(HW_RESET | (HW_RESET << 24), ®s->HostCtrl); 888 readl(®s->HostCtrl); /* PCI write posting */ 889 udelay(5); 890 891 /* 892 * Don't access any other registers before this point! 893 */ 894 #ifdef __BIG_ENDIAN 895 /* 896 * This will most likely need BYTE_SWAP once we switch 897 * to using __raw_writel() 898 */ 899 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)), 900 ®s->HostCtrl); 901 #else 902 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)), 903 ®s->HostCtrl); 904 #endif 905 readl(®s->HostCtrl); /* PCI write posting */ 906 907 /* 908 * Stop the NIC CPU and clear pending interrupts 909 */ 910 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); 911 readl(®s->CpuCtrl); /* PCI write posting */ 912 writel(0, ®s->Mb0Lo); 913 914 tig_ver = readl(®s->HostCtrl) >> 28; 915 916 switch(tig_ver){ 917 #ifndef CONFIG_ACENIC_OMIT_TIGON_I 918 case 4: 919 case 5: 920 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ", 921 tig_ver, ap->firmware_major, ap->firmware_minor, 922 ap->firmware_fix); 923 writel(0, ®s->LocalCtrl); 924 ap->version = 1; 925 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES; 926 break; 927 #endif 928 case 6: 929 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ", 930 tig_ver, ap->firmware_major, ap->firmware_minor, 931 ap->firmware_fix); 932 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl); 933 readl(®s->CpuBCtrl); /* PCI write posting */ 934 /* 935 * The SRAM bank size does _not_ indicate the amount 936 * of memory on the card, it controls the _bank_ size! 937 * Ie. a 1MB AceNIC will have two banks of 512KB. 938 */ 939 writel(SRAM_BANK_512K, ®s->LocalCtrl); 940 writel(SYNC_SRAM_TIMING, ®s->MiscCfg); 941 ap->version = 2; 942 ap->tx_ring_entries = MAX_TX_RING_ENTRIES; 943 break; 944 default: 945 printk(KERN_WARNING " Unsupported Tigon version detected " 946 "(%i)\n", tig_ver); 947 ecode = -ENODEV; 948 goto init_error; 949 } 950 951 /* 952 * ModeStat _must_ be set after the SRAM settings as this change 953 * seems to corrupt the ModeStat and possible other registers. 954 * The SRAM settings survive resets and setting it to the same 955 * value a second time works as well. This is what caused the 956 * `Firmware not running' problem on the Tigon II. 957 */ 958 #ifdef __BIG_ENDIAN 959 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD | 960 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat); 961 #else 962 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | 963 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat); 964 #endif 965 readl(®s->ModeStat); /* PCI write posting */ 966 967 mac1 = 0; 968 for(i = 0; i < 4; i++) { 969 int t; 970 971 mac1 = mac1 << 8; 972 t = read_eeprom_byte(dev, 0x8c+i); 973 if (t < 0) { 974 ecode = -EIO; 975 goto init_error; 976 } else 977 mac1 |= (t & 0xff); 978 } 979 mac2 = 0; 980 for(i = 4; i < 8; i++) { 981 int t; 982 983 mac2 = mac2 << 8; 984 t = read_eeprom_byte(dev, 0x8c+i); 985 if (t < 0) { 986 ecode = -EIO; 987 goto init_error; 988 } else 989 mac2 |= (t & 0xff); 990 } 991 992 writel(mac1, ®s->MacAddrHi); 993 writel(mac2, ®s->MacAddrLo); 994 995 dev->dev_addr[0] = (mac1 >> 8) & 0xff; 996 dev->dev_addr[1] = mac1 & 0xff; 997 dev->dev_addr[2] = (mac2 >> 24) & 0xff; 998 dev->dev_addr[3] = (mac2 >> 16) & 0xff; 999 dev->dev_addr[4] = (mac2 >> 8) & 0xff; 1000 dev->dev_addr[5] = mac2 & 0xff; 1001 1002 printk("MAC: %pM\n", dev->dev_addr); 1003 1004 /* 1005 * Looks like this is necessary to deal with on all architectures, 1006 * even this %$#%$# N440BX Intel based thing doesn't get it right. 1007 * Ie. having two NICs in the machine, one will have the cache 1008 * line set at boot time, the other will not. 1009 */ 1010 pdev = ap->pdev; 1011 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size); 1012 cache_size <<= 2; 1013 if (cache_size != SMP_CACHE_BYTES) { 1014 printk(KERN_INFO " PCI cache line size set incorrectly " 1015 "(%i bytes) by BIOS/FW, ", cache_size); 1016 if (cache_size > SMP_CACHE_BYTES) 1017 printk("expecting %i\n", SMP_CACHE_BYTES); 1018 else { 1019 printk("correcting to %i\n", SMP_CACHE_BYTES); 1020 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 1021 SMP_CACHE_BYTES >> 2); 1022 } 1023 } 1024 1025 pci_state = readl(®s->PciState); 1026 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, " 1027 "latency: %i clks\n", 1028 (pci_state & PCI_32BIT) ? 32 : 64, 1029 (pci_state & PCI_66MHZ) ? 66 : 33, 1030 ap->pci_latency); 1031 1032 /* 1033 * Set the max DMA transfer size. Seems that for most systems 1034 * the performance is better when no MAX parameter is 1035 * set. However for systems enabling PCI write and invalidate, 1036 * DMA writes must be set to the L1 cache line size to get 1037 * optimal performance. 1038 * 1039 * The default is now to turn the PCI write and invalidate off 1040 * - that is what Alteon does for NT. 1041 */ 1042 tmp = READ_CMD_MEM | WRITE_CMD_MEM; 1043 if (ap->version >= 2) { 1044 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ)); 1045 /* 1046 * Tuning parameters only supported for 8 cards 1047 */ 1048 if (board_idx == BOARD_IDX_OVERFLOW || 1049 dis_pci_mem_inval[board_idx]) { 1050 if (ap->pci_command & PCI_COMMAND_INVALIDATE) { 1051 ap->pci_command &= ~PCI_COMMAND_INVALIDATE; 1052 pci_write_config_word(pdev, PCI_COMMAND, 1053 ap->pci_command); 1054 printk(KERN_INFO " Disabling PCI memory " 1055 "write and invalidate\n"); 1056 } 1057 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) { 1058 printk(KERN_INFO " PCI memory write & invalidate " 1059 "enabled by BIOS, enabling counter measures\n"); 1060 1061 switch(SMP_CACHE_BYTES) { 1062 case 16: 1063 tmp |= DMA_WRITE_MAX_16; 1064 break; 1065 case 32: 1066 tmp |= DMA_WRITE_MAX_32; 1067 break; 1068 case 64: 1069 tmp |= DMA_WRITE_MAX_64; 1070 break; 1071 case 128: 1072 tmp |= DMA_WRITE_MAX_128; 1073 break; 1074 default: 1075 printk(KERN_INFO " Cache line size %i not " 1076 "supported, PCI write and invalidate " 1077 "disabled\n", SMP_CACHE_BYTES); 1078 ap->pci_command &= ~PCI_COMMAND_INVALIDATE; 1079 pci_write_config_word(pdev, PCI_COMMAND, 1080 ap->pci_command); 1081 } 1082 } 1083 } 1084 1085 #ifdef __sparc__ 1086 /* 1087 * On this platform, we know what the best dma settings 1088 * are. We use 64-byte maximum bursts, because if we 1089 * burst larger than the cache line size (or even cross 1090 * a 64byte boundary in a single burst) the UltraSparc 1091 * PCI controller will disconnect at 64-byte multiples. 1092 * 1093 * Read-multiple will be properly enabled above, and when 1094 * set will give the PCI controller proper hints about 1095 * prefetching. 1096 */ 1097 tmp &= ~DMA_READ_WRITE_MASK; 1098 tmp |= DMA_READ_MAX_64; 1099 tmp |= DMA_WRITE_MAX_64; 1100 #endif 1101 #ifdef __alpha__ 1102 tmp &= ~DMA_READ_WRITE_MASK; 1103 tmp |= DMA_READ_MAX_128; 1104 /* 1105 * All the docs say MUST NOT. Well, I did. 1106 * Nothing terrible happens, if we load wrong size. 1107 * Bit w&i still works better! 1108 */ 1109 tmp |= DMA_WRITE_MAX_128; 1110 #endif 1111 writel(tmp, ®s->PciState); 1112 1113 #if 0 1114 /* 1115 * The Host PCI bus controller driver has to set FBB. 1116 * If all devices on that PCI bus support FBB, then the controller 1117 * can enable FBB support in the Host PCI Bus controller (or on 1118 * the PCI-PCI bridge if that applies). 1119 * -ggg 1120 */ 1121 /* 1122 * I have received reports from people having problems when this 1123 * bit is enabled. 1124 */ 1125 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) { 1126 printk(KERN_INFO " Enabling PCI Fast Back to Back\n"); 1127 ap->pci_command |= PCI_COMMAND_FAST_BACK; 1128 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command); 1129 } 1130 #endif 1131 1132 /* 1133 * Configure DMA attributes. 1134 */ 1135 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 1136 ap->pci_using_dac = 1; 1137 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 1138 ap->pci_using_dac = 0; 1139 } else { 1140 ecode = -ENODEV; 1141 goto init_error; 1142 } 1143 1144 /* 1145 * Initialize the generic info block and the command+event rings 1146 * and the control blocks for the transmit and receive rings 1147 * as they need to be setup once and for all. 1148 */ 1149 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info), 1150 &ap->info_dma))) { 1151 ecode = -EAGAIN; 1152 goto init_error; 1153 } 1154 ap->info = info; 1155 1156 /* 1157 * Get the memory for the skb rings. 1158 */ 1159 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) { 1160 ecode = -EAGAIN; 1161 goto init_error; 1162 } 1163 1164 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED, 1165 DRV_NAME, dev); 1166 if (ecode) { 1167 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n", 1168 DRV_NAME, pdev->irq); 1169 goto init_error; 1170 } else 1171 dev->irq = pdev->irq; 1172 1173 #ifdef INDEX_DEBUG 1174 spin_lock_init(&ap->debug_lock); 1175 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1; 1176 ap->last_std_rx = 0; 1177 ap->last_mini_rx = 0; 1178 #endif 1179 1180 memset(ap->info, 0, sizeof(struct ace_info)); 1181 memset(ap->skb, 0, sizeof(struct ace_skb)); 1182 1183 ecode = ace_load_firmware(dev); 1184 if (ecode) 1185 goto init_error; 1186 1187 ap->fw_running = 0; 1188 1189 tmp_ptr = ap->info_dma; 1190 writel(tmp_ptr >> 32, ®s->InfoPtrHi); 1191 writel(tmp_ptr & 0xffffffff, ®s->InfoPtrLo); 1192 1193 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event)); 1194 1195 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma); 1196 info->evt_ctrl.flags = 0; 1197 1198 *(ap->evt_prd) = 0; 1199 wmb(); 1200 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma); 1201 writel(0, ®s->EvtCsm); 1202 1203 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100); 1204 info->cmd_ctrl.flags = 0; 1205 info->cmd_ctrl.max_len = 0; 1206 1207 for (i = 0; i < CMD_RING_ENTRIES; i++) 1208 writel(0, ®s->CmdRng[i]); 1209 1210 writel(0, ®s->CmdPrd); 1211 writel(0, ®s->CmdCsm); 1212 1213 tmp_ptr = ap->info_dma; 1214 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats); 1215 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr); 1216 1217 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma); 1218 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE; 1219 info->rx_std_ctrl.flags = 1220 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST; 1221 1222 memset(ap->rx_std_ring, 0, 1223 RX_STD_RING_ENTRIES * sizeof(struct rx_desc)); 1224 1225 for (i = 0; i < RX_STD_RING_ENTRIES; i++) 1226 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM; 1227 1228 ap->rx_std_skbprd = 0; 1229 atomic_set(&ap->cur_rx_bufs, 0); 1230 1231 set_aceaddr(&info->rx_jumbo_ctrl.rngptr, 1232 (ap->rx_ring_base_dma + 1233 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES))); 1234 info->rx_jumbo_ctrl.max_len = 0; 1235 info->rx_jumbo_ctrl.flags = 1236 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST; 1237 1238 memset(ap->rx_jumbo_ring, 0, 1239 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc)); 1240 1241 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) 1242 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO; 1243 1244 ap->rx_jumbo_skbprd = 0; 1245 atomic_set(&ap->cur_jumbo_bufs, 0); 1246 1247 memset(ap->rx_mini_ring, 0, 1248 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc)); 1249 1250 if (ap->version >= 2) { 1251 set_aceaddr(&info->rx_mini_ctrl.rngptr, 1252 (ap->rx_ring_base_dma + 1253 (sizeof(struct rx_desc) * 1254 (RX_STD_RING_ENTRIES + 1255 RX_JUMBO_RING_ENTRIES)))); 1256 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE; 1257 info->rx_mini_ctrl.flags = 1258 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|RCB_FLG_VLAN_ASSIST; 1259 1260 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) 1261 ap->rx_mini_ring[i].flags = 1262 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI; 1263 } else { 1264 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0); 1265 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE; 1266 info->rx_mini_ctrl.max_len = 0; 1267 } 1268 1269 ap->rx_mini_skbprd = 0; 1270 atomic_set(&ap->cur_mini_bufs, 0); 1271 1272 set_aceaddr(&info->rx_return_ctrl.rngptr, 1273 (ap->rx_ring_base_dma + 1274 (sizeof(struct rx_desc) * 1275 (RX_STD_RING_ENTRIES + 1276 RX_JUMBO_RING_ENTRIES + 1277 RX_MINI_RING_ENTRIES)))); 1278 info->rx_return_ctrl.flags = 0; 1279 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES; 1280 1281 memset(ap->rx_return_ring, 0, 1282 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc)); 1283 1284 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma); 1285 *(ap->rx_ret_prd) = 0; 1286 1287 writel(TX_RING_BASE, ®s->WinBase); 1288 1289 if (ACE_IS_TIGON_I(ap)) { 1290 ap->tx_ring = (__force struct tx_desc *) regs->Window; 1291 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES 1292 * sizeof(struct tx_desc)) / sizeof(u32); i++) 1293 writel(0, (__force void __iomem *)ap->tx_ring + i * 4); 1294 1295 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE); 1296 } else { 1297 memset(ap->tx_ring, 0, 1298 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc)); 1299 1300 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma); 1301 } 1302 1303 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap); 1304 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST; 1305 1306 /* 1307 * The Tigon I does not like having the TX ring in host memory ;-( 1308 */ 1309 if (!ACE_IS_TIGON_I(ap)) 1310 tmp |= RCB_FLG_TX_HOST_RING; 1311 #if TX_COAL_INTS_ONLY 1312 tmp |= RCB_FLG_COAL_INT_ONLY; 1313 #endif 1314 info->tx_ctrl.flags = tmp; 1315 1316 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma); 1317 1318 /* 1319 * Potential item for tuning parameter 1320 */ 1321 #if 0 /* NO */ 1322 writel(DMA_THRESH_16W, ®s->DmaReadCfg); 1323 writel(DMA_THRESH_16W, ®s->DmaWriteCfg); 1324 #else 1325 writel(DMA_THRESH_8W, ®s->DmaReadCfg); 1326 writel(DMA_THRESH_8W, ®s->DmaWriteCfg); 1327 #endif 1328 1329 writel(0, ®s->MaskInt); 1330 writel(1, ®s->IfIdx); 1331 #if 0 1332 /* 1333 * McKinley boxes do not like us fiddling with AssistState 1334 * this early 1335 */ 1336 writel(1, ®s->AssistState); 1337 #endif 1338 1339 writel(DEF_STAT, ®s->TuneStatTicks); 1340 writel(DEF_TRACE, ®s->TuneTrace); 1341 1342 ace_set_rxtx_parms(dev, 0); 1343 1344 if (board_idx == BOARD_IDX_OVERFLOW) { 1345 printk(KERN_WARNING "%s: more than %i NICs detected, " 1346 "ignoring module parameters!\n", 1347 ap->name, ACE_MAX_MOD_PARMS); 1348 } else if (board_idx >= 0) { 1349 if (tx_coal_tick[board_idx]) 1350 writel(tx_coal_tick[board_idx], 1351 ®s->TuneTxCoalTicks); 1352 if (max_tx_desc[board_idx]) 1353 writel(max_tx_desc[board_idx], ®s->TuneMaxTxDesc); 1354 1355 if (rx_coal_tick[board_idx]) 1356 writel(rx_coal_tick[board_idx], 1357 ®s->TuneRxCoalTicks); 1358 if (max_rx_desc[board_idx]) 1359 writel(max_rx_desc[board_idx], ®s->TuneMaxRxDesc); 1360 1361 if (trace[board_idx]) 1362 writel(trace[board_idx], ®s->TuneTrace); 1363 1364 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64)) 1365 writel(tx_ratio[board_idx], ®s->TxBufRat); 1366 } 1367 1368 /* 1369 * Default link parameters 1370 */ 1371 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB | 1372 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE; 1373 if(ap->version >= 2) 1374 tmp |= LNK_TX_FLOW_CTL_Y; 1375 1376 /* 1377 * Override link default parameters 1378 */ 1379 if ((board_idx >= 0) && link_state[board_idx]) { 1380 int option = link_state[board_idx]; 1381 1382 tmp = LNK_ENABLE; 1383 1384 if (option & 0x01) { 1385 printk(KERN_INFO "%s: Setting half duplex link\n", 1386 ap->name); 1387 tmp &= ~LNK_FULL_DUPLEX; 1388 } 1389 if (option & 0x02) 1390 tmp &= ~LNK_NEGOTIATE; 1391 if (option & 0x10) 1392 tmp |= LNK_10MB; 1393 if (option & 0x20) 1394 tmp |= LNK_100MB; 1395 if (option & 0x40) 1396 tmp |= LNK_1000MB; 1397 if ((option & 0x70) == 0) { 1398 printk(KERN_WARNING "%s: No media speed specified, " 1399 "forcing auto negotiation\n", ap->name); 1400 tmp |= LNK_NEGOTIATE | LNK_1000MB | 1401 LNK_100MB | LNK_10MB; 1402 } 1403 if ((option & 0x100) == 0) 1404 tmp |= LNK_NEG_FCTL; 1405 else 1406 printk(KERN_INFO "%s: Disabling flow control " 1407 "negotiation\n", ap->name); 1408 if (option & 0x200) 1409 tmp |= LNK_RX_FLOW_CTL_Y; 1410 if ((option & 0x400) && (ap->version >= 2)) { 1411 printk(KERN_INFO "%s: Enabling TX flow control\n", 1412 ap->name); 1413 tmp |= LNK_TX_FLOW_CTL_Y; 1414 } 1415 } 1416 1417 ap->link = tmp; 1418 writel(tmp, ®s->TuneLink); 1419 if (ap->version >= 2) 1420 writel(tmp, ®s->TuneFastLink); 1421 1422 writel(ap->firmware_start, ®s->Pc); 1423 1424 writel(0, ®s->Mb0Lo); 1425 1426 /* 1427 * Set tx_csm before we start receiving interrupts, otherwise 1428 * the interrupt handler might think it is supposed to process 1429 * tx ints before we are up and running, which may cause a null 1430 * pointer access in the int handler. 1431 */ 1432 ap->cur_rx = 0; 1433 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0; 1434 1435 wmb(); 1436 ace_set_txprd(regs, ap, 0); 1437 writel(0, ®s->RxRetCsm); 1438 1439 /* 1440 * Enable DMA engine now. 1441 * If we do this sooner, Mckinley box pukes. 1442 * I assume it's because Tigon II DMA engine wants to check 1443 * *something* even before the CPU is started. 1444 */ 1445 writel(1, ®s->AssistState); /* enable DMA */ 1446 1447 /* 1448 * Start the NIC CPU 1449 */ 1450 writel(readl(®s->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), ®s->CpuCtrl); 1451 readl(®s->CpuCtrl); 1452 1453 /* 1454 * Wait for the firmware to spin up - max 3 seconds. 1455 */ 1456 myjif = jiffies + 3 * HZ; 1457 while (time_before(jiffies, myjif) && !ap->fw_running) 1458 cpu_relax(); 1459 1460 if (!ap->fw_running) { 1461 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name); 1462 1463 ace_dump_trace(ap); 1464 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); 1465 readl(®s->CpuCtrl); 1466 1467 /* aman@sgi.com - account for badly behaving firmware/NIC: 1468 * - have observed that the NIC may continue to generate 1469 * interrupts for some reason; attempt to stop it - halt 1470 * second CPU for Tigon II cards, and also clear Mb0 1471 * - if we're a module, we'll fail to load if this was 1472 * the only GbE card in the system => if the kernel does 1473 * see an interrupt from the NIC, code to handle it is 1474 * gone and OOps! - so free_irq also 1475 */ 1476 if (ap->version >= 2) 1477 writel(readl(®s->CpuBCtrl) | CPU_HALT, 1478 ®s->CpuBCtrl); 1479 writel(0, ®s->Mb0Lo); 1480 readl(®s->Mb0Lo); 1481 1482 ecode = -EBUSY; 1483 goto init_error; 1484 } 1485 1486 /* 1487 * We load the ring here as there seem to be no way to tell the 1488 * firmware to wipe the ring without re-initializing it. 1489 */ 1490 if (!test_and_set_bit(0, &ap->std_refill_busy)) 1491 ace_load_std_rx_ring(dev, RX_RING_SIZE); 1492 else 1493 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n", 1494 ap->name); 1495 if (ap->version >= 2) { 1496 if (!test_and_set_bit(0, &ap->mini_refill_busy)) 1497 ace_load_mini_rx_ring(dev, RX_MINI_SIZE); 1498 else 1499 printk(KERN_ERR "%s: Someone is busy refilling " 1500 "the RX mini ring\n", ap->name); 1501 } 1502 return 0; 1503 1504 init_error: 1505 ace_init_cleanup(dev); 1506 return ecode; 1507 } 1508 1509 1510 static void ace_set_rxtx_parms(struct net_device *dev, int jumbo) 1511 { 1512 struct ace_private *ap = netdev_priv(dev); 1513 struct ace_regs __iomem *regs = ap->regs; 1514 int board_idx = ap->board_idx; 1515 1516 if (board_idx >= 0) { 1517 if (!jumbo) { 1518 if (!tx_coal_tick[board_idx]) 1519 writel(DEF_TX_COAL, ®s->TuneTxCoalTicks); 1520 if (!max_tx_desc[board_idx]) 1521 writel(DEF_TX_MAX_DESC, ®s->TuneMaxTxDesc); 1522 if (!rx_coal_tick[board_idx]) 1523 writel(DEF_RX_COAL, ®s->TuneRxCoalTicks); 1524 if (!max_rx_desc[board_idx]) 1525 writel(DEF_RX_MAX_DESC, ®s->TuneMaxRxDesc); 1526 if (!tx_ratio[board_idx]) 1527 writel(DEF_TX_RATIO, ®s->TxBufRat); 1528 } else { 1529 if (!tx_coal_tick[board_idx]) 1530 writel(DEF_JUMBO_TX_COAL, 1531 ®s->TuneTxCoalTicks); 1532 if (!max_tx_desc[board_idx]) 1533 writel(DEF_JUMBO_TX_MAX_DESC, 1534 ®s->TuneMaxTxDesc); 1535 if (!rx_coal_tick[board_idx]) 1536 writel(DEF_JUMBO_RX_COAL, 1537 ®s->TuneRxCoalTicks); 1538 if (!max_rx_desc[board_idx]) 1539 writel(DEF_JUMBO_RX_MAX_DESC, 1540 ®s->TuneMaxRxDesc); 1541 if (!tx_ratio[board_idx]) 1542 writel(DEF_JUMBO_TX_RATIO, ®s->TxBufRat); 1543 } 1544 } 1545 } 1546 1547 1548 static void ace_watchdog(struct net_device *data) 1549 { 1550 struct net_device *dev = data; 1551 struct ace_private *ap = netdev_priv(dev); 1552 struct ace_regs __iomem *regs = ap->regs; 1553 1554 /* 1555 * We haven't received a stats update event for more than 2.5 1556 * seconds and there is data in the transmit queue, thus we 1557 * assume the card is stuck. 1558 */ 1559 if (*ap->tx_csm != ap->tx_ret_csm) { 1560 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n", 1561 dev->name, (unsigned int)readl(®s->HostCtrl)); 1562 /* This can happen due to ieee flow control. */ 1563 } else { 1564 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n", 1565 dev->name); 1566 #if 0 1567 netif_wake_queue(dev); 1568 #endif 1569 } 1570 } 1571 1572 1573 static void ace_tasklet(unsigned long arg) 1574 { 1575 struct net_device *dev = (struct net_device *) arg; 1576 struct ace_private *ap = netdev_priv(dev); 1577 int cur_size; 1578 1579 cur_size = atomic_read(&ap->cur_rx_bufs); 1580 if ((cur_size < RX_LOW_STD_THRES) && 1581 !test_and_set_bit(0, &ap->std_refill_busy)) { 1582 #ifdef DEBUG 1583 printk("refilling buffers (current %i)\n", cur_size); 1584 #endif 1585 ace_load_std_rx_ring(dev, RX_RING_SIZE - cur_size); 1586 } 1587 1588 if (ap->version >= 2) { 1589 cur_size = atomic_read(&ap->cur_mini_bufs); 1590 if ((cur_size < RX_LOW_MINI_THRES) && 1591 !test_and_set_bit(0, &ap->mini_refill_busy)) { 1592 #ifdef DEBUG 1593 printk("refilling mini buffers (current %i)\n", 1594 cur_size); 1595 #endif 1596 ace_load_mini_rx_ring(dev, RX_MINI_SIZE - cur_size); 1597 } 1598 } 1599 1600 cur_size = atomic_read(&ap->cur_jumbo_bufs); 1601 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) && 1602 !test_and_set_bit(0, &ap->jumbo_refill_busy)) { 1603 #ifdef DEBUG 1604 printk("refilling jumbo buffers (current %i)\n", cur_size); 1605 #endif 1606 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE - cur_size); 1607 } 1608 ap->tasklet_pending = 0; 1609 } 1610 1611 1612 /* 1613 * Copy the contents of the NIC's trace buffer to kernel memory. 1614 */ 1615 static void ace_dump_trace(struct ace_private *ap) 1616 { 1617 #if 0 1618 if (!ap->trace_buf) 1619 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL))) 1620 return; 1621 #endif 1622 } 1623 1624 1625 /* 1626 * Load the standard rx ring. 1627 * 1628 * Loading rings is safe without holding the spin lock since this is 1629 * done only before the device is enabled, thus no interrupts are 1630 * generated and by the interrupt handler/tasklet handler. 1631 */ 1632 static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs) 1633 { 1634 struct ace_private *ap = netdev_priv(dev); 1635 struct ace_regs __iomem *regs = ap->regs; 1636 short i, idx; 1637 1638 1639 prefetchw(&ap->cur_rx_bufs); 1640 1641 idx = ap->rx_std_skbprd; 1642 1643 for (i = 0; i < nr_bufs; i++) { 1644 struct sk_buff *skb; 1645 struct rx_desc *rd; 1646 dma_addr_t mapping; 1647 1648 skb = netdev_alloc_skb_ip_align(dev, ACE_STD_BUFSIZE); 1649 if (!skb) 1650 break; 1651 1652 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data), 1653 offset_in_page(skb->data), 1654 ACE_STD_BUFSIZE, 1655 PCI_DMA_FROMDEVICE); 1656 ap->skb->rx_std_skbuff[idx].skb = skb; 1657 dma_unmap_addr_set(&ap->skb->rx_std_skbuff[idx], 1658 mapping, mapping); 1659 1660 rd = &ap->rx_std_ring[idx]; 1661 set_aceaddr(&rd->addr, mapping); 1662 rd->size = ACE_STD_BUFSIZE; 1663 rd->idx = idx; 1664 idx = (idx + 1) % RX_STD_RING_ENTRIES; 1665 } 1666 1667 if (!i) 1668 goto error_out; 1669 1670 atomic_add(i, &ap->cur_rx_bufs); 1671 ap->rx_std_skbprd = idx; 1672 1673 if (ACE_IS_TIGON_I(ap)) { 1674 struct cmd cmd; 1675 cmd.evt = C_SET_RX_PRD_IDX; 1676 cmd.code = 0; 1677 cmd.idx = ap->rx_std_skbprd; 1678 ace_issue_cmd(regs, &cmd); 1679 } else { 1680 writel(idx, ®s->RxStdPrd); 1681 wmb(); 1682 } 1683 1684 out: 1685 clear_bit(0, &ap->std_refill_busy); 1686 return; 1687 1688 error_out: 1689 printk(KERN_INFO "Out of memory when allocating " 1690 "standard receive buffers\n"); 1691 goto out; 1692 } 1693 1694 1695 static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs) 1696 { 1697 struct ace_private *ap = netdev_priv(dev); 1698 struct ace_regs __iomem *regs = ap->regs; 1699 short i, idx; 1700 1701 prefetchw(&ap->cur_mini_bufs); 1702 1703 idx = ap->rx_mini_skbprd; 1704 for (i = 0; i < nr_bufs; i++) { 1705 struct sk_buff *skb; 1706 struct rx_desc *rd; 1707 dma_addr_t mapping; 1708 1709 skb = netdev_alloc_skb_ip_align(dev, ACE_MINI_BUFSIZE); 1710 if (!skb) 1711 break; 1712 1713 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data), 1714 offset_in_page(skb->data), 1715 ACE_MINI_BUFSIZE, 1716 PCI_DMA_FROMDEVICE); 1717 ap->skb->rx_mini_skbuff[idx].skb = skb; 1718 dma_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx], 1719 mapping, mapping); 1720 1721 rd = &ap->rx_mini_ring[idx]; 1722 set_aceaddr(&rd->addr, mapping); 1723 rd->size = ACE_MINI_BUFSIZE; 1724 rd->idx = idx; 1725 idx = (idx + 1) % RX_MINI_RING_ENTRIES; 1726 } 1727 1728 if (!i) 1729 goto error_out; 1730 1731 atomic_add(i, &ap->cur_mini_bufs); 1732 1733 ap->rx_mini_skbprd = idx; 1734 1735 writel(idx, ®s->RxMiniPrd); 1736 wmb(); 1737 1738 out: 1739 clear_bit(0, &ap->mini_refill_busy); 1740 return; 1741 error_out: 1742 printk(KERN_INFO "Out of memory when allocating " 1743 "mini receive buffers\n"); 1744 goto out; 1745 } 1746 1747 1748 /* 1749 * Load the jumbo rx ring, this may happen at any time if the MTU 1750 * is changed to a value > 1500. 1751 */ 1752 static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs) 1753 { 1754 struct ace_private *ap = netdev_priv(dev); 1755 struct ace_regs __iomem *regs = ap->regs; 1756 short i, idx; 1757 1758 idx = ap->rx_jumbo_skbprd; 1759 1760 for (i = 0; i < nr_bufs; i++) { 1761 struct sk_buff *skb; 1762 struct rx_desc *rd; 1763 dma_addr_t mapping; 1764 1765 skb = netdev_alloc_skb_ip_align(dev, ACE_JUMBO_BUFSIZE); 1766 if (!skb) 1767 break; 1768 1769 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data), 1770 offset_in_page(skb->data), 1771 ACE_JUMBO_BUFSIZE, 1772 PCI_DMA_FROMDEVICE); 1773 ap->skb->rx_jumbo_skbuff[idx].skb = skb; 1774 dma_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx], 1775 mapping, mapping); 1776 1777 rd = &ap->rx_jumbo_ring[idx]; 1778 set_aceaddr(&rd->addr, mapping); 1779 rd->size = ACE_JUMBO_BUFSIZE; 1780 rd->idx = idx; 1781 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES; 1782 } 1783 1784 if (!i) 1785 goto error_out; 1786 1787 atomic_add(i, &ap->cur_jumbo_bufs); 1788 ap->rx_jumbo_skbprd = idx; 1789 1790 if (ACE_IS_TIGON_I(ap)) { 1791 struct cmd cmd; 1792 cmd.evt = C_SET_RX_JUMBO_PRD_IDX; 1793 cmd.code = 0; 1794 cmd.idx = ap->rx_jumbo_skbprd; 1795 ace_issue_cmd(regs, &cmd); 1796 } else { 1797 writel(idx, ®s->RxJumboPrd); 1798 wmb(); 1799 } 1800 1801 out: 1802 clear_bit(0, &ap->jumbo_refill_busy); 1803 return; 1804 error_out: 1805 if (net_ratelimit()) 1806 printk(KERN_INFO "Out of memory when allocating " 1807 "jumbo receive buffers\n"); 1808 goto out; 1809 } 1810 1811 1812 /* 1813 * All events are considered to be slow (RX/TX ints do not generate 1814 * events) and are handled here, outside the main interrupt handler, 1815 * to reduce the size of the handler. 1816 */ 1817 static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd) 1818 { 1819 struct ace_private *ap; 1820 1821 ap = netdev_priv(dev); 1822 1823 while (evtcsm != evtprd) { 1824 switch (ap->evt_ring[evtcsm].evt) { 1825 case E_FW_RUNNING: 1826 printk(KERN_INFO "%s: Firmware up and running\n", 1827 ap->name); 1828 ap->fw_running = 1; 1829 wmb(); 1830 break; 1831 case E_STATS_UPDATED: 1832 break; 1833 case E_LNK_STATE: 1834 { 1835 u16 code = ap->evt_ring[evtcsm].code; 1836 switch (code) { 1837 case E_C_LINK_UP: 1838 { 1839 u32 state = readl(&ap->regs->GigLnkState); 1840 printk(KERN_WARNING "%s: Optical link UP " 1841 "(%s Duplex, Flow Control: %s%s)\n", 1842 ap->name, 1843 state & LNK_FULL_DUPLEX ? "Full":"Half", 1844 state & LNK_TX_FLOW_CTL_Y ? "TX " : "", 1845 state & LNK_RX_FLOW_CTL_Y ? "RX" : ""); 1846 break; 1847 } 1848 case E_C_LINK_DOWN: 1849 printk(KERN_WARNING "%s: Optical link DOWN\n", 1850 ap->name); 1851 break; 1852 case E_C_LINK_10_100: 1853 printk(KERN_WARNING "%s: 10/100BaseT link " 1854 "UP\n", ap->name); 1855 break; 1856 default: 1857 printk(KERN_ERR "%s: Unknown optical link " 1858 "state %02x\n", ap->name, code); 1859 } 1860 break; 1861 } 1862 case E_ERROR: 1863 switch(ap->evt_ring[evtcsm].code) { 1864 case E_C_ERR_INVAL_CMD: 1865 printk(KERN_ERR "%s: invalid command error\n", 1866 ap->name); 1867 break; 1868 case E_C_ERR_UNIMP_CMD: 1869 printk(KERN_ERR "%s: unimplemented command " 1870 "error\n", ap->name); 1871 break; 1872 case E_C_ERR_BAD_CFG: 1873 printk(KERN_ERR "%s: bad config error\n", 1874 ap->name); 1875 break; 1876 default: 1877 printk(KERN_ERR "%s: unknown error %02x\n", 1878 ap->name, ap->evt_ring[evtcsm].code); 1879 } 1880 break; 1881 case E_RESET_JUMBO_RNG: 1882 { 1883 int i; 1884 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) { 1885 if (ap->skb->rx_jumbo_skbuff[i].skb) { 1886 ap->rx_jumbo_ring[i].size = 0; 1887 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0); 1888 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb); 1889 ap->skb->rx_jumbo_skbuff[i].skb = NULL; 1890 } 1891 } 1892 1893 if (ACE_IS_TIGON_I(ap)) { 1894 struct cmd cmd; 1895 cmd.evt = C_SET_RX_JUMBO_PRD_IDX; 1896 cmd.code = 0; 1897 cmd.idx = 0; 1898 ace_issue_cmd(ap->regs, &cmd); 1899 } else { 1900 writel(0, &((ap->regs)->RxJumboPrd)); 1901 wmb(); 1902 } 1903 1904 ap->jumbo = 0; 1905 ap->rx_jumbo_skbprd = 0; 1906 printk(KERN_INFO "%s: Jumbo ring flushed\n", 1907 ap->name); 1908 clear_bit(0, &ap->jumbo_refill_busy); 1909 break; 1910 } 1911 default: 1912 printk(KERN_ERR "%s: Unhandled event 0x%02x\n", 1913 ap->name, ap->evt_ring[evtcsm].evt); 1914 } 1915 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES; 1916 } 1917 1918 return evtcsm; 1919 } 1920 1921 1922 static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm) 1923 { 1924 struct ace_private *ap = netdev_priv(dev); 1925 u32 idx; 1926 int mini_count = 0, std_count = 0; 1927 1928 idx = rxretcsm; 1929 1930 prefetchw(&ap->cur_rx_bufs); 1931 prefetchw(&ap->cur_mini_bufs); 1932 1933 while (idx != rxretprd) { 1934 struct ring_info *rip; 1935 struct sk_buff *skb; 1936 struct rx_desc *retdesc; 1937 u32 skbidx; 1938 int bd_flags, desc_type, mapsize; 1939 u16 csum; 1940 1941 1942 /* make sure the rx descriptor isn't read before rxretprd */ 1943 if (idx == rxretcsm) 1944 rmb(); 1945 1946 retdesc = &ap->rx_return_ring[idx]; 1947 skbidx = retdesc->idx; 1948 bd_flags = retdesc->flags; 1949 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI); 1950 1951 switch(desc_type) { 1952 /* 1953 * Normal frames do not have any flags set 1954 * 1955 * Mini and normal frames arrive frequently, 1956 * so use a local counter to avoid doing 1957 * atomic operations for each packet arriving. 1958 */ 1959 case 0: 1960 rip = &ap->skb->rx_std_skbuff[skbidx]; 1961 mapsize = ACE_STD_BUFSIZE; 1962 std_count++; 1963 break; 1964 case BD_FLG_JUMBO: 1965 rip = &ap->skb->rx_jumbo_skbuff[skbidx]; 1966 mapsize = ACE_JUMBO_BUFSIZE; 1967 atomic_dec(&ap->cur_jumbo_bufs); 1968 break; 1969 case BD_FLG_MINI: 1970 rip = &ap->skb->rx_mini_skbuff[skbidx]; 1971 mapsize = ACE_MINI_BUFSIZE; 1972 mini_count++; 1973 break; 1974 default: 1975 printk(KERN_INFO "%s: unknown frame type (0x%02x) " 1976 "returned by NIC\n", dev->name, 1977 retdesc->flags); 1978 goto error; 1979 } 1980 1981 skb = rip->skb; 1982 rip->skb = NULL; 1983 pci_unmap_page(ap->pdev, 1984 dma_unmap_addr(rip, mapping), 1985 mapsize, 1986 PCI_DMA_FROMDEVICE); 1987 skb_put(skb, retdesc->size); 1988 1989 /* 1990 * Fly baby, fly! 1991 */ 1992 csum = retdesc->tcp_udp_csum; 1993 1994 skb->protocol = eth_type_trans(skb, dev); 1995 1996 /* 1997 * Instead of forcing the poor tigon mips cpu to calculate 1998 * pseudo hdr checksum, we do this ourselves. 1999 */ 2000 if (bd_flags & BD_FLG_TCP_UDP_SUM) { 2001 skb->csum = htons(csum); 2002 skb->ip_summed = CHECKSUM_COMPLETE; 2003 } else { 2004 skb_checksum_none_assert(skb); 2005 } 2006 2007 /* send it up */ 2008 if ((bd_flags & BD_FLG_VLAN_TAG)) 2009 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), retdesc->vlan); 2010 netif_rx(skb); 2011 2012 dev->stats.rx_packets++; 2013 dev->stats.rx_bytes += retdesc->size; 2014 2015 idx = (idx + 1) % RX_RETURN_RING_ENTRIES; 2016 } 2017 2018 atomic_sub(std_count, &ap->cur_rx_bufs); 2019 if (!ACE_IS_TIGON_I(ap)) 2020 atomic_sub(mini_count, &ap->cur_mini_bufs); 2021 2022 out: 2023 /* 2024 * According to the documentation RxRetCsm is obsolete with 2025 * the 12.3.x Firmware - my Tigon I NICs seem to disagree! 2026 */ 2027 if (ACE_IS_TIGON_I(ap)) { 2028 writel(idx, &ap->regs->RxRetCsm); 2029 } 2030 ap->cur_rx = idx; 2031 2032 return; 2033 error: 2034 idx = rxretprd; 2035 goto out; 2036 } 2037 2038 2039 static inline void ace_tx_int(struct net_device *dev, 2040 u32 txcsm, u32 idx) 2041 { 2042 struct ace_private *ap = netdev_priv(dev); 2043 2044 do { 2045 struct sk_buff *skb; 2046 struct tx_ring_info *info; 2047 2048 info = ap->skb->tx_skbuff + idx; 2049 skb = info->skb; 2050 2051 if (dma_unmap_len(info, maplen)) { 2052 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping), 2053 dma_unmap_len(info, maplen), 2054 PCI_DMA_TODEVICE); 2055 dma_unmap_len_set(info, maplen, 0); 2056 } 2057 2058 if (skb) { 2059 dev->stats.tx_packets++; 2060 dev->stats.tx_bytes += skb->len; 2061 dev_kfree_skb_irq(skb); 2062 info->skb = NULL; 2063 } 2064 2065 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap); 2066 } while (idx != txcsm); 2067 2068 if (netif_queue_stopped(dev)) 2069 netif_wake_queue(dev); 2070 2071 wmb(); 2072 ap->tx_ret_csm = txcsm; 2073 2074 /* So... tx_ret_csm is advanced _after_ check for device wakeup. 2075 * 2076 * We could try to make it before. In this case we would get 2077 * the following race condition: hard_start_xmit on other cpu 2078 * enters after we advanced tx_ret_csm and fills space, 2079 * which we have just freed, so that we make illegal device wakeup. 2080 * There is no good way to workaround this (at entry 2081 * to ace_start_xmit detects this condition and prevents 2082 * ring corruption, but it is not a good workaround.) 2083 * 2084 * When tx_ret_csm is advanced after, we wake up device _only_ 2085 * if we really have some space in ring (though the core doing 2086 * hard_start_xmit can see full ring for some period and has to 2087 * synchronize.) Superb. 2088 * BUT! We get another subtle race condition. hard_start_xmit 2089 * may think that ring is full between wakeup and advancing 2090 * tx_ret_csm and will stop device instantly! It is not so bad. 2091 * We are guaranteed that there is something in ring, so that 2092 * the next irq will resume transmission. To speedup this we could 2093 * mark descriptor, which closes ring with BD_FLG_COAL_NOW 2094 * (see ace_start_xmit). 2095 * 2096 * Well, this dilemma exists in all lock-free devices. 2097 * We, following scheme used in drivers by Donald Becker, 2098 * select the least dangerous. 2099 * --ANK 2100 */ 2101 } 2102 2103 2104 static irqreturn_t ace_interrupt(int irq, void *dev_id) 2105 { 2106 struct net_device *dev = (struct net_device *)dev_id; 2107 struct ace_private *ap = netdev_priv(dev); 2108 struct ace_regs __iomem *regs = ap->regs; 2109 u32 idx; 2110 u32 txcsm, rxretcsm, rxretprd; 2111 u32 evtcsm, evtprd; 2112 2113 /* 2114 * In case of PCI shared interrupts or spurious interrupts, 2115 * we want to make sure it is actually our interrupt before 2116 * spending any time in here. 2117 */ 2118 if (!(readl(®s->HostCtrl) & IN_INT)) 2119 return IRQ_NONE; 2120 2121 /* 2122 * ACK intr now. Otherwise we will lose updates to rx_ret_prd, 2123 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before 2124 * writel(0, ®s->Mb0Lo). 2125 * 2126 * "IRQ avoidance" recommended in docs applies to IRQs served 2127 * threads and it is wrong even for that case. 2128 */ 2129 writel(0, ®s->Mb0Lo); 2130 readl(®s->Mb0Lo); 2131 2132 /* 2133 * There is no conflict between transmit handling in 2134 * start_xmit and receive processing, thus there is no reason 2135 * to take a spin lock for RX handling. Wait until we start 2136 * working on the other stuff - hey we don't need a spin lock 2137 * anymore. 2138 */ 2139 rxretprd = *ap->rx_ret_prd; 2140 rxretcsm = ap->cur_rx; 2141 2142 if (rxretprd != rxretcsm) 2143 ace_rx_int(dev, rxretprd, rxretcsm); 2144 2145 txcsm = *ap->tx_csm; 2146 idx = ap->tx_ret_csm; 2147 2148 if (txcsm != idx) { 2149 /* 2150 * If each skb takes only one descriptor this check degenerates 2151 * to identity, because new space has just been opened. 2152 * But if skbs are fragmented we must check that this index 2153 * update releases enough of space, otherwise we just 2154 * wait for device to make more work. 2155 */ 2156 if (!tx_ring_full(ap, txcsm, ap->tx_prd)) 2157 ace_tx_int(dev, txcsm, idx); 2158 } 2159 2160 evtcsm = readl(®s->EvtCsm); 2161 evtprd = *ap->evt_prd; 2162 2163 if (evtcsm != evtprd) { 2164 evtcsm = ace_handle_event(dev, evtcsm, evtprd); 2165 writel(evtcsm, ®s->EvtCsm); 2166 } 2167 2168 /* 2169 * This has to go last in the interrupt handler and run with 2170 * the spin lock released ... what lock? 2171 */ 2172 if (netif_running(dev)) { 2173 int cur_size; 2174 int run_tasklet = 0; 2175 2176 cur_size = atomic_read(&ap->cur_rx_bufs); 2177 if (cur_size < RX_LOW_STD_THRES) { 2178 if ((cur_size < RX_PANIC_STD_THRES) && 2179 !test_and_set_bit(0, &ap->std_refill_busy)) { 2180 #ifdef DEBUG 2181 printk("low on std buffers %i\n", cur_size); 2182 #endif 2183 ace_load_std_rx_ring(dev, 2184 RX_RING_SIZE - cur_size); 2185 } else 2186 run_tasklet = 1; 2187 } 2188 2189 if (!ACE_IS_TIGON_I(ap)) { 2190 cur_size = atomic_read(&ap->cur_mini_bufs); 2191 if (cur_size < RX_LOW_MINI_THRES) { 2192 if ((cur_size < RX_PANIC_MINI_THRES) && 2193 !test_and_set_bit(0, 2194 &ap->mini_refill_busy)) { 2195 #ifdef DEBUG 2196 printk("low on mini buffers %i\n", 2197 cur_size); 2198 #endif 2199 ace_load_mini_rx_ring(dev, 2200 RX_MINI_SIZE - cur_size); 2201 } else 2202 run_tasklet = 1; 2203 } 2204 } 2205 2206 if (ap->jumbo) { 2207 cur_size = atomic_read(&ap->cur_jumbo_bufs); 2208 if (cur_size < RX_LOW_JUMBO_THRES) { 2209 if ((cur_size < RX_PANIC_JUMBO_THRES) && 2210 !test_and_set_bit(0, 2211 &ap->jumbo_refill_busy)){ 2212 #ifdef DEBUG 2213 printk("low on jumbo buffers %i\n", 2214 cur_size); 2215 #endif 2216 ace_load_jumbo_rx_ring(dev, 2217 RX_JUMBO_SIZE - cur_size); 2218 } else 2219 run_tasklet = 1; 2220 } 2221 } 2222 if (run_tasklet && !ap->tasklet_pending) { 2223 ap->tasklet_pending = 1; 2224 tasklet_schedule(&ap->ace_tasklet); 2225 } 2226 } 2227 2228 return IRQ_HANDLED; 2229 } 2230 2231 static int ace_open(struct net_device *dev) 2232 { 2233 struct ace_private *ap = netdev_priv(dev); 2234 struct ace_regs __iomem *regs = ap->regs; 2235 struct cmd cmd; 2236 2237 if (!(ap->fw_running)) { 2238 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name); 2239 return -EBUSY; 2240 } 2241 2242 writel(dev->mtu + ETH_HLEN + 4, ®s->IfMtu); 2243 2244 cmd.evt = C_CLEAR_STATS; 2245 cmd.code = 0; 2246 cmd.idx = 0; 2247 ace_issue_cmd(regs, &cmd); 2248 2249 cmd.evt = C_HOST_STATE; 2250 cmd.code = C_C_STACK_UP; 2251 cmd.idx = 0; 2252 ace_issue_cmd(regs, &cmd); 2253 2254 if (ap->jumbo && 2255 !test_and_set_bit(0, &ap->jumbo_refill_busy)) 2256 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE); 2257 2258 if (dev->flags & IFF_PROMISC) { 2259 cmd.evt = C_SET_PROMISC_MODE; 2260 cmd.code = C_C_PROMISC_ENABLE; 2261 cmd.idx = 0; 2262 ace_issue_cmd(regs, &cmd); 2263 2264 ap->promisc = 1; 2265 }else 2266 ap->promisc = 0; 2267 ap->mcast_all = 0; 2268 2269 #if 0 2270 cmd.evt = C_LNK_NEGOTIATION; 2271 cmd.code = 0; 2272 cmd.idx = 0; 2273 ace_issue_cmd(regs, &cmd); 2274 #endif 2275 2276 netif_start_queue(dev); 2277 2278 /* 2279 * Setup the bottom half rx ring refill handler 2280 */ 2281 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev); 2282 return 0; 2283 } 2284 2285 2286 static int ace_close(struct net_device *dev) 2287 { 2288 struct ace_private *ap = netdev_priv(dev); 2289 struct ace_regs __iomem *regs = ap->regs; 2290 struct cmd cmd; 2291 unsigned long flags; 2292 short i; 2293 2294 /* 2295 * Without (or before) releasing irq and stopping hardware, this 2296 * is an absolute non-sense, by the way. It will be reset instantly 2297 * by the first irq. 2298 */ 2299 netif_stop_queue(dev); 2300 2301 2302 if (ap->promisc) { 2303 cmd.evt = C_SET_PROMISC_MODE; 2304 cmd.code = C_C_PROMISC_DISABLE; 2305 cmd.idx = 0; 2306 ace_issue_cmd(regs, &cmd); 2307 ap->promisc = 0; 2308 } 2309 2310 cmd.evt = C_HOST_STATE; 2311 cmd.code = C_C_STACK_DOWN; 2312 cmd.idx = 0; 2313 ace_issue_cmd(regs, &cmd); 2314 2315 tasklet_kill(&ap->ace_tasklet); 2316 2317 /* 2318 * Make sure one CPU is not processing packets while 2319 * buffers are being released by another. 2320 */ 2321 2322 local_irq_save(flags); 2323 ace_mask_irq(dev); 2324 2325 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) { 2326 struct sk_buff *skb; 2327 struct tx_ring_info *info; 2328 2329 info = ap->skb->tx_skbuff + i; 2330 skb = info->skb; 2331 2332 if (dma_unmap_len(info, maplen)) { 2333 if (ACE_IS_TIGON_I(ap)) { 2334 /* NB: TIGON_1 is special, tx_ring is in io space */ 2335 struct tx_desc __iomem *tx; 2336 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i]; 2337 writel(0, &tx->addr.addrhi); 2338 writel(0, &tx->addr.addrlo); 2339 writel(0, &tx->flagsize); 2340 } else 2341 memset(ap->tx_ring + i, 0, 2342 sizeof(struct tx_desc)); 2343 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping), 2344 dma_unmap_len(info, maplen), 2345 PCI_DMA_TODEVICE); 2346 dma_unmap_len_set(info, maplen, 0); 2347 } 2348 if (skb) { 2349 dev_kfree_skb(skb); 2350 info->skb = NULL; 2351 } 2352 } 2353 2354 if (ap->jumbo) { 2355 cmd.evt = C_RESET_JUMBO_RNG; 2356 cmd.code = 0; 2357 cmd.idx = 0; 2358 ace_issue_cmd(regs, &cmd); 2359 } 2360 2361 ace_unmask_irq(dev); 2362 local_irq_restore(flags); 2363 2364 return 0; 2365 } 2366 2367 2368 static inline dma_addr_t 2369 ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb, 2370 struct sk_buff *tail, u32 idx) 2371 { 2372 dma_addr_t mapping; 2373 struct tx_ring_info *info; 2374 2375 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data), 2376 offset_in_page(skb->data), 2377 skb->len, PCI_DMA_TODEVICE); 2378 2379 info = ap->skb->tx_skbuff + idx; 2380 info->skb = tail; 2381 dma_unmap_addr_set(info, mapping, mapping); 2382 dma_unmap_len_set(info, maplen, skb->len); 2383 return mapping; 2384 } 2385 2386 2387 static inline void 2388 ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr, 2389 u32 flagsize, u32 vlan_tag) 2390 { 2391 #if !USE_TX_COAL_NOW 2392 flagsize &= ~BD_FLG_COAL_NOW; 2393 #endif 2394 2395 if (ACE_IS_TIGON_I(ap)) { 2396 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc; 2397 writel(addr >> 32, &io->addr.addrhi); 2398 writel(addr & 0xffffffff, &io->addr.addrlo); 2399 writel(flagsize, &io->flagsize); 2400 writel(vlan_tag, &io->vlanres); 2401 } else { 2402 desc->addr.addrhi = addr >> 32; 2403 desc->addr.addrlo = addr; 2404 desc->flagsize = flagsize; 2405 desc->vlanres = vlan_tag; 2406 } 2407 } 2408 2409 2410 static netdev_tx_t ace_start_xmit(struct sk_buff *skb, 2411 struct net_device *dev) 2412 { 2413 struct ace_private *ap = netdev_priv(dev); 2414 struct ace_regs __iomem *regs = ap->regs; 2415 struct tx_desc *desc; 2416 u32 idx, flagsize; 2417 unsigned long maxjiff = jiffies + 3*HZ; 2418 2419 restart: 2420 idx = ap->tx_prd; 2421 2422 if (tx_ring_full(ap, ap->tx_ret_csm, idx)) 2423 goto overflow; 2424 2425 if (!skb_shinfo(skb)->nr_frags) { 2426 dma_addr_t mapping; 2427 u32 vlan_tag = 0; 2428 2429 mapping = ace_map_tx_skb(ap, skb, skb, idx); 2430 flagsize = (skb->len << 16) | (BD_FLG_END); 2431 if (skb->ip_summed == CHECKSUM_PARTIAL) 2432 flagsize |= BD_FLG_TCP_UDP_SUM; 2433 if (skb_vlan_tag_present(skb)) { 2434 flagsize |= BD_FLG_VLAN_TAG; 2435 vlan_tag = skb_vlan_tag_get(skb); 2436 } 2437 desc = ap->tx_ring + idx; 2438 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap); 2439 2440 /* Look at ace_tx_int for explanations. */ 2441 if (tx_ring_full(ap, ap->tx_ret_csm, idx)) 2442 flagsize |= BD_FLG_COAL_NOW; 2443 2444 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag); 2445 } else { 2446 dma_addr_t mapping; 2447 u32 vlan_tag = 0; 2448 int i, len = 0; 2449 2450 mapping = ace_map_tx_skb(ap, skb, NULL, idx); 2451 flagsize = (skb_headlen(skb) << 16); 2452 if (skb->ip_summed == CHECKSUM_PARTIAL) 2453 flagsize |= BD_FLG_TCP_UDP_SUM; 2454 if (skb_vlan_tag_present(skb)) { 2455 flagsize |= BD_FLG_VLAN_TAG; 2456 vlan_tag = skb_vlan_tag_get(skb); 2457 } 2458 2459 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag); 2460 2461 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap); 2462 2463 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2464 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2465 struct tx_ring_info *info; 2466 2467 len += skb_frag_size(frag); 2468 info = ap->skb->tx_skbuff + idx; 2469 desc = ap->tx_ring + idx; 2470 2471 mapping = skb_frag_dma_map(&ap->pdev->dev, frag, 0, 2472 skb_frag_size(frag), 2473 DMA_TO_DEVICE); 2474 2475 flagsize = skb_frag_size(frag) << 16; 2476 if (skb->ip_summed == CHECKSUM_PARTIAL) 2477 flagsize |= BD_FLG_TCP_UDP_SUM; 2478 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap); 2479 2480 if (i == skb_shinfo(skb)->nr_frags - 1) { 2481 flagsize |= BD_FLG_END; 2482 if (tx_ring_full(ap, ap->tx_ret_csm, idx)) 2483 flagsize |= BD_FLG_COAL_NOW; 2484 2485 /* 2486 * Only the last fragment frees 2487 * the skb! 2488 */ 2489 info->skb = skb; 2490 } else { 2491 info->skb = NULL; 2492 } 2493 dma_unmap_addr_set(info, mapping, mapping); 2494 dma_unmap_len_set(info, maplen, skb_frag_size(frag)); 2495 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag); 2496 } 2497 } 2498 2499 wmb(); 2500 ap->tx_prd = idx; 2501 ace_set_txprd(regs, ap, idx); 2502 2503 if (flagsize & BD_FLG_COAL_NOW) { 2504 netif_stop_queue(dev); 2505 2506 /* 2507 * A TX-descriptor producer (an IRQ) might have gotten 2508 * between, making the ring free again. Since xmit is 2509 * serialized, this is the only situation we have to 2510 * re-test. 2511 */ 2512 if (!tx_ring_full(ap, ap->tx_ret_csm, idx)) 2513 netif_wake_queue(dev); 2514 } 2515 2516 return NETDEV_TX_OK; 2517 2518 overflow: 2519 /* 2520 * This race condition is unavoidable with lock-free drivers. 2521 * We wake up the queue _before_ tx_prd is advanced, so that we can 2522 * enter hard_start_xmit too early, while tx ring still looks closed. 2523 * This happens ~1-4 times per 100000 packets, so that we can allow 2524 * to loop syncing to other CPU. Probably, we need an additional 2525 * wmb() in ace_tx_intr as well. 2526 * 2527 * Note that this race is relieved by reserving one more entry 2528 * in tx ring than it is necessary (see original non-SG driver). 2529 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which 2530 * is already overkill. 2531 * 2532 * Alternative is to return with 1 not throttling queue. In this 2533 * case loop becomes longer, no more useful effects. 2534 */ 2535 if (time_before(jiffies, maxjiff)) { 2536 barrier(); 2537 cpu_relax(); 2538 goto restart; 2539 } 2540 2541 /* The ring is stuck full. */ 2542 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name); 2543 return NETDEV_TX_BUSY; 2544 } 2545 2546 2547 static int ace_change_mtu(struct net_device *dev, int new_mtu) 2548 { 2549 struct ace_private *ap = netdev_priv(dev); 2550 struct ace_regs __iomem *regs = ap->regs; 2551 2552 writel(new_mtu + ETH_HLEN + 4, ®s->IfMtu); 2553 dev->mtu = new_mtu; 2554 2555 if (new_mtu > ACE_STD_MTU) { 2556 if (!(ap->jumbo)) { 2557 printk(KERN_INFO "%s: Enabling Jumbo frame " 2558 "support\n", dev->name); 2559 ap->jumbo = 1; 2560 if (!test_and_set_bit(0, &ap->jumbo_refill_busy)) 2561 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE); 2562 ace_set_rxtx_parms(dev, 1); 2563 } 2564 } else { 2565 while (test_and_set_bit(0, &ap->jumbo_refill_busy)); 2566 ace_sync_irq(dev->irq); 2567 ace_set_rxtx_parms(dev, 0); 2568 if (ap->jumbo) { 2569 struct cmd cmd; 2570 2571 cmd.evt = C_RESET_JUMBO_RNG; 2572 cmd.code = 0; 2573 cmd.idx = 0; 2574 ace_issue_cmd(regs, &cmd); 2575 } 2576 } 2577 2578 return 0; 2579 } 2580 2581 static int ace_get_link_ksettings(struct net_device *dev, 2582 struct ethtool_link_ksettings *cmd) 2583 { 2584 struct ace_private *ap = netdev_priv(dev); 2585 struct ace_regs __iomem *regs = ap->regs; 2586 u32 link; 2587 u32 supported; 2588 2589 memset(cmd, 0, sizeof(struct ethtool_link_ksettings)); 2590 2591 supported = (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | 2592 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | 2593 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | 2594 SUPPORTED_Autoneg | SUPPORTED_FIBRE); 2595 2596 cmd->base.port = PORT_FIBRE; 2597 2598 link = readl(®s->GigLnkState); 2599 if (link & LNK_1000MB) { 2600 cmd->base.speed = SPEED_1000; 2601 } else { 2602 link = readl(®s->FastLnkState); 2603 if (link & LNK_100MB) 2604 cmd->base.speed = SPEED_100; 2605 else if (link & LNK_10MB) 2606 cmd->base.speed = SPEED_10; 2607 else 2608 cmd->base.speed = 0; 2609 } 2610 if (link & LNK_FULL_DUPLEX) 2611 cmd->base.duplex = DUPLEX_FULL; 2612 else 2613 cmd->base.duplex = DUPLEX_HALF; 2614 2615 if (link & LNK_NEGOTIATE) 2616 cmd->base.autoneg = AUTONEG_ENABLE; 2617 else 2618 cmd->base.autoneg = AUTONEG_DISABLE; 2619 2620 #if 0 2621 /* 2622 * Current struct ethtool_cmd is insufficient 2623 */ 2624 ecmd->trace = readl(®s->TuneTrace); 2625 2626 ecmd->txcoal = readl(®s->TuneTxCoalTicks); 2627 ecmd->rxcoal = readl(®s->TuneRxCoalTicks); 2628 #endif 2629 2630 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 2631 supported); 2632 2633 return 0; 2634 } 2635 2636 static int ace_set_link_ksettings(struct net_device *dev, 2637 const struct ethtool_link_ksettings *cmd) 2638 { 2639 struct ace_private *ap = netdev_priv(dev); 2640 struct ace_regs __iomem *regs = ap->regs; 2641 u32 link, speed; 2642 2643 link = readl(®s->GigLnkState); 2644 if (link & LNK_1000MB) 2645 speed = SPEED_1000; 2646 else { 2647 link = readl(®s->FastLnkState); 2648 if (link & LNK_100MB) 2649 speed = SPEED_100; 2650 else if (link & LNK_10MB) 2651 speed = SPEED_10; 2652 else 2653 speed = SPEED_100; 2654 } 2655 2656 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB | 2657 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL; 2658 if (!ACE_IS_TIGON_I(ap)) 2659 link |= LNK_TX_FLOW_CTL_Y; 2660 if (cmd->base.autoneg == AUTONEG_ENABLE) 2661 link |= LNK_NEGOTIATE; 2662 if (cmd->base.speed != speed) { 2663 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB); 2664 switch (cmd->base.speed) { 2665 case SPEED_1000: 2666 link |= LNK_1000MB; 2667 break; 2668 case SPEED_100: 2669 link |= LNK_100MB; 2670 break; 2671 case SPEED_10: 2672 link |= LNK_10MB; 2673 break; 2674 } 2675 } 2676 2677 if (cmd->base.duplex == DUPLEX_FULL) 2678 link |= LNK_FULL_DUPLEX; 2679 2680 if (link != ap->link) { 2681 struct cmd cmd; 2682 printk(KERN_INFO "%s: Renegotiating link state\n", 2683 dev->name); 2684 2685 ap->link = link; 2686 writel(link, ®s->TuneLink); 2687 if (!ACE_IS_TIGON_I(ap)) 2688 writel(link, ®s->TuneFastLink); 2689 wmb(); 2690 2691 cmd.evt = C_LNK_NEGOTIATION; 2692 cmd.code = 0; 2693 cmd.idx = 0; 2694 ace_issue_cmd(regs, &cmd); 2695 } 2696 return 0; 2697 } 2698 2699 static void ace_get_drvinfo(struct net_device *dev, 2700 struct ethtool_drvinfo *info) 2701 { 2702 struct ace_private *ap = netdev_priv(dev); 2703 2704 strlcpy(info->driver, "acenic", sizeof(info->driver)); 2705 snprintf(info->version, sizeof(info->version), "%i.%i.%i", 2706 ap->firmware_major, ap->firmware_minor, 2707 ap->firmware_fix); 2708 2709 if (ap->pdev) 2710 strlcpy(info->bus_info, pci_name(ap->pdev), 2711 sizeof(info->bus_info)); 2712 2713 } 2714 2715 /* 2716 * Set the hardware MAC address. 2717 */ 2718 static int ace_set_mac_addr(struct net_device *dev, void *p) 2719 { 2720 struct ace_private *ap = netdev_priv(dev); 2721 struct ace_regs __iomem *regs = ap->regs; 2722 struct sockaddr *addr=p; 2723 u8 *da; 2724 struct cmd cmd; 2725 2726 if(netif_running(dev)) 2727 return -EBUSY; 2728 2729 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len); 2730 2731 da = (u8 *)dev->dev_addr; 2732 2733 writel(da[0] << 8 | da[1], ®s->MacAddrHi); 2734 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5], 2735 ®s->MacAddrLo); 2736 2737 cmd.evt = C_SET_MAC_ADDR; 2738 cmd.code = 0; 2739 cmd.idx = 0; 2740 ace_issue_cmd(regs, &cmd); 2741 2742 return 0; 2743 } 2744 2745 2746 static void ace_set_multicast_list(struct net_device *dev) 2747 { 2748 struct ace_private *ap = netdev_priv(dev); 2749 struct ace_regs __iomem *regs = ap->regs; 2750 struct cmd cmd; 2751 2752 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) { 2753 cmd.evt = C_SET_MULTICAST_MODE; 2754 cmd.code = C_C_MCAST_ENABLE; 2755 cmd.idx = 0; 2756 ace_issue_cmd(regs, &cmd); 2757 ap->mcast_all = 1; 2758 } else if (ap->mcast_all) { 2759 cmd.evt = C_SET_MULTICAST_MODE; 2760 cmd.code = C_C_MCAST_DISABLE; 2761 cmd.idx = 0; 2762 ace_issue_cmd(regs, &cmd); 2763 ap->mcast_all = 0; 2764 } 2765 2766 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) { 2767 cmd.evt = C_SET_PROMISC_MODE; 2768 cmd.code = C_C_PROMISC_ENABLE; 2769 cmd.idx = 0; 2770 ace_issue_cmd(regs, &cmd); 2771 ap->promisc = 1; 2772 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) { 2773 cmd.evt = C_SET_PROMISC_MODE; 2774 cmd.code = C_C_PROMISC_DISABLE; 2775 cmd.idx = 0; 2776 ace_issue_cmd(regs, &cmd); 2777 ap->promisc = 0; 2778 } 2779 2780 /* 2781 * For the time being multicast relies on the upper layers 2782 * filtering it properly. The Firmware does not allow one to 2783 * set the entire multicast list at a time and keeping track of 2784 * it here is going to be messy. 2785 */ 2786 if (!netdev_mc_empty(dev) && !ap->mcast_all) { 2787 cmd.evt = C_SET_MULTICAST_MODE; 2788 cmd.code = C_C_MCAST_ENABLE; 2789 cmd.idx = 0; 2790 ace_issue_cmd(regs, &cmd); 2791 }else if (!ap->mcast_all) { 2792 cmd.evt = C_SET_MULTICAST_MODE; 2793 cmd.code = C_C_MCAST_DISABLE; 2794 cmd.idx = 0; 2795 ace_issue_cmd(regs, &cmd); 2796 } 2797 } 2798 2799 2800 static struct net_device_stats *ace_get_stats(struct net_device *dev) 2801 { 2802 struct ace_private *ap = netdev_priv(dev); 2803 struct ace_mac_stats __iomem *mac_stats = 2804 (struct ace_mac_stats __iomem *)ap->regs->Stats; 2805 2806 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space); 2807 dev->stats.multicast = readl(&mac_stats->kept_mc); 2808 dev->stats.collisions = readl(&mac_stats->coll); 2809 2810 return &dev->stats; 2811 } 2812 2813 2814 static void ace_copy(struct ace_regs __iomem *regs, const __be32 *src, 2815 u32 dest, int size) 2816 { 2817 void __iomem *tdest; 2818 short tsize, i; 2819 2820 if (size <= 0) 2821 return; 2822 2823 while (size > 0) { 2824 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1), 2825 min_t(u32, size, ACE_WINDOW_SIZE)); 2826 tdest = (void __iomem *) ®s->Window + 2827 (dest & (ACE_WINDOW_SIZE - 1)); 2828 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase); 2829 for (i = 0; i < (tsize / 4); i++) { 2830 /* Firmware is big-endian */ 2831 writel(be32_to_cpup(src), tdest); 2832 src++; 2833 tdest += 4; 2834 dest += 4; 2835 size -= 4; 2836 } 2837 } 2838 } 2839 2840 2841 static void ace_clear(struct ace_regs __iomem *regs, u32 dest, int size) 2842 { 2843 void __iomem *tdest; 2844 short tsize = 0, i; 2845 2846 if (size <= 0) 2847 return; 2848 2849 while (size > 0) { 2850 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1), 2851 min_t(u32, size, ACE_WINDOW_SIZE)); 2852 tdest = (void __iomem *) ®s->Window + 2853 (dest & (ACE_WINDOW_SIZE - 1)); 2854 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase); 2855 2856 for (i = 0; i < (tsize / 4); i++) { 2857 writel(0, tdest + i*4); 2858 } 2859 2860 dest += tsize; 2861 size -= tsize; 2862 } 2863 } 2864 2865 2866 /* 2867 * Download the firmware into the SRAM on the NIC 2868 * 2869 * This operation requires the NIC to be halted and is performed with 2870 * interrupts disabled and with the spinlock hold. 2871 */ 2872 static int ace_load_firmware(struct net_device *dev) 2873 { 2874 const struct firmware *fw; 2875 const char *fw_name = "acenic/tg2.bin"; 2876 struct ace_private *ap = netdev_priv(dev); 2877 struct ace_regs __iomem *regs = ap->regs; 2878 const __be32 *fw_data; 2879 u32 load_addr; 2880 int ret; 2881 2882 if (!(readl(®s->CpuCtrl) & CPU_HALTED)) { 2883 printk(KERN_ERR "%s: trying to download firmware while the " 2884 "CPU is running!\n", ap->name); 2885 return -EFAULT; 2886 } 2887 2888 if (ACE_IS_TIGON_I(ap)) 2889 fw_name = "acenic/tg1.bin"; 2890 2891 ret = request_firmware(&fw, fw_name, &ap->pdev->dev); 2892 if (ret) { 2893 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n", 2894 ap->name, fw_name); 2895 return ret; 2896 } 2897 2898 fw_data = (void *)fw->data; 2899 2900 /* Firmware blob starts with version numbers, followed by 2901 load and start address. Remainder is the blob to be loaded 2902 contiguously from load address. We don't bother to represent 2903 the BSS/SBSS sections any more, since we were clearing the 2904 whole thing anyway. */ 2905 ap->firmware_major = fw->data[0]; 2906 ap->firmware_minor = fw->data[1]; 2907 ap->firmware_fix = fw->data[2]; 2908 2909 ap->firmware_start = be32_to_cpu(fw_data[1]); 2910 if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) { 2911 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n", 2912 ap->name, ap->firmware_start, fw_name); 2913 ret = -EINVAL; 2914 goto out; 2915 } 2916 2917 load_addr = be32_to_cpu(fw_data[2]); 2918 if (load_addr < 0x4000 || load_addr >= 0x80000) { 2919 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n", 2920 ap->name, load_addr, fw_name); 2921 ret = -EINVAL; 2922 goto out; 2923 } 2924 2925 /* 2926 * Do not try to clear more than 512KiB or we end up seeing 2927 * funny things on NICs with only 512KiB SRAM 2928 */ 2929 ace_clear(regs, 0x2000, 0x80000-0x2000); 2930 ace_copy(regs, &fw_data[3], load_addr, fw->size-12); 2931 out: 2932 release_firmware(fw); 2933 return ret; 2934 } 2935 2936 2937 /* 2938 * The eeprom on the AceNIC is an Atmel i2c EEPROM. 2939 * 2940 * Accessing the EEPROM is `interesting' to say the least - don't read 2941 * this code right after dinner. 2942 * 2943 * This is all about black magic and bit-banging the device .... I 2944 * wonder in what hospital they have put the guy who designed the i2c 2945 * specs. 2946 * 2947 * Oh yes, this is only the beginning! 2948 * 2949 * Thanks to Stevarino Webinski for helping tracking down the bugs in the 2950 * code i2c readout code by beta testing all my hacks. 2951 */ 2952 static void eeprom_start(struct ace_regs __iomem *regs) 2953 { 2954 u32 local; 2955 2956 readl(®s->LocalCtrl); 2957 udelay(ACE_SHORT_DELAY); 2958 local = readl(®s->LocalCtrl); 2959 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE; 2960 writel(local, ®s->LocalCtrl); 2961 readl(®s->LocalCtrl); 2962 mb(); 2963 udelay(ACE_SHORT_DELAY); 2964 local |= EEPROM_CLK_OUT; 2965 writel(local, ®s->LocalCtrl); 2966 readl(®s->LocalCtrl); 2967 mb(); 2968 udelay(ACE_SHORT_DELAY); 2969 local &= ~EEPROM_DATA_OUT; 2970 writel(local, ®s->LocalCtrl); 2971 readl(®s->LocalCtrl); 2972 mb(); 2973 udelay(ACE_SHORT_DELAY); 2974 local &= ~EEPROM_CLK_OUT; 2975 writel(local, ®s->LocalCtrl); 2976 readl(®s->LocalCtrl); 2977 mb(); 2978 } 2979 2980 2981 static void eeprom_prep(struct ace_regs __iomem *regs, u8 magic) 2982 { 2983 short i; 2984 u32 local; 2985 2986 udelay(ACE_SHORT_DELAY); 2987 local = readl(®s->LocalCtrl); 2988 local &= ~EEPROM_DATA_OUT; 2989 local |= EEPROM_WRITE_ENABLE; 2990 writel(local, ®s->LocalCtrl); 2991 readl(®s->LocalCtrl); 2992 mb(); 2993 2994 for (i = 0; i < 8; i++, magic <<= 1) { 2995 udelay(ACE_SHORT_DELAY); 2996 if (magic & 0x80) 2997 local |= EEPROM_DATA_OUT; 2998 else 2999 local &= ~EEPROM_DATA_OUT; 3000 writel(local, ®s->LocalCtrl); 3001 readl(®s->LocalCtrl); 3002 mb(); 3003 3004 udelay(ACE_SHORT_DELAY); 3005 local |= EEPROM_CLK_OUT; 3006 writel(local, ®s->LocalCtrl); 3007 readl(®s->LocalCtrl); 3008 mb(); 3009 udelay(ACE_SHORT_DELAY); 3010 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT); 3011 writel(local, ®s->LocalCtrl); 3012 readl(®s->LocalCtrl); 3013 mb(); 3014 } 3015 } 3016 3017 3018 static int eeprom_check_ack(struct ace_regs __iomem *regs) 3019 { 3020 int state; 3021 u32 local; 3022 3023 local = readl(®s->LocalCtrl); 3024 local &= ~EEPROM_WRITE_ENABLE; 3025 writel(local, ®s->LocalCtrl); 3026 readl(®s->LocalCtrl); 3027 mb(); 3028 udelay(ACE_LONG_DELAY); 3029 local |= EEPROM_CLK_OUT; 3030 writel(local, ®s->LocalCtrl); 3031 readl(®s->LocalCtrl); 3032 mb(); 3033 udelay(ACE_SHORT_DELAY); 3034 /* sample data in middle of high clk */ 3035 state = (readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0; 3036 udelay(ACE_SHORT_DELAY); 3037 mb(); 3038 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl); 3039 readl(®s->LocalCtrl); 3040 mb(); 3041 3042 return state; 3043 } 3044 3045 3046 static void eeprom_stop(struct ace_regs __iomem *regs) 3047 { 3048 u32 local; 3049 3050 udelay(ACE_SHORT_DELAY); 3051 local = readl(®s->LocalCtrl); 3052 local |= EEPROM_WRITE_ENABLE; 3053 writel(local, ®s->LocalCtrl); 3054 readl(®s->LocalCtrl); 3055 mb(); 3056 udelay(ACE_SHORT_DELAY); 3057 local &= ~EEPROM_DATA_OUT; 3058 writel(local, ®s->LocalCtrl); 3059 readl(®s->LocalCtrl); 3060 mb(); 3061 udelay(ACE_SHORT_DELAY); 3062 local |= EEPROM_CLK_OUT; 3063 writel(local, ®s->LocalCtrl); 3064 readl(®s->LocalCtrl); 3065 mb(); 3066 udelay(ACE_SHORT_DELAY); 3067 local |= EEPROM_DATA_OUT; 3068 writel(local, ®s->LocalCtrl); 3069 readl(®s->LocalCtrl); 3070 mb(); 3071 udelay(ACE_LONG_DELAY); 3072 local &= ~EEPROM_CLK_OUT; 3073 writel(local, ®s->LocalCtrl); 3074 mb(); 3075 } 3076 3077 3078 /* 3079 * Read a whole byte from the EEPROM. 3080 */ 3081 static int read_eeprom_byte(struct net_device *dev, unsigned long offset) 3082 { 3083 struct ace_private *ap = netdev_priv(dev); 3084 struct ace_regs __iomem *regs = ap->regs; 3085 unsigned long flags; 3086 u32 local; 3087 int result = 0; 3088 short i; 3089 3090 /* 3091 * Don't take interrupts on this CPU will bit banging 3092 * the %#%#@$ I2C device 3093 */ 3094 local_irq_save(flags); 3095 3096 eeprom_start(regs); 3097 3098 eeprom_prep(regs, EEPROM_WRITE_SELECT); 3099 if (eeprom_check_ack(regs)) { 3100 local_irq_restore(flags); 3101 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name); 3102 result = -EIO; 3103 goto eeprom_read_error; 3104 } 3105 3106 eeprom_prep(regs, (offset >> 8) & 0xff); 3107 if (eeprom_check_ack(regs)) { 3108 local_irq_restore(flags); 3109 printk(KERN_ERR "%s: Unable to set address byte 0\n", 3110 ap->name); 3111 result = -EIO; 3112 goto eeprom_read_error; 3113 } 3114 3115 eeprom_prep(regs, offset & 0xff); 3116 if (eeprom_check_ack(regs)) { 3117 local_irq_restore(flags); 3118 printk(KERN_ERR "%s: Unable to set address byte 1\n", 3119 ap->name); 3120 result = -EIO; 3121 goto eeprom_read_error; 3122 } 3123 3124 eeprom_start(regs); 3125 eeprom_prep(regs, EEPROM_READ_SELECT); 3126 if (eeprom_check_ack(regs)) { 3127 local_irq_restore(flags); 3128 printk(KERN_ERR "%s: Unable to set READ_SELECT\n", 3129 ap->name); 3130 result = -EIO; 3131 goto eeprom_read_error; 3132 } 3133 3134 for (i = 0; i < 8; i++) { 3135 local = readl(®s->LocalCtrl); 3136 local &= ~EEPROM_WRITE_ENABLE; 3137 writel(local, ®s->LocalCtrl); 3138 readl(®s->LocalCtrl); 3139 udelay(ACE_LONG_DELAY); 3140 mb(); 3141 local |= EEPROM_CLK_OUT; 3142 writel(local, ®s->LocalCtrl); 3143 readl(®s->LocalCtrl); 3144 mb(); 3145 udelay(ACE_SHORT_DELAY); 3146 /* sample data mid high clk */ 3147 result = (result << 1) | 3148 ((readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0); 3149 udelay(ACE_SHORT_DELAY); 3150 mb(); 3151 local = readl(®s->LocalCtrl); 3152 local &= ~EEPROM_CLK_OUT; 3153 writel(local, ®s->LocalCtrl); 3154 readl(®s->LocalCtrl); 3155 udelay(ACE_SHORT_DELAY); 3156 mb(); 3157 if (i == 7) { 3158 local |= EEPROM_WRITE_ENABLE; 3159 writel(local, ®s->LocalCtrl); 3160 readl(®s->LocalCtrl); 3161 mb(); 3162 udelay(ACE_SHORT_DELAY); 3163 } 3164 } 3165 3166 local |= EEPROM_DATA_OUT; 3167 writel(local, ®s->LocalCtrl); 3168 readl(®s->LocalCtrl); 3169 mb(); 3170 udelay(ACE_SHORT_DELAY); 3171 writel(readl(®s->LocalCtrl) | EEPROM_CLK_OUT, ®s->LocalCtrl); 3172 readl(®s->LocalCtrl); 3173 udelay(ACE_LONG_DELAY); 3174 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl); 3175 readl(®s->LocalCtrl); 3176 mb(); 3177 udelay(ACE_SHORT_DELAY); 3178 eeprom_stop(regs); 3179 3180 local_irq_restore(flags); 3181 out: 3182 return result; 3183 3184 eeprom_read_error: 3185 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n", 3186 ap->name, offset); 3187 goto out; 3188 } 3189 3190 module_pci_driver(acenic_pci_driver); 3191