1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
4  *           and other Tigon based cards.
5  *
6  * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
7  *
8  * Thanks to Alteon and 3Com for providing hardware and documentation
9  * enabling me to write this driver.
10  *
11  * A mailing list for discussing the use of this driver has been
12  * setup, please subscribe to the lists if you have any questions
13  * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
14  * see how to subscribe.
15  *
16  * Additional credits:
17  *   Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
18  *       dump support. The trace dump support has not been
19  *       integrated yet however.
20  *   Troy Benjegerdes: Big Endian (PPC) patches.
21  *   Nate Stahl: Better out of memory handling and stats support.
22  *   Aman Singla: Nasty race between interrupt handler and tx code dealing
23  *                with 'testing the tx_ret_csm and setting tx_full'
24  *   David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
25  *                                       infrastructure and Sparc support
26  *   Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
27  *                              driver under Linux/Sparc64
28  *   Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
29  *                                       ETHTOOL_GDRVINFO support
30  *   Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
31  *                                       handler and close() cleanup.
32  *   Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
33  *                                       memory mapped IO is enabled to
34  *                                       make the driver work on RS/6000.
35  *   Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
36  *                                       where the driver would disable
37  *                                       bus master mode if it had to disable
38  *                                       write and invalidate.
39  *   Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
40  *                                       endian systems.
41  *   Val Henson <vhenson@esscom.com>:    Reset Jumbo skb producer and
42  *                                       rx producer index when
43  *                                       flushing the Jumbo ring.
44  *   Hans Grobler <grobh@sun.ac.za>:     Memory leak fixes in the
45  *                                       driver init path.
46  *   Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
47  */
48 
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/types.h>
52 #include <linux/errno.h>
53 #include <linux/ioport.h>
54 #include <linux/pci.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/kernel.h>
57 #include <linux/netdevice.h>
58 #include <linux/etherdevice.h>
59 #include <linux/skbuff.h>
60 #include <linux/delay.h>
61 #include <linux/mm.h>
62 #include <linux/highmem.h>
63 #include <linux/sockios.h>
64 #include <linux/firmware.h>
65 #include <linux/slab.h>
66 #include <linux/prefetch.h>
67 #include <linux/if_vlan.h>
68 
69 #ifdef SIOCETHTOOL
70 #include <linux/ethtool.h>
71 #endif
72 
73 #include <net/sock.h>
74 #include <net/ip.h>
75 
76 #include <asm/io.h>
77 #include <asm/irq.h>
78 #include <asm/byteorder.h>
79 #include <linux/uaccess.h>
80 
81 
82 #define DRV_NAME "acenic"
83 
84 #undef INDEX_DEBUG
85 
86 #ifdef CONFIG_ACENIC_OMIT_TIGON_I
87 #define ACE_IS_TIGON_I(ap)	0
88 #define ACE_TX_RING_ENTRIES(ap)	MAX_TX_RING_ENTRIES
89 #else
90 #define ACE_IS_TIGON_I(ap)	(ap->version == 1)
91 #define ACE_TX_RING_ENTRIES(ap)	ap->tx_ring_entries
92 #endif
93 
94 #ifndef PCI_VENDOR_ID_ALTEON
95 #define PCI_VENDOR_ID_ALTEON		0x12ae
96 #endif
97 #ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
98 #define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE  0x0001
99 #define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
100 #endif
101 #ifndef PCI_DEVICE_ID_3COM_3C985
102 #define PCI_DEVICE_ID_3COM_3C985	0x0001
103 #endif
104 #ifndef PCI_VENDOR_ID_NETGEAR
105 #define PCI_VENDOR_ID_NETGEAR		0x1385
106 #define PCI_DEVICE_ID_NETGEAR_GA620	0x620a
107 #endif
108 #ifndef PCI_DEVICE_ID_NETGEAR_GA620T
109 #define PCI_DEVICE_ID_NETGEAR_GA620T	0x630a
110 #endif
111 
112 
113 /*
114  * Farallon used the DEC vendor ID by mistake and they seem not
115  * to care - stinky!
116  */
117 #ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
118 #define PCI_DEVICE_ID_FARALLON_PN9000SX	0x1a
119 #endif
120 #ifndef PCI_DEVICE_ID_FARALLON_PN9100T
121 #define PCI_DEVICE_ID_FARALLON_PN9100T  0xfa
122 #endif
123 #ifndef PCI_VENDOR_ID_SGI
124 #define PCI_VENDOR_ID_SGI		0x10a9
125 #endif
126 #ifndef PCI_DEVICE_ID_SGI_ACENIC
127 #define PCI_DEVICE_ID_SGI_ACENIC	0x0009
128 #endif
129 
130 static const struct pci_device_id acenic_pci_tbl[] = {
131 	{ PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
132 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
133 	{ PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
134 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
135 	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
136 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
137 	{ PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
138 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
139 	{ PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
140 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
141 	/*
142 	 * Farallon used the DEC vendor ID on their cards incorrectly,
143 	 * then later Alteon's ID.
144 	 */
145 	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
146 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
147 	{ PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
148 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
149 	{ PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
150 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
151 	{ }
152 };
153 MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
154 
155 #define ace_sync_irq(irq)	synchronize_irq(irq)
156 
157 #ifndef offset_in_page
158 #define offset_in_page(ptr)	((unsigned long)(ptr) & ~PAGE_MASK)
159 #endif
160 
161 #define ACE_MAX_MOD_PARMS	8
162 #define BOARD_IDX_STATIC	0
163 #define BOARD_IDX_OVERFLOW	-1
164 
165 #include "acenic.h"
166 
167 /*
168  * These must be defined before the firmware is included.
169  */
170 #define MAX_TEXT_LEN	96*1024
171 #define MAX_RODATA_LEN	8*1024
172 #define MAX_DATA_LEN	2*1024
173 
174 #ifndef tigon2FwReleaseLocal
175 #define tigon2FwReleaseLocal 0
176 #endif
177 
178 /*
179  * This driver currently supports Tigon I and Tigon II based cards
180  * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
181  * GA620. The driver should also work on the SGI, DEC and Farallon
182  * versions of the card, however I have not been able to test that
183  * myself.
184  *
185  * This card is really neat, it supports receive hardware checksumming
186  * and jumbo frames (up to 9000 bytes) and does a lot of work in the
187  * firmware. Also the programming interface is quite neat, except for
188  * the parts dealing with the i2c eeprom on the card ;-)
189  *
190  * Using jumbo frames:
191  *
192  * To enable jumbo frames, simply specify an mtu between 1500 and 9000
193  * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
194  * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
195  * interface number and <MTU> being the MTU value.
196  *
197  * Module parameters:
198  *
199  * When compiled as a loadable module, the driver allows for a number
200  * of module parameters to be specified. The driver supports the
201  * following module parameters:
202  *
203  *  trace=<val> - Firmware trace level. This requires special traced
204  *                firmware to replace the firmware supplied with
205  *                the driver - for debugging purposes only.
206  *
207  *  link=<val>  - Link state. Normally you want to use the default link
208  *                parameters set by the driver. This can be used to
209  *                override these in case your switch doesn't negotiate
210  *                the link properly. Valid values are:
211  *         0x0001 - Force half duplex link.
212  *         0x0002 - Do not negotiate line speed with the other end.
213  *         0x0010 - 10Mbit/sec link.
214  *         0x0020 - 100Mbit/sec link.
215  *         0x0040 - 1000Mbit/sec link.
216  *         0x0100 - Do not negotiate flow control.
217  *         0x0200 - Enable RX flow control Y
218  *         0x0400 - Enable TX flow control Y (Tigon II NICs only).
219  *                Default value is 0x0270, ie. enable link+flow
220  *                control negotiation. Negotiating the highest
221  *                possible link speed with RX flow control enabled.
222  *
223  *                When disabling link speed negotiation, only one link
224  *                speed is allowed to be specified!
225  *
226  *  tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
227  *                to wait for more packets to arive before
228  *                interrupting the host, from the time the first
229  *                packet arrives.
230  *
231  *  rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
232  *                to wait for more packets to arive in the transmit ring,
233  *                before interrupting the host, after transmitting the
234  *                first packet in the ring.
235  *
236  *  max_tx_desc=<val> - maximum number of transmit descriptors
237  *                (packets) transmitted before interrupting the host.
238  *
239  *  max_rx_desc=<val> - maximum number of receive descriptors
240  *                (packets) received before interrupting the host.
241  *
242  *  tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
243  *                increments of the NIC's on board memory to be used for
244  *                transmit and receive buffers. For the 1MB NIC app. 800KB
245  *                is available, on the 1/2MB NIC app. 300KB is available.
246  *                68KB will always be available as a minimum for both
247  *                directions. The default value is a 50/50 split.
248  *  dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
249  *                operations, default (1) is to always disable this as
250  *                that is what Alteon does on NT. I have not been able
251  *                to measure any real performance differences with
252  *                this on my systems. Set <val>=0 if you want to
253  *                enable these operations.
254  *
255  * If you use more than one NIC, specify the parameters for the
256  * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
257  * run tracing on NIC #2 but not on NIC #1 and #3.
258  *
259  * TODO:
260  *
261  * - Proper multicast support.
262  * - NIC dump support.
263  * - More tuning parameters.
264  *
265  * The mini ring is not used under Linux and I am not sure it makes sense
266  * to actually use it.
267  *
268  * New interrupt handler strategy:
269  *
270  * The old interrupt handler worked using the traditional method of
271  * replacing an skbuff with a new one when a packet arrives. However
272  * the rx rings do not need to contain a static number of buffer
273  * descriptors, thus it makes sense to move the memory allocation out
274  * of the main interrupt handler and do it in a bottom half handler
275  * and only allocate new buffers when the number of buffers in the
276  * ring is below a certain threshold. In order to avoid starving the
277  * NIC under heavy load it is however necessary to force allocation
278  * when hitting a minimum threshold. The strategy for alloction is as
279  * follows:
280  *
281  *     RX_LOW_BUF_THRES    - allocate buffers in the bottom half
282  *     RX_PANIC_LOW_THRES  - we are very low on buffers, allocate
283  *                           the buffers in the interrupt handler
284  *     RX_RING_THRES       - maximum number of buffers in the rx ring
285  *     RX_MINI_THRES       - maximum number of buffers in the mini ring
286  *     RX_JUMBO_THRES      - maximum number of buffers in the jumbo ring
287  *
288  * One advantagous side effect of this allocation approach is that the
289  * entire rx processing can be done without holding any spin lock
290  * since the rx rings and registers are totally independent of the tx
291  * ring and its registers.  This of course includes the kmalloc's of
292  * new skb's. Thus start_xmit can run in parallel with rx processing
293  * and the memory allocation on SMP systems.
294  *
295  * Note that running the skb reallocation in a bottom half opens up
296  * another can of races which needs to be handled properly. In
297  * particular it can happen that the interrupt handler tries to run
298  * the reallocation while the bottom half is either running on another
299  * CPU or was interrupted on the same CPU. To get around this the
300  * driver uses bitops to prevent the reallocation routines from being
301  * reentered.
302  *
303  * TX handling can also be done without holding any spin lock, wheee
304  * this is fun! since tx_ret_csm is only written to by the interrupt
305  * handler. The case to be aware of is when shutting down the device
306  * and cleaning up where it is necessary to make sure that
307  * start_xmit() is not running while this is happening. Well DaveM
308  * informs me that this case is already protected against ... bye bye
309  * Mr. Spin Lock, it was nice to know you.
310  *
311  * TX interrupts are now partly disabled so the NIC will only generate
312  * TX interrupts for the number of coal ticks, not for the number of
313  * TX packets in the queue. This should reduce the number of TX only,
314  * ie. when no RX processing is done, interrupts seen.
315  */
316 
317 /*
318  * Threshold values for RX buffer allocation - the low water marks for
319  * when to start refilling the rings are set to 75% of the ring
320  * sizes. It seems to make sense to refill the rings entirely from the
321  * intrrupt handler once it gets below the panic threshold, that way
322  * we don't risk that the refilling is moved to another CPU when the
323  * one running the interrupt handler just got the slab code hot in its
324  * cache.
325  */
326 #define RX_RING_SIZE		72
327 #define RX_MINI_SIZE		64
328 #define RX_JUMBO_SIZE		48
329 
330 #define RX_PANIC_STD_THRES	16
331 #define RX_PANIC_STD_REFILL	(3*RX_PANIC_STD_THRES)/2
332 #define RX_LOW_STD_THRES	(3*RX_RING_SIZE)/4
333 #define RX_PANIC_MINI_THRES	12
334 #define RX_PANIC_MINI_REFILL	(3*RX_PANIC_MINI_THRES)/2
335 #define RX_LOW_MINI_THRES	(3*RX_MINI_SIZE)/4
336 #define RX_PANIC_JUMBO_THRES	6
337 #define RX_PANIC_JUMBO_REFILL	(3*RX_PANIC_JUMBO_THRES)/2
338 #define RX_LOW_JUMBO_THRES	(3*RX_JUMBO_SIZE)/4
339 
340 
341 /*
342  * Size of the mini ring entries, basically these just should be big
343  * enough to take TCP ACKs
344  */
345 #define ACE_MINI_SIZE		100
346 
347 #define ACE_MINI_BUFSIZE	ACE_MINI_SIZE
348 #define ACE_STD_BUFSIZE		(ACE_STD_MTU + ETH_HLEN + 4)
349 #define ACE_JUMBO_BUFSIZE	(ACE_JUMBO_MTU + ETH_HLEN + 4)
350 
351 /*
352  * There seems to be a magic difference in the effect between 995 and 996
353  * but little difference between 900 and 995 ... no idea why.
354  *
355  * There is now a default set of tuning parameters which is set, depending
356  * on whether or not the user enables Jumbo frames. It's assumed that if
357  * Jumbo frames are enabled, the user wants optimal tuning for that case.
358  */
359 #define DEF_TX_COAL		400 /* 996 */
360 #define DEF_TX_MAX_DESC		60  /* was 40 */
361 #define DEF_RX_COAL		120 /* 1000 */
362 #define DEF_RX_MAX_DESC		25
363 #define DEF_TX_RATIO		21 /* 24 */
364 
365 #define DEF_JUMBO_TX_COAL	20
366 #define DEF_JUMBO_TX_MAX_DESC	60
367 #define DEF_JUMBO_RX_COAL	30
368 #define DEF_JUMBO_RX_MAX_DESC	6
369 #define DEF_JUMBO_TX_RATIO	21
370 
371 #if tigon2FwReleaseLocal < 20001118
372 /*
373  * Standard firmware and early modifications duplicate
374  * IRQ load without this flag (coal timer is never reset).
375  * Note that with this flag tx_coal should be less than
376  * time to xmit full tx ring.
377  * 400usec is not so bad for tx ring size of 128.
378  */
379 #define TX_COAL_INTS_ONLY	1	/* worth it */
380 #else
381 /*
382  * With modified firmware, this is not necessary, but still useful.
383  */
384 #define TX_COAL_INTS_ONLY	1
385 #endif
386 
387 #define DEF_TRACE		0
388 #define DEF_STAT		(2 * TICKS_PER_SEC)
389 
390 
391 static int link_state[ACE_MAX_MOD_PARMS];
392 static int trace[ACE_MAX_MOD_PARMS];
393 static int tx_coal_tick[ACE_MAX_MOD_PARMS];
394 static int rx_coal_tick[ACE_MAX_MOD_PARMS];
395 static int max_tx_desc[ACE_MAX_MOD_PARMS];
396 static int max_rx_desc[ACE_MAX_MOD_PARMS];
397 static int tx_ratio[ACE_MAX_MOD_PARMS];
398 static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
399 
400 MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
401 MODULE_LICENSE("GPL");
402 MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
403 #ifndef CONFIG_ACENIC_OMIT_TIGON_I
404 MODULE_FIRMWARE("acenic/tg1.bin");
405 #endif
406 MODULE_FIRMWARE("acenic/tg2.bin");
407 
408 module_param_array_named(link, link_state, int, NULL, 0);
409 module_param_array(trace, int, NULL, 0);
410 module_param_array(tx_coal_tick, int, NULL, 0);
411 module_param_array(max_tx_desc, int, NULL, 0);
412 module_param_array(rx_coal_tick, int, NULL, 0);
413 module_param_array(max_rx_desc, int, NULL, 0);
414 module_param_array(tx_ratio, int, NULL, 0);
415 MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
416 MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
417 MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
418 MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
419 MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
420 MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
421 MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
422 
423 
424 static const char version[] =
425   "acenic.c: v0.92 08/05/2002  Jes Sorensen, linux-acenic@SunSITE.dk\n"
426   "                            http://home.cern.ch/~jes/gige/acenic.html\n";
427 
428 static int ace_get_link_ksettings(struct net_device *,
429 				  struct ethtool_link_ksettings *);
430 static int ace_set_link_ksettings(struct net_device *,
431 				  const struct ethtool_link_ksettings *);
432 static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
433 
434 static const struct ethtool_ops ace_ethtool_ops = {
435 	.get_drvinfo = ace_get_drvinfo,
436 	.get_link_ksettings = ace_get_link_ksettings,
437 	.set_link_ksettings = ace_set_link_ksettings,
438 };
439 
440 static void ace_watchdog(struct net_device *dev);
441 
442 static const struct net_device_ops ace_netdev_ops = {
443 	.ndo_open		= ace_open,
444 	.ndo_stop		= ace_close,
445 	.ndo_tx_timeout		= ace_watchdog,
446 	.ndo_get_stats		= ace_get_stats,
447 	.ndo_start_xmit		= ace_start_xmit,
448 	.ndo_set_rx_mode	= ace_set_multicast_list,
449 	.ndo_validate_addr	= eth_validate_addr,
450 	.ndo_set_mac_address	= ace_set_mac_addr,
451 	.ndo_change_mtu		= ace_change_mtu,
452 };
453 
454 static int acenic_probe_one(struct pci_dev *pdev,
455 			    const struct pci_device_id *id)
456 {
457 	struct net_device *dev;
458 	struct ace_private *ap;
459 	static int boards_found;
460 
461 	dev = alloc_etherdev(sizeof(struct ace_private));
462 	if (dev == NULL)
463 		return -ENOMEM;
464 
465 	SET_NETDEV_DEV(dev, &pdev->dev);
466 
467 	ap = netdev_priv(dev);
468 	ap->pdev = pdev;
469 	ap->name = pci_name(pdev);
470 
471 	dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
472 	dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
473 
474 	dev->watchdog_timeo = 5*HZ;
475 	dev->min_mtu = 0;
476 	dev->max_mtu = ACE_JUMBO_MTU;
477 
478 	dev->netdev_ops = &ace_netdev_ops;
479 	dev->ethtool_ops = &ace_ethtool_ops;
480 
481 	/* we only display this string ONCE */
482 	if (!boards_found)
483 		printk(version);
484 
485 	if (pci_enable_device(pdev))
486 		goto fail_free_netdev;
487 
488 	/*
489 	 * Enable master mode before we start playing with the
490 	 * pci_command word since pci_set_master() will modify
491 	 * it.
492 	 */
493 	pci_set_master(pdev);
494 
495 	pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
496 
497 	/* OpenFirmware on Mac's does not set this - DOH.. */
498 	if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
499 		printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
500 		       "access - was not enabled by BIOS/Firmware\n",
501 		       ap->name);
502 		ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
503 		pci_write_config_word(ap->pdev, PCI_COMMAND,
504 				      ap->pci_command);
505 		wmb();
506 	}
507 
508 	pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
509 	if (ap->pci_latency <= 0x40) {
510 		ap->pci_latency = 0x40;
511 		pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
512 	}
513 
514 	/*
515 	 * Remap the regs into kernel space - this is abuse of
516 	 * dev->base_addr since it was means for I/O port
517 	 * addresses but who gives a damn.
518 	 */
519 	dev->base_addr = pci_resource_start(pdev, 0);
520 	ap->regs = ioremap(dev->base_addr, 0x4000);
521 	if (!ap->regs) {
522 		printk(KERN_ERR "%s:  Unable to map I/O register, "
523 		       "AceNIC %i will be disabled.\n",
524 		       ap->name, boards_found);
525 		goto fail_free_netdev;
526 	}
527 
528 	switch(pdev->vendor) {
529 	case PCI_VENDOR_ID_ALTEON:
530 		if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
531 			printk(KERN_INFO "%s: Farallon PN9100-T ",
532 			       ap->name);
533 		} else {
534 			printk(KERN_INFO "%s: Alteon AceNIC ",
535 			       ap->name);
536 		}
537 		break;
538 	case PCI_VENDOR_ID_3COM:
539 		printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
540 		break;
541 	case PCI_VENDOR_ID_NETGEAR:
542 		printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
543 		break;
544 	case PCI_VENDOR_ID_DEC:
545 		if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
546 			printk(KERN_INFO "%s: Farallon PN9000-SX ",
547 			       ap->name);
548 			break;
549 		}
550 		/* Fall through */
551 	case PCI_VENDOR_ID_SGI:
552 		printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
553 		break;
554 	default:
555 		printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
556 		break;
557 	}
558 
559 	printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
560 	printk("irq %d\n", pdev->irq);
561 
562 #ifdef CONFIG_ACENIC_OMIT_TIGON_I
563 	if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
564 		printk(KERN_ERR "%s: Driver compiled without Tigon I"
565 		       " support - NIC disabled\n", dev->name);
566 		goto fail_uninit;
567 	}
568 #endif
569 
570 	if (ace_allocate_descriptors(dev))
571 		goto fail_free_netdev;
572 
573 #ifdef MODULE
574 	if (boards_found >= ACE_MAX_MOD_PARMS)
575 		ap->board_idx = BOARD_IDX_OVERFLOW;
576 	else
577 		ap->board_idx = boards_found;
578 #else
579 	ap->board_idx = BOARD_IDX_STATIC;
580 #endif
581 
582 	if (ace_init(dev))
583 		goto fail_free_netdev;
584 
585 	if (register_netdev(dev)) {
586 		printk(KERN_ERR "acenic: device registration failed\n");
587 		goto fail_uninit;
588 	}
589 	ap->name = dev->name;
590 
591 	if (ap->pci_using_dac)
592 		dev->features |= NETIF_F_HIGHDMA;
593 
594 	pci_set_drvdata(pdev, dev);
595 
596 	boards_found++;
597 	return 0;
598 
599  fail_uninit:
600 	ace_init_cleanup(dev);
601  fail_free_netdev:
602 	free_netdev(dev);
603 	return -ENODEV;
604 }
605 
606 static void acenic_remove_one(struct pci_dev *pdev)
607 {
608 	struct net_device *dev = pci_get_drvdata(pdev);
609 	struct ace_private *ap = netdev_priv(dev);
610 	struct ace_regs __iomem *regs = ap->regs;
611 	short i;
612 
613 	unregister_netdev(dev);
614 
615 	writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
616 	if (ap->version >= 2)
617 		writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
618 
619 	/*
620 	 * This clears any pending interrupts
621 	 */
622 	writel(1, &regs->Mb0Lo);
623 	readl(&regs->CpuCtrl);	/* flush */
624 
625 	/*
626 	 * Make sure no other CPUs are processing interrupts
627 	 * on the card before the buffers are being released.
628 	 * Otherwise one might experience some `interesting'
629 	 * effects.
630 	 *
631 	 * Then release the RX buffers - jumbo buffers were
632 	 * already released in ace_close().
633 	 */
634 	ace_sync_irq(dev->irq);
635 
636 	for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
637 		struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
638 
639 		if (skb) {
640 			struct ring_info *ringp;
641 			dma_addr_t mapping;
642 
643 			ringp = &ap->skb->rx_std_skbuff[i];
644 			mapping = dma_unmap_addr(ringp, mapping);
645 			pci_unmap_page(ap->pdev, mapping,
646 				       ACE_STD_BUFSIZE,
647 				       PCI_DMA_FROMDEVICE);
648 
649 			ap->rx_std_ring[i].size = 0;
650 			ap->skb->rx_std_skbuff[i].skb = NULL;
651 			dev_kfree_skb(skb);
652 		}
653 	}
654 
655 	if (ap->version >= 2) {
656 		for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
657 			struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
658 
659 			if (skb) {
660 				struct ring_info *ringp;
661 				dma_addr_t mapping;
662 
663 				ringp = &ap->skb->rx_mini_skbuff[i];
664 				mapping = dma_unmap_addr(ringp,mapping);
665 				pci_unmap_page(ap->pdev, mapping,
666 					       ACE_MINI_BUFSIZE,
667 					       PCI_DMA_FROMDEVICE);
668 
669 				ap->rx_mini_ring[i].size = 0;
670 				ap->skb->rx_mini_skbuff[i].skb = NULL;
671 				dev_kfree_skb(skb);
672 			}
673 		}
674 	}
675 
676 	for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
677 		struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
678 		if (skb) {
679 			struct ring_info *ringp;
680 			dma_addr_t mapping;
681 
682 			ringp = &ap->skb->rx_jumbo_skbuff[i];
683 			mapping = dma_unmap_addr(ringp, mapping);
684 			pci_unmap_page(ap->pdev, mapping,
685 				       ACE_JUMBO_BUFSIZE,
686 				       PCI_DMA_FROMDEVICE);
687 
688 			ap->rx_jumbo_ring[i].size = 0;
689 			ap->skb->rx_jumbo_skbuff[i].skb = NULL;
690 			dev_kfree_skb(skb);
691 		}
692 	}
693 
694 	ace_init_cleanup(dev);
695 	free_netdev(dev);
696 }
697 
698 static struct pci_driver acenic_pci_driver = {
699 	.name		= "acenic",
700 	.id_table	= acenic_pci_tbl,
701 	.probe		= acenic_probe_one,
702 	.remove		= acenic_remove_one,
703 };
704 
705 static void ace_free_descriptors(struct net_device *dev)
706 {
707 	struct ace_private *ap = netdev_priv(dev);
708 	int size;
709 
710 	if (ap->rx_std_ring != NULL) {
711 		size = (sizeof(struct rx_desc) *
712 			(RX_STD_RING_ENTRIES +
713 			 RX_JUMBO_RING_ENTRIES +
714 			 RX_MINI_RING_ENTRIES +
715 			 RX_RETURN_RING_ENTRIES));
716 		pci_free_consistent(ap->pdev, size, ap->rx_std_ring,
717 				    ap->rx_ring_base_dma);
718 		ap->rx_std_ring = NULL;
719 		ap->rx_jumbo_ring = NULL;
720 		ap->rx_mini_ring = NULL;
721 		ap->rx_return_ring = NULL;
722 	}
723 	if (ap->evt_ring != NULL) {
724 		size = (sizeof(struct event) * EVT_RING_ENTRIES);
725 		pci_free_consistent(ap->pdev, size, ap->evt_ring,
726 				    ap->evt_ring_dma);
727 		ap->evt_ring = NULL;
728 	}
729 	if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
730 		size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
731 		pci_free_consistent(ap->pdev, size, ap->tx_ring,
732 				    ap->tx_ring_dma);
733 	}
734 	ap->tx_ring = NULL;
735 
736 	if (ap->evt_prd != NULL) {
737 		pci_free_consistent(ap->pdev, sizeof(u32),
738 				    (void *)ap->evt_prd, ap->evt_prd_dma);
739 		ap->evt_prd = NULL;
740 	}
741 	if (ap->rx_ret_prd != NULL) {
742 		pci_free_consistent(ap->pdev, sizeof(u32),
743 				    (void *)ap->rx_ret_prd,
744 				    ap->rx_ret_prd_dma);
745 		ap->rx_ret_prd = NULL;
746 	}
747 	if (ap->tx_csm != NULL) {
748 		pci_free_consistent(ap->pdev, sizeof(u32),
749 				    (void *)ap->tx_csm, ap->tx_csm_dma);
750 		ap->tx_csm = NULL;
751 	}
752 }
753 
754 
755 static int ace_allocate_descriptors(struct net_device *dev)
756 {
757 	struct ace_private *ap = netdev_priv(dev);
758 	int size;
759 
760 	size = (sizeof(struct rx_desc) *
761 		(RX_STD_RING_ENTRIES +
762 		 RX_JUMBO_RING_ENTRIES +
763 		 RX_MINI_RING_ENTRIES +
764 		 RX_RETURN_RING_ENTRIES));
765 
766 	ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size,
767 					       &ap->rx_ring_base_dma);
768 	if (ap->rx_std_ring == NULL)
769 		goto fail;
770 
771 	ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
772 	ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
773 	ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
774 
775 	size = (sizeof(struct event) * EVT_RING_ENTRIES);
776 
777 	ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma);
778 
779 	if (ap->evt_ring == NULL)
780 		goto fail;
781 
782 	/*
783 	 * Only allocate a host TX ring for the Tigon II, the Tigon I
784 	 * has to use PCI registers for this ;-(
785 	 */
786 	if (!ACE_IS_TIGON_I(ap)) {
787 		size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
788 
789 		ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
790 						   &ap->tx_ring_dma);
791 
792 		if (ap->tx_ring == NULL)
793 			goto fail;
794 	}
795 
796 	ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
797 					   &ap->evt_prd_dma);
798 	if (ap->evt_prd == NULL)
799 		goto fail;
800 
801 	ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
802 					      &ap->rx_ret_prd_dma);
803 	if (ap->rx_ret_prd == NULL)
804 		goto fail;
805 
806 	ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32),
807 					  &ap->tx_csm_dma);
808 	if (ap->tx_csm == NULL)
809 		goto fail;
810 
811 	return 0;
812 
813 fail:
814 	/* Clean up. */
815 	ace_init_cleanup(dev);
816 	return 1;
817 }
818 
819 
820 /*
821  * Generic cleanup handling data allocated during init. Used when the
822  * module is unloaded or if an error occurs during initialization
823  */
824 static void ace_init_cleanup(struct net_device *dev)
825 {
826 	struct ace_private *ap;
827 
828 	ap = netdev_priv(dev);
829 
830 	ace_free_descriptors(dev);
831 
832 	if (ap->info)
833 		pci_free_consistent(ap->pdev, sizeof(struct ace_info),
834 				    ap->info, ap->info_dma);
835 	kfree(ap->skb);
836 	kfree(ap->trace_buf);
837 
838 	if (dev->irq)
839 		free_irq(dev->irq, dev);
840 
841 	iounmap(ap->regs);
842 }
843 
844 
845 /*
846  * Commands are considered to be slow.
847  */
848 static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
849 {
850 	u32 idx;
851 
852 	idx = readl(&regs->CmdPrd);
853 
854 	writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
855 	idx = (idx + 1) % CMD_RING_ENTRIES;
856 
857 	writel(idx, &regs->CmdPrd);
858 }
859 
860 
861 static int ace_init(struct net_device *dev)
862 {
863 	struct ace_private *ap;
864 	struct ace_regs __iomem *regs;
865 	struct ace_info *info = NULL;
866 	struct pci_dev *pdev;
867 	unsigned long myjif;
868 	u64 tmp_ptr;
869 	u32 tig_ver, mac1, mac2, tmp, pci_state;
870 	int board_idx, ecode = 0;
871 	short i;
872 	unsigned char cache_size;
873 
874 	ap = netdev_priv(dev);
875 	regs = ap->regs;
876 
877 	board_idx = ap->board_idx;
878 
879 	/*
880 	 * aman@sgi.com - its useful to do a NIC reset here to
881 	 * address the `Firmware not running' problem subsequent
882 	 * to any crashes involving the NIC
883 	 */
884 	writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
885 	readl(&regs->HostCtrl);		/* PCI write posting */
886 	udelay(5);
887 
888 	/*
889 	 * Don't access any other registers before this point!
890 	 */
891 #ifdef __BIG_ENDIAN
892 	/*
893 	 * This will most likely need BYTE_SWAP once we switch
894 	 * to using __raw_writel()
895 	 */
896 	writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
897 	       &regs->HostCtrl);
898 #else
899 	writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
900 	       &regs->HostCtrl);
901 #endif
902 	readl(&regs->HostCtrl);		/* PCI write posting */
903 
904 	/*
905 	 * Stop the NIC CPU and clear pending interrupts
906 	 */
907 	writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
908 	readl(&regs->CpuCtrl);		/* PCI write posting */
909 	writel(0, &regs->Mb0Lo);
910 
911 	tig_ver = readl(&regs->HostCtrl) >> 28;
912 
913 	switch(tig_ver){
914 #ifndef CONFIG_ACENIC_OMIT_TIGON_I
915 	case 4:
916 	case 5:
917 		printk(KERN_INFO "  Tigon I  (Rev. %i), Firmware: %i.%i.%i, ",
918 		       tig_ver, ap->firmware_major, ap->firmware_minor,
919 		       ap->firmware_fix);
920 		writel(0, &regs->LocalCtrl);
921 		ap->version = 1;
922 		ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
923 		break;
924 #endif
925 	case 6:
926 		printk(KERN_INFO "  Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
927 		       tig_ver, ap->firmware_major, ap->firmware_minor,
928 		       ap->firmware_fix);
929 		writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
930 		readl(&regs->CpuBCtrl);		/* PCI write posting */
931 		/*
932 		 * The SRAM bank size does _not_ indicate the amount
933 		 * of memory on the card, it controls the _bank_ size!
934 		 * Ie. a 1MB AceNIC will have two banks of 512KB.
935 		 */
936 		writel(SRAM_BANK_512K, &regs->LocalCtrl);
937 		writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
938 		ap->version = 2;
939 		ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
940 		break;
941 	default:
942 		printk(KERN_WARNING "  Unsupported Tigon version detected "
943 		       "(%i)\n", tig_ver);
944 		ecode = -ENODEV;
945 		goto init_error;
946 	}
947 
948 	/*
949 	 * ModeStat _must_ be set after the SRAM settings as this change
950 	 * seems to corrupt the ModeStat and possible other registers.
951 	 * The SRAM settings survive resets and setting it to the same
952 	 * value a second time works as well. This is what caused the
953 	 * `Firmware not running' problem on the Tigon II.
954 	 */
955 #ifdef __BIG_ENDIAN
956 	writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
957 	       ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
958 #else
959 	writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
960 	       ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
961 #endif
962 	readl(&regs->ModeStat);		/* PCI write posting */
963 
964 	mac1 = 0;
965 	for(i = 0; i < 4; i++) {
966 		int t;
967 
968 		mac1 = mac1 << 8;
969 		t = read_eeprom_byte(dev, 0x8c+i);
970 		if (t < 0) {
971 			ecode = -EIO;
972 			goto init_error;
973 		} else
974 			mac1 |= (t & 0xff);
975 	}
976 	mac2 = 0;
977 	for(i = 4; i < 8; i++) {
978 		int t;
979 
980 		mac2 = mac2 << 8;
981 		t = read_eeprom_byte(dev, 0x8c+i);
982 		if (t < 0) {
983 			ecode = -EIO;
984 			goto init_error;
985 		} else
986 			mac2 |= (t & 0xff);
987 	}
988 
989 	writel(mac1, &regs->MacAddrHi);
990 	writel(mac2, &regs->MacAddrLo);
991 
992 	dev->dev_addr[0] = (mac1 >> 8) & 0xff;
993 	dev->dev_addr[1] = mac1 & 0xff;
994 	dev->dev_addr[2] = (mac2 >> 24) & 0xff;
995 	dev->dev_addr[3] = (mac2 >> 16) & 0xff;
996 	dev->dev_addr[4] = (mac2 >> 8) & 0xff;
997 	dev->dev_addr[5] = mac2 & 0xff;
998 
999 	printk("MAC: %pM\n", dev->dev_addr);
1000 
1001 	/*
1002 	 * Looks like this is necessary to deal with on all architectures,
1003 	 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1004 	 * Ie. having two NICs in the machine, one will have the cache
1005 	 * line set at boot time, the other will not.
1006 	 */
1007 	pdev = ap->pdev;
1008 	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1009 	cache_size <<= 2;
1010 	if (cache_size != SMP_CACHE_BYTES) {
1011 		printk(KERN_INFO "  PCI cache line size set incorrectly "
1012 		       "(%i bytes) by BIOS/FW, ", cache_size);
1013 		if (cache_size > SMP_CACHE_BYTES)
1014 			printk("expecting %i\n", SMP_CACHE_BYTES);
1015 		else {
1016 			printk("correcting to %i\n", SMP_CACHE_BYTES);
1017 			pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1018 					      SMP_CACHE_BYTES >> 2);
1019 		}
1020 	}
1021 
1022 	pci_state = readl(&regs->PciState);
1023 	printk(KERN_INFO "  PCI bus width: %i bits, speed: %iMHz, "
1024 	       "latency: %i clks\n",
1025 	       	(pci_state & PCI_32BIT) ? 32 : 64,
1026 		(pci_state & PCI_66MHZ) ? 66 : 33,
1027 		ap->pci_latency);
1028 
1029 	/*
1030 	 * Set the max DMA transfer size. Seems that for most systems
1031 	 * the performance is better when no MAX parameter is
1032 	 * set. However for systems enabling PCI write and invalidate,
1033 	 * DMA writes must be set to the L1 cache line size to get
1034 	 * optimal performance.
1035 	 *
1036 	 * The default is now to turn the PCI write and invalidate off
1037 	 * - that is what Alteon does for NT.
1038 	 */
1039 	tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1040 	if (ap->version >= 2) {
1041 		tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1042 		/*
1043 		 * Tuning parameters only supported for 8 cards
1044 		 */
1045 		if (board_idx == BOARD_IDX_OVERFLOW ||
1046 		    dis_pci_mem_inval[board_idx]) {
1047 			if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1048 				ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1049 				pci_write_config_word(pdev, PCI_COMMAND,
1050 						      ap->pci_command);
1051 				printk(KERN_INFO "  Disabling PCI memory "
1052 				       "write and invalidate\n");
1053 			}
1054 		} else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1055 			printk(KERN_INFO "  PCI memory write & invalidate "
1056 			       "enabled by BIOS, enabling counter measures\n");
1057 
1058 			switch(SMP_CACHE_BYTES) {
1059 			case 16:
1060 				tmp |= DMA_WRITE_MAX_16;
1061 				break;
1062 			case 32:
1063 				tmp |= DMA_WRITE_MAX_32;
1064 				break;
1065 			case 64:
1066 				tmp |= DMA_WRITE_MAX_64;
1067 				break;
1068 			case 128:
1069 				tmp |= DMA_WRITE_MAX_128;
1070 				break;
1071 			default:
1072 				printk(KERN_INFO "  Cache line size %i not "
1073 				       "supported, PCI write and invalidate "
1074 				       "disabled\n", SMP_CACHE_BYTES);
1075 				ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1076 				pci_write_config_word(pdev, PCI_COMMAND,
1077 						      ap->pci_command);
1078 			}
1079 		}
1080 	}
1081 
1082 #ifdef __sparc__
1083 	/*
1084 	 * On this platform, we know what the best dma settings
1085 	 * are.  We use 64-byte maximum bursts, because if we
1086 	 * burst larger than the cache line size (or even cross
1087 	 * a 64byte boundary in a single burst) the UltraSparc
1088 	 * PCI controller will disconnect at 64-byte multiples.
1089 	 *
1090 	 * Read-multiple will be properly enabled above, and when
1091 	 * set will give the PCI controller proper hints about
1092 	 * prefetching.
1093 	 */
1094 	tmp &= ~DMA_READ_WRITE_MASK;
1095 	tmp |= DMA_READ_MAX_64;
1096 	tmp |= DMA_WRITE_MAX_64;
1097 #endif
1098 #ifdef __alpha__
1099 	tmp &= ~DMA_READ_WRITE_MASK;
1100 	tmp |= DMA_READ_MAX_128;
1101 	/*
1102 	 * All the docs say MUST NOT. Well, I did.
1103 	 * Nothing terrible happens, if we load wrong size.
1104 	 * Bit w&i still works better!
1105 	 */
1106 	tmp |= DMA_WRITE_MAX_128;
1107 #endif
1108 	writel(tmp, &regs->PciState);
1109 
1110 #if 0
1111 	/*
1112 	 * The Host PCI bus controller driver has to set FBB.
1113 	 * If all devices on that PCI bus support FBB, then the controller
1114 	 * can enable FBB support in the Host PCI Bus controller (or on
1115 	 * the PCI-PCI bridge if that applies).
1116 	 * -ggg
1117 	 */
1118 	/*
1119 	 * I have received reports from people having problems when this
1120 	 * bit is enabled.
1121 	 */
1122 	if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1123 		printk(KERN_INFO "  Enabling PCI Fast Back to Back\n");
1124 		ap->pci_command |= PCI_COMMAND_FAST_BACK;
1125 		pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1126 	}
1127 #endif
1128 
1129 	/*
1130 	 * Configure DMA attributes.
1131 	 */
1132 	if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1133 		ap->pci_using_dac = 1;
1134 	} else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1135 		ap->pci_using_dac = 0;
1136 	} else {
1137 		ecode = -ENODEV;
1138 		goto init_error;
1139 	}
1140 
1141 	/*
1142 	 * Initialize the generic info block and the command+event rings
1143 	 * and the control blocks for the transmit and receive rings
1144 	 * as they need to be setup once and for all.
1145 	 */
1146 	if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info),
1147 					  &ap->info_dma))) {
1148 		ecode = -EAGAIN;
1149 		goto init_error;
1150 	}
1151 	ap->info = info;
1152 
1153 	/*
1154 	 * Get the memory for the skb rings.
1155 	 */
1156 	if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1157 		ecode = -EAGAIN;
1158 		goto init_error;
1159 	}
1160 
1161 	ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1162 			    DRV_NAME, dev);
1163 	if (ecode) {
1164 		printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1165 		       DRV_NAME, pdev->irq);
1166 		goto init_error;
1167 	} else
1168 		dev->irq = pdev->irq;
1169 
1170 #ifdef INDEX_DEBUG
1171 	spin_lock_init(&ap->debug_lock);
1172 	ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1173 	ap->last_std_rx = 0;
1174 	ap->last_mini_rx = 0;
1175 #endif
1176 
1177 	memset(ap->info, 0, sizeof(struct ace_info));
1178 	memset(ap->skb, 0, sizeof(struct ace_skb));
1179 
1180 	ecode = ace_load_firmware(dev);
1181 	if (ecode)
1182 		goto init_error;
1183 
1184 	ap->fw_running = 0;
1185 
1186 	tmp_ptr = ap->info_dma;
1187 	writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1188 	writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1189 
1190 	memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1191 
1192 	set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1193 	info->evt_ctrl.flags = 0;
1194 
1195 	*(ap->evt_prd) = 0;
1196 	wmb();
1197 	set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1198 	writel(0, &regs->EvtCsm);
1199 
1200 	set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1201 	info->cmd_ctrl.flags = 0;
1202 	info->cmd_ctrl.max_len = 0;
1203 
1204 	for (i = 0; i < CMD_RING_ENTRIES; i++)
1205 		writel(0, &regs->CmdRng[i]);
1206 
1207 	writel(0, &regs->CmdPrd);
1208 	writel(0, &regs->CmdCsm);
1209 
1210 	tmp_ptr = ap->info_dma;
1211 	tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1212 	set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1213 
1214 	set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1215 	info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1216 	info->rx_std_ctrl.flags =
1217 	  RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1218 
1219 	memset(ap->rx_std_ring, 0,
1220 	       RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1221 
1222 	for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1223 		ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1224 
1225 	ap->rx_std_skbprd = 0;
1226 	atomic_set(&ap->cur_rx_bufs, 0);
1227 
1228 	set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1229 		    (ap->rx_ring_base_dma +
1230 		     (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1231 	info->rx_jumbo_ctrl.max_len = 0;
1232 	info->rx_jumbo_ctrl.flags =
1233 	  RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1234 
1235 	memset(ap->rx_jumbo_ring, 0,
1236 	       RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1237 
1238 	for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1239 		ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1240 
1241 	ap->rx_jumbo_skbprd = 0;
1242 	atomic_set(&ap->cur_jumbo_bufs, 0);
1243 
1244 	memset(ap->rx_mini_ring, 0,
1245 	       RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1246 
1247 	if (ap->version >= 2) {
1248 		set_aceaddr(&info->rx_mini_ctrl.rngptr,
1249 			    (ap->rx_ring_base_dma +
1250 			     (sizeof(struct rx_desc) *
1251 			      (RX_STD_RING_ENTRIES +
1252 			       RX_JUMBO_RING_ENTRIES))));
1253 		info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
1254 		info->rx_mini_ctrl.flags =
1255 		  RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|RCB_FLG_VLAN_ASSIST;
1256 
1257 		for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1258 			ap->rx_mini_ring[i].flags =
1259 				BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1260 	} else {
1261 		set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1262 		info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1263 		info->rx_mini_ctrl.max_len = 0;
1264 	}
1265 
1266 	ap->rx_mini_skbprd = 0;
1267 	atomic_set(&ap->cur_mini_bufs, 0);
1268 
1269 	set_aceaddr(&info->rx_return_ctrl.rngptr,
1270 		    (ap->rx_ring_base_dma +
1271 		     (sizeof(struct rx_desc) *
1272 		      (RX_STD_RING_ENTRIES +
1273 		       RX_JUMBO_RING_ENTRIES +
1274 		       RX_MINI_RING_ENTRIES))));
1275 	info->rx_return_ctrl.flags = 0;
1276 	info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1277 
1278 	memset(ap->rx_return_ring, 0,
1279 	       RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1280 
1281 	set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1282 	*(ap->rx_ret_prd) = 0;
1283 
1284 	writel(TX_RING_BASE, &regs->WinBase);
1285 
1286 	if (ACE_IS_TIGON_I(ap)) {
1287 		ap->tx_ring = (__force struct tx_desc *) regs->Window;
1288 		for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1289 				 * sizeof(struct tx_desc)) / sizeof(u32); i++)
1290 			writel(0, (__force void __iomem *)ap->tx_ring  + i * 4);
1291 
1292 		set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1293 	} else {
1294 		memset(ap->tx_ring, 0,
1295 		       MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1296 
1297 		set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1298 	}
1299 
1300 	info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1301 	tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1302 
1303 	/*
1304 	 * The Tigon I does not like having the TX ring in host memory ;-(
1305 	 */
1306 	if (!ACE_IS_TIGON_I(ap))
1307 		tmp |= RCB_FLG_TX_HOST_RING;
1308 #if TX_COAL_INTS_ONLY
1309 	tmp |= RCB_FLG_COAL_INT_ONLY;
1310 #endif
1311 	info->tx_ctrl.flags = tmp;
1312 
1313 	set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1314 
1315 	/*
1316 	 * Potential item for tuning parameter
1317 	 */
1318 #if 0 /* NO */
1319 	writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1320 	writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1321 #else
1322 	writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1323 	writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1324 #endif
1325 
1326 	writel(0, &regs->MaskInt);
1327 	writel(1, &regs->IfIdx);
1328 #if 0
1329 	/*
1330 	 * McKinley boxes do not like us fiddling with AssistState
1331 	 * this early
1332 	 */
1333 	writel(1, &regs->AssistState);
1334 #endif
1335 
1336 	writel(DEF_STAT, &regs->TuneStatTicks);
1337 	writel(DEF_TRACE, &regs->TuneTrace);
1338 
1339 	ace_set_rxtx_parms(dev, 0);
1340 
1341 	if (board_idx == BOARD_IDX_OVERFLOW) {
1342 		printk(KERN_WARNING "%s: more than %i NICs detected, "
1343 		       "ignoring module parameters!\n",
1344 		       ap->name, ACE_MAX_MOD_PARMS);
1345 	} else if (board_idx >= 0) {
1346 		if (tx_coal_tick[board_idx])
1347 			writel(tx_coal_tick[board_idx],
1348 			       &regs->TuneTxCoalTicks);
1349 		if (max_tx_desc[board_idx])
1350 			writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1351 
1352 		if (rx_coal_tick[board_idx])
1353 			writel(rx_coal_tick[board_idx],
1354 			       &regs->TuneRxCoalTicks);
1355 		if (max_rx_desc[board_idx])
1356 			writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1357 
1358 		if (trace[board_idx])
1359 			writel(trace[board_idx], &regs->TuneTrace);
1360 
1361 		if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1362 			writel(tx_ratio[board_idx], &regs->TxBufRat);
1363 	}
1364 
1365 	/*
1366 	 * Default link parameters
1367 	 */
1368 	tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1369 		LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1370 	if(ap->version >= 2)
1371 		tmp |= LNK_TX_FLOW_CTL_Y;
1372 
1373 	/*
1374 	 * Override link default parameters
1375 	 */
1376 	if ((board_idx >= 0) && link_state[board_idx]) {
1377 		int option = link_state[board_idx];
1378 
1379 		tmp = LNK_ENABLE;
1380 
1381 		if (option & 0x01) {
1382 			printk(KERN_INFO "%s: Setting half duplex link\n",
1383 			       ap->name);
1384 			tmp &= ~LNK_FULL_DUPLEX;
1385 		}
1386 		if (option & 0x02)
1387 			tmp &= ~LNK_NEGOTIATE;
1388 		if (option & 0x10)
1389 			tmp |= LNK_10MB;
1390 		if (option & 0x20)
1391 			tmp |= LNK_100MB;
1392 		if (option & 0x40)
1393 			tmp |= LNK_1000MB;
1394 		if ((option & 0x70) == 0) {
1395 			printk(KERN_WARNING "%s: No media speed specified, "
1396 			       "forcing auto negotiation\n", ap->name);
1397 			tmp |= LNK_NEGOTIATE | LNK_1000MB |
1398 				LNK_100MB | LNK_10MB;
1399 		}
1400 		if ((option & 0x100) == 0)
1401 			tmp |= LNK_NEG_FCTL;
1402 		else
1403 			printk(KERN_INFO "%s: Disabling flow control "
1404 			       "negotiation\n", ap->name);
1405 		if (option & 0x200)
1406 			tmp |= LNK_RX_FLOW_CTL_Y;
1407 		if ((option & 0x400) && (ap->version >= 2)) {
1408 			printk(KERN_INFO "%s: Enabling TX flow control\n",
1409 			       ap->name);
1410 			tmp |= LNK_TX_FLOW_CTL_Y;
1411 		}
1412 	}
1413 
1414 	ap->link = tmp;
1415 	writel(tmp, &regs->TuneLink);
1416 	if (ap->version >= 2)
1417 		writel(tmp, &regs->TuneFastLink);
1418 
1419 	writel(ap->firmware_start, &regs->Pc);
1420 
1421 	writel(0, &regs->Mb0Lo);
1422 
1423 	/*
1424 	 * Set tx_csm before we start receiving interrupts, otherwise
1425 	 * the interrupt handler might think it is supposed to process
1426 	 * tx ints before we are up and running, which may cause a null
1427 	 * pointer access in the int handler.
1428 	 */
1429 	ap->cur_rx = 0;
1430 	ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1431 
1432 	wmb();
1433 	ace_set_txprd(regs, ap, 0);
1434 	writel(0, &regs->RxRetCsm);
1435 
1436 	/*
1437 	 * Enable DMA engine now.
1438 	 * If we do this sooner, Mckinley box pukes.
1439 	 * I assume it's because Tigon II DMA engine wants to check
1440 	 * *something* even before the CPU is started.
1441 	 */
1442 	writel(1, &regs->AssistState);  /* enable DMA */
1443 
1444 	/*
1445 	 * Start the NIC CPU
1446 	 */
1447 	writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1448 	readl(&regs->CpuCtrl);
1449 
1450 	/*
1451 	 * Wait for the firmware to spin up - max 3 seconds.
1452 	 */
1453 	myjif = jiffies + 3 * HZ;
1454 	while (time_before(jiffies, myjif) && !ap->fw_running)
1455 		cpu_relax();
1456 
1457 	if (!ap->fw_running) {
1458 		printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1459 
1460 		ace_dump_trace(ap);
1461 		writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1462 		readl(&regs->CpuCtrl);
1463 
1464 		/* aman@sgi.com - account for badly behaving firmware/NIC:
1465 		 * - have observed that the NIC may continue to generate
1466 		 *   interrupts for some reason; attempt to stop it - halt
1467 		 *   second CPU for Tigon II cards, and also clear Mb0
1468 		 * - if we're a module, we'll fail to load if this was
1469 		 *   the only GbE card in the system => if the kernel does
1470 		 *   see an interrupt from the NIC, code to handle it is
1471 		 *   gone and OOps! - so free_irq also
1472 		 */
1473 		if (ap->version >= 2)
1474 			writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1475 			       &regs->CpuBCtrl);
1476 		writel(0, &regs->Mb0Lo);
1477 		readl(&regs->Mb0Lo);
1478 
1479 		ecode = -EBUSY;
1480 		goto init_error;
1481 	}
1482 
1483 	/*
1484 	 * We load the ring here as there seem to be no way to tell the
1485 	 * firmware to wipe the ring without re-initializing it.
1486 	 */
1487 	if (!test_and_set_bit(0, &ap->std_refill_busy))
1488 		ace_load_std_rx_ring(dev, RX_RING_SIZE);
1489 	else
1490 		printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1491 		       ap->name);
1492 	if (ap->version >= 2) {
1493 		if (!test_and_set_bit(0, &ap->mini_refill_busy))
1494 			ace_load_mini_rx_ring(dev, RX_MINI_SIZE);
1495 		else
1496 			printk(KERN_ERR "%s: Someone is busy refilling "
1497 			       "the RX mini ring\n", ap->name);
1498 	}
1499 	return 0;
1500 
1501  init_error:
1502 	ace_init_cleanup(dev);
1503 	return ecode;
1504 }
1505 
1506 
1507 static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1508 {
1509 	struct ace_private *ap = netdev_priv(dev);
1510 	struct ace_regs __iomem *regs = ap->regs;
1511 	int board_idx = ap->board_idx;
1512 
1513 	if (board_idx >= 0) {
1514 		if (!jumbo) {
1515 			if (!tx_coal_tick[board_idx])
1516 				writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1517 			if (!max_tx_desc[board_idx])
1518 				writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1519 			if (!rx_coal_tick[board_idx])
1520 				writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1521 			if (!max_rx_desc[board_idx])
1522 				writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1523 			if (!tx_ratio[board_idx])
1524 				writel(DEF_TX_RATIO, &regs->TxBufRat);
1525 		} else {
1526 			if (!tx_coal_tick[board_idx])
1527 				writel(DEF_JUMBO_TX_COAL,
1528 				       &regs->TuneTxCoalTicks);
1529 			if (!max_tx_desc[board_idx])
1530 				writel(DEF_JUMBO_TX_MAX_DESC,
1531 				       &regs->TuneMaxTxDesc);
1532 			if (!rx_coal_tick[board_idx])
1533 				writel(DEF_JUMBO_RX_COAL,
1534 				       &regs->TuneRxCoalTicks);
1535 			if (!max_rx_desc[board_idx])
1536 				writel(DEF_JUMBO_RX_MAX_DESC,
1537 				       &regs->TuneMaxRxDesc);
1538 			if (!tx_ratio[board_idx])
1539 				writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1540 		}
1541 	}
1542 }
1543 
1544 
1545 static void ace_watchdog(struct net_device *data)
1546 {
1547 	struct net_device *dev = data;
1548 	struct ace_private *ap = netdev_priv(dev);
1549 	struct ace_regs __iomem *regs = ap->regs;
1550 
1551 	/*
1552 	 * We haven't received a stats update event for more than 2.5
1553 	 * seconds and there is data in the transmit queue, thus we
1554 	 * assume the card is stuck.
1555 	 */
1556 	if (*ap->tx_csm != ap->tx_ret_csm) {
1557 		printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1558 		       dev->name, (unsigned int)readl(&regs->HostCtrl));
1559 		/* This can happen due to ieee flow control. */
1560 	} else {
1561 		printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1562 		       dev->name);
1563 #if 0
1564 		netif_wake_queue(dev);
1565 #endif
1566 	}
1567 }
1568 
1569 
1570 static void ace_tasklet(unsigned long arg)
1571 {
1572 	struct net_device *dev = (struct net_device *) arg;
1573 	struct ace_private *ap = netdev_priv(dev);
1574 	int cur_size;
1575 
1576 	cur_size = atomic_read(&ap->cur_rx_bufs);
1577 	if ((cur_size < RX_LOW_STD_THRES) &&
1578 	    !test_and_set_bit(0, &ap->std_refill_busy)) {
1579 #ifdef DEBUG
1580 		printk("refilling buffers (current %i)\n", cur_size);
1581 #endif
1582 		ace_load_std_rx_ring(dev, RX_RING_SIZE - cur_size);
1583 	}
1584 
1585 	if (ap->version >= 2) {
1586 		cur_size = atomic_read(&ap->cur_mini_bufs);
1587 		if ((cur_size < RX_LOW_MINI_THRES) &&
1588 		    !test_and_set_bit(0, &ap->mini_refill_busy)) {
1589 #ifdef DEBUG
1590 			printk("refilling mini buffers (current %i)\n",
1591 			       cur_size);
1592 #endif
1593 			ace_load_mini_rx_ring(dev, RX_MINI_SIZE - cur_size);
1594 		}
1595 	}
1596 
1597 	cur_size = atomic_read(&ap->cur_jumbo_bufs);
1598 	if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1599 	    !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1600 #ifdef DEBUG
1601 		printk("refilling jumbo buffers (current %i)\n", cur_size);
1602 #endif
1603 		ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE - cur_size);
1604 	}
1605 	ap->tasklet_pending = 0;
1606 }
1607 
1608 
1609 /*
1610  * Copy the contents of the NIC's trace buffer to kernel memory.
1611  */
1612 static void ace_dump_trace(struct ace_private *ap)
1613 {
1614 #if 0
1615 	if (!ap->trace_buf)
1616 		if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1617 		    return;
1618 #endif
1619 }
1620 
1621 
1622 /*
1623  * Load the standard rx ring.
1624  *
1625  * Loading rings is safe without holding the spin lock since this is
1626  * done only before the device is enabled, thus no interrupts are
1627  * generated and by the interrupt handler/tasklet handler.
1628  */
1629 static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs)
1630 {
1631 	struct ace_private *ap = netdev_priv(dev);
1632 	struct ace_regs __iomem *regs = ap->regs;
1633 	short i, idx;
1634 
1635 
1636 	prefetchw(&ap->cur_rx_bufs);
1637 
1638 	idx = ap->rx_std_skbprd;
1639 
1640 	for (i = 0; i < nr_bufs; i++) {
1641 		struct sk_buff *skb;
1642 		struct rx_desc *rd;
1643 		dma_addr_t mapping;
1644 
1645 		skb = netdev_alloc_skb_ip_align(dev, ACE_STD_BUFSIZE);
1646 		if (!skb)
1647 			break;
1648 
1649 		mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1650 				       offset_in_page(skb->data),
1651 				       ACE_STD_BUFSIZE,
1652 				       PCI_DMA_FROMDEVICE);
1653 		ap->skb->rx_std_skbuff[idx].skb = skb;
1654 		dma_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1655 				   mapping, mapping);
1656 
1657 		rd = &ap->rx_std_ring[idx];
1658 		set_aceaddr(&rd->addr, mapping);
1659 		rd->size = ACE_STD_BUFSIZE;
1660 		rd->idx = idx;
1661 		idx = (idx + 1) % RX_STD_RING_ENTRIES;
1662 	}
1663 
1664 	if (!i)
1665 		goto error_out;
1666 
1667 	atomic_add(i, &ap->cur_rx_bufs);
1668 	ap->rx_std_skbprd = idx;
1669 
1670 	if (ACE_IS_TIGON_I(ap)) {
1671 		struct cmd cmd;
1672 		cmd.evt = C_SET_RX_PRD_IDX;
1673 		cmd.code = 0;
1674 		cmd.idx = ap->rx_std_skbprd;
1675 		ace_issue_cmd(regs, &cmd);
1676 	} else {
1677 		writel(idx, &regs->RxStdPrd);
1678 		wmb();
1679 	}
1680 
1681  out:
1682 	clear_bit(0, &ap->std_refill_busy);
1683 	return;
1684 
1685  error_out:
1686 	printk(KERN_INFO "Out of memory when allocating "
1687 	       "standard receive buffers\n");
1688 	goto out;
1689 }
1690 
1691 
1692 static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs)
1693 {
1694 	struct ace_private *ap = netdev_priv(dev);
1695 	struct ace_regs __iomem *regs = ap->regs;
1696 	short i, idx;
1697 
1698 	prefetchw(&ap->cur_mini_bufs);
1699 
1700 	idx = ap->rx_mini_skbprd;
1701 	for (i = 0; i < nr_bufs; i++) {
1702 		struct sk_buff *skb;
1703 		struct rx_desc *rd;
1704 		dma_addr_t mapping;
1705 
1706 		skb = netdev_alloc_skb_ip_align(dev, ACE_MINI_BUFSIZE);
1707 		if (!skb)
1708 			break;
1709 
1710 		mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1711 				       offset_in_page(skb->data),
1712 				       ACE_MINI_BUFSIZE,
1713 				       PCI_DMA_FROMDEVICE);
1714 		ap->skb->rx_mini_skbuff[idx].skb = skb;
1715 		dma_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1716 				   mapping, mapping);
1717 
1718 		rd = &ap->rx_mini_ring[idx];
1719 		set_aceaddr(&rd->addr, mapping);
1720 		rd->size = ACE_MINI_BUFSIZE;
1721 		rd->idx = idx;
1722 		idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1723 	}
1724 
1725 	if (!i)
1726 		goto error_out;
1727 
1728 	atomic_add(i, &ap->cur_mini_bufs);
1729 
1730 	ap->rx_mini_skbprd = idx;
1731 
1732 	writel(idx, &regs->RxMiniPrd);
1733 	wmb();
1734 
1735  out:
1736 	clear_bit(0, &ap->mini_refill_busy);
1737 	return;
1738  error_out:
1739 	printk(KERN_INFO "Out of memory when allocating "
1740 	       "mini receive buffers\n");
1741 	goto out;
1742 }
1743 
1744 
1745 /*
1746  * Load the jumbo rx ring, this may happen at any time if the MTU
1747  * is changed to a value > 1500.
1748  */
1749 static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs)
1750 {
1751 	struct ace_private *ap = netdev_priv(dev);
1752 	struct ace_regs __iomem *regs = ap->regs;
1753 	short i, idx;
1754 
1755 	idx = ap->rx_jumbo_skbprd;
1756 
1757 	for (i = 0; i < nr_bufs; i++) {
1758 		struct sk_buff *skb;
1759 		struct rx_desc *rd;
1760 		dma_addr_t mapping;
1761 
1762 		skb = netdev_alloc_skb_ip_align(dev, ACE_JUMBO_BUFSIZE);
1763 		if (!skb)
1764 			break;
1765 
1766 		mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
1767 				       offset_in_page(skb->data),
1768 				       ACE_JUMBO_BUFSIZE,
1769 				       PCI_DMA_FROMDEVICE);
1770 		ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1771 		dma_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1772 				   mapping, mapping);
1773 
1774 		rd = &ap->rx_jumbo_ring[idx];
1775 		set_aceaddr(&rd->addr, mapping);
1776 		rd->size = ACE_JUMBO_BUFSIZE;
1777 		rd->idx = idx;
1778 		idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1779 	}
1780 
1781 	if (!i)
1782 		goto error_out;
1783 
1784 	atomic_add(i, &ap->cur_jumbo_bufs);
1785 	ap->rx_jumbo_skbprd = idx;
1786 
1787 	if (ACE_IS_TIGON_I(ap)) {
1788 		struct cmd cmd;
1789 		cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1790 		cmd.code = 0;
1791 		cmd.idx = ap->rx_jumbo_skbprd;
1792 		ace_issue_cmd(regs, &cmd);
1793 	} else {
1794 		writel(idx, &regs->RxJumboPrd);
1795 		wmb();
1796 	}
1797 
1798  out:
1799 	clear_bit(0, &ap->jumbo_refill_busy);
1800 	return;
1801  error_out:
1802 	if (net_ratelimit())
1803 		printk(KERN_INFO "Out of memory when allocating "
1804 		       "jumbo receive buffers\n");
1805 	goto out;
1806 }
1807 
1808 
1809 /*
1810  * All events are considered to be slow (RX/TX ints do not generate
1811  * events) and are handled here, outside the main interrupt handler,
1812  * to reduce the size of the handler.
1813  */
1814 static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1815 {
1816 	struct ace_private *ap;
1817 
1818 	ap = netdev_priv(dev);
1819 
1820 	while (evtcsm != evtprd) {
1821 		switch (ap->evt_ring[evtcsm].evt) {
1822 		case E_FW_RUNNING:
1823 			printk(KERN_INFO "%s: Firmware up and running\n",
1824 			       ap->name);
1825 			ap->fw_running = 1;
1826 			wmb();
1827 			break;
1828 		case E_STATS_UPDATED:
1829 			break;
1830 		case E_LNK_STATE:
1831 		{
1832 			u16 code = ap->evt_ring[evtcsm].code;
1833 			switch (code) {
1834 			case E_C_LINK_UP:
1835 			{
1836 				u32 state = readl(&ap->regs->GigLnkState);
1837 				printk(KERN_WARNING "%s: Optical link UP "
1838 				       "(%s Duplex, Flow Control: %s%s)\n",
1839 				       ap->name,
1840 				       state & LNK_FULL_DUPLEX ? "Full":"Half",
1841 				       state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1842 				       state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1843 				break;
1844 			}
1845 			case E_C_LINK_DOWN:
1846 				printk(KERN_WARNING "%s: Optical link DOWN\n",
1847 				       ap->name);
1848 				break;
1849 			case E_C_LINK_10_100:
1850 				printk(KERN_WARNING "%s: 10/100BaseT link "
1851 				       "UP\n", ap->name);
1852 				break;
1853 			default:
1854 				printk(KERN_ERR "%s: Unknown optical link "
1855 				       "state %02x\n", ap->name, code);
1856 			}
1857 			break;
1858 		}
1859 		case E_ERROR:
1860 			switch(ap->evt_ring[evtcsm].code) {
1861 			case E_C_ERR_INVAL_CMD:
1862 				printk(KERN_ERR "%s: invalid command error\n",
1863 				       ap->name);
1864 				break;
1865 			case E_C_ERR_UNIMP_CMD:
1866 				printk(KERN_ERR "%s: unimplemented command "
1867 				       "error\n", ap->name);
1868 				break;
1869 			case E_C_ERR_BAD_CFG:
1870 				printk(KERN_ERR "%s: bad config error\n",
1871 				       ap->name);
1872 				break;
1873 			default:
1874 				printk(KERN_ERR "%s: unknown error %02x\n",
1875 				       ap->name, ap->evt_ring[evtcsm].code);
1876 			}
1877 			break;
1878 		case E_RESET_JUMBO_RNG:
1879 		{
1880 			int i;
1881 			for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1882 				if (ap->skb->rx_jumbo_skbuff[i].skb) {
1883 					ap->rx_jumbo_ring[i].size = 0;
1884 					set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1885 					dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1886 					ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1887 				}
1888 			}
1889 
1890  			if (ACE_IS_TIGON_I(ap)) {
1891  				struct cmd cmd;
1892  				cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1893  				cmd.code = 0;
1894  				cmd.idx = 0;
1895  				ace_issue_cmd(ap->regs, &cmd);
1896  			} else {
1897  				writel(0, &((ap->regs)->RxJumboPrd));
1898  				wmb();
1899  			}
1900 
1901 			ap->jumbo = 0;
1902 			ap->rx_jumbo_skbprd = 0;
1903 			printk(KERN_INFO "%s: Jumbo ring flushed\n",
1904 			       ap->name);
1905 			clear_bit(0, &ap->jumbo_refill_busy);
1906 			break;
1907 		}
1908 		default:
1909 			printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1910 			       ap->name, ap->evt_ring[evtcsm].evt);
1911 		}
1912 		evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1913 	}
1914 
1915 	return evtcsm;
1916 }
1917 
1918 
1919 static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1920 {
1921 	struct ace_private *ap = netdev_priv(dev);
1922 	u32 idx;
1923 	int mini_count = 0, std_count = 0;
1924 
1925 	idx = rxretcsm;
1926 
1927 	prefetchw(&ap->cur_rx_bufs);
1928 	prefetchw(&ap->cur_mini_bufs);
1929 
1930 	while (idx != rxretprd) {
1931 		struct ring_info *rip;
1932 		struct sk_buff *skb;
1933 		struct rx_desc *retdesc;
1934 		u32 skbidx;
1935 		int bd_flags, desc_type, mapsize;
1936 		u16 csum;
1937 
1938 
1939 		/* make sure the rx descriptor isn't read before rxretprd */
1940 		if (idx == rxretcsm)
1941 			rmb();
1942 
1943 		retdesc = &ap->rx_return_ring[idx];
1944 		skbidx = retdesc->idx;
1945 		bd_flags = retdesc->flags;
1946 		desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1947 
1948 		switch(desc_type) {
1949 			/*
1950 			 * Normal frames do not have any flags set
1951 			 *
1952 			 * Mini and normal frames arrive frequently,
1953 			 * so use a local counter to avoid doing
1954 			 * atomic operations for each packet arriving.
1955 			 */
1956 		case 0:
1957 			rip = &ap->skb->rx_std_skbuff[skbidx];
1958 			mapsize = ACE_STD_BUFSIZE;
1959 			std_count++;
1960 			break;
1961 		case BD_FLG_JUMBO:
1962 			rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1963 			mapsize = ACE_JUMBO_BUFSIZE;
1964 			atomic_dec(&ap->cur_jumbo_bufs);
1965 			break;
1966 		case BD_FLG_MINI:
1967 			rip = &ap->skb->rx_mini_skbuff[skbidx];
1968 			mapsize = ACE_MINI_BUFSIZE;
1969 			mini_count++;
1970 			break;
1971 		default:
1972 			printk(KERN_INFO "%s: unknown frame type (0x%02x) "
1973 			       "returned by NIC\n", dev->name,
1974 			       retdesc->flags);
1975 			goto error;
1976 		}
1977 
1978 		skb = rip->skb;
1979 		rip->skb = NULL;
1980 		pci_unmap_page(ap->pdev,
1981 			       dma_unmap_addr(rip, mapping),
1982 			       mapsize,
1983 			       PCI_DMA_FROMDEVICE);
1984 		skb_put(skb, retdesc->size);
1985 
1986 		/*
1987 		 * Fly baby, fly!
1988 		 */
1989 		csum = retdesc->tcp_udp_csum;
1990 
1991 		skb->protocol = eth_type_trans(skb, dev);
1992 
1993 		/*
1994 		 * Instead of forcing the poor tigon mips cpu to calculate
1995 		 * pseudo hdr checksum, we do this ourselves.
1996 		 */
1997 		if (bd_flags & BD_FLG_TCP_UDP_SUM) {
1998 			skb->csum = htons(csum);
1999 			skb->ip_summed = CHECKSUM_COMPLETE;
2000 		} else {
2001 			skb_checksum_none_assert(skb);
2002 		}
2003 
2004 		/* send it up */
2005 		if ((bd_flags & BD_FLG_VLAN_TAG))
2006 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), retdesc->vlan);
2007 		netif_rx(skb);
2008 
2009 		dev->stats.rx_packets++;
2010 		dev->stats.rx_bytes += retdesc->size;
2011 
2012 		idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2013 	}
2014 
2015 	atomic_sub(std_count, &ap->cur_rx_bufs);
2016 	if (!ACE_IS_TIGON_I(ap))
2017 		atomic_sub(mini_count, &ap->cur_mini_bufs);
2018 
2019  out:
2020 	/*
2021 	 * According to the documentation RxRetCsm is obsolete with
2022 	 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2023 	 */
2024 	if (ACE_IS_TIGON_I(ap)) {
2025 		writel(idx, &ap->regs->RxRetCsm);
2026 	}
2027 	ap->cur_rx = idx;
2028 
2029 	return;
2030  error:
2031 	idx = rxretprd;
2032 	goto out;
2033 }
2034 
2035 
2036 static inline void ace_tx_int(struct net_device *dev,
2037 			      u32 txcsm, u32 idx)
2038 {
2039 	struct ace_private *ap = netdev_priv(dev);
2040 
2041 	do {
2042 		struct sk_buff *skb;
2043 		struct tx_ring_info *info;
2044 
2045 		info = ap->skb->tx_skbuff + idx;
2046 		skb = info->skb;
2047 
2048 		if (dma_unmap_len(info, maplen)) {
2049 			pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping),
2050 				       dma_unmap_len(info, maplen),
2051 				       PCI_DMA_TODEVICE);
2052 			dma_unmap_len_set(info, maplen, 0);
2053 		}
2054 
2055 		if (skb) {
2056 			dev->stats.tx_packets++;
2057 			dev->stats.tx_bytes += skb->len;
2058 			dev_consume_skb_irq(skb);
2059 			info->skb = NULL;
2060 		}
2061 
2062 		idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2063 	} while (idx != txcsm);
2064 
2065 	if (netif_queue_stopped(dev))
2066 		netif_wake_queue(dev);
2067 
2068 	wmb();
2069 	ap->tx_ret_csm = txcsm;
2070 
2071 	/* So... tx_ret_csm is advanced _after_ check for device wakeup.
2072 	 *
2073 	 * We could try to make it before. In this case we would get
2074 	 * the following race condition: hard_start_xmit on other cpu
2075 	 * enters after we advanced tx_ret_csm and fills space,
2076 	 * which we have just freed, so that we make illegal device wakeup.
2077 	 * There is no good way to workaround this (at entry
2078 	 * to ace_start_xmit detects this condition and prevents
2079 	 * ring corruption, but it is not a good workaround.)
2080 	 *
2081 	 * When tx_ret_csm is advanced after, we wake up device _only_
2082 	 * if we really have some space in ring (though the core doing
2083 	 * hard_start_xmit can see full ring for some period and has to
2084 	 * synchronize.) Superb.
2085 	 * BUT! We get another subtle race condition. hard_start_xmit
2086 	 * may think that ring is full between wakeup and advancing
2087 	 * tx_ret_csm and will stop device instantly! It is not so bad.
2088 	 * We are guaranteed that there is something in ring, so that
2089 	 * the next irq will resume transmission. To speedup this we could
2090 	 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2091 	 * (see ace_start_xmit).
2092 	 *
2093 	 * Well, this dilemma exists in all lock-free devices.
2094 	 * We, following scheme used in drivers by Donald Becker,
2095 	 * select the least dangerous.
2096 	 *							--ANK
2097 	 */
2098 }
2099 
2100 
2101 static irqreturn_t ace_interrupt(int irq, void *dev_id)
2102 {
2103 	struct net_device *dev = (struct net_device *)dev_id;
2104 	struct ace_private *ap = netdev_priv(dev);
2105 	struct ace_regs __iomem *regs = ap->regs;
2106 	u32 idx;
2107 	u32 txcsm, rxretcsm, rxretprd;
2108 	u32 evtcsm, evtprd;
2109 
2110 	/*
2111 	 * In case of PCI shared interrupts or spurious interrupts,
2112 	 * we want to make sure it is actually our interrupt before
2113 	 * spending any time in here.
2114 	 */
2115 	if (!(readl(&regs->HostCtrl) & IN_INT))
2116 		return IRQ_NONE;
2117 
2118 	/*
2119 	 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2120 	 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2121 	 * writel(0, &regs->Mb0Lo).
2122 	 *
2123 	 * "IRQ avoidance" recommended in docs applies to IRQs served
2124 	 * threads and it is wrong even for that case.
2125 	 */
2126 	writel(0, &regs->Mb0Lo);
2127 	readl(&regs->Mb0Lo);
2128 
2129 	/*
2130 	 * There is no conflict between transmit handling in
2131 	 * start_xmit and receive processing, thus there is no reason
2132 	 * to take a spin lock for RX handling. Wait until we start
2133 	 * working on the other stuff - hey we don't need a spin lock
2134 	 * anymore.
2135 	 */
2136 	rxretprd = *ap->rx_ret_prd;
2137 	rxretcsm = ap->cur_rx;
2138 
2139 	if (rxretprd != rxretcsm)
2140 		ace_rx_int(dev, rxretprd, rxretcsm);
2141 
2142 	txcsm = *ap->tx_csm;
2143 	idx = ap->tx_ret_csm;
2144 
2145 	if (txcsm != idx) {
2146 		/*
2147 		 * If each skb takes only one descriptor this check degenerates
2148 		 * to identity, because new space has just been opened.
2149 		 * But if skbs are fragmented we must check that this index
2150 		 * update releases enough of space, otherwise we just
2151 		 * wait for device to make more work.
2152 		 */
2153 		if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2154 			ace_tx_int(dev, txcsm, idx);
2155 	}
2156 
2157 	evtcsm = readl(&regs->EvtCsm);
2158 	evtprd = *ap->evt_prd;
2159 
2160 	if (evtcsm != evtprd) {
2161 		evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2162 		writel(evtcsm, &regs->EvtCsm);
2163 	}
2164 
2165 	/*
2166 	 * This has to go last in the interrupt handler and run with
2167 	 * the spin lock released ... what lock?
2168 	 */
2169 	if (netif_running(dev)) {
2170 		int cur_size;
2171 		int run_tasklet = 0;
2172 
2173 		cur_size = atomic_read(&ap->cur_rx_bufs);
2174 		if (cur_size < RX_LOW_STD_THRES) {
2175 			if ((cur_size < RX_PANIC_STD_THRES) &&
2176 			    !test_and_set_bit(0, &ap->std_refill_busy)) {
2177 #ifdef DEBUG
2178 				printk("low on std buffers %i\n", cur_size);
2179 #endif
2180 				ace_load_std_rx_ring(dev,
2181 						     RX_RING_SIZE - cur_size);
2182 			} else
2183 				run_tasklet = 1;
2184 		}
2185 
2186 		if (!ACE_IS_TIGON_I(ap)) {
2187 			cur_size = atomic_read(&ap->cur_mini_bufs);
2188 			if (cur_size < RX_LOW_MINI_THRES) {
2189 				if ((cur_size < RX_PANIC_MINI_THRES) &&
2190 				    !test_and_set_bit(0,
2191 						      &ap->mini_refill_busy)) {
2192 #ifdef DEBUG
2193 					printk("low on mini buffers %i\n",
2194 					       cur_size);
2195 #endif
2196 					ace_load_mini_rx_ring(dev,
2197 							      RX_MINI_SIZE - cur_size);
2198 				} else
2199 					run_tasklet = 1;
2200 			}
2201 		}
2202 
2203 		if (ap->jumbo) {
2204 			cur_size = atomic_read(&ap->cur_jumbo_bufs);
2205 			if (cur_size < RX_LOW_JUMBO_THRES) {
2206 				if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2207 				    !test_and_set_bit(0,
2208 						      &ap->jumbo_refill_busy)){
2209 #ifdef DEBUG
2210 					printk("low on jumbo buffers %i\n",
2211 					       cur_size);
2212 #endif
2213 					ace_load_jumbo_rx_ring(dev,
2214 							       RX_JUMBO_SIZE - cur_size);
2215 				} else
2216 					run_tasklet = 1;
2217 			}
2218 		}
2219 		if (run_tasklet && !ap->tasklet_pending) {
2220 			ap->tasklet_pending = 1;
2221 			tasklet_schedule(&ap->ace_tasklet);
2222 		}
2223 	}
2224 
2225 	return IRQ_HANDLED;
2226 }
2227 
2228 static int ace_open(struct net_device *dev)
2229 {
2230 	struct ace_private *ap = netdev_priv(dev);
2231 	struct ace_regs __iomem *regs = ap->regs;
2232 	struct cmd cmd;
2233 
2234 	if (!(ap->fw_running)) {
2235 		printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2236 		return -EBUSY;
2237 	}
2238 
2239 	writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2240 
2241 	cmd.evt = C_CLEAR_STATS;
2242 	cmd.code = 0;
2243 	cmd.idx = 0;
2244 	ace_issue_cmd(regs, &cmd);
2245 
2246 	cmd.evt = C_HOST_STATE;
2247 	cmd.code = C_C_STACK_UP;
2248 	cmd.idx = 0;
2249 	ace_issue_cmd(regs, &cmd);
2250 
2251 	if (ap->jumbo &&
2252 	    !test_and_set_bit(0, &ap->jumbo_refill_busy))
2253 		ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE);
2254 
2255 	if (dev->flags & IFF_PROMISC) {
2256 		cmd.evt = C_SET_PROMISC_MODE;
2257 		cmd.code = C_C_PROMISC_ENABLE;
2258 		cmd.idx = 0;
2259 		ace_issue_cmd(regs, &cmd);
2260 
2261 		ap->promisc = 1;
2262 	}else
2263 		ap->promisc = 0;
2264 	ap->mcast_all = 0;
2265 
2266 #if 0
2267 	cmd.evt = C_LNK_NEGOTIATION;
2268 	cmd.code = 0;
2269 	cmd.idx = 0;
2270 	ace_issue_cmd(regs, &cmd);
2271 #endif
2272 
2273 	netif_start_queue(dev);
2274 
2275 	/*
2276 	 * Setup the bottom half rx ring refill handler
2277 	 */
2278 	tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev);
2279 	return 0;
2280 }
2281 
2282 
2283 static int ace_close(struct net_device *dev)
2284 {
2285 	struct ace_private *ap = netdev_priv(dev);
2286 	struct ace_regs __iomem *regs = ap->regs;
2287 	struct cmd cmd;
2288 	unsigned long flags;
2289 	short i;
2290 
2291 	/*
2292 	 * Without (or before) releasing irq and stopping hardware, this
2293 	 * is an absolute non-sense, by the way. It will be reset instantly
2294 	 * by the first irq.
2295 	 */
2296 	netif_stop_queue(dev);
2297 
2298 
2299 	if (ap->promisc) {
2300 		cmd.evt = C_SET_PROMISC_MODE;
2301 		cmd.code = C_C_PROMISC_DISABLE;
2302 		cmd.idx = 0;
2303 		ace_issue_cmd(regs, &cmd);
2304 		ap->promisc = 0;
2305 	}
2306 
2307 	cmd.evt = C_HOST_STATE;
2308 	cmd.code = C_C_STACK_DOWN;
2309 	cmd.idx = 0;
2310 	ace_issue_cmd(regs, &cmd);
2311 
2312 	tasklet_kill(&ap->ace_tasklet);
2313 
2314 	/*
2315 	 * Make sure one CPU is not processing packets while
2316 	 * buffers are being released by another.
2317 	 */
2318 
2319 	local_irq_save(flags);
2320 	ace_mask_irq(dev);
2321 
2322 	for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2323 		struct sk_buff *skb;
2324 		struct tx_ring_info *info;
2325 
2326 		info = ap->skb->tx_skbuff + i;
2327 		skb = info->skb;
2328 
2329 		if (dma_unmap_len(info, maplen)) {
2330 			if (ACE_IS_TIGON_I(ap)) {
2331 				/* NB: TIGON_1 is special, tx_ring is in io space */
2332 				struct tx_desc __iomem *tx;
2333 				tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
2334 				writel(0, &tx->addr.addrhi);
2335 				writel(0, &tx->addr.addrlo);
2336 				writel(0, &tx->flagsize);
2337 			} else
2338 				memset(ap->tx_ring + i, 0,
2339 				       sizeof(struct tx_desc));
2340 			pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping),
2341 				       dma_unmap_len(info, maplen),
2342 				       PCI_DMA_TODEVICE);
2343 			dma_unmap_len_set(info, maplen, 0);
2344 		}
2345 		if (skb) {
2346 			dev_kfree_skb(skb);
2347 			info->skb = NULL;
2348 		}
2349 	}
2350 
2351 	if (ap->jumbo) {
2352 		cmd.evt = C_RESET_JUMBO_RNG;
2353 		cmd.code = 0;
2354 		cmd.idx = 0;
2355 		ace_issue_cmd(regs, &cmd);
2356 	}
2357 
2358 	ace_unmask_irq(dev);
2359 	local_irq_restore(flags);
2360 
2361 	return 0;
2362 }
2363 
2364 
2365 static inline dma_addr_t
2366 ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2367 	       struct sk_buff *tail, u32 idx)
2368 {
2369 	dma_addr_t mapping;
2370 	struct tx_ring_info *info;
2371 
2372 	mapping = pci_map_page(ap->pdev, virt_to_page(skb->data),
2373 			       offset_in_page(skb->data),
2374 			       skb->len, PCI_DMA_TODEVICE);
2375 
2376 	info = ap->skb->tx_skbuff + idx;
2377 	info->skb = tail;
2378 	dma_unmap_addr_set(info, mapping, mapping);
2379 	dma_unmap_len_set(info, maplen, skb->len);
2380 	return mapping;
2381 }
2382 
2383 
2384 static inline void
2385 ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2386 	       u32 flagsize, u32 vlan_tag)
2387 {
2388 #if !USE_TX_COAL_NOW
2389 	flagsize &= ~BD_FLG_COAL_NOW;
2390 #endif
2391 
2392 	if (ACE_IS_TIGON_I(ap)) {
2393 		struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
2394 		writel(addr >> 32, &io->addr.addrhi);
2395 		writel(addr & 0xffffffff, &io->addr.addrlo);
2396 		writel(flagsize, &io->flagsize);
2397 		writel(vlan_tag, &io->vlanres);
2398 	} else {
2399 		desc->addr.addrhi = addr >> 32;
2400 		desc->addr.addrlo = addr;
2401 		desc->flagsize = flagsize;
2402 		desc->vlanres = vlan_tag;
2403 	}
2404 }
2405 
2406 
2407 static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
2408 				  struct net_device *dev)
2409 {
2410 	struct ace_private *ap = netdev_priv(dev);
2411 	struct ace_regs __iomem *regs = ap->regs;
2412 	struct tx_desc *desc;
2413 	u32 idx, flagsize;
2414 	unsigned long maxjiff = jiffies + 3*HZ;
2415 
2416 restart:
2417 	idx = ap->tx_prd;
2418 
2419 	if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2420 		goto overflow;
2421 
2422 	if (!skb_shinfo(skb)->nr_frags)	{
2423 		dma_addr_t mapping;
2424 		u32 vlan_tag = 0;
2425 
2426 		mapping = ace_map_tx_skb(ap, skb, skb, idx);
2427 		flagsize = (skb->len << 16) | (BD_FLG_END);
2428 		if (skb->ip_summed == CHECKSUM_PARTIAL)
2429 			flagsize |= BD_FLG_TCP_UDP_SUM;
2430 		if (skb_vlan_tag_present(skb)) {
2431 			flagsize |= BD_FLG_VLAN_TAG;
2432 			vlan_tag = skb_vlan_tag_get(skb);
2433 		}
2434 		desc = ap->tx_ring + idx;
2435 		idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2436 
2437 		/* Look at ace_tx_int for explanations. */
2438 		if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2439 			flagsize |= BD_FLG_COAL_NOW;
2440 
2441 		ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2442 	} else {
2443 		dma_addr_t mapping;
2444 		u32 vlan_tag = 0;
2445 		int i, len = 0;
2446 
2447 		mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2448 		flagsize = (skb_headlen(skb) << 16);
2449 		if (skb->ip_summed == CHECKSUM_PARTIAL)
2450 			flagsize |= BD_FLG_TCP_UDP_SUM;
2451 		if (skb_vlan_tag_present(skb)) {
2452 			flagsize |= BD_FLG_VLAN_TAG;
2453 			vlan_tag = skb_vlan_tag_get(skb);
2454 		}
2455 
2456 		ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2457 
2458 		idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2459 
2460 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2461 			const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2462 			struct tx_ring_info *info;
2463 
2464 			len += skb_frag_size(frag);
2465 			info = ap->skb->tx_skbuff + idx;
2466 			desc = ap->tx_ring + idx;
2467 
2468 			mapping = skb_frag_dma_map(&ap->pdev->dev, frag, 0,
2469 						   skb_frag_size(frag),
2470 						   DMA_TO_DEVICE);
2471 
2472 			flagsize = skb_frag_size(frag) << 16;
2473 			if (skb->ip_summed == CHECKSUM_PARTIAL)
2474 				flagsize |= BD_FLG_TCP_UDP_SUM;
2475 			idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2476 
2477 			if (i == skb_shinfo(skb)->nr_frags - 1) {
2478 				flagsize |= BD_FLG_END;
2479 				if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2480 					flagsize |= BD_FLG_COAL_NOW;
2481 
2482 				/*
2483 				 * Only the last fragment frees
2484 				 * the skb!
2485 				 */
2486 				info->skb = skb;
2487 			} else {
2488 				info->skb = NULL;
2489 			}
2490 			dma_unmap_addr_set(info, mapping, mapping);
2491 			dma_unmap_len_set(info, maplen, skb_frag_size(frag));
2492 			ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2493 		}
2494 	}
2495 
2496  	wmb();
2497  	ap->tx_prd = idx;
2498  	ace_set_txprd(regs, ap, idx);
2499 
2500 	if (flagsize & BD_FLG_COAL_NOW) {
2501 		netif_stop_queue(dev);
2502 
2503 		/*
2504 		 * A TX-descriptor producer (an IRQ) might have gotten
2505 		 * between, making the ring free again. Since xmit is
2506 		 * serialized, this is the only situation we have to
2507 		 * re-test.
2508 		 */
2509 		if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2510 			netif_wake_queue(dev);
2511 	}
2512 
2513 	return NETDEV_TX_OK;
2514 
2515 overflow:
2516 	/*
2517 	 * This race condition is unavoidable with lock-free drivers.
2518 	 * We wake up the queue _before_ tx_prd is advanced, so that we can
2519 	 * enter hard_start_xmit too early, while tx ring still looks closed.
2520 	 * This happens ~1-4 times per 100000 packets, so that we can allow
2521 	 * to loop syncing to other CPU. Probably, we need an additional
2522 	 * wmb() in ace_tx_intr as well.
2523 	 *
2524 	 * Note that this race is relieved by reserving one more entry
2525 	 * in tx ring than it is necessary (see original non-SG driver).
2526 	 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2527 	 * is already overkill.
2528 	 *
2529 	 * Alternative is to return with 1 not throttling queue. In this
2530 	 * case loop becomes longer, no more useful effects.
2531 	 */
2532 	if (time_before(jiffies, maxjiff)) {
2533 		barrier();
2534 		cpu_relax();
2535 		goto restart;
2536 	}
2537 
2538 	/* The ring is stuck full. */
2539 	printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2540 	return NETDEV_TX_BUSY;
2541 }
2542 
2543 
2544 static int ace_change_mtu(struct net_device *dev, int new_mtu)
2545 {
2546 	struct ace_private *ap = netdev_priv(dev);
2547 	struct ace_regs __iomem *regs = ap->regs;
2548 
2549 	writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2550 	dev->mtu = new_mtu;
2551 
2552 	if (new_mtu > ACE_STD_MTU) {
2553 		if (!(ap->jumbo)) {
2554 			printk(KERN_INFO "%s: Enabling Jumbo frame "
2555 			       "support\n", dev->name);
2556 			ap->jumbo = 1;
2557 			if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2558 				ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE);
2559 			ace_set_rxtx_parms(dev, 1);
2560 		}
2561 	} else {
2562 		while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2563 		ace_sync_irq(dev->irq);
2564 		ace_set_rxtx_parms(dev, 0);
2565 		if (ap->jumbo) {
2566 			struct cmd cmd;
2567 
2568 			cmd.evt = C_RESET_JUMBO_RNG;
2569 			cmd.code = 0;
2570 			cmd.idx = 0;
2571 			ace_issue_cmd(regs, &cmd);
2572 		}
2573 	}
2574 
2575 	return 0;
2576 }
2577 
2578 static int ace_get_link_ksettings(struct net_device *dev,
2579 				  struct ethtool_link_ksettings *cmd)
2580 {
2581 	struct ace_private *ap = netdev_priv(dev);
2582 	struct ace_regs __iomem *regs = ap->regs;
2583 	u32 link;
2584 	u32 supported;
2585 
2586 	memset(cmd, 0, sizeof(struct ethtool_link_ksettings));
2587 
2588 	supported = (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2589 		     SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2590 		     SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2591 		     SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2592 
2593 	cmd->base.port = PORT_FIBRE;
2594 
2595 	link = readl(&regs->GigLnkState);
2596 	if (link & LNK_1000MB) {
2597 		cmd->base.speed = SPEED_1000;
2598 	} else {
2599 		link = readl(&regs->FastLnkState);
2600 		if (link & LNK_100MB)
2601 			cmd->base.speed = SPEED_100;
2602 		else if (link & LNK_10MB)
2603 			cmd->base.speed = SPEED_10;
2604 		else
2605 			cmd->base.speed = 0;
2606 	}
2607 	if (link & LNK_FULL_DUPLEX)
2608 		cmd->base.duplex = DUPLEX_FULL;
2609 	else
2610 		cmd->base.duplex = DUPLEX_HALF;
2611 
2612 	if (link & LNK_NEGOTIATE)
2613 		cmd->base.autoneg = AUTONEG_ENABLE;
2614 	else
2615 		cmd->base.autoneg = AUTONEG_DISABLE;
2616 
2617 #if 0
2618 	/*
2619 	 * Current struct ethtool_cmd is insufficient
2620 	 */
2621 	ecmd->trace = readl(&regs->TuneTrace);
2622 
2623 	ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2624 	ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2625 #endif
2626 
2627 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2628 						supported);
2629 
2630 	return 0;
2631 }
2632 
2633 static int ace_set_link_ksettings(struct net_device *dev,
2634 				  const struct ethtool_link_ksettings *cmd)
2635 {
2636 	struct ace_private *ap = netdev_priv(dev);
2637 	struct ace_regs __iomem *regs = ap->regs;
2638 	u32 link, speed;
2639 
2640 	link = readl(&regs->GigLnkState);
2641 	if (link & LNK_1000MB)
2642 		speed = SPEED_1000;
2643 	else {
2644 		link = readl(&regs->FastLnkState);
2645 		if (link & LNK_100MB)
2646 			speed = SPEED_100;
2647 		else if (link & LNK_10MB)
2648 			speed = SPEED_10;
2649 		else
2650 			speed = SPEED_100;
2651 	}
2652 
2653 	link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2654 		LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2655 	if (!ACE_IS_TIGON_I(ap))
2656 		link |= LNK_TX_FLOW_CTL_Y;
2657 	if (cmd->base.autoneg == AUTONEG_ENABLE)
2658 		link |= LNK_NEGOTIATE;
2659 	if (cmd->base.speed != speed) {
2660 		link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2661 		switch (cmd->base.speed) {
2662 		case SPEED_1000:
2663 			link |= LNK_1000MB;
2664 			break;
2665 		case SPEED_100:
2666 			link |= LNK_100MB;
2667 			break;
2668 		case SPEED_10:
2669 			link |= LNK_10MB;
2670 			break;
2671 		}
2672 	}
2673 
2674 	if (cmd->base.duplex == DUPLEX_FULL)
2675 		link |= LNK_FULL_DUPLEX;
2676 
2677 	if (link != ap->link) {
2678 		struct cmd cmd;
2679 		printk(KERN_INFO "%s: Renegotiating link state\n",
2680 		       dev->name);
2681 
2682 		ap->link = link;
2683 		writel(link, &regs->TuneLink);
2684 		if (!ACE_IS_TIGON_I(ap))
2685 			writel(link, &regs->TuneFastLink);
2686 		wmb();
2687 
2688 		cmd.evt = C_LNK_NEGOTIATION;
2689 		cmd.code = 0;
2690 		cmd.idx = 0;
2691 		ace_issue_cmd(regs, &cmd);
2692 	}
2693 	return 0;
2694 }
2695 
2696 static void ace_get_drvinfo(struct net_device *dev,
2697 			    struct ethtool_drvinfo *info)
2698 {
2699 	struct ace_private *ap = netdev_priv(dev);
2700 
2701 	strlcpy(info->driver, "acenic", sizeof(info->driver));
2702 	snprintf(info->version, sizeof(info->version), "%i.%i.%i",
2703 		 ap->firmware_major, ap->firmware_minor,
2704 		 ap->firmware_fix);
2705 
2706 	if (ap->pdev)
2707 		strlcpy(info->bus_info, pci_name(ap->pdev),
2708 			sizeof(info->bus_info));
2709 
2710 }
2711 
2712 /*
2713  * Set the hardware MAC address.
2714  */
2715 static int ace_set_mac_addr(struct net_device *dev, void *p)
2716 {
2717 	struct ace_private *ap = netdev_priv(dev);
2718 	struct ace_regs __iomem *regs = ap->regs;
2719 	struct sockaddr *addr=p;
2720 	u8 *da;
2721 	struct cmd cmd;
2722 
2723 	if(netif_running(dev))
2724 		return -EBUSY;
2725 
2726 	memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2727 
2728 	da = (u8 *)dev->dev_addr;
2729 
2730 	writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2731 	writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2732 	       &regs->MacAddrLo);
2733 
2734 	cmd.evt = C_SET_MAC_ADDR;
2735 	cmd.code = 0;
2736 	cmd.idx = 0;
2737 	ace_issue_cmd(regs, &cmd);
2738 
2739 	return 0;
2740 }
2741 
2742 
2743 static void ace_set_multicast_list(struct net_device *dev)
2744 {
2745 	struct ace_private *ap = netdev_priv(dev);
2746 	struct ace_regs __iomem *regs = ap->regs;
2747 	struct cmd cmd;
2748 
2749 	if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2750 		cmd.evt = C_SET_MULTICAST_MODE;
2751 		cmd.code = C_C_MCAST_ENABLE;
2752 		cmd.idx = 0;
2753 		ace_issue_cmd(regs, &cmd);
2754 		ap->mcast_all = 1;
2755 	} else if (ap->mcast_all) {
2756 		cmd.evt = C_SET_MULTICAST_MODE;
2757 		cmd.code = C_C_MCAST_DISABLE;
2758 		cmd.idx = 0;
2759 		ace_issue_cmd(regs, &cmd);
2760 		ap->mcast_all = 0;
2761 	}
2762 
2763 	if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2764 		cmd.evt = C_SET_PROMISC_MODE;
2765 		cmd.code = C_C_PROMISC_ENABLE;
2766 		cmd.idx = 0;
2767 		ace_issue_cmd(regs, &cmd);
2768 		ap->promisc = 1;
2769 	}else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2770 		cmd.evt = C_SET_PROMISC_MODE;
2771 		cmd.code = C_C_PROMISC_DISABLE;
2772 		cmd.idx = 0;
2773 		ace_issue_cmd(regs, &cmd);
2774 		ap->promisc = 0;
2775 	}
2776 
2777 	/*
2778 	 * For the time being multicast relies on the upper layers
2779 	 * filtering it properly. The Firmware does not allow one to
2780 	 * set the entire multicast list at a time and keeping track of
2781 	 * it here is going to be messy.
2782 	 */
2783 	if (!netdev_mc_empty(dev) && !ap->mcast_all) {
2784 		cmd.evt = C_SET_MULTICAST_MODE;
2785 		cmd.code = C_C_MCAST_ENABLE;
2786 		cmd.idx = 0;
2787 		ace_issue_cmd(regs, &cmd);
2788 	}else if (!ap->mcast_all) {
2789 		cmd.evt = C_SET_MULTICAST_MODE;
2790 		cmd.code = C_C_MCAST_DISABLE;
2791 		cmd.idx = 0;
2792 		ace_issue_cmd(regs, &cmd);
2793 	}
2794 }
2795 
2796 
2797 static struct net_device_stats *ace_get_stats(struct net_device *dev)
2798 {
2799 	struct ace_private *ap = netdev_priv(dev);
2800 	struct ace_mac_stats __iomem *mac_stats =
2801 		(struct ace_mac_stats __iomem *)ap->regs->Stats;
2802 
2803 	dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2804 	dev->stats.multicast = readl(&mac_stats->kept_mc);
2805 	dev->stats.collisions = readl(&mac_stats->coll);
2806 
2807 	return &dev->stats;
2808 }
2809 
2810 
2811 static void ace_copy(struct ace_regs __iomem *regs, const __be32 *src,
2812 		     u32 dest, int size)
2813 {
2814 	void __iomem *tdest;
2815 	short tsize, i;
2816 
2817 	if (size <= 0)
2818 		return;
2819 
2820 	while (size > 0) {
2821 		tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2822 			    min_t(u32, size, ACE_WINDOW_SIZE));
2823 		tdest = (void __iomem *) &regs->Window +
2824 			(dest & (ACE_WINDOW_SIZE - 1));
2825 		writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2826 		for (i = 0; i < (tsize / 4); i++) {
2827 			/* Firmware is big-endian */
2828 			writel(be32_to_cpup(src), tdest);
2829 			src++;
2830 			tdest += 4;
2831 			dest += 4;
2832 			size -= 4;
2833 		}
2834 	}
2835 }
2836 
2837 
2838 static void ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2839 {
2840 	void __iomem *tdest;
2841 	short tsize = 0, i;
2842 
2843 	if (size <= 0)
2844 		return;
2845 
2846 	while (size > 0) {
2847 		tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2848 				min_t(u32, size, ACE_WINDOW_SIZE));
2849 		tdest = (void __iomem *) &regs->Window +
2850 			(dest & (ACE_WINDOW_SIZE - 1));
2851 		writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2852 
2853 		for (i = 0; i < (tsize / 4); i++) {
2854 			writel(0, tdest + i*4);
2855 		}
2856 
2857 		dest += tsize;
2858 		size -= tsize;
2859 	}
2860 }
2861 
2862 
2863 /*
2864  * Download the firmware into the SRAM on the NIC
2865  *
2866  * This operation requires the NIC to be halted and is performed with
2867  * interrupts disabled and with the spinlock hold.
2868  */
2869 static int ace_load_firmware(struct net_device *dev)
2870 {
2871 	const struct firmware *fw;
2872 	const char *fw_name = "acenic/tg2.bin";
2873 	struct ace_private *ap = netdev_priv(dev);
2874 	struct ace_regs __iomem *regs = ap->regs;
2875 	const __be32 *fw_data;
2876 	u32 load_addr;
2877 	int ret;
2878 
2879 	if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2880 		printk(KERN_ERR "%s: trying to download firmware while the "
2881 		       "CPU is running!\n", ap->name);
2882 		return -EFAULT;
2883 	}
2884 
2885 	if (ACE_IS_TIGON_I(ap))
2886 		fw_name = "acenic/tg1.bin";
2887 
2888 	ret = request_firmware(&fw, fw_name, &ap->pdev->dev);
2889 	if (ret) {
2890 		printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
2891 		       ap->name, fw_name);
2892 		return ret;
2893 	}
2894 
2895 	fw_data = (void *)fw->data;
2896 
2897 	/* Firmware blob starts with version numbers, followed by
2898 	   load and start address. Remainder is the blob to be loaded
2899 	   contiguously from load address. We don't bother to represent
2900 	   the BSS/SBSS sections any more, since we were clearing the
2901 	   whole thing anyway. */
2902 	ap->firmware_major = fw->data[0];
2903 	ap->firmware_minor = fw->data[1];
2904 	ap->firmware_fix = fw->data[2];
2905 
2906 	ap->firmware_start = be32_to_cpu(fw_data[1]);
2907 	if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) {
2908 		printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2909 		       ap->name, ap->firmware_start, fw_name);
2910 		ret = -EINVAL;
2911 		goto out;
2912 	}
2913 
2914 	load_addr = be32_to_cpu(fw_data[2]);
2915 	if (load_addr < 0x4000 || load_addr >= 0x80000) {
2916 		printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2917 		       ap->name, load_addr, fw_name);
2918 		ret = -EINVAL;
2919 		goto out;
2920 	}
2921 
2922 	/*
2923 	 * Do not try to clear more than 512KiB or we end up seeing
2924 	 * funny things on NICs with only 512KiB SRAM
2925 	 */
2926 	ace_clear(regs, 0x2000, 0x80000-0x2000);
2927 	ace_copy(regs, &fw_data[3], load_addr, fw->size-12);
2928  out:
2929 	release_firmware(fw);
2930 	return ret;
2931 }
2932 
2933 
2934 /*
2935  * The eeprom on the AceNIC is an Atmel i2c EEPROM.
2936  *
2937  * Accessing the EEPROM is `interesting' to say the least - don't read
2938  * this code right after dinner.
2939  *
2940  * This is all about black magic and bit-banging the device .... I
2941  * wonder in what hospital they have put the guy who designed the i2c
2942  * specs.
2943  *
2944  * Oh yes, this is only the beginning!
2945  *
2946  * Thanks to Stevarino Webinski for helping tracking down the bugs in the
2947  * code i2c readout code by beta testing all my hacks.
2948  */
2949 static void eeprom_start(struct ace_regs __iomem *regs)
2950 {
2951 	u32 local;
2952 
2953 	readl(&regs->LocalCtrl);
2954 	udelay(ACE_SHORT_DELAY);
2955 	local = readl(&regs->LocalCtrl);
2956 	local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
2957 	writel(local, &regs->LocalCtrl);
2958 	readl(&regs->LocalCtrl);
2959 	mb();
2960 	udelay(ACE_SHORT_DELAY);
2961 	local |= EEPROM_CLK_OUT;
2962 	writel(local, &regs->LocalCtrl);
2963 	readl(&regs->LocalCtrl);
2964 	mb();
2965 	udelay(ACE_SHORT_DELAY);
2966 	local &= ~EEPROM_DATA_OUT;
2967 	writel(local, &regs->LocalCtrl);
2968 	readl(&regs->LocalCtrl);
2969 	mb();
2970 	udelay(ACE_SHORT_DELAY);
2971 	local &= ~EEPROM_CLK_OUT;
2972 	writel(local, &regs->LocalCtrl);
2973 	readl(&regs->LocalCtrl);
2974 	mb();
2975 }
2976 
2977 
2978 static void eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
2979 {
2980 	short i;
2981 	u32 local;
2982 
2983 	udelay(ACE_SHORT_DELAY);
2984 	local = readl(&regs->LocalCtrl);
2985 	local &= ~EEPROM_DATA_OUT;
2986 	local |= EEPROM_WRITE_ENABLE;
2987 	writel(local, &regs->LocalCtrl);
2988 	readl(&regs->LocalCtrl);
2989 	mb();
2990 
2991 	for (i = 0; i < 8; i++, magic <<= 1) {
2992 		udelay(ACE_SHORT_DELAY);
2993 		if (magic & 0x80)
2994 			local |= EEPROM_DATA_OUT;
2995 		else
2996 			local &= ~EEPROM_DATA_OUT;
2997 		writel(local, &regs->LocalCtrl);
2998 		readl(&regs->LocalCtrl);
2999 		mb();
3000 
3001 		udelay(ACE_SHORT_DELAY);
3002 		local |= EEPROM_CLK_OUT;
3003 		writel(local, &regs->LocalCtrl);
3004 		readl(&regs->LocalCtrl);
3005 		mb();
3006 		udelay(ACE_SHORT_DELAY);
3007 		local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3008 		writel(local, &regs->LocalCtrl);
3009 		readl(&regs->LocalCtrl);
3010 		mb();
3011 	}
3012 }
3013 
3014 
3015 static int eeprom_check_ack(struct ace_regs __iomem *regs)
3016 {
3017 	int state;
3018 	u32 local;
3019 
3020 	local = readl(&regs->LocalCtrl);
3021 	local &= ~EEPROM_WRITE_ENABLE;
3022 	writel(local, &regs->LocalCtrl);
3023 	readl(&regs->LocalCtrl);
3024 	mb();
3025 	udelay(ACE_LONG_DELAY);
3026 	local |= EEPROM_CLK_OUT;
3027 	writel(local, &regs->LocalCtrl);
3028 	readl(&regs->LocalCtrl);
3029 	mb();
3030 	udelay(ACE_SHORT_DELAY);
3031 	/* sample data in middle of high clk */
3032 	state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3033 	udelay(ACE_SHORT_DELAY);
3034 	mb();
3035 	writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3036 	readl(&regs->LocalCtrl);
3037 	mb();
3038 
3039 	return state;
3040 }
3041 
3042 
3043 static void eeprom_stop(struct ace_regs __iomem *regs)
3044 {
3045 	u32 local;
3046 
3047 	udelay(ACE_SHORT_DELAY);
3048 	local = readl(&regs->LocalCtrl);
3049 	local |= EEPROM_WRITE_ENABLE;
3050 	writel(local, &regs->LocalCtrl);
3051 	readl(&regs->LocalCtrl);
3052 	mb();
3053 	udelay(ACE_SHORT_DELAY);
3054 	local &= ~EEPROM_DATA_OUT;
3055 	writel(local, &regs->LocalCtrl);
3056 	readl(&regs->LocalCtrl);
3057 	mb();
3058 	udelay(ACE_SHORT_DELAY);
3059 	local |= EEPROM_CLK_OUT;
3060 	writel(local, &regs->LocalCtrl);
3061 	readl(&regs->LocalCtrl);
3062 	mb();
3063 	udelay(ACE_SHORT_DELAY);
3064 	local |= EEPROM_DATA_OUT;
3065 	writel(local, &regs->LocalCtrl);
3066 	readl(&regs->LocalCtrl);
3067 	mb();
3068 	udelay(ACE_LONG_DELAY);
3069 	local &= ~EEPROM_CLK_OUT;
3070 	writel(local, &regs->LocalCtrl);
3071 	mb();
3072 }
3073 
3074 
3075 /*
3076  * Read a whole byte from the EEPROM.
3077  */
3078 static int read_eeprom_byte(struct net_device *dev, unsigned long offset)
3079 {
3080 	struct ace_private *ap = netdev_priv(dev);
3081 	struct ace_regs __iomem *regs = ap->regs;
3082 	unsigned long flags;
3083 	u32 local;
3084 	int result = 0;
3085 	short i;
3086 
3087 	/*
3088 	 * Don't take interrupts on this CPU will bit banging
3089 	 * the %#%#@$ I2C device
3090 	 */
3091 	local_irq_save(flags);
3092 
3093 	eeprom_start(regs);
3094 
3095 	eeprom_prep(regs, EEPROM_WRITE_SELECT);
3096 	if (eeprom_check_ack(regs)) {
3097 		local_irq_restore(flags);
3098 		printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3099 		result = -EIO;
3100 		goto eeprom_read_error;
3101 	}
3102 
3103 	eeprom_prep(regs, (offset >> 8) & 0xff);
3104 	if (eeprom_check_ack(regs)) {
3105 		local_irq_restore(flags);
3106 		printk(KERN_ERR "%s: Unable to set address byte 0\n",
3107 		       ap->name);
3108 		result = -EIO;
3109 		goto eeprom_read_error;
3110 	}
3111 
3112 	eeprom_prep(regs, offset & 0xff);
3113 	if (eeprom_check_ack(regs)) {
3114 		local_irq_restore(flags);
3115 		printk(KERN_ERR "%s: Unable to set address byte 1\n",
3116 		       ap->name);
3117 		result = -EIO;
3118 		goto eeprom_read_error;
3119 	}
3120 
3121 	eeprom_start(regs);
3122 	eeprom_prep(regs, EEPROM_READ_SELECT);
3123 	if (eeprom_check_ack(regs)) {
3124 		local_irq_restore(flags);
3125 		printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3126 		       ap->name);
3127 		result = -EIO;
3128 		goto eeprom_read_error;
3129 	}
3130 
3131 	for (i = 0; i < 8; i++) {
3132 		local = readl(&regs->LocalCtrl);
3133 		local &= ~EEPROM_WRITE_ENABLE;
3134 		writel(local, &regs->LocalCtrl);
3135 		readl(&regs->LocalCtrl);
3136 		udelay(ACE_LONG_DELAY);
3137 		mb();
3138 		local |= EEPROM_CLK_OUT;
3139 		writel(local, &regs->LocalCtrl);
3140 		readl(&regs->LocalCtrl);
3141 		mb();
3142 		udelay(ACE_SHORT_DELAY);
3143 		/* sample data mid high clk */
3144 		result = (result << 1) |
3145 			((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3146 		udelay(ACE_SHORT_DELAY);
3147 		mb();
3148 		local = readl(&regs->LocalCtrl);
3149 		local &= ~EEPROM_CLK_OUT;
3150 		writel(local, &regs->LocalCtrl);
3151 		readl(&regs->LocalCtrl);
3152 		udelay(ACE_SHORT_DELAY);
3153 		mb();
3154 		if (i == 7) {
3155 			local |= EEPROM_WRITE_ENABLE;
3156 			writel(local, &regs->LocalCtrl);
3157 			readl(&regs->LocalCtrl);
3158 			mb();
3159 			udelay(ACE_SHORT_DELAY);
3160 		}
3161 	}
3162 
3163 	local |= EEPROM_DATA_OUT;
3164 	writel(local, &regs->LocalCtrl);
3165 	readl(&regs->LocalCtrl);
3166 	mb();
3167 	udelay(ACE_SHORT_DELAY);
3168 	writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3169 	readl(&regs->LocalCtrl);
3170 	udelay(ACE_LONG_DELAY);
3171 	writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3172 	readl(&regs->LocalCtrl);
3173 	mb();
3174 	udelay(ACE_SHORT_DELAY);
3175 	eeprom_stop(regs);
3176 
3177 	local_irq_restore(flags);
3178  out:
3179 	return result;
3180 
3181  eeprom_read_error:
3182 	printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3183 	       ap->name, offset);
3184 	goto out;
3185 }
3186 
3187 module_pci_driver(acenic_pci_driver);
3188