1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
4  *           and other Tigon based cards.
5  *
6  * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
7  *
8  * Thanks to Alteon and 3Com for providing hardware and documentation
9  * enabling me to write this driver.
10  *
11  * A mailing list for discussing the use of this driver has been
12  * setup, please subscribe to the lists if you have any questions
13  * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to
14  * see how to subscribe.
15  *
16  * Additional credits:
17  *   Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace
18  *       dump support. The trace dump support has not been
19  *       integrated yet however.
20  *   Troy Benjegerdes: Big Endian (PPC) patches.
21  *   Nate Stahl: Better out of memory handling and stats support.
22  *   Aman Singla: Nasty race between interrupt handler and tx code dealing
23  *                with 'testing the tx_ret_csm and setting tx_full'
24  *   David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping
25  *                                       infrastructure and Sparc support
26  *   Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
27  *                              driver under Linux/Sparc64
28  *   Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
29  *                                       ETHTOOL_GDRVINFO support
30  *   Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
31  *                                       handler and close() cleanup.
32  *   Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
33  *                                       memory mapped IO is enabled to
34  *                                       make the driver work on RS/6000.
35  *   Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem
36  *                                       where the driver would disable
37  *                                       bus master mode if it had to disable
38  *                                       write and invalidate.
39  *   Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little
40  *                                       endian systems.
41  *   Val Henson <vhenson@esscom.com>:    Reset Jumbo skb producer and
42  *                                       rx producer index when
43  *                                       flushing the Jumbo ring.
44  *   Hans Grobler <grobh@sun.ac.za>:     Memory leak fixes in the
45  *                                       driver init path.
46  *   Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes.
47  */
48 
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/types.h>
52 #include <linux/errno.h>
53 #include <linux/ioport.h>
54 #include <linux/pci.h>
55 #include <linux/dma-mapping.h>
56 #include <linux/kernel.h>
57 #include <linux/netdevice.h>
58 #include <linux/etherdevice.h>
59 #include <linux/skbuff.h>
60 #include <linux/delay.h>
61 #include <linux/mm.h>
62 #include <linux/highmem.h>
63 #include <linux/sockios.h>
64 #include <linux/firmware.h>
65 #include <linux/slab.h>
66 #include <linux/prefetch.h>
67 #include <linux/if_vlan.h>
68 
69 #ifdef SIOCETHTOOL
70 #include <linux/ethtool.h>
71 #endif
72 
73 #include <net/sock.h>
74 #include <net/ip.h>
75 
76 #include <asm/io.h>
77 #include <asm/irq.h>
78 #include <asm/byteorder.h>
79 #include <linux/uaccess.h>
80 
81 
82 #define DRV_NAME "acenic"
83 
84 #undef INDEX_DEBUG
85 
86 #ifdef CONFIG_ACENIC_OMIT_TIGON_I
87 #define ACE_IS_TIGON_I(ap)	0
88 #define ACE_TX_RING_ENTRIES(ap)	MAX_TX_RING_ENTRIES
89 #else
90 #define ACE_IS_TIGON_I(ap)	(ap->version == 1)
91 #define ACE_TX_RING_ENTRIES(ap)	ap->tx_ring_entries
92 #endif
93 
94 #ifndef PCI_VENDOR_ID_ALTEON
95 #define PCI_VENDOR_ID_ALTEON		0x12ae
96 #endif
97 #ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE
98 #define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE  0x0001
99 #define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002
100 #endif
101 #ifndef PCI_DEVICE_ID_3COM_3C985
102 #define PCI_DEVICE_ID_3COM_3C985	0x0001
103 #endif
104 #ifndef PCI_VENDOR_ID_NETGEAR
105 #define PCI_VENDOR_ID_NETGEAR		0x1385
106 #define PCI_DEVICE_ID_NETGEAR_GA620	0x620a
107 #endif
108 #ifndef PCI_DEVICE_ID_NETGEAR_GA620T
109 #define PCI_DEVICE_ID_NETGEAR_GA620T	0x630a
110 #endif
111 
112 
113 /*
114  * Farallon used the DEC vendor ID by mistake and they seem not
115  * to care - stinky!
116  */
117 #ifndef PCI_DEVICE_ID_FARALLON_PN9000SX
118 #define PCI_DEVICE_ID_FARALLON_PN9000SX	0x1a
119 #endif
120 #ifndef PCI_DEVICE_ID_FARALLON_PN9100T
121 #define PCI_DEVICE_ID_FARALLON_PN9100T  0xfa
122 #endif
123 #ifndef PCI_VENDOR_ID_SGI
124 #define PCI_VENDOR_ID_SGI		0x10a9
125 #endif
126 #ifndef PCI_DEVICE_ID_SGI_ACENIC
127 #define PCI_DEVICE_ID_SGI_ACENIC	0x0009
128 #endif
129 
130 static const struct pci_device_id acenic_pci_tbl[] = {
131 	{ PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE,
132 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
133 	{ PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER,
134 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
135 	{ PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985,
136 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
137 	{ PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620,
138 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
139 	{ PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T,
140 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
141 	/*
142 	 * Farallon used the DEC vendor ID on their cards incorrectly,
143 	 * then later Alteon's ID.
144 	 */
145 	{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX,
146 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
147 	{ PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T,
148 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
149 	{ PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC,
150 	  PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, },
151 	{ }
152 };
153 MODULE_DEVICE_TABLE(pci, acenic_pci_tbl);
154 
155 #define ace_sync_irq(irq)	synchronize_irq(irq)
156 
157 #ifndef offset_in_page
158 #define offset_in_page(ptr)	((unsigned long)(ptr) & ~PAGE_MASK)
159 #endif
160 
161 #define ACE_MAX_MOD_PARMS	8
162 #define BOARD_IDX_STATIC	0
163 #define BOARD_IDX_OVERFLOW	-1
164 
165 #include "acenic.h"
166 
167 /*
168  * These must be defined before the firmware is included.
169  */
170 #define MAX_TEXT_LEN	96*1024
171 #define MAX_RODATA_LEN	8*1024
172 #define MAX_DATA_LEN	2*1024
173 
174 #ifndef tigon2FwReleaseLocal
175 #define tigon2FwReleaseLocal 0
176 #endif
177 
178 /*
179  * This driver currently supports Tigon I and Tigon II based cards
180  * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear
181  * GA620. The driver should also work on the SGI, DEC and Farallon
182  * versions of the card, however I have not been able to test that
183  * myself.
184  *
185  * This card is really neat, it supports receive hardware checksumming
186  * and jumbo frames (up to 9000 bytes) and does a lot of work in the
187  * firmware. Also the programming interface is quite neat, except for
188  * the parts dealing with the i2c eeprom on the card ;-)
189  *
190  * Using jumbo frames:
191  *
192  * To enable jumbo frames, simply specify an mtu between 1500 and 9000
193  * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time
194  * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet
195  * interface number and <MTU> being the MTU value.
196  *
197  * Module parameters:
198  *
199  * When compiled as a loadable module, the driver allows for a number
200  * of module parameters to be specified. The driver supports the
201  * following module parameters:
202  *
203  *  trace=<val> - Firmware trace level. This requires special traced
204  *                firmware to replace the firmware supplied with
205  *                the driver - for debugging purposes only.
206  *
207  *  link=<val>  - Link state. Normally you want to use the default link
208  *                parameters set by the driver. This can be used to
209  *                override these in case your switch doesn't negotiate
210  *                the link properly. Valid values are:
211  *         0x0001 - Force half duplex link.
212  *         0x0002 - Do not negotiate line speed with the other end.
213  *         0x0010 - 10Mbit/sec link.
214  *         0x0020 - 100Mbit/sec link.
215  *         0x0040 - 1000Mbit/sec link.
216  *         0x0100 - Do not negotiate flow control.
217  *         0x0200 - Enable RX flow control Y
218  *         0x0400 - Enable TX flow control Y (Tigon II NICs only).
219  *                Default value is 0x0270, ie. enable link+flow
220  *                control negotiation. Negotiating the highest
221  *                possible link speed with RX flow control enabled.
222  *
223  *                When disabling link speed negotiation, only one link
224  *                speed is allowed to be specified!
225  *
226  *  tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
227  *                to wait for more packets to arive before
228  *                interrupting the host, from the time the first
229  *                packet arrives.
230  *
231  *  rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed
232  *                to wait for more packets to arive in the transmit ring,
233  *                before interrupting the host, after transmitting the
234  *                first packet in the ring.
235  *
236  *  max_tx_desc=<val> - maximum number of transmit descriptors
237  *                (packets) transmitted before interrupting the host.
238  *
239  *  max_rx_desc=<val> - maximum number of receive descriptors
240  *                (packets) received before interrupting the host.
241  *
242  *  tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th
243  *                increments of the NIC's on board memory to be used for
244  *                transmit and receive buffers. For the 1MB NIC app. 800KB
245  *                is available, on the 1/2MB NIC app. 300KB is available.
246  *                68KB will always be available as a minimum for both
247  *                directions. The default value is a 50/50 split.
248  *  dis_pci_mem_inval=<val> - disable PCI memory write and invalidate
249  *                operations, default (1) is to always disable this as
250  *                that is what Alteon does on NT. I have not been able
251  *                to measure any real performance differences with
252  *                this on my systems. Set <val>=0 if you want to
253  *                enable these operations.
254  *
255  * If you use more than one NIC, specify the parameters for the
256  * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to
257  * run tracing on NIC #2 but not on NIC #1 and #3.
258  *
259  * TODO:
260  *
261  * - Proper multicast support.
262  * - NIC dump support.
263  * - More tuning parameters.
264  *
265  * The mini ring is not used under Linux and I am not sure it makes sense
266  * to actually use it.
267  *
268  * New interrupt handler strategy:
269  *
270  * The old interrupt handler worked using the traditional method of
271  * replacing an skbuff with a new one when a packet arrives. However
272  * the rx rings do not need to contain a static number of buffer
273  * descriptors, thus it makes sense to move the memory allocation out
274  * of the main interrupt handler and do it in a bottom half handler
275  * and only allocate new buffers when the number of buffers in the
276  * ring is below a certain threshold. In order to avoid starving the
277  * NIC under heavy load it is however necessary to force allocation
278  * when hitting a minimum threshold. The strategy for alloction is as
279  * follows:
280  *
281  *     RX_LOW_BUF_THRES    - allocate buffers in the bottom half
282  *     RX_PANIC_LOW_THRES  - we are very low on buffers, allocate
283  *                           the buffers in the interrupt handler
284  *     RX_RING_THRES       - maximum number of buffers in the rx ring
285  *     RX_MINI_THRES       - maximum number of buffers in the mini ring
286  *     RX_JUMBO_THRES      - maximum number of buffers in the jumbo ring
287  *
288  * One advantagous side effect of this allocation approach is that the
289  * entire rx processing can be done without holding any spin lock
290  * since the rx rings and registers are totally independent of the tx
291  * ring and its registers.  This of course includes the kmalloc's of
292  * new skb's. Thus start_xmit can run in parallel with rx processing
293  * and the memory allocation on SMP systems.
294  *
295  * Note that running the skb reallocation in a bottom half opens up
296  * another can of races which needs to be handled properly. In
297  * particular it can happen that the interrupt handler tries to run
298  * the reallocation while the bottom half is either running on another
299  * CPU or was interrupted on the same CPU. To get around this the
300  * driver uses bitops to prevent the reallocation routines from being
301  * reentered.
302  *
303  * TX handling can also be done without holding any spin lock, wheee
304  * this is fun! since tx_ret_csm is only written to by the interrupt
305  * handler. The case to be aware of is when shutting down the device
306  * and cleaning up where it is necessary to make sure that
307  * start_xmit() is not running while this is happening. Well DaveM
308  * informs me that this case is already protected against ... bye bye
309  * Mr. Spin Lock, it was nice to know you.
310  *
311  * TX interrupts are now partly disabled so the NIC will only generate
312  * TX interrupts for the number of coal ticks, not for the number of
313  * TX packets in the queue. This should reduce the number of TX only,
314  * ie. when no RX processing is done, interrupts seen.
315  */
316 
317 /*
318  * Threshold values for RX buffer allocation - the low water marks for
319  * when to start refilling the rings are set to 75% of the ring
320  * sizes. It seems to make sense to refill the rings entirely from the
321  * intrrupt handler once it gets below the panic threshold, that way
322  * we don't risk that the refilling is moved to another CPU when the
323  * one running the interrupt handler just got the slab code hot in its
324  * cache.
325  */
326 #define RX_RING_SIZE		72
327 #define RX_MINI_SIZE		64
328 #define RX_JUMBO_SIZE		48
329 
330 #define RX_PANIC_STD_THRES	16
331 #define RX_PANIC_STD_REFILL	(3*RX_PANIC_STD_THRES)/2
332 #define RX_LOW_STD_THRES	(3*RX_RING_SIZE)/4
333 #define RX_PANIC_MINI_THRES	12
334 #define RX_PANIC_MINI_REFILL	(3*RX_PANIC_MINI_THRES)/2
335 #define RX_LOW_MINI_THRES	(3*RX_MINI_SIZE)/4
336 #define RX_PANIC_JUMBO_THRES	6
337 #define RX_PANIC_JUMBO_REFILL	(3*RX_PANIC_JUMBO_THRES)/2
338 #define RX_LOW_JUMBO_THRES	(3*RX_JUMBO_SIZE)/4
339 
340 
341 /*
342  * Size of the mini ring entries, basically these just should be big
343  * enough to take TCP ACKs
344  */
345 #define ACE_MINI_SIZE		100
346 
347 #define ACE_MINI_BUFSIZE	ACE_MINI_SIZE
348 #define ACE_STD_BUFSIZE		(ACE_STD_MTU + ETH_HLEN + 4)
349 #define ACE_JUMBO_BUFSIZE	(ACE_JUMBO_MTU + ETH_HLEN + 4)
350 
351 /*
352  * There seems to be a magic difference in the effect between 995 and 996
353  * but little difference between 900 and 995 ... no idea why.
354  *
355  * There is now a default set of tuning parameters which is set, depending
356  * on whether or not the user enables Jumbo frames. It's assumed that if
357  * Jumbo frames are enabled, the user wants optimal tuning for that case.
358  */
359 #define DEF_TX_COAL		400 /* 996 */
360 #define DEF_TX_MAX_DESC		60  /* was 40 */
361 #define DEF_RX_COAL		120 /* 1000 */
362 #define DEF_RX_MAX_DESC		25
363 #define DEF_TX_RATIO		21 /* 24 */
364 
365 #define DEF_JUMBO_TX_COAL	20
366 #define DEF_JUMBO_TX_MAX_DESC	60
367 #define DEF_JUMBO_RX_COAL	30
368 #define DEF_JUMBO_RX_MAX_DESC	6
369 #define DEF_JUMBO_TX_RATIO	21
370 
371 #if tigon2FwReleaseLocal < 20001118
372 /*
373  * Standard firmware and early modifications duplicate
374  * IRQ load without this flag (coal timer is never reset).
375  * Note that with this flag tx_coal should be less than
376  * time to xmit full tx ring.
377  * 400usec is not so bad for tx ring size of 128.
378  */
379 #define TX_COAL_INTS_ONLY	1	/* worth it */
380 #else
381 /*
382  * With modified firmware, this is not necessary, but still useful.
383  */
384 #define TX_COAL_INTS_ONLY	1
385 #endif
386 
387 #define DEF_TRACE		0
388 #define DEF_STAT		(2 * TICKS_PER_SEC)
389 
390 
391 static int link_state[ACE_MAX_MOD_PARMS];
392 static int trace[ACE_MAX_MOD_PARMS];
393 static int tx_coal_tick[ACE_MAX_MOD_PARMS];
394 static int rx_coal_tick[ACE_MAX_MOD_PARMS];
395 static int max_tx_desc[ACE_MAX_MOD_PARMS];
396 static int max_rx_desc[ACE_MAX_MOD_PARMS];
397 static int tx_ratio[ACE_MAX_MOD_PARMS];
398 static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
399 
400 MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>");
401 MODULE_LICENSE("GPL");
402 MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver");
403 #ifndef CONFIG_ACENIC_OMIT_TIGON_I
404 MODULE_FIRMWARE("acenic/tg1.bin");
405 #endif
406 MODULE_FIRMWARE("acenic/tg2.bin");
407 
408 module_param_array_named(link, link_state, int, NULL, 0);
409 module_param_array(trace, int, NULL, 0);
410 module_param_array(tx_coal_tick, int, NULL, 0);
411 module_param_array(max_tx_desc, int, NULL, 0);
412 module_param_array(rx_coal_tick, int, NULL, 0);
413 module_param_array(max_rx_desc, int, NULL, 0);
414 module_param_array(tx_ratio, int, NULL, 0);
415 MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state");
416 MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level");
417 MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives");
418 MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait");
419 MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives");
420 MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait");
421 MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)");
422 
423 
424 static const char version[] =
425   "acenic.c: v0.92 08/05/2002  Jes Sorensen, linux-acenic@SunSITE.dk\n"
426   "                            http://home.cern.ch/~jes/gige/acenic.html\n";
427 
428 static int ace_get_link_ksettings(struct net_device *,
429 				  struct ethtool_link_ksettings *);
430 static int ace_set_link_ksettings(struct net_device *,
431 				  const struct ethtool_link_ksettings *);
432 static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *);
433 
434 static const struct ethtool_ops ace_ethtool_ops = {
435 	.get_drvinfo = ace_get_drvinfo,
436 	.get_link_ksettings = ace_get_link_ksettings,
437 	.set_link_ksettings = ace_set_link_ksettings,
438 };
439 
440 static void ace_watchdog(struct net_device *dev, unsigned int txqueue);
441 
442 static const struct net_device_ops ace_netdev_ops = {
443 	.ndo_open		= ace_open,
444 	.ndo_stop		= ace_close,
445 	.ndo_tx_timeout		= ace_watchdog,
446 	.ndo_get_stats		= ace_get_stats,
447 	.ndo_start_xmit		= ace_start_xmit,
448 	.ndo_set_rx_mode	= ace_set_multicast_list,
449 	.ndo_validate_addr	= eth_validate_addr,
450 	.ndo_set_mac_address	= ace_set_mac_addr,
451 	.ndo_change_mtu		= ace_change_mtu,
452 };
453 
454 static int acenic_probe_one(struct pci_dev *pdev,
455 			    const struct pci_device_id *id)
456 {
457 	struct net_device *dev;
458 	struct ace_private *ap;
459 	static int boards_found;
460 
461 	dev = alloc_etherdev(sizeof(struct ace_private));
462 	if (dev == NULL)
463 		return -ENOMEM;
464 
465 	SET_NETDEV_DEV(dev, &pdev->dev);
466 
467 	ap = netdev_priv(dev);
468 	ap->ndev = dev;
469 	ap->pdev = pdev;
470 	ap->name = pci_name(pdev);
471 
472 	dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
473 	dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
474 
475 	dev->watchdog_timeo = 5*HZ;
476 	dev->min_mtu = 0;
477 	dev->max_mtu = ACE_JUMBO_MTU;
478 
479 	dev->netdev_ops = &ace_netdev_ops;
480 	dev->ethtool_ops = &ace_ethtool_ops;
481 
482 	/* we only display this string ONCE */
483 	if (!boards_found)
484 		printk(version);
485 
486 	if (pci_enable_device(pdev))
487 		goto fail_free_netdev;
488 
489 	/*
490 	 * Enable master mode before we start playing with the
491 	 * pci_command word since pci_set_master() will modify
492 	 * it.
493 	 */
494 	pci_set_master(pdev);
495 
496 	pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command);
497 
498 	/* OpenFirmware on Mac's does not set this - DOH.. */
499 	if (!(ap->pci_command & PCI_COMMAND_MEMORY)) {
500 		printk(KERN_INFO "%s: Enabling PCI Memory Mapped "
501 		       "access - was not enabled by BIOS/Firmware\n",
502 		       ap->name);
503 		ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY;
504 		pci_write_config_word(ap->pdev, PCI_COMMAND,
505 				      ap->pci_command);
506 		wmb();
507 	}
508 
509 	pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency);
510 	if (ap->pci_latency <= 0x40) {
511 		ap->pci_latency = 0x40;
512 		pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency);
513 	}
514 
515 	/*
516 	 * Remap the regs into kernel space - this is abuse of
517 	 * dev->base_addr since it was means for I/O port
518 	 * addresses but who gives a damn.
519 	 */
520 	dev->base_addr = pci_resource_start(pdev, 0);
521 	ap->regs = ioremap(dev->base_addr, 0x4000);
522 	if (!ap->regs) {
523 		printk(KERN_ERR "%s:  Unable to map I/O register, "
524 		       "AceNIC %i will be disabled.\n",
525 		       ap->name, boards_found);
526 		goto fail_free_netdev;
527 	}
528 
529 	switch(pdev->vendor) {
530 	case PCI_VENDOR_ID_ALTEON:
531 		if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) {
532 			printk(KERN_INFO "%s: Farallon PN9100-T ",
533 			       ap->name);
534 		} else {
535 			printk(KERN_INFO "%s: Alteon AceNIC ",
536 			       ap->name);
537 		}
538 		break;
539 	case PCI_VENDOR_ID_3COM:
540 		printk(KERN_INFO "%s: 3Com 3C985 ", ap->name);
541 		break;
542 	case PCI_VENDOR_ID_NETGEAR:
543 		printk(KERN_INFO "%s: NetGear GA620 ", ap->name);
544 		break;
545 	case PCI_VENDOR_ID_DEC:
546 		if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) {
547 			printk(KERN_INFO "%s: Farallon PN9000-SX ",
548 			       ap->name);
549 			break;
550 		}
551 		fallthrough;
552 	case PCI_VENDOR_ID_SGI:
553 		printk(KERN_INFO "%s: SGI AceNIC ", ap->name);
554 		break;
555 	default:
556 		printk(KERN_INFO "%s: Unknown AceNIC ", ap->name);
557 		break;
558 	}
559 
560 	printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
561 	printk("irq %d\n", pdev->irq);
562 
563 #ifdef CONFIG_ACENIC_OMIT_TIGON_I
564 	if ((readl(&ap->regs->HostCtrl) >> 28) == 4) {
565 		printk(KERN_ERR "%s: Driver compiled without Tigon I"
566 		       " support - NIC disabled\n", dev->name);
567 		goto fail_uninit;
568 	}
569 #endif
570 
571 	if (ace_allocate_descriptors(dev))
572 		goto fail_free_netdev;
573 
574 #ifdef MODULE
575 	if (boards_found >= ACE_MAX_MOD_PARMS)
576 		ap->board_idx = BOARD_IDX_OVERFLOW;
577 	else
578 		ap->board_idx = boards_found;
579 #else
580 	ap->board_idx = BOARD_IDX_STATIC;
581 #endif
582 
583 	if (ace_init(dev))
584 		goto fail_free_netdev;
585 
586 	if (register_netdev(dev)) {
587 		printk(KERN_ERR "acenic: device registration failed\n");
588 		goto fail_uninit;
589 	}
590 	ap->name = dev->name;
591 
592 	if (ap->pci_using_dac)
593 		dev->features |= NETIF_F_HIGHDMA;
594 
595 	pci_set_drvdata(pdev, dev);
596 
597 	boards_found++;
598 	return 0;
599 
600  fail_uninit:
601 	ace_init_cleanup(dev);
602  fail_free_netdev:
603 	free_netdev(dev);
604 	return -ENODEV;
605 }
606 
607 static void acenic_remove_one(struct pci_dev *pdev)
608 {
609 	struct net_device *dev = pci_get_drvdata(pdev);
610 	struct ace_private *ap = netdev_priv(dev);
611 	struct ace_regs __iomem *regs = ap->regs;
612 	short i;
613 
614 	unregister_netdev(dev);
615 
616 	writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
617 	if (ap->version >= 2)
618 		writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
619 
620 	/*
621 	 * This clears any pending interrupts
622 	 */
623 	writel(1, &regs->Mb0Lo);
624 	readl(&regs->CpuCtrl);	/* flush */
625 
626 	/*
627 	 * Make sure no other CPUs are processing interrupts
628 	 * on the card before the buffers are being released.
629 	 * Otherwise one might experience some `interesting'
630 	 * effects.
631 	 *
632 	 * Then release the RX buffers - jumbo buffers were
633 	 * already released in ace_close().
634 	 */
635 	ace_sync_irq(dev->irq);
636 
637 	for (i = 0; i < RX_STD_RING_ENTRIES; i++) {
638 		struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb;
639 
640 		if (skb) {
641 			struct ring_info *ringp;
642 			dma_addr_t mapping;
643 
644 			ringp = &ap->skb->rx_std_skbuff[i];
645 			mapping = dma_unmap_addr(ringp, mapping);
646 			dma_unmap_page(&ap->pdev->dev, mapping,
647 				       ACE_STD_BUFSIZE, DMA_FROM_DEVICE);
648 
649 			ap->rx_std_ring[i].size = 0;
650 			ap->skb->rx_std_skbuff[i].skb = NULL;
651 			dev_kfree_skb(skb);
652 		}
653 	}
654 
655 	if (ap->version >= 2) {
656 		for (i = 0; i < RX_MINI_RING_ENTRIES; i++) {
657 			struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb;
658 
659 			if (skb) {
660 				struct ring_info *ringp;
661 				dma_addr_t mapping;
662 
663 				ringp = &ap->skb->rx_mini_skbuff[i];
664 				mapping = dma_unmap_addr(ringp,mapping);
665 				dma_unmap_page(&ap->pdev->dev, mapping,
666 					       ACE_MINI_BUFSIZE,
667 					       DMA_FROM_DEVICE);
668 
669 				ap->rx_mini_ring[i].size = 0;
670 				ap->skb->rx_mini_skbuff[i].skb = NULL;
671 				dev_kfree_skb(skb);
672 			}
673 		}
674 	}
675 
676 	for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
677 		struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb;
678 		if (skb) {
679 			struct ring_info *ringp;
680 			dma_addr_t mapping;
681 
682 			ringp = &ap->skb->rx_jumbo_skbuff[i];
683 			mapping = dma_unmap_addr(ringp, mapping);
684 			dma_unmap_page(&ap->pdev->dev, mapping,
685 				       ACE_JUMBO_BUFSIZE, DMA_FROM_DEVICE);
686 
687 			ap->rx_jumbo_ring[i].size = 0;
688 			ap->skb->rx_jumbo_skbuff[i].skb = NULL;
689 			dev_kfree_skb(skb);
690 		}
691 	}
692 
693 	ace_init_cleanup(dev);
694 	free_netdev(dev);
695 }
696 
697 static struct pci_driver acenic_pci_driver = {
698 	.name		= "acenic",
699 	.id_table	= acenic_pci_tbl,
700 	.probe		= acenic_probe_one,
701 	.remove		= acenic_remove_one,
702 };
703 
704 static void ace_free_descriptors(struct net_device *dev)
705 {
706 	struct ace_private *ap = netdev_priv(dev);
707 	int size;
708 
709 	if (ap->rx_std_ring != NULL) {
710 		size = (sizeof(struct rx_desc) *
711 			(RX_STD_RING_ENTRIES +
712 			 RX_JUMBO_RING_ENTRIES +
713 			 RX_MINI_RING_ENTRIES +
714 			 RX_RETURN_RING_ENTRIES));
715 		dma_free_coherent(&ap->pdev->dev, size, ap->rx_std_ring,
716 				  ap->rx_ring_base_dma);
717 		ap->rx_std_ring = NULL;
718 		ap->rx_jumbo_ring = NULL;
719 		ap->rx_mini_ring = NULL;
720 		ap->rx_return_ring = NULL;
721 	}
722 	if (ap->evt_ring != NULL) {
723 		size = (sizeof(struct event) * EVT_RING_ENTRIES);
724 		dma_free_coherent(&ap->pdev->dev, size, ap->evt_ring,
725 				  ap->evt_ring_dma);
726 		ap->evt_ring = NULL;
727 	}
728 	if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
729 		size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
730 		dma_free_coherent(&ap->pdev->dev, size, ap->tx_ring,
731 				  ap->tx_ring_dma);
732 	}
733 	ap->tx_ring = NULL;
734 
735 	if (ap->evt_prd != NULL) {
736 		dma_free_coherent(&ap->pdev->dev, sizeof(u32),
737 				  (void *)ap->evt_prd, ap->evt_prd_dma);
738 		ap->evt_prd = NULL;
739 	}
740 	if (ap->rx_ret_prd != NULL) {
741 		dma_free_coherent(&ap->pdev->dev, sizeof(u32),
742 				  (void *)ap->rx_ret_prd, ap->rx_ret_prd_dma);
743 		ap->rx_ret_prd = NULL;
744 	}
745 	if (ap->tx_csm != NULL) {
746 		dma_free_coherent(&ap->pdev->dev, sizeof(u32),
747 				  (void *)ap->tx_csm, ap->tx_csm_dma);
748 		ap->tx_csm = NULL;
749 	}
750 }
751 
752 
753 static int ace_allocate_descriptors(struct net_device *dev)
754 {
755 	struct ace_private *ap = netdev_priv(dev);
756 	int size;
757 
758 	size = (sizeof(struct rx_desc) *
759 		(RX_STD_RING_ENTRIES +
760 		 RX_JUMBO_RING_ENTRIES +
761 		 RX_MINI_RING_ENTRIES +
762 		 RX_RETURN_RING_ENTRIES));
763 
764 	ap->rx_std_ring = dma_alloc_coherent(&ap->pdev->dev, size,
765 					     &ap->rx_ring_base_dma, GFP_KERNEL);
766 	if (ap->rx_std_ring == NULL)
767 		goto fail;
768 
769 	ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES;
770 	ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES;
771 	ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES;
772 
773 	size = (sizeof(struct event) * EVT_RING_ENTRIES);
774 
775 	ap->evt_ring = dma_alloc_coherent(&ap->pdev->dev, size,
776 					  &ap->evt_ring_dma, GFP_KERNEL);
777 
778 	if (ap->evt_ring == NULL)
779 		goto fail;
780 
781 	/*
782 	 * Only allocate a host TX ring for the Tigon II, the Tigon I
783 	 * has to use PCI registers for this ;-(
784 	 */
785 	if (!ACE_IS_TIGON_I(ap)) {
786 		size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
787 
788 		ap->tx_ring = dma_alloc_coherent(&ap->pdev->dev, size,
789 						 &ap->tx_ring_dma, GFP_KERNEL);
790 
791 		if (ap->tx_ring == NULL)
792 			goto fail;
793 	}
794 
795 	ap->evt_prd = dma_alloc_coherent(&ap->pdev->dev, sizeof(u32),
796 					 &ap->evt_prd_dma, GFP_KERNEL);
797 	if (ap->evt_prd == NULL)
798 		goto fail;
799 
800 	ap->rx_ret_prd = dma_alloc_coherent(&ap->pdev->dev, sizeof(u32),
801 					    &ap->rx_ret_prd_dma, GFP_KERNEL);
802 	if (ap->rx_ret_prd == NULL)
803 		goto fail;
804 
805 	ap->tx_csm = dma_alloc_coherent(&ap->pdev->dev, sizeof(u32),
806 					&ap->tx_csm_dma, GFP_KERNEL);
807 	if (ap->tx_csm == NULL)
808 		goto fail;
809 
810 	return 0;
811 
812 fail:
813 	/* Clean up. */
814 	ace_init_cleanup(dev);
815 	return 1;
816 }
817 
818 
819 /*
820  * Generic cleanup handling data allocated during init. Used when the
821  * module is unloaded or if an error occurs during initialization
822  */
823 static void ace_init_cleanup(struct net_device *dev)
824 {
825 	struct ace_private *ap;
826 
827 	ap = netdev_priv(dev);
828 
829 	ace_free_descriptors(dev);
830 
831 	if (ap->info)
832 		dma_free_coherent(&ap->pdev->dev, sizeof(struct ace_info),
833 				  ap->info, ap->info_dma);
834 	kfree(ap->skb);
835 	kfree(ap->trace_buf);
836 
837 	if (dev->irq)
838 		free_irq(dev->irq, dev);
839 
840 	iounmap(ap->regs);
841 }
842 
843 
844 /*
845  * Commands are considered to be slow.
846  */
847 static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd)
848 {
849 	u32 idx;
850 
851 	idx = readl(&regs->CmdPrd);
852 
853 	writel(*(u32 *)(cmd), &regs->CmdRng[idx]);
854 	idx = (idx + 1) % CMD_RING_ENTRIES;
855 
856 	writel(idx, &regs->CmdPrd);
857 }
858 
859 
860 static int ace_init(struct net_device *dev)
861 {
862 	struct ace_private *ap;
863 	struct ace_regs __iomem *regs;
864 	struct ace_info *info = NULL;
865 	struct pci_dev *pdev;
866 	unsigned long myjif;
867 	u64 tmp_ptr;
868 	u32 tig_ver, mac1, mac2, tmp, pci_state;
869 	int board_idx, ecode = 0;
870 	short i;
871 	unsigned char cache_size;
872 
873 	ap = netdev_priv(dev);
874 	regs = ap->regs;
875 
876 	board_idx = ap->board_idx;
877 
878 	/*
879 	 * aman@sgi.com - its useful to do a NIC reset here to
880 	 * address the `Firmware not running' problem subsequent
881 	 * to any crashes involving the NIC
882 	 */
883 	writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl);
884 	readl(&regs->HostCtrl);		/* PCI write posting */
885 	udelay(5);
886 
887 	/*
888 	 * Don't access any other registers before this point!
889 	 */
890 #ifdef __BIG_ENDIAN
891 	/*
892 	 * This will most likely need BYTE_SWAP once we switch
893 	 * to using __raw_writel()
894 	 */
895 	writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)),
896 	       &regs->HostCtrl);
897 #else
898 	writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)),
899 	       &regs->HostCtrl);
900 #endif
901 	readl(&regs->HostCtrl);		/* PCI write posting */
902 
903 	/*
904 	 * Stop the NIC CPU and clear pending interrupts
905 	 */
906 	writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
907 	readl(&regs->CpuCtrl);		/* PCI write posting */
908 	writel(0, &regs->Mb0Lo);
909 
910 	tig_ver = readl(&regs->HostCtrl) >> 28;
911 
912 	switch(tig_ver){
913 #ifndef CONFIG_ACENIC_OMIT_TIGON_I
914 	case 4:
915 	case 5:
916 		printk(KERN_INFO "  Tigon I  (Rev. %i), Firmware: %i.%i.%i, ",
917 		       tig_ver, ap->firmware_major, ap->firmware_minor,
918 		       ap->firmware_fix);
919 		writel(0, &regs->LocalCtrl);
920 		ap->version = 1;
921 		ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
922 		break;
923 #endif
924 	case 6:
925 		printk(KERN_INFO "  Tigon II (Rev. %i), Firmware: %i.%i.%i, ",
926 		       tig_ver, ap->firmware_major, ap->firmware_minor,
927 		       ap->firmware_fix);
928 		writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl);
929 		readl(&regs->CpuBCtrl);		/* PCI write posting */
930 		/*
931 		 * The SRAM bank size does _not_ indicate the amount
932 		 * of memory on the card, it controls the _bank_ size!
933 		 * Ie. a 1MB AceNIC will have two banks of 512KB.
934 		 */
935 		writel(SRAM_BANK_512K, &regs->LocalCtrl);
936 		writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
937 		ap->version = 2;
938 		ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
939 		break;
940 	default:
941 		printk(KERN_WARNING "  Unsupported Tigon version detected "
942 		       "(%i)\n", tig_ver);
943 		ecode = -ENODEV;
944 		goto init_error;
945 	}
946 
947 	/*
948 	 * ModeStat _must_ be set after the SRAM settings as this change
949 	 * seems to corrupt the ModeStat and possible other registers.
950 	 * The SRAM settings survive resets and setting it to the same
951 	 * value a second time works as well. This is what caused the
952 	 * `Firmware not running' problem on the Tigon II.
953 	 */
954 #ifdef __BIG_ENDIAN
955 	writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD |
956 	       ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
957 #else
958 	writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL |
959 	       ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, &regs->ModeStat);
960 #endif
961 	readl(&regs->ModeStat);		/* PCI write posting */
962 
963 	mac1 = 0;
964 	for(i = 0; i < 4; i++) {
965 		int t;
966 
967 		mac1 = mac1 << 8;
968 		t = read_eeprom_byte(dev, 0x8c+i);
969 		if (t < 0) {
970 			ecode = -EIO;
971 			goto init_error;
972 		} else
973 			mac1 |= (t & 0xff);
974 	}
975 	mac2 = 0;
976 	for(i = 4; i < 8; i++) {
977 		int t;
978 
979 		mac2 = mac2 << 8;
980 		t = read_eeprom_byte(dev, 0x8c+i);
981 		if (t < 0) {
982 			ecode = -EIO;
983 			goto init_error;
984 		} else
985 			mac2 |= (t & 0xff);
986 	}
987 
988 	writel(mac1, &regs->MacAddrHi);
989 	writel(mac2, &regs->MacAddrLo);
990 
991 	dev->dev_addr[0] = (mac1 >> 8) & 0xff;
992 	dev->dev_addr[1] = mac1 & 0xff;
993 	dev->dev_addr[2] = (mac2 >> 24) & 0xff;
994 	dev->dev_addr[3] = (mac2 >> 16) & 0xff;
995 	dev->dev_addr[4] = (mac2 >> 8) & 0xff;
996 	dev->dev_addr[5] = mac2 & 0xff;
997 
998 	printk("MAC: %pM\n", dev->dev_addr);
999 
1000 	/*
1001 	 * Looks like this is necessary to deal with on all architectures,
1002 	 * even this %$#%$# N440BX Intel based thing doesn't get it right.
1003 	 * Ie. having two NICs in the machine, one will have the cache
1004 	 * line set at boot time, the other will not.
1005 	 */
1006 	pdev = ap->pdev;
1007 	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
1008 	cache_size <<= 2;
1009 	if (cache_size != SMP_CACHE_BYTES) {
1010 		printk(KERN_INFO "  PCI cache line size set incorrectly "
1011 		       "(%i bytes) by BIOS/FW, ", cache_size);
1012 		if (cache_size > SMP_CACHE_BYTES)
1013 			printk("expecting %i\n", SMP_CACHE_BYTES);
1014 		else {
1015 			printk("correcting to %i\n", SMP_CACHE_BYTES);
1016 			pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
1017 					      SMP_CACHE_BYTES >> 2);
1018 		}
1019 	}
1020 
1021 	pci_state = readl(&regs->PciState);
1022 	printk(KERN_INFO "  PCI bus width: %i bits, speed: %iMHz, "
1023 	       "latency: %i clks\n",
1024 	       	(pci_state & PCI_32BIT) ? 32 : 64,
1025 		(pci_state & PCI_66MHZ) ? 66 : 33,
1026 		ap->pci_latency);
1027 
1028 	/*
1029 	 * Set the max DMA transfer size. Seems that for most systems
1030 	 * the performance is better when no MAX parameter is
1031 	 * set. However for systems enabling PCI write and invalidate,
1032 	 * DMA writes must be set to the L1 cache line size to get
1033 	 * optimal performance.
1034 	 *
1035 	 * The default is now to turn the PCI write and invalidate off
1036 	 * - that is what Alteon does for NT.
1037 	 */
1038 	tmp = READ_CMD_MEM | WRITE_CMD_MEM;
1039 	if (ap->version >= 2) {
1040 		tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ));
1041 		/*
1042 		 * Tuning parameters only supported for 8 cards
1043 		 */
1044 		if (board_idx == BOARD_IDX_OVERFLOW ||
1045 		    dis_pci_mem_inval[board_idx]) {
1046 			if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1047 				ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1048 				pci_write_config_word(pdev, PCI_COMMAND,
1049 						      ap->pci_command);
1050 				printk(KERN_INFO "  Disabling PCI memory "
1051 				       "write and invalidate\n");
1052 			}
1053 		} else if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
1054 			printk(KERN_INFO "  PCI memory write & invalidate "
1055 			       "enabled by BIOS, enabling counter measures\n");
1056 
1057 			switch(SMP_CACHE_BYTES) {
1058 			case 16:
1059 				tmp |= DMA_WRITE_MAX_16;
1060 				break;
1061 			case 32:
1062 				tmp |= DMA_WRITE_MAX_32;
1063 				break;
1064 			case 64:
1065 				tmp |= DMA_WRITE_MAX_64;
1066 				break;
1067 			case 128:
1068 				tmp |= DMA_WRITE_MAX_128;
1069 				break;
1070 			default:
1071 				printk(KERN_INFO "  Cache line size %i not "
1072 				       "supported, PCI write and invalidate "
1073 				       "disabled\n", SMP_CACHE_BYTES);
1074 				ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
1075 				pci_write_config_word(pdev, PCI_COMMAND,
1076 						      ap->pci_command);
1077 			}
1078 		}
1079 	}
1080 
1081 #ifdef __sparc__
1082 	/*
1083 	 * On this platform, we know what the best dma settings
1084 	 * are.  We use 64-byte maximum bursts, because if we
1085 	 * burst larger than the cache line size (or even cross
1086 	 * a 64byte boundary in a single burst) the UltraSparc
1087 	 * PCI controller will disconnect at 64-byte multiples.
1088 	 *
1089 	 * Read-multiple will be properly enabled above, and when
1090 	 * set will give the PCI controller proper hints about
1091 	 * prefetching.
1092 	 */
1093 	tmp &= ~DMA_READ_WRITE_MASK;
1094 	tmp |= DMA_READ_MAX_64;
1095 	tmp |= DMA_WRITE_MAX_64;
1096 #endif
1097 #ifdef __alpha__
1098 	tmp &= ~DMA_READ_WRITE_MASK;
1099 	tmp |= DMA_READ_MAX_128;
1100 	/*
1101 	 * All the docs say MUST NOT. Well, I did.
1102 	 * Nothing terrible happens, if we load wrong size.
1103 	 * Bit w&i still works better!
1104 	 */
1105 	tmp |= DMA_WRITE_MAX_128;
1106 #endif
1107 	writel(tmp, &regs->PciState);
1108 
1109 #if 0
1110 	/*
1111 	 * The Host PCI bus controller driver has to set FBB.
1112 	 * If all devices on that PCI bus support FBB, then the controller
1113 	 * can enable FBB support in the Host PCI Bus controller (or on
1114 	 * the PCI-PCI bridge if that applies).
1115 	 * -ggg
1116 	 */
1117 	/*
1118 	 * I have received reports from people having problems when this
1119 	 * bit is enabled.
1120 	 */
1121 	if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
1122 		printk(KERN_INFO "  Enabling PCI Fast Back to Back\n");
1123 		ap->pci_command |= PCI_COMMAND_FAST_BACK;
1124 		pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
1125 	}
1126 #endif
1127 
1128 	/*
1129 	 * Configure DMA attributes.
1130 	 */
1131 	if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
1132 		ap->pci_using_dac = 1;
1133 	} else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
1134 		ap->pci_using_dac = 0;
1135 	} else {
1136 		ecode = -ENODEV;
1137 		goto init_error;
1138 	}
1139 
1140 	/*
1141 	 * Initialize the generic info block and the command+event rings
1142 	 * and the control blocks for the transmit and receive rings
1143 	 * as they need to be setup once and for all.
1144 	 */
1145 	if (!(info = dma_alloc_coherent(&ap->pdev->dev, sizeof(struct ace_info),
1146 					&ap->info_dma, GFP_KERNEL))) {
1147 		ecode = -EAGAIN;
1148 		goto init_error;
1149 	}
1150 	ap->info = info;
1151 
1152 	/*
1153 	 * Get the memory for the skb rings.
1154 	 */
1155 	if (!(ap->skb = kzalloc(sizeof(struct ace_skb), GFP_KERNEL))) {
1156 		ecode = -EAGAIN;
1157 		goto init_error;
1158 	}
1159 
1160 	ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED,
1161 			    DRV_NAME, dev);
1162 	if (ecode) {
1163 		printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
1164 		       DRV_NAME, pdev->irq);
1165 		goto init_error;
1166 	} else
1167 		dev->irq = pdev->irq;
1168 
1169 #ifdef INDEX_DEBUG
1170 	spin_lock_init(&ap->debug_lock);
1171 	ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
1172 	ap->last_std_rx = 0;
1173 	ap->last_mini_rx = 0;
1174 #endif
1175 
1176 	ecode = ace_load_firmware(dev);
1177 	if (ecode)
1178 		goto init_error;
1179 
1180 	ap->fw_running = 0;
1181 
1182 	tmp_ptr = ap->info_dma;
1183 	writel(tmp_ptr >> 32, &regs->InfoPtrHi);
1184 	writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo);
1185 
1186 	memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event));
1187 
1188 	set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma);
1189 	info->evt_ctrl.flags = 0;
1190 
1191 	*(ap->evt_prd) = 0;
1192 	wmb();
1193 	set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma);
1194 	writel(0, &regs->EvtCsm);
1195 
1196 	set_aceaddr(&info->cmd_ctrl.rngptr, 0x100);
1197 	info->cmd_ctrl.flags = 0;
1198 	info->cmd_ctrl.max_len = 0;
1199 
1200 	for (i = 0; i < CMD_RING_ENTRIES; i++)
1201 		writel(0, &regs->CmdRng[i]);
1202 
1203 	writel(0, &regs->CmdPrd);
1204 	writel(0, &regs->CmdCsm);
1205 
1206 	tmp_ptr = ap->info_dma;
1207 	tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats);
1208 	set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr);
1209 
1210 	set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
1211 	info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE;
1212 	info->rx_std_ctrl.flags =
1213 	  RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1214 
1215 	memset(ap->rx_std_ring, 0,
1216 	       RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
1217 
1218 	for (i = 0; i < RX_STD_RING_ENTRIES; i++)
1219 		ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM;
1220 
1221 	ap->rx_std_skbprd = 0;
1222 	atomic_set(&ap->cur_rx_bufs, 0);
1223 
1224 	set_aceaddr(&info->rx_jumbo_ctrl.rngptr,
1225 		    (ap->rx_ring_base_dma +
1226 		     (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
1227 	info->rx_jumbo_ctrl.max_len = 0;
1228 	info->rx_jumbo_ctrl.flags =
1229 	  RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1230 
1231 	memset(ap->rx_jumbo_ring, 0,
1232 	       RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
1233 
1234 	for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++)
1235 		ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO;
1236 
1237 	ap->rx_jumbo_skbprd = 0;
1238 	atomic_set(&ap->cur_jumbo_bufs, 0);
1239 
1240 	memset(ap->rx_mini_ring, 0,
1241 	       RX_MINI_RING_ENTRIES * sizeof(struct rx_desc));
1242 
1243 	if (ap->version >= 2) {
1244 		set_aceaddr(&info->rx_mini_ctrl.rngptr,
1245 			    (ap->rx_ring_base_dma +
1246 			     (sizeof(struct rx_desc) *
1247 			      (RX_STD_RING_ENTRIES +
1248 			       RX_JUMBO_RING_ENTRIES))));
1249 		info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
1250 		info->rx_mini_ctrl.flags =
1251 		  RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|RCB_FLG_VLAN_ASSIST;
1252 
1253 		for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
1254 			ap->rx_mini_ring[i].flags =
1255 				BD_FLG_TCP_UDP_SUM | BD_FLG_MINI;
1256 	} else {
1257 		set_aceaddr(&info->rx_mini_ctrl.rngptr, 0);
1258 		info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE;
1259 		info->rx_mini_ctrl.max_len = 0;
1260 	}
1261 
1262 	ap->rx_mini_skbprd = 0;
1263 	atomic_set(&ap->cur_mini_bufs, 0);
1264 
1265 	set_aceaddr(&info->rx_return_ctrl.rngptr,
1266 		    (ap->rx_ring_base_dma +
1267 		     (sizeof(struct rx_desc) *
1268 		      (RX_STD_RING_ENTRIES +
1269 		       RX_JUMBO_RING_ENTRIES +
1270 		       RX_MINI_RING_ENTRIES))));
1271 	info->rx_return_ctrl.flags = 0;
1272 	info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES;
1273 
1274 	memset(ap->rx_return_ring, 0,
1275 	       RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc));
1276 
1277 	set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma);
1278 	*(ap->rx_ret_prd) = 0;
1279 
1280 	writel(TX_RING_BASE, &regs->WinBase);
1281 
1282 	if (ACE_IS_TIGON_I(ap)) {
1283 		ap->tx_ring = (__force struct tx_desc *) regs->Window;
1284 		for (i = 0; i < (TIGON_I_TX_RING_ENTRIES
1285 				 * sizeof(struct tx_desc)) / sizeof(u32); i++)
1286 			writel(0, (__force void __iomem *)ap->tx_ring  + i * 4);
1287 
1288 		set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
1289 	} else {
1290 		memset(ap->tx_ring, 0,
1291 		       MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
1292 
1293 		set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
1294 	}
1295 
1296 	info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
1297 	tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST;
1298 
1299 	/*
1300 	 * The Tigon I does not like having the TX ring in host memory ;-(
1301 	 */
1302 	if (!ACE_IS_TIGON_I(ap))
1303 		tmp |= RCB_FLG_TX_HOST_RING;
1304 #if TX_COAL_INTS_ONLY
1305 	tmp |= RCB_FLG_COAL_INT_ONLY;
1306 #endif
1307 	info->tx_ctrl.flags = tmp;
1308 
1309 	set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
1310 
1311 	/*
1312 	 * Potential item for tuning parameter
1313 	 */
1314 #if 0 /* NO */
1315 	writel(DMA_THRESH_16W, &regs->DmaReadCfg);
1316 	writel(DMA_THRESH_16W, &regs->DmaWriteCfg);
1317 #else
1318 	writel(DMA_THRESH_8W, &regs->DmaReadCfg);
1319 	writel(DMA_THRESH_8W, &regs->DmaWriteCfg);
1320 #endif
1321 
1322 	writel(0, &regs->MaskInt);
1323 	writel(1, &regs->IfIdx);
1324 #if 0
1325 	/*
1326 	 * McKinley boxes do not like us fiddling with AssistState
1327 	 * this early
1328 	 */
1329 	writel(1, &regs->AssistState);
1330 #endif
1331 
1332 	writel(DEF_STAT, &regs->TuneStatTicks);
1333 	writel(DEF_TRACE, &regs->TuneTrace);
1334 
1335 	ace_set_rxtx_parms(dev, 0);
1336 
1337 	if (board_idx == BOARD_IDX_OVERFLOW) {
1338 		printk(KERN_WARNING "%s: more than %i NICs detected, "
1339 		       "ignoring module parameters!\n",
1340 		       ap->name, ACE_MAX_MOD_PARMS);
1341 	} else if (board_idx >= 0) {
1342 		if (tx_coal_tick[board_idx])
1343 			writel(tx_coal_tick[board_idx],
1344 			       &regs->TuneTxCoalTicks);
1345 		if (max_tx_desc[board_idx])
1346 			writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc);
1347 
1348 		if (rx_coal_tick[board_idx])
1349 			writel(rx_coal_tick[board_idx],
1350 			       &regs->TuneRxCoalTicks);
1351 		if (max_rx_desc[board_idx])
1352 			writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc);
1353 
1354 		if (trace[board_idx])
1355 			writel(trace[board_idx], &regs->TuneTrace);
1356 
1357 		if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64))
1358 			writel(tx_ratio[board_idx], &regs->TxBufRat);
1359 	}
1360 
1361 	/*
1362 	 * Default link parameters
1363 	 */
1364 	tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB |
1365 		LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE;
1366 	if(ap->version >= 2)
1367 		tmp |= LNK_TX_FLOW_CTL_Y;
1368 
1369 	/*
1370 	 * Override link default parameters
1371 	 */
1372 	if ((board_idx >= 0) && link_state[board_idx]) {
1373 		int option = link_state[board_idx];
1374 
1375 		tmp = LNK_ENABLE;
1376 
1377 		if (option & 0x01) {
1378 			printk(KERN_INFO "%s: Setting half duplex link\n",
1379 			       ap->name);
1380 			tmp &= ~LNK_FULL_DUPLEX;
1381 		}
1382 		if (option & 0x02)
1383 			tmp &= ~LNK_NEGOTIATE;
1384 		if (option & 0x10)
1385 			tmp |= LNK_10MB;
1386 		if (option & 0x20)
1387 			tmp |= LNK_100MB;
1388 		if (option & 0x40)
1389 			tmp |= LNK_1000MB;
1390 		if ((option & 0x70) == 0) {
1391 			printk(KERN_WARNING "%s: No media speed specified, "
1392 			       "forcing auto negotiation\n", ap->name);
1393 			tmp |= LNK_NEGOTIATE | LNK_1000MB |
1394 				LNK_100MB | LNK_10MB;
1395 		}
1396 		if ((option & 0x100) == 0)
1397 			tmp |= LNK_NEG_FCTL;
1398 		else
1399 			printk(KERN_INFO "%s: Disabling flow control "
1400 			       "negotiation\n", ap->name);
1401 		if (option & 0x200)
1402 			tmp |= LNK_RX_FLOW_CTL_Y;
1403 		if ((option & 0x400) && (ap->version >= 2)) {
1404 			printk(KERN_INFO "%s: Enabling TX flow control\n",
1405 			       ap->name);
1406 			tmp |= LNK_TX_FLOW_CTL_Y;
1407 		}
1408 	}
1409 
1410 	ap->link = tmp;
1411 	writel(tmp, &regs->TuneLink);
1412 	if (ap->version >= 2)
1413 		writel(tmp, &regs->TuneFastLink);
1414 
1415 	writel(ap->firmware_start, &regs->Pc);
1416 
1417 	writel(0, &regs->Mb0Lo);
1418 
1419 	/*
1420 	 * Set tx_csm before we start receiving interrupts, otherwise
1421 	 * the interrupt handler might think it is supposed to process
1422 	 * tx ints before we are up and running, which may cause a null
1423 	 * pointer access in the int handler.
1424 	 */
1425 	ap->cur_rx = 0;
1426 	ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0;
1427 
1428 	wmb();
1429 	ace_set_txprd(regs, ap, 0);
1430 	writel(0, &regs->RxRetCsm);
1431 
1432 	/*
1433 	 * Enable DMA engine now.
1434 	 * If we do this sooner, Mckinley box pukes.
1435 	 * I assume it's because Tigon II DMA engine wants to check
1436 	 * *something* even before the CPU is started.
1437 	 */
1438 	writel(1, &regs->AssistState);  /* enable DMA */
1439 
1440 	/*
1441 	 * Start the NIC CPU
1442 	 */
1443 	writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl);
1444 	readl(&regs->CpuCtrl);
1445 
1446 	/*
1447 	 * Wait for the firmware to spin up - max 3 seconds.
1448 	 */
1449 	myjif = jiffies + 3 * HZ;
1450 	while (time_before(jiffies, myjif) && !ap->fw_running)
1451 		cpu_relax();
1452 
1453 	if (!ap->fw_running) {
1454 		printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name);
1455 
1456 		ace_dump_trace(ap);
1457 		writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl);
1458 		readl(&regs->CpuCtrl);
1459 
1460 		/* aman@sgi.com - account for badly behaving firmware/NIC:
1461 		 * - have observed that the NIC may continue to generate
1462 		 *   interrupts for some reason; attempt to stop it - halt
1463 		 *   second CPU for Tigon II cards, and also clear Mb0
1464 		 * - if we're a module, we'll fail to load if this was
1465 		 *   the only GbE card in the system => if the kernel does
1466 		 *   see an interrupt from the NIC, code to handle it is
1467 		 *   gone and OOps! - so free_irq also
1468 		 */
1469 		if (ap->version >= 2)
1470 			writel(readl(&regs->CpuBCtrl) | CPU_HALT,
1471 			       &regs->CpuBCtrl);
1472 		writel(0, &regs->Mb0Lo);
1473 		readl(&regs->Mb0Lo);
1474 
1475 		ecode = -EBUSY;
1476 		goto init_error;
1477 	}
1478 
1479 	/*
1480 	 * We load the ring here as there seem to be no way to tell the
1481 	 * firmware to wipe the ring without re-initializing it.
1482 	 */
1483 	if (!test_and_set_bit(0, &ap->std_refill_busy))
1484 		ace_load_std_rx_ring(dev, RX_RING_SIZE);
1485 	else
1486 		printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n",
1487 		       ap->name);
1488 	if (ap->version >= 2) {
1489 		if (!test_and_set_bit(0, &ap->mini_refill_busy))
1490 			ace_load_mini_rx_ring(dev, RX_MINI_SIZE);
1491 		else
1492 			printk(KERN_ERR "%s: Someone is busy refilling "
1493 			       "the RX mini ring\n", ap->name);
1494 	}
1495 	return 0;
1496 
1497  init_error:
1498 	ace_init_cleanup(dev);
1499 	return ecode;
1500 }
1501 
1502 
1503 static void ace_set_rxtx_parms(struct net_device *dev, int jumbo)
1504 {
1505 	struct ace_private *ap = netdev_priv(dev);
1506 	struct ace_regs __iomem *regs = ap->regs;
1507 	int board_idx = ap->board_idx;
1508 
1509 	if (board_idx >= 0) {
1510 		if (!jumbo) {
1511 			if (!tx_coal_tick[board_idx])
1512 				writel(DEF_TX_COAL, &regs->TuneTxCoalTicks);
1513 			if (!max_tx_desc[board_idx])
1514 				writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc);
1515 			if (!rx_coal_tick[board_idx])
1516 				writel(DEF_RX_COAL, &regs->TuneRxCoalTicks);
1517 			if (!max_rx_desc[board_idx])
1518 				writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc);
1519 			if (!tx_ratio[board_idx])
1520 				writel(DEF_TX_RATIO, &regs->TxBufRat);
1521 		} else {
1522 			if (!tx_coal_tick[board_idx])
1523 				writel(DEF_JUMBO_TX_COAL,
1524 				       &regs->TuneTxCoalTicks);
1525 			if (!max_tx_desc[board_idx])
1526 				writel(DEF_JUMBO_TX_MAX_DESC,
1527 				       &regs->TuneMaxTxDesc);
1528 			if (!rx_coal_tick[board_idx])
1529 				writel(DEF_JUMBO_RX_COAL,
1530 				       &regs->TuneRxCoalTicks);
1531 			if (!max_rx_desc[board_idx])
1532 				writel(DEF_JUMBO_RX_MAX_DESC,
1533 				       &regs->TuneMaxRxDesc);
1534 			if (!tx_ratio[board_idx])
1535 				writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat);
1536 		}
1537 	}
1538 }
1539 
1540 
1541 static void ace_watchdog(struct net_device *data, unsigned int txqueue)
1542 {
1543 	struct net_device *dev = data;
1544 	struct ace_private *ap = netdev_priv(dev);
1545 	struct ace_regs __iomem *regs = ap->regs;
1546 
1547 	/*
1548 	 * We haven't received a stats update event for more than 2.5
1549 	 * seconds and there is data in the transmit queue, thus we
1550 	 * assume the card is stuck.
1551 	 */
1552 	if (*ap->tx_csm != ap->tx_ret_csm) {
1553 		printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n",
1554 		       dev->name, (unsigned int)readl(&regs->HostCtrl));
1555 		/* This can happen due to ieee flow control. */
1556 	} else {
1557 		printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n",
1558 		       dev->name);
1559 #if 0
1560 		netif_wake_queue(dev);
1561 #endif
1562 	}
1563 }
1564 
1565 
1566 static void ace_tasklet(struct tasklet_struct *t)
1567 {
1568 	struct ace_private *ap = from_tasklet(ap, t, ace_tasklet);
1569 	struct net_device *dev = ap->ndev;
1570 	int cur_size;
1571 
1572 	cur_size = atomic_read(&ap->cur_rx_bufs);
1573 	if ((cur_size < RX_LOW_STD_THRES) &&
1574 	    !test_and_set_bit(0, &ap->std_refill_busy)) {
1575 #ifdef DEBUG
1576 		printk("refilling buffers (current %i)\n", cur_size);
1577 #endif
1578 		ace_load_std_rx_ring(dev, RX_RING_SIZE - cur_size);
1579 	}
1580 
1581 	if (ap->version >= 2) {
1582 		cur_size = atomic_read(&ap->cur_mini_bufs);
1583 		if ((cur_size < RX_LOW_MINI_THRES) &&
1584 		    !test_and_set_bit(0, &ap->mini_refill_busy)) {
1585 #ifdef DEBUG
1586 			printk("refilling mini buffers (current %i)\n",
1587 			       cur_size);
1588 #endif
1589 			ace_load_mini_rx_ring(dev, RX_MINI_SIZE - cur_size);
1590 		}
1591 	}
1592 
1593 	cur_size = atomic_read(&ap->cur_jumbo_bufs);
1594 	if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) &&
1595 	    !test_and_set_bit(0, &ap->jumbo_refill_busy)) {
1596 #ifdef DEBUG
1597 		printk("refilling jumbo buffers (current %i)\n", cur_size);
1598 #endif
1599 		ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE - cur_size);
1600 	}
1601 	ap->tasklet_pending = 0;
1602 }
1603 
1604 
1605 /*
1606  * Copy the contents of the NIC's trace buffer to kernel memory.
1607  */
1608 static void ace_dump_trace(struct ace_private *ap)
1609 {
1610 #if 0
1611 	if (!ap->trace_buf)
1612 		if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL)))
1613 		    return;
1614 #endif
1615 }
1616 
1617 
1618 /*
1619  * Load the standard rx ring.
1620  *
1621  * Loading rings is safe without holding the spin lock since this is
1622  * done only before the device is enabled, thus no interrupts are
1623  * generated and by the interrupt handler/tasklet handler.
1624  */
1625 static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs)
1626 {
1627 	struct ace_private *ap = netdev_priv(dev);
1628 	struct ace_regs __iomem *regs = ap->regs;
1629 	short i, idx;
1630 
1631 
1632 	prefetchw(&ap->cur_rx_bufs);
1633 
1634 	idx = ap->rx_std_skbprd;
1635 
1636 	for (i = 0; i < nr_bufs; i++) {
1637 		struct sk_buff *skb;
1638 		struct rx_desc *rd;
1639 		dma_addr_t mapping;
1640 
1641 		skb = netdev_alloc_skb_ip_align(dev, ACE_STD_BUFSIZE);
1642 		if (!skb)
1643 			break;
1644 
1645 		mapping = dma_map_page(&ap->pdev->dev,
1646 				       virt_to_page(skb->data),
1647 				       offset_in_page(skb->data),
1648 				       ACE_STD_BUFSIZE, DMA_FROM_DEVICE);
1649 		ap->skb->rx_std_skbuff[idx].skb = skb;
1650 		dma_unmap_addr_set(&ap->skb->rx_std_skbuff[idx],
1651 				   mapping, mapping);
1652 
1653 		rd = &ap->rx_std_ring[idx];
1654 		set_aceaddr(&rd->addr, mapping);
1655 		rd->size = ACE_STD_BUFSIZE;
1656 		rd->idx = idx;
1657 		idx = (idx + 1) % RX_STD_RING_ENTRIES;
1658 	}
1659 
1660 	if (!i)
1661 		goto error_out;
1662 
1663 	atomic_add(i, &ap->cur_rx_bufs);
1664 	ap->rx_std_skbprd = idx;
1665 
1666 	if (ACE_IS_TIGON_I(ap)) {
1667 		struct cmd cmd;
1668 		cmd.evt = C_SET_RX_PRD_IDX;
1669 		cmd.code = 0;
1670 		cmd.idx = ap->rx_std_skbprd;
1671 		ace_issue_cmd(regs, &cmd);
1672 	} else {
1673 		writel(idx, &regs->RxStdPrd);
1674 		wmb();
1675 	}
1676 
1677  out:
1678 	clear_bit(0, &ap->std_refill_busy);
1679 	return;
1680 
1681  error_out:
1682 	printk(KERN_INFO "Out of memory when allocating "
1683 	       "standard receive buffers\n");
1684 	goto out;
1685 }
1686 
1687 
1688 static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs)
1689 {
1690 	struct ace_private *ap = netdev_priv(dev);
1691 	struct ace_regs __iomem *regs = ap->regs;
1692 	short i, idx;
1693 
1694 	prefetchw(&ap->cur_mini_bufs);
1695 
1696 	idx = ap->rx_mini_skbprd;
1697 	for (i = 0; i < nr_bufs; i++) {
1698 		struct sk_buff *skb;
1699 		struct rx_desc *rd;
1700 		dma_addr_t mapping;
1701 
1702 		skb = netdev_alloc_skb_ip_align(dev, ACE_MINI_BUFSIZE);
1703 		if (!skb)
1704 			break;
1705 
1706 		mapping = dma_map_page(&ap->pdev->dev,
1707 				       virt_to_page(skb->data),
1708 				       offset_in_page(skb->data),
1709 				       ACE_MINI_BUFSIZE, DMA_FROM_DEVICE);
1710 		ap->skb->rx_mini_skbuff[idx].skb = skb;
1711 		dma_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx],
1712 				   mapping, mapping);
1713 
1714 		rd = &ap->rx_mini_ring[idx];
1715 		set_aceaddr(&rd->addr, mapping);
1716 		rd->size = ACE_MINI_BUFSIZE;
1717 		rd->idx = idx;
1718 		idx = (idx + 1) % RX_MINI_RING_ENTRIES;
1719 	}
1720 
1721 	if (!i)
1722 		goto error_out;
1723 
1724 	atomic_add(i, &ap->cur_mini_bufs);
1725 
1726 	ap->rx_mini_skbprd = idx;
1727 
1728 	writel(idx, &regs->RxMiniPrd);
1729 	wmb();
1730 
1731  out:
1732 	clear_bit(0, &ap->mini_refill_busy);
1733 	return;
1734  error_out:
1735 	printk(KERN_INFO "Out of memory when allocating "
1736 	       "mini receive buffers\n");
1737 	goto out;
1738 }
1739 
1740 
1741 /*
1742  * Load the jumbo rx ring, this may happen at any time if the MTU
1743  * is changed to a value > 1500.
1744  */
1745 static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs)
1746 {
1747 	struct ace_private *ap = netdev_priv(dev);
1748 	struct ace_regs __iomem *regs = ap->regs;
1749 	short i, idx;
1750 
1751 	idx = ap->rx_jumbo_skbprd;
1752 
1753 	for (i = 0; i < nr_bufs; i++) {
1754 		struct sk_buff *skb;
1755 		struct rx_desc *rd;
1756 		dma_addr_t mapping;
1757 
1758 		skb = netdev_alloc_skb_ip_align(dev, ACE_JUMBO_BUFSIZE);
1759 		if (!skb)
1760 			break;
1761 
1762 		mapping = dma_map_page(&ap->pdev->dev,
1763 				       virt_to_page(skb->data),
1764 				       offset_in_page(skb->data),
1765 				       ACE_JUMBO_BUFSIZE, DMA_FROM_DEVICE);
1766 		ap->skb->rx_jumbo_skbuff[idx].skb = skb;
1767 		dma_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx],
1768 				   mapping, mapping);
1769 
1770 		rd = &ap->rx_jumbo_ring[idx];
1771 		set_aceaddr(&rd->addr, mapping);
1772 		rd->size = ACE_JUMBO_BUFSIZE;
1773 		rd->idx = idx;
1774 		idx = (idx + 1) % RX_JUMBO_RING_ENTRIES;
1775 	}
1776 
1777 	if (!i)
1778 		goto error_out;
1779 
1780 	atomic_add(i, &ap->cur_jumbo_bufs);
1781 	ap->rx_jumbo_skbprd = idx;
1782 
1783 	if (ACE_IS_TIGON_I(ap)) {
1784 		struct cmd cmd;
1785 		cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1786 		cmd.code = 0;
1787 		cmd.idx = ap->rx_jumbo_skbprd;
1788 		ace_issue_cmd(regs, &cmd);
1789 	} else {
1790 		writel(idx, &regs->RxJumboPrd);
1791 		wmb();
1792 	}
1793 
1794  out:
1795 	clear_bit(0, &ap->jumbo_refill_busy);
1796 	return;
1797  error_out:
1798 	if (net_ratelimit())
1799 		printk(KERN_INFO "Out of memory when allocating "
1800 		       "jumbo receive buffers\n");
1801 	goto out;
1802 }
1803 
1804 
1805 /*
1806  * All events are considered to be slow (RX/TX ints do not generate
1807  * events) and are handled here, outside the main interrupt handler,
1808  * to reduce the size of the handler.
1809  */
1810 static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd)
1811 {
1812 	struct ace_private *ap;
1813 
1814 	ap = netdev_priv(dev);
1815 
1816 	while (evtcsm != evtprd) {
1817 		switch (ap->evt_ring[evtcsm].evt) {
1818 		case E_FW_RUNNING:
1819 			printk(KERN_INFO "%s: Firmware up and running\n",
1820 			       ap->name);
1821 			ap->fw_running = 1;
1822 			wmb();
1823 			break;
1824 		case E_STATS_UPDATED:
1825 			break;
1826 		case E_LNK_STATE:
1827 		{
1828 			u16 code = ap->evt_ring[evtcsm].code;
1829 			switch (code) {
1830 			case E_C_LINK_UP:
1831 			{
1832 				u32 state = readl(&ap->regs->GigLnkState);
1833 				printk(KERN_WARNING "%s: Optical link UP "
1834 				       "(%s Duplex, Flow Control: %s%s)\n",
1835 				       ap->name,
1836 				       state & LNK_FULL_DUPLEX ? "Full":"Half",
1837 				       state & LNK_TX_FLOW_CTL_Y ? "TX " : "",
1838 				       state & LNK_RX_FLOW_CTL_Y ? "RX" : "");
1839 				break;
1840 			}
1841 			case E_C_LINK_DOWN:
1842 				printk(KERN_WARNING "%s: Optical link DOWN\n",
1843 				       ap->name);
1844 				break;
1845 			case E_C_LINK_10_100:
1846 				printk(KERN_WARNING "%s: 10/100BaseT link "
1847 				       "UP\n", ap->name);
1848 				break;
1849 			default:
1850 				printk(KERN_ERR "%s: Unknown optical link "
1851 				       "state %02x\n", ap->name, code);
1852 			}
1853 			break;
1854 		}
1855 		case E_ERROR:
1856 			switch(ap->evt_ring[evtcsm].code) {
1857 			case E_C_ERR_INVAL_CMD:
1858 				printk(KERN_ERR "%s: invalid command error\n",
1859 				       ap->name);
1860 				break;
1861 			case E_C_ERR_UNIMP_CMD:
1862 				printk(KERN_ERR "%s: unimplemented command "
1863 				       "error\n", ap->name);
1864 				break;
1865 			case E_C_ERR_BAD_CFG:
1866 				printk(KERN_ERR "%s: bad config error\n",
1867 				       ap->name);
1868 				break;
1869 			default:
1870 				printk(KERN_ERR "%s: unknown error %02x\n",
1871 				       ap->name, ap->evt_ring[evtcsm].code);
1872 			}
1873 			break;
1874 		case E_RESET_JUMBO_RNG:
1875 		{
1876 			int i;
1877 			for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) {
1878 				if (ap->skb->rx_jumbo_skbuff[i].skb) {
1879 					ap->rx_jumbo_ring[i].size = 0;
1880 					set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0);
1881 					dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb);
1882 					ap->skb->rx_jumbo_skbuff[i].skb = NULL;
1883 				}
1884 			}
1885 
1886  			if (ACE_IS_TIGON_I(ap)) {
1887  				struct cmd cmd;
1888  				cmd.evt = C_SET_RX_JUMBO_PRD_IDX;
1889  				cmd.code = 0;
1890  				cmd.idx = 0;
1891  				ace_issue_cmd(ap->regs, &cmd);
1892  			} else {
1893  				writel(0, &((ap->regs)->RxJumboPrd));
1894  				wmb();
1895  			}
1896 
1897 			ap->jumbo = 0;
1898 			ap->rx_jumbo_skbprd = 0;
1899 			printk(KERN_INFO "%s: Jumbo ring flushed\n",
1900 			       ap->name);
1901 			clear_bit(0, &ap->jumbo_refill_busy);
1902 			break;
1903 		}
1904 		default:
1905 			printk(KERN_ERR "%s: Unhandled event 0x%02x\n",
1906 			       ap->name, ap->evt_ring[evtcsm].evt);
1907 		}
1908 		evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES;
1909 	}
1910 
1911 	return evtcsm;
1912 }
1913 
1914 
1915 static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
1916 {
1917 	struct ace_private *ap = netdev_priv(dev);
1918 	u32 idx;
1919 	int mini_count = 0, std_count = 0;
1920 
1921 	idx = rxretcsm;
1922 
1923 	prefetchw(&ap->cur_rx_bufs);
1924 	prefetchw(&ap->cur_mini_bufs);
1925 
1926 	while (idx != rxretprd) {
1927 		struct ring_info *rip;
1928 		struct sk_buff *skb;
1929 		struct rx_desc *retdesc;
1930 		u32 skbidx;
1931 		int bd_flags, desc_type, mapsize;
1932 		u16 csum;
1933 
1934 
1935 		/* make sure the rx descriptor isn't read before rxretprd */
1936 		if (idx == rxretcsm)
1937 			rmb();
1938 
1939 		retdesc = &ap->rx_return_ring[idx];
1940 		skbidx = retdesc->idx;
1941 		bd_flags = retdesc->flags;
1942 		desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI);
1943 
1944 		switch(desc_type) {
1945 			/*
1946 			 * Normal frames do not have any flags set
1947 			 *
1948 			 * Mini and normal frames arrive frequently,
1949 			 * so use a local counter to avoid doing
1950 			 * atomic operations for each packet arriving.
1951 			 */
1952 		case 0:
1953 			rip = &ap->skb->rx_std_skbuff[skbidx];
1954 			mapsize = ACE_STD_BUFSIZE;
1955 			std_count++;
1956 			break;
1957 		case BD_FLG_JUMBO:
1958 			rip = &ap->skb->rx_jumbo_skbuff[skbidx];
1959 			mapsize = ACE_JUMBO_BUFSIZE;
1960 			atomic_dec(&ap->cur_jumbo_bufs);
1961 			break;
1962 		case BD_FLG_MINI:
1963 			rip = &ap->skb->rx_mini_skbuff[skbidx];
1964 			mapsize = ACE_MINI_BUFSIZE;
1965 			mini_count++;
1966 			break;
1967 		default:
1968 			printk(KERN_INFO "%s: unknown frame type (0x%02x) "
1969 			       "returned by NIC\n", dev->name,
1970 			       retdesc->flags);
1971 			goto error;
1972 		}
1973 
1974 		skb = rip->skb;
1975 		rip->skb = NULL;
1976 		dma_unmap_page(&ap->pdev->dev, dma_unmap_addr(rip, mapping),
1977 			       mapsize, DMA_FROM_DEVICE);
1978 		skb_put(skb, retdesc->size);
1979 
1980 		/*
1981 		 * Fly baby, fly!
1982 		 */
1983 		csum = retdesc->tcp_udp_csum;
1984 
1985 		skb->protocol = eth_type_trans(skb, dev);
1986 
1987 		/*
1988 		 * Instead of forcing the poor tigon mips cpu to calculate
1989 		 * pseudo hdr checksum, we do this ourselves.
1990 		 */
1991 		if (bd_flags & BD_FLG_TCP_UDP_SUM) {
1992 			skb->csum = htons(csum);
1993 			skb->ip_summed = CHECKSUM_COMPLETE;
1994 		} else {
1995 			skb_checksum_none_assert(skb);
1996 		}
1997 
1998 		/* send it up */
1999 		if ((bd_flags & BD_FLG_VLAN_TAG))
2000 			__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), retdesc->vlan);
2001 		netif_rx(skb);
2002 
2003 		dev->stats.rx_packets++;
2004 		dev->stats.rx_bytes += retdesc->size;
2005 
2006 		idx = (idx + 1) % RX_RETURN_RING_ENTRIES;
2007 	}
2008 
2009 	atomic_sub(std_count, &ap->cur_rx_bufs);
2010 	if (!ACE_IS_TIGON_I(ap))
2011 		atomic_sub(mini_count, &ap->cur_mini_bufs);
2012 
2013  out:
2014 	/*
2015 	 * According to the documentation RxRetCsm is obsolete with
2016 	 * the 12.3.x Firmware - my Tigon I NICs seem to disagree!
2017 	 */
2018 	if (ACE_IS_TIGON_I(ap)) {
2019 		writel(idx, &ap->regs->RxRetCsm);
2020 	}
2021 	ap->cur_rx = idx;
2022 
2023 	return;
2024  error:
2025 	idx = rxretprd;
2026 	goto out;
2027 }
2028 
2029 
2030 static inline void ace_tx_int(struct net_device *dev,
2031 			      u32 txcsm, u32 idx)
2032 {
2033 	struct ace_private *ap = netdev_priv(dev);
2034 
2035 	do {
2036 		struct sk_buff *skb;
2037 		struct tx_ring_info *info;
2038 
2039 		info = ap->skb->tx_skbuff + idx;
2040 		skb = info->skb;
2041 
2042 		if (dma_unmap_len(info, maplen)) {
2043 			dma_unmap_page(&ap->pdev->dev,
2044 				       dma_unmap_addr(info, mapping),
2045 				       dma_unmap_len(info, maplen),
2046 				       DMA_TO_DEVICE);
2047 			dma_unmap_len_set(info, maplen, 0);
2048 		}
2049 
2050 		if (skb) {
2051 			dev->stats.tx_packets++;
2052 			dev->stats.tx_bytes += skb->len;
2053 			dev_consume_skb_irq(skb);
2054 			info->skb = NULL;
2055 		}
2056 
2057 		idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2058 	} while (idx != txcsm);
2059 
2060 	if (netif_queue_stopped(dev))
2061 		netif_wake_queue(dev);
2062 
2063 	wmb();
2064 	ap->tx_ret_csm = txcsm;
2065 
2066 	/* So... tx_ret_csm is advanced _after_ check for device wakeup.
2067 	 *
2068 	 * We could try to make it before. In this case we would get
2069 	 * the following race condition: hard_start_xmit on other cpu
2070 	 * enters after we advanced tx_ret_csm and fills space,
2071 	 * which we have just freed, so that we make illegal device wakeup.
2072 	 * There is no good way to workaround this (at entry
2073 	 * to ace_start_xmit detects this condition and prevents
2074 	 * ring corruption, but it is not a good workaround.)
2075 	 *
2076 	 * When tx_ret_csm is advanced after, we wake up device _only_
2077 	 * if we really have some space in ring (though the core doing
2078 	 * hard_start_xmit can see full ring for some period and has to
2079 	 * synchronize.) Superb.
2080 	 * BUT! We get another subtle race condition. hard_start_xmit
2081 	 * may think that ring is full between wakeup and advancing
2082 	 * tx_ret_csm and will stop device instantly! It is not so bad.
2083 	 * We are guaranteed that there is something in ring, so that
2084 	 * the next irq will resume transmission. To speedup this we could
2085 	 * mark descriptor, which closes ring with BD_FLG_COAL_NOW
2086 	 * (see ace_start_xmit).
2087 	 *
2088 	 * Well, this dilemma exists in all lock-free devices.
2089 	 * We, following scheme used in drivers by Donald Becker,
2090 	 * select the least dangerous.
2091 	 *							--ANK
2092 	 */
2093 }
2094 
2095 
2096 static irqreturn_t ace_interrupt(int irq, void *dev_id)
2097 {
2098 	struct net_device *dev = (struct net_device *)dev_id;
2099 	struct ace_private *ap = netdev_priv(dev);
2100 	struct ace_regs __iomem *regs = ap->regs;
2101 	u32 idx;
2102 	u32 txcsm, rxretcsm, rxretprd;
2103 	u32 evtcsm, evtprd;
2104 
2105 	/*
2106 	 * In case of PCI shared interrupts or spurious interrupts,
2107 	 * we want to make sure it is actually our interrupt before
2108 	 * spending any time in here.
2109 	 */
2110 	if (!(readl(&regs->HostCtrl) & IN_INT))
2111 		return IRQ_NONE;
2112 
2113 	/*
2114 	 * ACK intr now. Otherwise we will lose updates to rx_ret_prd,
2115 	 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before
2116 	 * writel(0, &regs->Mb0Lo).
2117 	 *
2118 	 * "IRQ avoidance" recommended in docs applies to IRQs served
2119 	 * threads and it is wrong even for that case.
2120 	 */
2121 	writel(0, &regs->Mb0Lo);
2122 	readl(&regs->Mb0Lo);
2123 
2124 	/*
2125 	 * There is no conflict between transmit handling in
2126 	 * start_xmit and receive processing, thus there is no reason
2127 	 * to take a spin lock for RX handling. Wait until we start
2128 	 * working on the other stuff - hey we don't need a spin lock
2129 	 * anymore.
2130 	 */
2131 	rxretprd = *ap->rx_ret_prd;
2132 	rxretcsm = ap->cur_rx;
2133 
2134 	if (rxretprd != rxretcsm)
2135 		ace_rx_int(dev, rxretprd, rxretcsm);
2136 
2137 	txcsm = *ap->tx_csm;
2138 	idx = ap->tx_ret_csm;
2139 
2140 	if (txcsm != idx) {
2141 		/*
2142 		 * If each skb takes only one descriptor this check degenerates
2143 		 * to identity, because new space has just been opened.
2144 		 * But if skbs are fragmented we must check that this index
2145 		 * update releases enough of space, otherwise we just
2146 		 * wait for device to make more work.
2147 		 */
2148 		if (!tx_ring_full(ap, txcsm, ap->tx_prd))
2149 			ace_tx_int(dev, txcsm, idx);
2150 	}
2151 
2152 	evtcsm = readl(&regs->EvtCsm);
2153 	evtprd = *ap->evt_prd;
2154 
2155 	if (evtcsm != evtprd) {
2156 		evtcsm = ace_handle_event(dev, evtcsm, evtprd);
2157 		writel(evtcsm, &regs->EvtCsm);
2158 	}
2159 
2160 	/*
2161 	 * This has to go last in the interrupt handler and run with
2162 	 * the spin lock released ... what lock?
2163 	 */
2164 	if (netif_running(dev)) {
2165 		int cur_size;
2166 		int run_tasklet = 0;
2167 
2168 		cur_size = atomic_read(&ap->cur_rx_bufs);
2169 		if (cur_size < RX_LOW_STD_THRES) {
2170 			if ((cur_size < RX_PANIC_STD_THRES) &&
2171 			    !test_and_set_bit(0, &ap->std_refill_busy)) {
2172 #ifdef DEBUG
2173 				printk("low on std buffers %i\n", cur_size);
2174 #endif
2175 				ace_load_std_rx_ring(dev,
2176 						     RX_RING_SIZE - cur_size);
2177 			} else
2178 				run_tasklet = 1;
2179 		}
2180 
2181 		if (!ACE_IS_TIGON_I(ap)) {
2182 			cur_size = atomic_read(&ap->cur_mini_bufs);
2183 			if (cur_size < RX_LOW_MINI_THRES) {
2184 				if ((cur_size < RX_PANIC_MINI_THRES) &&
2185 				    !test_and_set_bit(0,
2186 						      &ap->mini_refill_busy)) {
2187 #ifdef DEBUG
2188 					printk("low on mini buffers %i\n",
2189 					       cur_size);
2190 #endif
2191 					ace_load_mini_rx_ring(dev,
2192 							      RX_MINI_SIZE - cur_size);
2193 				} else
2194 					run_tasklet = 1;
2195 			}
2196 		}
2197 
2198 		if (ap->jumbo) {
2199 			cur_size = atomic_read(&ap->cur_jumbo_bufs);
2200 			if (cur_size < RX_LOW_JUMBO_THRES) {
2201 				if ((cur_size < RX_PANIC_JUMBO_THRES) &&
2202 				    !test_and_set_bit(0,
2203 						      &ap->jumbo_refill_busy)){
2204 #ifdef DEBUG
2205 					printk("low on jumbo buffers %i\n",
2206 					       cur_size);
2207 #endif
2208 					ace_load_jumbo_rx_ring(dev,
2209 							       RX_JUMBO_SIZE - cur_size);
2210 				} else
2211 					run_tasklet = 1;
2212 			}
2213 		}
2214 		if (run_tasklet && !ap->tasklet_pending) {
2215 			ap->tasklet_pending = 1;
2216 			tasklet_schedule(&ap->ace_tasklet);
2217 		}
2218 	}
2219 
2220 	return IRQ_HANDLED;
2221 }
2222 
2223 static int ace_open(struct net_device *dev)
2224 {
2225 	struct ace_private *ap = netdev_priv(dev);
2226 	struct ace_regs __iomem *regs = ap->regs;
2227 	struct cmd cmd;
2228 
2229 	if (!(ap->fw_running)) {
2230 		printk(KERN_WARNING "%s: Firmware not running!\n", dev->name);
2231 		return -EBUSY;
2232 	}
2233 
2234 	writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu);
2235 
2236 	cmd.evt = C_CLEAR_STATS;
2237 	cmd.code = 0;
2238 	cmd.idx = 0;
2239 	ace_issue_cmd(regs, &cmd);
2240 
2241 	cmd.evt = C_HOST_STATE;
2242 	cmd.code = C_C_STACK_UP;
2243 	cmd.idx = 0;
2244 	ace_issue_cmd(regs, &cmd);
2245 
2246 	if (ap->jumbo &&
2247 	    !test_and_set_bit(0, &ap->jumbo_refill_busy))
2248 		ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE);
2249 
2250 	if (dev->flags & IFF_PROMISC) {
2251 		cmd.evt = C_SET_PROMISC_MODE;
2252 		cmd.code = C_C_PROMISC_ENABLE;
2253 		cmd.idx = 0;
2254 		ace_issue_cmd(regs, &cmd);
2255 
2256 		ap->promisc = 1;
2257 	}else
2258 		ap->promisc = 0;
2259 	ap->mcast_all = 0;
2260 
2261 #if 0
2262 	cmd.evt = C_LNK_NEGOTIATION;
2263 	cmd.code = 0;
2264 	cmd.idx = 0;
2265 	ace_issue_cmd(regs, &cmd);
2266 #endif
2267 
2268 	netif_start_queue(dev);
2269 
2270 	/*
2271 	 * Setup the bottom half rx ring refill handler
2272 	 */
2273 	tasklet_setup(&ap->ace_tasklet, ace_tasklet);
2274 	return 0;
2275 }
2276 
2277 
2278 static int ace_close(struct net_device *dev)
2279 {
2280 	struct ace_private *ap = netdev_priv(dev);
2281 	struct ace_regs __iomem *regs = ap->regs;
2282 	struct cmd cmd;
2283 	unsigned long flags;
2284 	short i;
2285 
2286 	/*
2287 	 * Without (or before) releasing irq and stopping hardware, this
2288 	 * is an absolute non-sense, by the way. It will be reset instantly
2289 	 * by the first irq.
2290 	 */
2291 	netif_stop_queue(dev);
2292 
2293 
2294 	if (ap->promisc) {
2295 		cmd.evt = C_SET_PROMISC_MODE;
2296 		cmd.code = C_C_PROMISC_DISABLE;
2297 		cmd.idx = 0;
2298 		ace_issue_cmd(regs, &cmd);
2299 		ap->promisc = 0;
2300 	}
2301 
2302 	cmd.evt = C_HOST_STATE;
2303 	cmd.code = C_C_STACK_DOWN;
2304 	cmd.idx = 0;
2305 	ace_issue_cmd(regs, &cmd);
2306 
2307 	tasklet_kill(&ap->ace_tasklet);
2308 
2309 	/*
2310 	 * Make sure one CPU is not processing packets while
2311 	 * buffers are being released by another.
2312 	 */
2313 
2314 	local_irq_save(flags);
2315 	ace_mask_irq(dev);
2316 
2317 	for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
2318 		struct sk_buff *skb;
2319 		struct tx_ring_info *info;
2320 
2321 		info = ap->skb->tx_skbuff + i;
2322 		skb = info->skb;
2323 
2324 		if (dma_unmap_len(info, maplen)) {
2325 			if (ACE_IS_TIGON_I(ap)) {
2326 				/* NB: TIGON_1 is special, tx_ring is in io space */
2327 				struct tx_desc __iomem *tx;
2328 				tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i];
2329 				writel(0, &tx->addr.addrhi);
2330 				writel(0, &tx->addr.addrlo);
2331 				writel(0, &tx->flagsize);
2332 			} else
2333 				memset(ap->tx_ring + i, 0,
2334 				       sizeof(struct tx_desc));
2335 			dma_unmap_page(&ap->pdev->dev,
2336 				       dma_unmap_addr(info, mapping),
2337 				       dma_unmap_len(info, maplen),
2338 				       DMA_TO_DEVICE);
2339 			dma_unmap_len_set(info, maplen, 0);
2340 		}
2341 		if (skb) {
2342 			dev_kfree_skb(skb);
2343 			info->skb = NULL;
2344 		}
2345 	}
2346 
2347 	if (ap->jumbo) {
2348 		cmd.evt = C_RESET_JUMBO_RNG;
2349 		cmd.code = 0;
2350 		cmd.idx = 0;
2351 		ace_issue_cmd(regs, &cmd);
2352 	}
2353 
2354 	ace_unmask_irq(dev);
2355 	local_irq_restore(flags);
2356 
2357 	return 0;
2358 }
2359 
2360 
2361 static inline dma_addr_t
2362 ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
2363 	       struct sk_buff *tail, u32 idx)
2364 {
2365 	dma_addr_t mapping;
2366 	struct tx_ring_info *info;
2367 
2368 	mapping = dma_map_page(&ap->pdev->dev, virt_to_page(skb->data),
2369 			       offset_in_page(skb->data), skb->len,
2370 			       DMA_TO_DEVICE);
2371 
2372 	info = ap->skb->tx_skbuff + idx;
2373 	info->skb = tail;
2374 	dma_unmap_addr_set(info, mapping, mapping);
2375 	dma_unmap_len_set(info, maplen, skb->len);
2376 	return mapping;
2377 }
2378 
2379 
2380 static inline void
2381 ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
2382 	       u32 flagsize, u32 vlan_tag)
2383 {
2384 #if !USE_TX_COAL_NOW
2385 	flagsize &= ~BD_FLG_COAL_NOW;
2386 #endif
2387 
2388 	if (ACE_IS_TIGON_I(ap)) {
2389 		struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc;
2390 		writel(addr >> 32, &io->addr.addrhi);
2391 		writel(addr & 0xffffffff, &io->addr.addrlo);
2392 		writel(flagsize, &io->flagsize);
2393 		writel(vlan_tag, &io->vlanres);
2394 	} else {
2395 		desc->addr.addrhi = addr >> 32;
2396 		desc->addr.addrlo = addr;
2397 		desc->flagsize = flagsize;
2398 		desc->vlanres = vlan_tag;
2399 	}
2400 }
2401 
2402 
2403 static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
2404 				  struct net_device *dev)
2405 {
2406 	struct ace_private *ap = netdev_priv(dev);
2407 	struct ace_regs __iomem *regs = ap->regs;
2408 	struct tx_desc *desc;
2409 	u32 idx, flagsize;
2410 	unsigned long maxjiff = jiffies + 3*HZ;
2411 
2412 restart:
2413 	idx = ap->tx_prd;
2414 
2415 	if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2416 		goto overflow;
2417 
2418 	if (!skb_shinfo(skb)->nr_frags)	{
2419 		dma_addr_t mapping;
2420 		u32 vlan_tag = 0;
2421 
2422 		mapping = ace_map_tx_skb(ap, skb, skb, idx);
2423 		flagsize = (skb->len << 16) | (BD_FLG_END);
2424 		if (skb->ip_summed == CHECKSUM_PARTIAL)
2425 			flagsize |= BD_FLG_TCP_UDP_SUM;
2426 		if (skb_vlan_tag_present(skb)) {
2427 			flagsize |= BD_FLG_VLAN_TAG;
2428 			vlan_tag = skb_vlan_tag_get(skb);
2429 		}
2430 		desc = ap->tx_ring + idx;
2431 		idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2432 
2433 		/* Look at ace_tx_int for explanations. */
2434 		if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2435 			flagsize |= BD_FLG_COAL_NOW;
2436 
2437 		ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2438 	} else {
2439 		dma_addr_t mapping;
2440 		u32 vlan_tag = 0;
2441 		int i, len = 0;
2442 
2443 		mapping = ace_map_tx_skb(ap, skb, NULL, idx);
2444 		flagsize = (skb_headlen(skb) << 16);
2445 		if (skb->ip_summed == CHECKSUM_PARTIAL)
2446 			flagsize |= BD_FLG_TCP_UDP_SUM;
2447 		if (skb_vlan_tag_present(skb)) {
2448 			flagsize |= BD_FLG_VLAN_TAG;
2449 			vlan_tag = skb_vlan_tag_get(skb);
2450 		}
2451 
2452 		ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
2453 
2454 		idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2455 
2456 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2457 			const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2458 			struct tx_ring_info *info;
2459 
2460 			len += skb_frag_size(frag);
2461 			info = ap->skb->tx_skbuff + idx;
2462 			desc = ap->tx_ring + idx;
2463 
2464 			mapping = skb_frag_dma_map(&ap->pdev->dev, frag, 0,
2465 						   skb_frag_size(frag),
2466 						   DMA_TO_DEVICE);
2467 
2468 			flagsize = skb_frag_size(frag) << 16;
2469 			if (skb->ip_summed == CHECKSUM_PARTIAL)
2470 				flagsize |= BD_FLG_TCP_UDP_SUM;
2471 			idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
2472 
2473 			if (i == skb_shinfo(skb)->nr_frags - 1) {
2474 				flagsize |= BD_FLG_END;
2475 				if (tx_ring_full(ap, ap->tx_ret_csm, idx))
2476 					flagsize |= BD_FLG_COAL_NOW;
2477 
2478 				/*
2479 				 * Only the last fragment frees
2480 				 * the skb!
2481 				 */
2482 				info->skb = skb;
2483 			} else {
2484 				info->skb = NULL;
2485 			}
2486 			dma_unmap_addr_set(info, mapping, mapping);
2487 			dma_unmap_len_set(info, maplen, skb_frag_size(frag));
2488 			ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
2489 		}
2490 	}
2491 
2492  	wmb();
2493  	ap->tx_prd = idx;
2494  	ace_set_txprd(regs, ap, idx);
2495 
2496 	if (flagsize & BD_FLG_COAL_NOW) {
2497 		netif_stop_queue(dev);
2498 
2499 		/*
2500 		 * A TX-descriptor producer (an IRQ) might have gotten
2501 		 * between, making the ring free again. Since xmit is
2502 		 * serialized, this is the only situation we have to
2503 		 * re-test.
2504 		 */
2505 		if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
2506 			netif_wake_queue(dev);
2507 	}
2508 
2509 	return NETDEV_TX_OK;
2510 
2511 overflow:
2512 	/*
2513 	 * This race condition is unavoidable with lock-free drivers.
2514 	 * We wake up the queue _before_ tx_prd is advanced, so that we can
2515 	 * enter hard_start_xmit too early, while tx ring still looks closed.
2516 	 * This happens ~1-4 times per 100000 packets, so that we can allow
2517 	 * to loop syncing to other CPU. Probably, we need an additional
2518 	 * wmb() in ace_tx_intr as well.
2519 	 *
2520 	 * Note that this race is relieved by reserving one more entry
2521 	 * in tx ring than it is necessary (see original non-SG driver).
2522 	 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which
2523 	 * is already overkill.
2524 	 *
2525 	 * Alternative is to return with 1 not throttling queue. In this
2526 	 * case loop becomes longer, no more useful effects.
2527 	 */
2528 	if (time_before(jiffies, maxjiff)) {
2529 		barrier();
2530 		cpu_relax();
2531 		goto restart;
2532 	}
2533 
2534 	/* The ring is stuck full. */
2535 	printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name);
2536 	return NETDEV_TX_BUSY;
2537 }
2538 
2539 
2540 static int ace_change_mtu(struct net_device *dev, int new_mtu)
2541 {
2542 	struct ace_private *ap = netdev_priv(dev);
2543 	struct ace_regs __iomem *regs = ap->regs;
2544 
2545 	writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu);
2546 	dev->mtu = new_mtu;
2547 
2548 	if (new_mtu > ACE_STD_MTU) {
2549 		if (!(ap->jumbo)) {
2550 			printk(KERN_INFO "%s: Enabling Jumbo frame "
2551 			       "support\n", dev->name);
2552 			ap->jumbo = 1;
2553 			if (!test_and_set_bit(0, &ap->jumbo_refill_busy))
2554 				ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE);
2555 			ace_set_rxtx_parms(dev, 1);
2556 		}
2557 	} else {
2558 		while (test_and_set_bit(0, &ap->jumbo_refill_busy));
2559 		ace_sync_irq(dev->irq);
2560 		ace_set_rxtx_parms(dev, 0);
2561 		if (ap->jumbo) {
2562 			struct cmd cmd;
2563 
2564 			cmd.evt = C_RESET_JUMBO_RNG;
2565 			cmd.code = 0;
2566 			cmd.idx = 0;
2567 			ace_issue_cmd(regs, &cmd);
2568 		}
2569 	}
2570 
2571 	return 0;
2572 }
2573 
2574 static int ace_get_link_ksettings(struct net_device *dev,
2575 				  struct ethtool_link_ksettings *cmd)
2576 {
2577 	struct ace_private *ap = netdev_priv(dev);
2578 	struct ace_regs __iomem *regs = ap->regs;
2579 	u32 link;
2580 	u32 supported;
2581 
2582 	memset(cmd, 0, sizeof(struct ethtool_link_ksettings));
2583 
2584 	supported = (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2585 		     SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2586 		     SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full |
2587 		     SUPPORTED_Autoneg | SUPPORTED_FIBRE);
2588 
2589 	cmd->base.port = PORT_FIBRE;
2590 
2591 	link = readl(&regs->GigLnkState);
2592 	if (link & LNK_1000MB) {
2593 		cmd->base.speed = SPEED_1000;
2594 	} else {
2595 		link = readl(&regs->FastLnkState);
2596 		if (link & LNK_100MB)
2597 			cmd->base.speed = SPEED_100;
2598 		else if (link & LNK_10MB)
2599 			cmd->base.speed = SPEED_10;
2600 		else
2601 			cmd->base.speed = 0;
2602 	}
2603 	if (link & LNK_FULL_DUPLEX)
2604 		cmd->base.duplex = DUPLEX_FULL;
2605 	else
2606 		cmd->base.duplex = DUPLEX_HALF;
2607 
2608 	if (link & LNK_NEGOTIATE)
2609 		cmd->base.autoneg = AUTONEG_ENABLE;
2610 	else
2611 		cmd->base.autoneg = AUTONEG_DISABLE;
2612 
2613 #if 0
2614 	/*
2615 	 * Current struct ethtool_cmd is insufficient
2616 	 */
2617 	ecmd->trace = readl(&regs->TuneTrace);
2618 
2619 	ecmd->txcoal = readl(&regs->TuneTxCoalTicks);
2620 	ecmd->rxcoal = readl(&regs->TuneRxCoalTicks);
2621 #endif
2622 
2623 	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2624 						supported);
2625 
2626 	return 0;
2627 }
2628 
2629 static int ace_set_link_ksettings(struct net_device *dev,
2630 				  const struct ethtool_link_ksettings *cmd)
2631 {
2632 	struct ace_private *ap = netdev_priv(dev);
2633 	struct ace_regs __iomem *regs = ap->regs;
2634 	u32 link, speed;
2635 
2636 	link = readl(&regs->GigLnkState);
2637 	if (link & LNK_1000MB)
2638 		speed = SPEED_1000;
2639 	else {
2640 		link = readl(&regs->FastLnkState);
2641 		if (link & LNK_100MB)
2642 			speed = SPEED_100;
2643 		else if (link & LNK_10MB)
2644 			speed = SPEED_10;
2645 		else
2646 			speed = SPEED_100;
2647 	}
2648 
2649 	link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB |
2650 		LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL;
2651 	if (!ACE_IS_TIGON_I(ap))
2652 		link |= LNK_TX_FLOW_CTL_Y;
2653 	if (cmd->base.autoneg == AUTONEG_ENABLE)
2654 		link |= LNK_NEGOTIATE;
2655 	if (cmd->base.speed != speed) {
2656 		link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB);
2657 		switch (cmd->base.speed) {
2658 		case SPEED_1000:
2659 			link |= LNK_1000MB;
2660 			break;
2661 		case SPEED_100:
2662 			link |= LNK_100MB;
2663 			break;
2664 		case SPEED_10:
2665 			link |= LNK_10MB;
2666 			break;
2667 		}
2668 	}
2669 
2670 	if (cmd->base.duplex == DUPLEX_FULL)
2671 		link |= LNK_FULL_DUPLEX;
2672 
2673 	if (link != ap->link) {
2674 		struct cmd cmd;
2675 		printk(KERN_INFO "%s: Renegotiating link state\n",
2676 		       dev->name);
2677 
2678 		ap->link = link;
2679 		writel(link, &regs->TuneLink);
2680 		if (!ACE_IS_TIGON_I(ap))
2681 			writel(link, &regs->TuneFastLink);
2682 		wmb();
2683 
2684 		cmd.evt = C_LNK_NEGOTIATION;
2685 		cmd.code = 0;
2686 		cmd.idx = 0;
2687 		ace_issue_cmd(regs, &cmd);
2688 	}
2689 	return 0;
2690 }
2691 
2692 static void ace_get_drvinfo(struct net_device *dev,
2693 			    struct ethtool_drvinfo *info)
2694 {
2695 	struct ace_private *ap = netdev_priv(dev);
2696 
2697 	strlcpy(info->driver, "acenic", sizeof(info->driver));
2698 	snprintf(info->fw_version, sizeof(info->version), "%i.%i.%i",
2699 		 ap->firmware_major, ap->firmware_minor, ap->firmware_fix);
2700 
2701 	if (ap->pdev)
2702 		strlcpy(info->bus_info, pci_name(ap->pdev),
2703 			sizeof(info->bus_info));
2704 
2705 }
2706 
2707 /*
2708  * Set the hardware MAC address.
2709  */
2710 static int ace_set_mac_addr(struct net_device *dev, void *p)
2711 {
2712 	struct ace_private *ap = netdev_priv(dev);
2713 	struct ace_regs __iomem *regs = ap->regs;
2714 	struct sockaddr *addr=p;
2715 	u8 *da;
2716 	struct cmd cmd;
2717 
2718 	if(netif_running(dev))
2719 		return -EBUSY;
2720 
2721 	memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
2722 
2723 	da = (u8 *)dev->dev_addr;
2724 
2725 	writel(da[0] << 8 | da[1], &regs->MacAddrHi);
2726 	writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5],
2727 	       &regs->MacAddrLo);
2728 
2729 	cmd.evt = C_SET_MAC_ADDR;
2730 	cmd.code = 0;
2731 	cmd.idx = 0;
2732 	ace_issue_cmd(regs, &cmd);
2733 
2734 	return 0;
2735 }
2736 
2737 
2738 static void ace_set_multicast_list(struct net_device *dev)
2739 {
2740 	struct ace_private *ap = netdev_priv(dev);
2741 	struct ace_regs __iomem *regs = ap->regs;
2742 	struct cmd cmd;
2743 
2744 	if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) {
2745 		cmd.evt = C_SET_MULTICAST_MODE;
2746 		cmd.code = C_C_MCAST_ENABLE;
2747 		cmd.idx = 0;
2748 		ace_issue_cmd(regs, &cmd);
2749 		ap->mcast_all = 1;
2750 	} else if (ap->mcast_all) {
2751 		cmd.evt = C_SET_MULTICAST_MODE;
2752 		cmd.code = C_C_MCAST_DISABLE;
2753 		cmd.idx = 0;
2754 		ace_issue_cmd(regs, &cmd);
2755 		ap->mcast_all = 0;
2756 	}
2757 
2758 	if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) {
2759 		cmd.evt = C_SET_PROMISC_MODE;
2760 		cmd.code = C_C_PROMISC_ENABLE;
2761 		cmd.idx = 0;
2762 		ace_issue_cmd(regs, &cmd);
2763 		ap->promisc = 1;
2764 	}else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) {
2765 		cmd.evt = C_SET_PROMISC_MODE;
2766 		cmd.code = C_C_PROMISC_DISABLE;
2767 		cmd.idx = 0;
2768 		ace_issue_cmd(regs, &cmd);
2769 		ap->promisc = 0;
2770 	}
2771 
2772 	/*
2773 	 * For the time being multicast relies on the upper layers
2774 	 * filtering it properly. The Firmware does not allow one to
2775 	 * set the entire multicast list at a time and keeping track of
2776 	 * it here is going to be messy.
2777 	 */
2778 	if (!netdev_mc_empty(dev) && !ap->mcast_all) {
2779 		cmd.evt = C_SET_MULTICAST_MODE;
2780 		cmd.code = C_C_MCAST_ENABLE;
2781 		cmd.idx = 0;
2782 		ace_issue_cmd(regs, &cmd);
2783 	}else if (!ap->mcast_all) {
2784 		cmd.evt = C_SET_MULTICAST_MODE;
2785 		cmd.code = C_C_MCAST_DISABLE;
2786 		cmd.idx = 0;
2787 		ace_issue_cmd(regs, &cmd);
2788 	}
2789 }
2790 
2791 
2792 static struct net_device_stats *ace_get_stats(struct net_device *dev)
2793 {
2794 	struct ace_private *ap = netdev_priv(dev);
2795 	struct ace_mac_stats __iomem *mac_stats =
2796 		(struct ace_mac_stats __iomem *)ap->regs->Stats;
2797 
2798 	dev->stats.rx_missed_errors = readl(&mac_stats->drop_space);
2799 	dev->stats.multicast = readl(&mac_stats->kept_mc);
2800 	dev->stats.collisions = readl(&mac_stats->coll);
2801 
2802 	return &dev->stats;
2803 }
2804 
2805 
2806 static void ace_copy(struct ace_regs __iomem *regs, const __be32 *src,
2807 		     u32 dest, int size)
2808 {
2809 	void __iomem *tdest;
2810 	short tsize, i;
2811 
2812 	if (size <= 0)
2813 		return;
2814 
2815 	while (size > 0) {
2816 		tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2817 			    min_t(u32, size, ACE_WINDOW_SIZE));
2818 		tdest = (void __iomem *) &regs->Window +
2819 			(dest & (ACE_WINDOW_SIZE - 1));
2820 		writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2821 		for (i = 0; i < (tsize / 4); i++) {
2822 			/* Firmware is big-endian */
2823 			writel(be32_to_cpup(src), tdest);
2824 			src++;
2825 			tdest += 4;
2826 			dest += 4;
2827 			size -= 4;
2828 		}
2829 	}
2830 }
2831 
2832 
2833 static void ace_clear(struct ace_regs __iomem *regs, u32 dest, int size)
2834 {
2835 	void __iomem *tdest;
2836 	short tsize = 0, i;
2837 
2838 	if (size <= 0)
2839 		return;
2840 
2841 	while (size > 0) {
2842 		tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1),
2843 				min_t(u32, size, ACE_WINDOW_SIZE));
2844 		tdest = (void __iomem *) &regs->Window +
2845 			(dest & (ACE_WINDOW_SIZE - 1));
2846 		writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase);
2847 
2848 		for (i = 0; i < (tsize / 4); i++) {
2849 			writel(0, tdest + i*4);
2850 		}
2851 
2852 		dest += tsize;
2853 		size -= tsize;
2854 	}
2855 }
2856 
2857 
2858 /*
2859  * Download the firmware into the SRAM on the NIC
2860  *
2861  * This operation requires the NIC to be halted and is performed with
2862  * interrupts disabled and with the spinlock hold.
2863  */
2864 static int ace_load_firmware(struct net_device *dev)
2865 {
2866 	const struct firmware *fw;
2867 	const char *fw_name = "acenic/tg2.bin";
2868 	struct ace_private *ap = netdev_priv(dev);
2869 	struct ace_regs __iomem *regs = ap->regs;
2870 	const __be32 *fw_data;
2871 	u32 load_addr;
2872 	int ret;
2873 
2874 	if (!(readl(&regs->CpuCtrl) & CPU_HALTED)) {
2875 		printk(KERN_ERR "%s: trying to download firmware while the "
2876 		       "CPU is running!\n", ap->name);
2877 		return -EFAULT;
2878 	}
2879 
2880 	if (ACE_IS_TIGON_I(ap))
2881 		fw_name = "acenic/tg1.bin";
2882 
2883 	ret = request_firmware(&fw, fw_name, &ap->pdev->dev);
2884 	if (ret) {
2885 		printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
2886 		       ap->name, fw_name);
2887 		return ret;
2888 	}
2889 
2890 	fw_data = (void *)fw->data;
2891 
2892 	/* Firmware blob starts with version numbers, followed by
2893 	   load and start address. Remainder is the blob to be loaded
2894 	   contiguously from load address. We don't bother to represent
2895 	   the BSS/SBSS sections any more, since we were clearing the
2896 	   whole thing anyway. */
2897 	ap->firmware_major = fw->data[0];
2898 	ap->firmware_minor = fw->data[1];
2899 	ap->firmware_fix = fw->data[2];
2900 
2901 	ap->firmware_start = be32_to_cpu(fw_data[1]);
2902 	if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) {
2903 		printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2904 		       ap->name, ap->firmware_start, fw_name);
2905 		ret = -EINVAL;
2906 		goto out;
2907 	}
2908 
2909 	load_addr = be32_to_cpu(fw_data[2]);
2910 	if (load_addr < 0x4000 || load_addr >= 0x80000) {
2911 		printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n",
2912 		       ap->name, load_addr, fw_name);
2913 		ret = -EINVAL;
2914 		goto out;
2915 	}
2916 
2917 	/*
2918 	 * Do not try to clear more than 512KiB or we end up seeing
2919 	 * funny things on NICs with only 512KiB SRAM
2920 	 */
2921 	ace_clear(regs, 0x2000, 0x80000-0x2000);
2922 	ace_copy(regs, &fw_data[3], load_addr, fw->size-12);
2923  out:
2924 	release_firmware(fw);
2925 	return ret;
2926 }
2927 
2928 
2929 /*
2930  * The eeprom on the AceNIC is an Atmel i2c EEPROM.
2931  *
2932  * Accessing the EEPROM is `interesting' to say the least - don't read
2933  * this code right after dinner.
2934  *
2935  * This is all about black magic and bit-banging the device .... I
2936  * wonder in what hospital they have put the guy who designed the i2c
2937  * specs.
2938  *
2939  * Oh yes, this is only the beginning!
2940  *
2941  * Thanks to Stevarino Webinski for helping tracking down the bugs in the
2942  * code i2c readout code by beta testing all my hacks.
2943  */
2944 static void eeprom_start(struct ace_regs __iomem *regs)
2945 {
2946 	u32 local;
2947 
2948 	readl(&regs->LocalCtrl);
2949 	udelay(ACE_SHORT_DELAY);
2950 	local = readl(&regs->LocalCtrl);
2951 	local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE;
2952 	writel(local, &regs->LocalCtrl);
2953 	readl(&regs->LocalCtrl);
2954 	mb();
2955 	udelay(ACE_SHORT_DELAY);
2956 	local |= EEPROM_CLK_OUT;
2957 	writel(local, &regs->LocalCtrl);
2958 	readl(&regs->LocalCtrl);
2959 	mb();
2960 	udelay(ACE_SHORT_DELAY);
2961 	local &= ~EEPROM_DATA_OUT;
2962 	writel(local, &regs->LocalCtrl);
2963 	readl(&regs->LocalCtrl);
2964 	mb();
2965 	udelay(ACE_SHORT_DELAY);
2966 	local &= ~EEPROM_CLK_OUT;
2967 	writel(local, &regs->LocalCtrl);
2968 	readl(&regs->LocalCtrl);
2969 	mb();
2970 }
2971 
2972 
2973 static void eeprom_prep(struct ace_regs __iomem *regs, u8 magic)
2974 {
2975 	short i;
2976 	u32 local;
2977 
2978 	udelay(ACE_SHORT_DELAY);
2979 	local = readl(&regs->LocalCtrl);
2980 	local &= ~EEPROM_DATA_OUT;
2981 	local |= EEPROM_WRITE_ENABLE;
2982 	writel(local, &regs->LocalCtrl);
2983 	readl(&regs->LocalCtrl);
2984 	mb();
2985 
2986 	for (i = 0; i < 8; i++, magic <<= 1) {
2987 		udelay(ACE_SHORT_DELAY);
2988 		if (magic & 0x80)
2989 			local |= EEPROM_DATA_OUT;
2990 		else
2991 			local &= ~EEPROM_DATA_OUT;
2992 		writel(local, &regs->LocalCtrl);
2993 		readl(&regs->LocalCtrl);
2994 		mb();
2995 
2996 		udelay(ACE_SHORT_DELAY);
2997 		local |= EEPROM_CLK_OUT;
2998 		writel(local, &regs->LocalCtrl);
2999 		readl(&regs->LocalCtrl);
3000 		mb();
3001 		udelay(ACE_SHORT_DELAY);
3002 		local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT);
3003 		writel(local, &regs->LocalCtrl);
3004 		readl(&regs->LocalCtrl);
3005 		mb();
3006 	}
3007 }
3008 
3009 
3010 static int eeprom_check_ack(struct ace_regs __iomem *regs)
3011 {
3012 	int state;
3013 	u32 local;
3014 
3015 	local = readl(&regs->LocalCtrl);
3016 	local &= ~EEPROM_WRITE_ENABLE;
3017 	writel(local, &regs->LocalCtrl);
3018 	readl(&regs->LocalCtrl);
3019 	mb();
3020 	udelay(ACE_LONG_DELAY);
3021 	local |= EEPROM_CLK_OUT;
3022 	writel(local, &regs->LocalCtrl);
3023 	readl(&regs->LocalCtrl);
3024 	mb();
3025 	udelay(ACE_SHORT_DELAY);
3026 	/* sample data in middle of high clk */
3027 	state = (readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0;
3028 	udelay(ACE_SHORT_DELAY);
3029 	mb();
3030 	writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3031 	readl(&regs->LocalCtrl);
3032 	mb();
3033 
3034 	return state;
3035 }
3036 
3037 
3038 static void eeprom_stop(struct ace_regs __iomem *regs)
3039 {
3040 	u32 local;
3041 
3042 	udelay(ACE_SHORT_DELAY);
3043 	local = readl(&regs->LocalCtrl);
3044 	local |= EEPROM_WRITE_ENABLE;
3045 	writel(local, &regs->LocalCtrl);
3046 	readl(&regs->LocalCtrl);
3047 	mb();
3048 	udelay(ACE_SHORT_DELAY);
3049 	local &= ~EEPROM_DATA_OUT;
3050 	writel(local, &regs->LocalCtrl);
3051 	readl(&regs->LocalCtrl);
3052 	mb();
3053 	udelay(ACE_SHORT_DELAY);
3054 	local |= EEPROM_CLK_OUT;
3055 	writel(local, &regs->LocalCtrl);
3056 	readl(&regs->LocalCtrl);
3057 	mb();
3058 	udelay(ACE_SHORT_DELAY);
3059 	local |= EEPROM_DATA_OUT;
3060 	writel(local, &regs->LocalCtrl);
3061 	readl(&regs->LocalCtrl);
3062 	mb();
3063 	udelay(ACE_LONG_DELAY);
3064 	local &= ~EEPROM_CLK_OUT;
3065 	writel(local, &regs->LocalCtrl);
3066 	mb();
3067 }
3068 
3069 
3070 /*
3071  * Read a whole byte from the EEPROM.
3072  */
3073 static int read_eeprom_byte(struct net_device *dev, unsigned long offset)
3074 {
3075 	struct ace_private *ap = netdev_priv(dev);
3076 	struct ace_regs __iomem *regs = ap->regs;
3077 	unsigned long flags;
3078 	u32 local;
3079 	int result = 0;
3080 	short i;
3081 
3082 	/*
3083 	 * Don't take interrupts on this CPU will bit banging
3084 	 * the %#%#@$ I2C device
3085 	 */
3086 	local_irq_save(flags);
3087 
3088 	eeprom_start(regs);
3089 
3090 	eeprom_prep(regs, EEPROM_WRITE_SELECT);
3091 	if (eeprom_check_ack(regs)) {
3092 		local_irq_restore(flags);
3093 		printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name);
3094 		result = -EIO;
3095 		goto eeprom_read_error;
3096 	}
3097 
3098 	eeprom_prep(regs, (offset >> 8) & 0xff);
3099 	if (eeprom_check_ack(regs)) {
3100 		local_irq_restore(flags);
3101 		printk(KERN_ERR "%s: Unable to set address byte 0\n",
3102 		       ap->name);
3103 		result = -EIO;
3104 		goto eeprom_read_error;
3105 	}
3106 
3107 	eeprom_prep(regs, offset & 0xff);
3108 	if (eeprom_check_ack(regs)) {
3109 		local_irq_restore(flags);
3110 		printk(KERN_ERR "%s: Unable to set address byte 1\n",
3111 		       ap->name);
3112 		result = -EIO;
3113 		goto eeprom_read_error;
3114 	}
3115 
3116 	eeprom_start(regs);
3117 	eeprom_prep(regs, EEPROM_READ_SELECT);
3118 	if (eeprom_check_ack(regs)) {
3119 		local_irq_restore(flags);
3120 		printk(KERN_ERR "%s: Unable to set READ_SELECT\n",
3121 		       ap->name);
3122 		result = -EIO;
3123 		goto eeprom_read_error;
3124 	}
3125 
3126 	for (i = 0; i < 8; i++) {
3127 		local = readl(&regs->LocalCtrl);
3128 		local &= ~EEPROM_WRITE_ENABLE;
3129 		writel(local, &regs->LocalCtrl);
3130 		readl(&regs->LocalCtrl);
3131 		udelay(ACE_LONG_DELAY);
3132 		mb();
3133 		local |= EEPROM_CLK_OUT;
3134 		writel(local, &regs->LocalCtrl);
3135 		readl(&regs->LocalCtrl);
3136 		mb();
3137 		udelay(ACE_SHORT_DELAY);
3138 		/* sample data mid high clk */
3139 		result = (result << 1) |
3140 			((readl(&regs->LocalCtrl) & EEPROM_DATA_IN) != 0);
3141 		udelay(ACE_SHORT_DELAY);
3142 		mb();
3143 		local = readl(&regs->LocalCtrl);
3144 		local &= ~EEPROM_CLK_OUT;
3145 		writel(local, &regs->LocalCtrl);
3146 		readl(&regs->LocalCtrl);
3147 		udelay(ACE_SHORT_DELAY);
3148 		mb();
3149 		if (i == 7) {
3150 			local |= EEPROM_WRITE_ENABLE;
3151 			writel(local, &regs->LocalCtrl);
3152 			readl(&regs->LocalCtrl);
3153 			mb();
3154 			udelay(ACE_SHORT_DELAY);
3155 		}
3156 	}
3157 
3158 	local |= EEPROM_DATA_OUT;
3159 	writel(local, &regs->LocalCtrl);
3160 	readl(&regs->LocalCtrl);
3161 	mb();
3162 	udelay(ACE_SHORT_DELAY);
3163 	writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl);
3164 	readl(&regs->LocalCtrl);
3165 	udelay(ACE_LONG_DELAY);
3166 	writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl);
3167 	readl(&regs->LocalCtrl);
3168 	mb();
3169 	udelay(ACE_SHORT_DELAY);
3170 	eeprom_stop(regs);
3171 
3172 	local_irq_restore(flags);
3173  out:
3174 	return result;
3175 
3176  eeprom_read_error:
3177 	printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n",
3178 	       ap->name, offset);
3179 	goto out;
3180 }
3181 
3182 module_pci_driver(acenic_pci_driver);
3183