1 /* 2 * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card 3 * and other Tigon based cards. 4 * 5 * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>. 6 * 7 * Thanks to Alteon and 3Com for providing hardware and documentation 8 * enabling me to write this driver. 9 * 10 * A mailing list for discussing the use of this driver has been 11 * setup, please subscribe to the lists if you have any questions 12 * about the driver. Send mail to linux-acenic-help@sunsite.auc.dk to 13 * see how to subscribe. 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2 of the License, or 18 * (at your option) any later version. 19 * 20 * Additional credits: 21 * Pete Wyckoff <wyckoff@ca.sandia.gov>: Initial Linux/Alpha and trace 22 * dump support. The trace dump support has not been 23 * integrated yet however. 24 * Troy Benjegerdes: Big Endian (PPC) patches. 25 * Nate Stahl: Better out of memory handling and stats support. 26 * Aman Singla: Nasty race between interrupt handler and tx code dealing 27 * with 'testing the tx_ret_csm and setting tx_full' 28 * David S. Miller <davem@redhat.com>: conversion to new PCI dma mapping 29 * infrastructure and Sparc support 30 * Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the 31 * driver under Linux/Sparc64 32 * Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards 33 * ETHTOOL_GDRVINFO support 34 * Chip Salzenberg <chip@valinux.com>: Fix race condition between tx 35 * handler and close() cleanup. 36 * Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether 37 * memory mapped IO is enabled to 38 * make the driver work on RS/6000. 39 * Takayoshi Kouchi <kouchi@hpc.bs1.fc.nec.co.jp>: Identifying problem 40 * where the driver would disable 41 * bus master mode if it had to disable 42 * write and invalidate. 43 * Stephen Hack <stephen_hack@hp.com>: Fixed ace_set_mac_addr for little 44 * endian systems. 45 * Val Henson <vhenson@esscom.com>: Reset Jumbo skb producer and 46 * rx producer index when 47 * flushing the Jumbo ring. 48 * Hans Grobler <grobh@sun.ac.za>: Memory leak fixes in the 49 * driver init path. 50 * Grant Grundler <grundler@cup.hp.com>: PCI write posting fixes. 51 */ 52 53 #include <linux/module.h> 54 #include <linux/moduleparam.h> 55 #include <linux/types.h> 56 #include <linux/errno.h> 57 #include <linux/ioport.h> 58 #include <linux/pci.h> 59 #include <linux/dma-mapping.h> 60 #include <linux/kernel.h> 61 #include <linux/netdevice.h> 62 #include <linux/etherdevice.h> 63 #include <linux/skbuff.h> 64 #include <linux/init.h> 65 #include <linux/delay.h> 66 #include <linux/mm.h> 67 #include <linux/highmem.h> 68 #include <linux/sockios.h> 69 #include <linux/firmware.h> 70 #include <linux/slab.h> 71 #include <linux/prefetch.h> 72 #include <linux/if_vlan.h> 73 74 #ifdef SIOCETHTOOL 75 #include <linux/ethtool.h> 76 #endif 77 78 #include <net/sock.h> 79 #include <net/ip.h> 80 81 #include <asm/io.h> 82 #include <asm/irq.h> 83 #include <asm/byteorder.h> 84 #include <asm/uaccess.h> 85 86 87 #define DRV_NAME "acenic" 88 89 #undef INDEX_DEBUG 90 91 #ifdef CONFIG_ACENIC_OMIT_TIGON_I 92 #define ACE_IS_TIGON_I(ap) 0 93 #define ACE_TX_RING_ENTRIES(ap) MAX_TX_RING_ENTRIES 94 #else 95 #define ACE_IS_TIGON_I(ap) (ap->version == 1) 96 #define ACE_TX_RING_ENTRIES(ap) ap->tx_ring_entries 97 #endif 98 99 #ifndef PCI_VENDOR_ID_ALTEON 100 #define PCI_VENDOR_ID_ALTEON 0x12ae 101 #endif 102 #ifndef PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 103 #define PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE 0x0001 104 #define PCI_DEVICE_ID_ALTEON_ACENIC_COPPER 0x0002 105 #endif 106 #ifndef PCI_DEVICE_ID_3COM_3C985 107 #define PCI_DEVICE_ID_3COM_3C985 0x0001 108 #endif 109 #ifndef PCI_VENDOR_ID_NETGEAR 110 #define PCI_VENDOR_ID_NETGEAR 0x1385 111 #define PCI_DEVICE_ID_NETGEAR_GA620 0x620a 112 #endif 113 #ifndef PCI_DEVICE_ID_NETGEAR_GA620T 114 #define PCI_DEVICE_ID_NETGEAR_GA620T 0x630a 115 #endif 116 117 118 /* 119 * Farallon used the DEC vendor ID by mistake and they seem not 120 * to care - stinky! 121 */ 122 #ifndef PCI_DEVICE_ID_FARALLON_PN9000SX 123 #define PCI_DEVICE_ID_FARALLON_PN9000SX 0x1a 124 #endif 125 #ifndef PCI_DEVICE_ID_FARALLON_PN9100T 126 #define PCI_DEVICE_ID_FARALLON_PN9100T 0xfa 127 #endif 128 #ifndef PCI_VENDOR_ID_SGI 129 #define PCI_VENDOR_ID_SGI 0x10a9 130 #endif 131 #ifndef PCI_DEVICE_ID_SGI_ACENIC 132 #define PCI_DEVICE_ID_SGI_ACENIC 0x0009 133 #endif 134 135 static DEFINE_PCI_DEVICE_TABLE(acenic_pci_tbl) = { 136 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_FIBRE, 137 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 138 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_ALTEON_ACENIC_COPPER, 139 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 140 { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C985, 141 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 142 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620, 143 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 144 { PCI_VENDOR_ID_NETGEAR, PCI_DEVICE_ID_NETGEAR_GA620T, 145 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 146 /* 147 * Farallon used the DEC vendor ID on their cards incorrectly, 148 * then later Alteon's ID. 149 */ 150 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_FARALLON_PN9000SX, 151 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 152 { PCI_VENDOR_ID_ALTEON, PCI_DEVICE_ID_FARALLON_PN9100T, 153 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 154 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_ACENIC, 155 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, }, 156 { } 157 }; 158 MODULE_DEVICE_TABLE(pci, acenic_pci_tbl); 159 160 #define ace_sync_irq(irq) synchronize_irq(irq) 161 162 #ifndef offset_in_page 163 #define offset_in_page(ptr) ((unsigned long)(ptr) & ~PAGE_MASK) 164 #endif 165 166 #define ACE_MAX_MOD_PARMS 8 167 #define BOARD_IDX_STATIC 0 168 #define BOARD_IDX_OVERFLOW -1 169 170 #include "acenic.h" 171 172 /* 173 * These must be defined before the firmware is included. 174 */ 175 #define MAX_TEXT_LEN 96*1024 176 #define MAX_RODATA_LEN 8*1024 177 #define MAX_DATA_LEN 2*1024 178 179 #ifndef tigon2FwReleaseLocal 180 #define tigon2FwReleaseLocal 0 181 #endif 182 183 /* 184 * This driver currently supports Tigon I and Tigon II based cards 185 * including the Alteon AceNIC, the 3Com 3C985[B] and NetGear 186 * GA620. The driver should also work on the SGI, DEC and Farallon 187 * versions of the card, however I have not been able to test that 188 * myself. 189 * 190 * This card is really neat, it supports receive hardware checksumming 191 * and jumbo frames (up to 9000 bytes) and does a lot of work in the 192 * firmware. Also the programming interface is quite neat, except for 193 * the parts dealing with the i2c eeprom on the card ;-) 194 * 195 * Using jumbo frames: 196 * 197 * To enable jumbo frames, simply specify an mtu between 1500 and 9000 198 * bytes to ifconfig. Jumbo frames can be enabled or disabled at any time 199 * by running `ifconfig eth<X> mtu <MTU>' with <X> being the Ethernet 200 * interface number and <MTU> being the MTU value. 201 * 202 * Module parameters: 203 * 204 * When compiled as a loadable module, the driver allows for a number 205 * of module parameters to be specified. The driver supports the 206 * following module parameters: 207 * 208 * trace=<val> - Firmware trace level. This requires special traced 209 * firmware to replace the firmware supplied with 210 * the driver - for debugging purposes only. 211 * 212 * link=<val> - Link state. Normally you want to use the default link 213 * parameters set by the driver. This can be used to 214 * override these in case your switch doesn't negotiate 215 * the link properly. Valid values are: 216 * 0x0001 - Force half duplex link. 217 * 0x0002 - Do not negotiate line speed with the other end. 218 * 0x0010 - 10Mbit/sec link. 219 * 0x0020 - 100Mbit/sec link. 220 * 0x0040 - 1000Mbit/sec link. 221 * 0x0100 - Do not negotiate flow control. 222 * 0x0200 - Enable RX flow control Y 223 * 0x0400 - Enable TX flow control Y (Tigon II NICs only). 224 * Default value is 0x0270, ie. enable link+flow 225 * control negotiation. Negotiating the highest 226 * possible link speed with RX flow control enabled. 227 * 228 * When disabling link speed negotiation, only one link 229 * speed is allowed to be specified! 230 * 231 * tx_coal_tick=<val> - number of coalescing clock ticks (us) allowed 232 * to wait for more packets to arive before 233 * interrupting the host, from the time the first 234 * packet arrives. 235 * 236 * rx_coal_tick=<val> - number of coalescing clock ticks (us) allowed 237 * to wait for more packets to arive in the transmit ring, 238 * before interrupting the host, after transmitting the 239 * first packet in the ring. 240 * 241 * max_tx_desc=<val> - maximum number of transmit descriptors 242 * (packets) transmitted before interrupting the host. 243 * 244 * max_rx_desc=<val> - maximum number of receive descriptors 245 * (packets) received before interrupting the host. 246 * 247 * tx_ratio=<val> - 7 bit value (0 - 63) specifying the split in 64th 248 * increments of the NIC's on board memory to be used for 249 * transmit and receive buffers. For the 1MB NIC app. 800KB 250 * is available, on the 1/2MB NIC app. 300KB is available. 251 * 68KB will always be available as a minimum for both 252 * directions. The default value is a 50/50 split. 253 * dis_pci_mem_inval=<val> - disable PCI memory write and invalidate 254 * operations, default (1) is to always disable this as 255 * that is what Alteon does on NT. I have not been able 256 * to measure any real performance differences with 257 * this on my systems. Set <val>=0 if you want to 258 * enable these operations. 259 * 260 * If you use more than one NIC, specify the parameters for the 261 * individual NICs with a comma, ie. trace=0,0x00001fff,0 you want to 262 * run tracing on NIC #2 but not on NIC #1 and #3. 263 * 264 * TODO: 265 * 266 * - Proper multicast support. 267 * - NIC dump support. 268 * - More tuning parameters. 269 * 270 * The mini ring is not used under Linux and I am not sure it makes sense 271 * to actually use it. 272 * 273 * New interrupt handler strategy: 274 * 275 * The old interrupt handler worked using the traditional method of 276 * replacing an skbuff with a new one when a packet arrives. However 277 * the rx rings do not need to contain a static number of buffer 278 * descriptors, thus it makes sense to move the memory allocation out 279 * of the main interrupt handler and do it in a bottom half handler 280 * and only allocate new buffers when the number of buffers in the 281 * ring is below a certain threshold. In order to avoid starving the 282 * NIC under heavy load it is however necessary to force allocation 283 * when hitting a minimum threshold. The strategy for alloction is as 284 * follows: 285 * 286 * RX_LOW_BUF_THRES - allocate buffers in the bottom half 287 * RX_PANIC_LOW_THRES - we are very low on buffers, allocate 288 * the buffers in the interrupt handler 289 * RX_RING_THRES - maximum number of buffers in the rx ring 290 * RX_MINI_THRES - maximum number of buffers in the mini ring 291 * RX_JUMBO_THRES - maximum number of buffers in the jumbo ring 292 * 293 * One advantagous side effect of this allocation approach is that the 294 * entire rx processing can be done without holding any spin lock 295 * since the rx rings and registers are totally independent of the tx 296 * ring and its registers. This of course includes the kmalloc's of 297 * new skb's. Thus start_xmit can run in parallel with rx processing 298 * and the memory allocation on SMP systems. 299 * 300 * Note that running the skb reallocation in a bottom half opens up 301 * another can of races which needs to be handled properly. In 302 * particular it can happen that the interrupt handler tries to run 303 * the reallocation while the bottom half is either running on another 304 * CPU or was interrupted on the same CPU. To get around this the 305 * driver uses bitops to prevent the reallocation routines from being 306 * reentered. 307 * 308 * TX handling can also be done without holding any spin lock, wheee 309 * this is fun! since tx_ret_csm is only written to by the interrupt 310 * handler. The case to be aware of is when shutting down the device 311 * and cleaning up where it is necessary to make sure that 312 * start_xmit() is not running while this is happening. Well DaveM 313 * informs me that this case is already protected against ... bye bye 314 * Mr. Spin Lock, it was nice to know you. 315 * 316 * TX interrupts are now partly disabled so the NIC will only generate 317 * TX interrupts for the number of coal ticks, not for the number of 318 * TX packets in the queue. This should reduce the number of TX only, 319 * ie. when no RX processing is done, interrupts seen. 320 */ 321 322 /* 323 * Threshold values for RX buffer allocation - the low water marks for 324 * when to start refilling the rings are set to 75% of the ring 325 * sizes. It seems to make sense to refill the rings entirely from the 326 * intrrupt handler once it gets below the panic threshold, that way 327 * we don't risk that the refilling is moved to another CPU when the 328 * one running the interrupt handler just got the slab code hot in its 329 * cache. 330 */ 331 #define RX_RING_SIZE 72 332 #define RX_MINI_SIZE 64 333 #define RX_JUMBO_SIZE 48 334 335 #define RX_PANIC_STD_THRES 16 336 #define RX_PANIC_STD_REFILL (3*RX_PANIC_STD_THRES)/2 337 #define RX_LOW_STD_THRES (3*RX_RING_SIZE)/4 338 #define RX_PANIC_MINI_THRES 12 339 #define RX_PANIC_MINI_REFILL (3*RX_PANIC_MINI_THRES)/2 340 #define RX_LOW_MINI_THRES (3*RX_MINI_SIZE)/4 341 #define RX_PANIC_JUMBO_THRES 6 342 #define RX_PANIC_JUMBO_REFILL (3*RX_PANIC_JUMBO_THRES)/2 343 #define RX_LOW_JUMBO_THRES (3*RX_JUMBO_SIZE)/4 344 345 346 /* 347 * Size of the mini ring entries, basically these just should be big 348 * enough to take TCP ACKs 349 */ 350 #define ACE_MINI_SIZE 100 351 352 #define ACE_MINI_BUFSIZE ACE_MINI_SIZE 353 #define ACE_STD_BUFSIZE (ACE_STD_MTU + ETH_HLEN + 4) 354 #define ACE_JUMBO_BUFSIZE (ACE_JUMBO_MTU + ETH_HLEN + 4) 355 356 /* 357 * There seems to be a magic difference in the effect between 995 and 996 358 * but little difference between 900 and 995 ... no idea why. 359 * 360 * There is now a default set of tuning parameters which is set, depending 361 * on whether or not the user enables Jumbo frames. It's assumed that if 362 * Jumbo frames are enabled, the user wants optimal tuning for that case. 363 */ 364 #define DEF_TX_COAL 400 /* 996 */ 365 #define DEF_TX_MAX_DESC 60 /* was 40 */ 366 #define DEF_RX_COAL 120 /* 1000 */ 367 #define DEF_RX_MAX_DESC 25 368 #define DEF_TX_RATIO 21 /* 24 */ 369 370 #define DEF_JUMBO_TX_COAL 20 371 #define DEF_JUMBO_TX_MAX_DESC 60 372 #define DEF_JUMBO_RX_COAL 30 373 #define DEF_JUMBO_RX_MAX_DESC 6 374 #define DEF_JUMBO_TX_RATIO 21 375 376 #if tigon2FwReleaseLocal < 20001118 377 /* 378 * Standard firmware and early modifications duplicate 379 * IRQ load without this flag (coal timer is never reset). 380 * Note that with this flag tx_coal should be less than 381 * time to xmit full tx ring. 382 * 400usec is not so bad for tx ring size of 128. 383 */ 384 #define TX_COAL_INTS_ONLY 1 /* worth it */ 385 #else 386 /* 387 * With modified firmware, this is not necessary, but still useful. 388 */ 389 #define TX_COAL_INTS_ONLY 1 390 #endif 391 392 #define DEF_TRACE 0 393 #define DEF_STAT (2 * TICKS_PER_SEC) 394 395 396 static int link_state[ACE_MAX_MOD_PARMS]; 397 static int trace[ACE_MAX_MOD_PARMS]; 398 static int tx_coal_tick[ACE_MAX_MOD_PARMS]; 399 static int rx_coal_tick[ACE_MAX_MOD_PARMS]; 400 static int max_tx_desc[ACE_MAX_MOD_PARMS]; 401 static int max_rx_desc[ACE_MAX_MOD_PARMS]; 402 static int tx_ratio[ACE_MAX_MOD_PARMS]; 403 static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1}; 404 405 MODULE_AUTHOR("Jes Sorensen <jes@trained-monkey.org>"); 406 MODULE_LICENSE("GPL"); 407 MODULE_DESCRIPTION("AceNIC/3C985/GA620 Gigabit Ethernet driver"); 408 #ifndef CONFIG_ACENIC_OMIT_TIGON_I 409 MODULE_FIRMWARE("acenic/tg1.bin"); 410 #endif 411 MODULE_FIRMWARE("acenic/tg2.bin"); 412 413 module_param_array_named(link, link_state, int, NULL, 0); 414 module_param_array(trace, int, NULL, 0); 415 module_param_array(tx_coal_tick, int, NULL, 0); 416 module_param_array(max_tx_desc, int, NULL, 0); 417 module_param_array(rx_coal_tick, int, NULL, 0); 418 module_param_array(max_rx_desc, int, NULL, 0); 419 module_param_array(tx_ratio, int, NULL, 0); 420 MODULE_PARM_DESC(link, "AceNIC/3C985/NetGear link state"); 421 MODULE_PARM_DESC(trace, "AceNIC/3C985/NetGear firmware trace level"); 422 MODULE_PARM_DESC(tx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first tx descriptor arrives"); 423 MODULE_PARM_DESC(max_tx_desc, "AceNIC/3C985/GA620 max number of transmit descriptors to wait"); 424 MODULE_PARM_DESC(rx_coal_tick, "AceNIC/3C985/GA620 max clock ticks to wait from first rx descriptor arrives"); 425 MODULE_PARM_DESC(max_rx_desc, "AceNIC/3C985/GA620 max number of receive descriptors to wait"); 426 MODULE_PARM_DESC(tx_ratio, "AceNIC/3C985/GA620 ratio of NIC memory used for TX/RX descriptors (range 0-63)"); 427 428 429 static const char version[] = 430 "acenic.c: v0.92 08/05/2002 Jes Sorensen, linux-acenic@SunSITE.dk\n" 431 " http://home.cern.ch/~jes/gige/acenic.html\n"; 432 433 static int ace_get_settings(struct net_device *, struct ethtool_cmd *); 434 static int ace_set_settings(struct net_device *, struct ethtool_cmd *); 435 static void ace_get_drvinfo(struct net_device *, struct ethtool_drvinfo *); 436 437 static const struct ethtool_ops ace_ethtool_ops = { 438 .get_settings = ace_get_settings, 439 .set_settings = ace_set_settings, 440 .get_drvinfo = ace_get_drvinfo, 441 }; 442 443 static void ace_watchdog(struct net_device *dev); 444 445 static const struct net_device_ops ace_netdev_ops = { 446 .ndo_open = ace_open, 447 .ndo_stop = ace_close, 448 .ndo_tx_timeout = ace_watchdog, 449 .ndo_get_stats = ace_get_stats, 450 .ndo_start_xmit = ace_start_xmit, 451 .ndo_set_rx_mode = ace_set_multicast_list, 452 .ndo_validate_addr = eth_validate_addr, 453 .ndo_set_mac_address = ace_set_mac_addr, 454 .ndo_change_mtu = ace_change_mtu, 455 }; 456 457 static int acenic_probe_one(struct pci_dev *pdev, 458 const struct pci_device_id *id) 459 { 460 struct net_device *dev; 461 struct ace_private *ap; 462 static int boards_found; 463 464 dev = alloc_etherdev(sizeof(struct ace_private)); 465 if (dev == NULL) 466 return -ENOMEM; 467 468 SET_NETDEV_DEV(dev, &pdev->dev); 469 470 ap = netdev_priv(dev); 471 ap->pdev = pdev; 472 ap->name = pci_name(pdev); 473 474 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM; 475 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 476 477 dev->watchdog_timeo = 5*HZ; 478 479 dev->netdev_ops = &ace_netdev_ops; 480 SET_ETHTOOL_OPS(dev, &ace_ethtool_ops); 481 482 /* we only display this string ONCE */ 483 if (!boards_found) 484 printk(version); 485 486 if (pci_enable_device(pdev)) 487 goto fail_free_netdev; 488 489 /* 490 * Enable master mode before we start playing with the 491 * pci_command word since pci_set_master() will modify 492 * it. 493 */ 494 pci_set_master(pdev); 495 496 pci_read_config_word(pdev, PCI_COMMAND, &ap->pci_command); 497 498 /* OpenFirmware on Mac's does not set this - DOH.. */ 499 if (!(ap->pci_command & PCI_COMMAND_MEMORY)) { 500 printk(KERN_INFO "%s: Enabling PCI Memory Mapped " 501 "access - was not enabled by BIOS/Firmware\n", 502 ap->name); 503 ap->pci_command = ap->pci_command | PCI_COMMAND_MEMORY; 504 pci_write_config_word(ap->pdev, PCI_COMMAND, 505 ap->pci_command); 506 wmb(); 507 } 508 509 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &ap->pci_latency); 510 if (ap->pci_latency <= 0x40) { 511 ap->pci_latency = 0x40; 512 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, ap->pci_latency); 513 } 514 515 /* 516 * Remap the regs into kernel space - this is abuse of 517 * dev->base_addr since it was means for I/O port 518 * addresses but who gives a damn. 519 */ 520 dev->base_addr = pci_resource_start(pdev, 0); 521 ap->regs = ioremap(dev->base_addr, 0x4000); 522 if (!ap->regs) { 523 printk(KERN_ERR "%s: Unable to map I/O register, " 524 "AceNIC %i will be disabled.\n", 525 ap->name, boards_found); 526 goto fail_free_netdev; 527 } 528 529 switch(pdev->vendor) { 530 case PCI_VENDOR_ID_ALTEON: 531 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9100T) { 532 printk(KERN_INFO "%s: Farallon PN9100-T ", 533 ap->name); 534 } else { 535 printk(KERN_INFO "%s: Alteon AceNIC ", 536 ap->name); 537 } 538 break; 539 case PCI_VENDOR_ID_3COM: 540 printk(KERN_INFO "%s: 3Com 3C985 ", ap->name); 541 break; 542 case PCI_VENDOR_ID_NETGEAR: 543 printk(KERN_INFO "%s: NetGear GA620 ", ap->name); 544 break; 545 case PCI_VENDOR_ID_DEC: 546 if (pdev->device == PCI_DEVICE_ID_FARALLON_PN9000SX) { 547 printk(KERN_INFO "%s: Farallon PN9000-SX ", 548 ap->name); 549 break; 550 } 551 case PCI_VENDOR_ID_SGI: 552 printk(KERN_INFO "%s: SGI AceNIC ", ap->name); 553 break; 554 default: 555 printk(KERN_INFO "%s: Unknown AceNIC ", ap->name); 556 break; 557 } 558 559 printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr); 560 printk("irq %d\n", pdev->irq); 561 562 #ifdef CONFIG_ACENIC_OMIT_TIGON_I 563 if ((readl(&ap->regs->HostCtrl) >> 28) == 4) { 564 printk(KERN_ERR "%s: Driver compiled without Tigon I" 565 " support - NIC disabled\n", dev->name); 566 goto fail_uninit; 567 } 568 #endif 569 570 if (ace_allocate_descriptors(dev)) 571 goto fail_free_netdev; 572 573 #ifdef MODULE 574 if (boards_found >= ACE_MAX_MOD_PARMS) 575 ap->board_idx = BOARD_IDX_OVERFLOW; 576 else 577 ap->board_idx = boards_found; 578 #else 579 ap->board_idx = BOARD_IDX_STATIC; 580 #endif 581 582 if (ace_init(dev)) 583 goto fail_free_netdev; 584 585 if (register_netdev(dev)) { 586 printk(KERN_ERR "acenic: device registration failed\n"); 587 goto fail_uninit; 588 } 589 ap->name = dev->name; 590 591 if (ap->pci_using_dac) 592 dev->features |= NETIF_F_HIGHDMA; 593 594 pci_set_drvdata(pdev, dev); 595 596 boards_found++; 597 return 0; 598 599 fail_uninit: 600 ace_init_cleanup(dev); 601 fail_free_netdev: 602 free_netdev(dev); 603 return -ENODEV; 604 } 605 606 static void acenic_remove_one(struct pci_dev *pdev) 607 { 608 struct net_device *dev = pci_get_drvdata(pdev); 609 struct ace_private *ap = netdev_priv(dev); 610 struct ace_regs __iomem *regs = ap->regs; 611 short i; 612 613 unregister_netdev(dev); 614 615 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); 616 if (ap->version >= 2) 617 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl); 618 619 /* 620 * This clears any pending interrupts 621 */ 622 writel(1, ®s->Mb0Lo); 623 readl(®s->CpuCtrl); /* flush */ 624 625 /* 626 * Make sure no other CPUs are processing interrupts 627 * on the card before the buffers are being released. 628 * Otherwise one might experience some `interesting' 629 * effects. 630 * 631 * Then release the RX buffers - jumbo buffers were 632 * already released in ace_close(). 633 */ 634 ace_sync_irq(dev->irq); 635 636 for (i = 0; i < RX_STD_RING_ENTRIES; i++) { 637 struct sk_buff *skb = ap->skb->rx_std_skbuff[i].skb; 638 639 if (skb) { 640 struct ring_info *ringp; 641 dma_addr_t mapping; 642 643 ringp = &ap->skb->rx_std_skbuff[i]; 644 mapping = dma_unmap_addr(ringp, mapping); 645 pci_unmap_page(ap->pdev, mapping, 646 ACE_STD_BUFSIZE, 647 PCI_DMA_FROMDEVICE); 648 649 ap->rx_std_ring[i].size = 0; 650 ap->skb->rx_std_skbuff[i].skb = NULL; 651 dev_kfree_skb(skb); 652 } 653 } 654 655 if (ap->version >= 2) { 656 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) { 657 struct sk_buff *skb = ap->skb->rx_mini_skbuff[i].skb; 658 659 if (skb) { 660 struct ring_info *ringp; 661 dma_addr_t mapping; 662 663 ringp = &ap->skb->rx_mini_skbuff[i]; 664 mapping = dma_unmap_addr(ringp,mapping); 665 pci_unmap_page(ap->pdev, mapping, 666 ACE_MINI_BUFSIZE, 667 PCI_DMA_FROMDEVICE); 668 669 ap->rx_mini_ring[i].size = 0; 670 ap->skb->rx_mini_skbuff[i].skb = NULL; 671 dev_kfree_skb(skb); 672 } 673 } 674 } 675 676 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) { 677 struct sk_buff *skb = ap->skb->rx_jumbo_skbuff[i].skb; 678 if (skb) { 679 struct ring_info *ringp; 680 dma_addr_t mapping; 681 682 ringp = &ap->skb->rx_jumbo_skbuff[i]; 683 mapping = dma_unmap_addr(ringp, mapping); 684 pci_unmap_page(ap->pdev, mapping, 685 ACE_JUMBO_BUFSIZE, 686 PCI_DMA_FROMDEVICE); 687 688 ap->rx_jumbo_ring[i].size = 0; 689 ap->skb->rx_jumbo_skbuff[i].skb = NULL; 690 dev_kfree_skb(skb); 691 } 692 } 693 694 ace_init_cleanup(dev); 695 free_netdev(dev); 696 } 697 698 static struct pci_driver acenic_pci_driver = { 699 .name = "acenic", 700 .id_table = acenic_pci_tbl, 701 .probe = acenic_probe_one, 702 .remove = acenic_remove_one, 703 }; 704 705 static void ace_free_descriptors(struct net_device *dev) 706 { 707 struct ace_private *ap = netdev_priv(dev); 708 int size; 709 710 if (ap->rx_std_ring != NULL) { 711 size = (sizeof(struct rx_desc) * 712 (RX_STD_RING_ENTRIES + 713 RX_JUMBO_RING_ENTRIES + 714 RX_MINI_RING_ENTRIES + 715 RX_RETURN_RING_ENTRIES)); 716 pci_free_consistent(ap->pdev, size, ap->rx_std_ring, 717 ap->rx_ring_base_dma); 718 ap->rx_std_ring = NULL; 719 ap->rx_jumbo_ring = NULL; 720 ap->rx_mini_ring = NULL; 721 ap->rx_return_ring = NULL; 722 } 723 if (ap->evt_ring != NULL) { 724 size = (sizeof(struct event) * EVT_RING_ENTRIES); 725 pci_free_consistent(ap->pdev, size, ap->evt_ring, 726 ap->evt_ring_dma); 727 ap->evt_ring = NULL; 728 } 729 if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) { 730 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES); 731 pci_free_consistent(ap->pdev, size, ap->tx_ring, 732 ap->tx_ring_dma); 733 } 734 ap->tx_ring = NULL; 735 736 if (ap->evt_prd != NULL) { 737 pci_free_consistent(ap->pdev, sizeof(u32), 738 (void *)ap->evt_prd, ap->evt_prd_dma); 739 ap->evt_prd = NULL; 740 } 741 if (ap->rx_ret_prd != NULL) { 742 pci_free_consistent(ap->pdev, sizeof(u32), 743 (void *)ap->rx_ret_prd, 744 ap->rx_ret_prd_dma); 745 ap->rx_ret_prd = NULL; 746 } 747 if (ap->tx_csm != NULL) { 748 pci_free_consistent(ap->pdev, sizeof(u32), 749 (void *)ap->tx_csm, ap->tx_csm_dma); 750 ap->tx_csm = NULL; 751 } 752 } 753 754 755 static int ace_allocate_descriptors(struct net_device *dev) 756 { 757 struct ace_private *ap = netdev_priv(dev); 758 int size; 759 760 size = (sizeof(struct rx_desc) * 761 (RX_STD_RING_ENTRIES + 762 RX_JUMBO_RING_ENTRIES + 763 RX_MINI_RING_ENTRIES + 764 RX_RETURN_RING_ENTRIES)); 765 766 ap->rx_std_ring = pci_alloc_consistent(ap->pdev, size, 767 &ap->rx_ring_base_dma); 768 if (ap->rx_std_ring == NULL) 769 goto fail; 770 771 ap->rx_jumbo_ring = ap->rx_std_ring + RX_STD_RING_ENTRIES; 772 ap->rx_mini_ring = ap->rx_jumbo_ring + RX_JUMBO_RING_ENTRIES; 773 ap->rx_return_ring = ap->rx_mini_ring + RX_MINI_RING_ENTRIES; 774 775 size = (sizeof(struct event) * EVT_RING_ENTRIES); 776 777 ap->evt_ring = pci_alloc_consistent(ap->pdev, size, &ap->evt_ring_dma); 778 779 if (ap->evt_ring == NULL) 780 goto fail; 781 782 /* 783 * Only allocate a host TX ring for the Tigon II, the Tigon I 784 * has to use PCI registers for this ;-( 785 */ 786 if (!ACE_IS_TIGON_I(ap)) { 787 size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES); 788 789 ap->tx_ring = pci_alloc_consistent(ap->pdev, size, 790 &ap->tx_ring_dma); 791 792 if (ap->tx_ring == NULL) 793 goto fail; 794 } 795 796 ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32), 797 &ap->evt_prd_dma); 798 if (ap->evt_prd == NULL) 799 goto fail; 800 801 ap->rx_ret_prd = pci_alloc_consistent(ap->pdev, sizeof(u32), 802 &ap->rx_ret_prd_dma); 803 if (ap->rx_ret_prd == NULL) 804 goto fail; 805 806 ap->tx_csm = pci_alloc_consistent(ap->pdev, sizeof(u32), 807 &ap->tx_csm_dma); 808 if (ap->tx_csm == NULL) 809 goto fail; 810 811 return 0; 812 813 fail: 814 /* Clean up. */ 815 ace_init_cleanup(dev); 816 return 1; 817 } 818 819 820 /* 821 * Generic cleanup handling data allocated during init. Used when the 822 * module is unloaded or if an error occurs during initialization 823 */ 824 static void ace_init_cleanup(struct net_device *dev) 825 { 826 struct ace_private *ap; 827 828 ap = netdev_priv(dev); 829 830 ace_free_descriptors(dev); 831 832 if (ap->info) 833 pci_free_consistent(ap->pdev, sizeof(struct ace_info), 834 ap->info, ap->info_dma); 835 kfree(ap->skb); 836 kfree(ap->trace_buf); 837 838 if (dev->irq) 839 free_irq(dev->irq, dev); 840 841 iounmap(ap->regs); 842 } 843 844 845 /* 846 * Commands are considered to be slow. 847 */ 848 static inline void ace_issue_cmd(struct ace_regs __iomem *regs, struct cmd *cmd) 849 { 850 u32 idx; 851 852 idx = readl(®s->CmdPrd); 853 854 writel(*(u32 *)(cmd), ®s->CmdRng[idx]); 855 idx = (idx + 1) % CMD_RING_ENTRIES; 856 857 writel(idx, ®s->CmdPrd); 858 } 859 860 861 static int ace_init(struct net_device *dev) 862 { 863 struct ace_private *ap; 864 struct ace_regs __iomem *regs; 865 struct ace_info *info = NULL; 866 struct pci_dev *pdev; 867 unsigned long myjif; 868 u64 tmp_ptr; 869 u32 tig_ver, mac1, mac2, tmp, pci_state; 870 int board_idx, ecode = 0; 871 short i; 872 unsigned char cache_size; 873 874 ap = netdev_priv(dev); 875 regs = ap->regs; 876 877 board_idx = ap->board_idx; 878 879 /* 880 * aman@sgi.com - its useful to do a NIC reset here to 881 * address the `Firmware not running' problem subsequent 882 * to any crashes involving the NIC 883 */ 884 writel(HW_RESET | (HW_RESET << 24), ®s->HostCtrl); 885 readl(®s->HostCtrl); /* PCI write posting */ 886 udelay(5); 887 888 /* 889 * Don't access any other registers before this point! 890 */ 891 #ifdef __BIG_ENDIAN 892 /* 893 * This will most likely need BYTE_SWAP once we switch 894 * to using __raw_writel() 895 */ 896 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)), 897 ®s->HostCtrl); 898 #else 899 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)), 900 ®s->HostCtrl); 901 #endif 902 readl(®s->HostCtrl); /* PCI write posting */ 903 904 /* 905 * Stop the NIC CPU and clear pending interrupts 906 */ 907 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); 908 readl(®s->CpuCtrl); /* PCI write posting */ 909 writel(0, ®s->Mb0Lo); 910 911 tig_ver = readl(®s->HostCtrl) >> 28; 912 913 switch(tig_ver){ 914 #ifndef CONFIG_ACENIC_OMIT_TIGON_I 915 case 4: 916 case 5: 917 printk(KERN_INFO " Tigon I (Rev. %i), Firmware: %i.%i.%i, ", 918 tig_ver, ap->firmware_major, ap->firmware_minor, 919 ap->firmware_fix); 920 writel(0, ®s->LocalCtrl); 921 ap->version = 1; 922 ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES; 923 break; 924 #endif 925 case 6: 926 printk(KERN_INFO " Tigon II (Rev. %i), Firmware: %i.%i.%i, ", 927 tig_ver, ap->firmware_major, ap->firmware_minor, 928 ap->firmware_fix); 929 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl); 930 readl(®s->CpuBCtrl); /* PCI write posting */ 931 /* 932 * The SRAM bank size does _not_ indicate the amount 933 * of memory on the card, it controls the _bank_ size! 934 * Ie. a 1MB AceNIC will have two banks of 512KB. 935 */ 936 writel(SRAM_BANK_512K, ®s->LocalCtrl); 937 writel(SYNC_SRAM_TIMING, ®s->MiscCfg); 938 ap->version = 2; 939 ap->tx_ring_entries = MAX_TX_RING_ENTRIES; 940 break; 941 default: 942 printk(KERN_WARNING " Unsupported Tigon version detected " 943 "(%i)\n", tig_ver); 944 ecode = -ENODEV; 945 goto init_error; 946 } 947 948 /* 949 * ModeStat _must_ be set after the SRAM settings as this change 950 * seems to corrupt the ModeStat and possible other registers. 951 * The SRAM settings survive resets and setting it to the same 952 * value a second time works as well. This is what caused the 953 * `Firmware not running' problem on the Tigon II. 954 */ 955 #ifdef __BIG_ENDIAN 956 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD | 957 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat); 958 #else 959 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | 960 ACE_WORD_SWAP_BD | ACE_NO_JUMBO_FRAG, ®s->ModeStat); 961 #endif 962 readl(®s->ModeStat); /* PCI write posting */ 963 964 mac1 = 0; 965 for(i = 0; i < 4; i++) { 966 int t; 967 968 mac1 = mac1 << 8; 969 t = read_eeprom_byte(dev, 0x8c+i); 970 if (t < 0) { 971 ecode = -EIO; 972 goto init_error; 973 } else 974 mac1 |= (t & 0xff); 975 } 976 mac2 = 0; 977 for(i = 4; i < 8; i++) { 978 int t; 979 980 mac2 = mac2 << 8; 981 t = read_eeprom_byte(dev, 0x8c+i); 982 if (t < 0) { 983 ecode = -EIO; 984 goto init_error; 985 } else 986 mac2 |= (t & 0xff); 987 } 988 989 writel(mac1, ®s->MacAddrHi); 990 writel(mac2, ®s->MacAddrLo); 991 992 dev->dev_addr[0] = (mac1 >> 8) & 0xff; 993 dev->dev_addr[1] = mac1 & 0xff; 994 dev->dev_addr[2] = (mac2 >> 24) & 0xff; 995 dev->dev_addr[3] = (mac2 >> 16) & 0xff; 996 dev->dev_addr[4] = (mac2 >> 8) & 0xff; 997 dev->dev_addr[5] = mac2 & 0xff; 998 999 printk("MAC: %pM\n", dev->dev_addr); 1000 1001 /* 1002 * Looks like this is necessary to deal with on all architectures, 1003 * even this %$#%$# N440BX Intel based thing doesn't get it right. 1004 * Ie. having two NICs in the machine, one will have the cache 1005 * line set at boot time, the other will not. 1006 */ 1007 pdev = ap->pdev; 1008 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size); 1009 cache_size <<= 2; 1010 if (cache_size != SMP_CACHE_BYTES) { 1011 printk(KERN_INFO " PCI cache line size set incorrectly " 1012 "(%i bytes) by BIOS/FW, ", cache_size); 1013 if (cache_size > SMP_CACHE_BYTES) 1014 printk("expecting %i\n", SMP_CACHE_BYTES); 1015 else { 1016 printk("correcting to %i\n", SMP_CACHE_BYTES); 1017 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 1018 SMP_CACHE_BYTES >> 2); 1019 } 1020 } 1021 1022 pci_state = readl(®s->PciState); 1023 printk(KERN_INFO " PCI bus width: %i bits, speed: %iMHz, " 1024 "latency: %i clks\n", 1025 (pci_state & PCI_32BIT) ? 32 : 64, 1026 (pci_state & PCI_66MHZ) ? 66 : 33, 1027 ap->pci_latency); 1028 1029 /* 1030 * Set the max DMA transfer size. Seems that for most systems 1031 * the performance is better when no MAX parameter is 1032 * set. However for systems enabling PCI write and invalidate, 1033 * DMA writes must be set to the L1 cache line size to get 1034 * optimal performance. 1035 * 1036 * The default is now to turn the PCI write and invalidate off 1037 * - that is what Alteon does for NT. 1038 */ 1039 tmp = READ_CMD_MEM | WRITE_CMD_MEM; 1040 if (ap->version >= 2) { 1041 tmp |= (MEM_READ_MULTIPLE | (pci_state & PCI_66MHZ)); 1042 /* 1043 * Tuning parameters only supported for 8 cards 1044 */ 1045 if (board_idx == BOARD_IDX_OVERFLOW || 1046 dis_pci_mem_inval[board_idx]) { 1047 if (ap->pci_command & PCI_COMMAND_INVALIDATE) { 1048 ap->pci_command &= ~PCI_COMMAND_INVALIDATE; 1049 pci_write_config_word(pdev, PCI_COMMAND, 1050 ap->pci_command); 1051 printk(KERN_INFO " Disabling PCI memory " 1052 "write and invalidate\n"); 1053 } 1054 } else if (ap->pci_command & PCI_COMMAND_INVALIDATE) { 1055 printk(KERN_INFO " PCI memory write & invalidate " 1056 "enabled by BIOS, enabling counter measures\n"); 1057 1058 switch(SMP_CACHE_BYTES) { 1059 case 16: 1060 tmp |= DMA_WRITE_MAX_16; 1061 break; 1062 case 32: 1063 tmp |= DMA_WRITE_MAX_32; 1064 break; 1065 case 64: 1066 tmp |= DMA_WRITE_MAX_64; 1067 break; 1068 case 128: 1069 tmp |= DMA_WRITE_MAX_128; 1070 break; 1071 default: 1072 printk(KERN_INFO " Cache line size %i not " 1073 "supported, PCI write and invalidate " 1074 "disabled\n", SMP_CACHE_BYTES); 1075 ap->pci_command &= ~PCI_COMMAND_INVALIDATE; 1076 pci_write_config_word(pdev, PCI_COMMAND, 1077 ap->pci_command); 1078 } 1079 } 1080 } 1081 1082 #ifdef __sparc__ 1083 /* 1084 * On this platform, we know what the best dma settings 1085 * are. We use 64-byte maximum bursts, because if we 1086 * burst larger than the cache line size (or even cross 1087 * a 64byte boundary in a single burst) the UltraSparc 1088 * PCI controller will disconnect at 64-byte multiples. 1089 * 1090 * Read-multiple will be properly enabled above, and when 1091 * set will give the PCI controller proper hints about 1092 * prefetching. 1093 */ 1094 tmp &= ~DMA_READ_WRITE_MASK; 1095 tmp |= DMA_READ_MAX_64; 1096 tmp |= DMA_WRITE_MAX_64; 1097 #endif 1098 #ifdef __alpha__ 1099 tmp &= ~DMA_READ_WRITE_MASK; 1100 tmp |= DMA_READ_MAX_128; 1101 /* 1102 * All the docs say MUST NOT. Well, I did. 1103 * Nothing terrible happens, if we load wrong size. 1104 * Bit w&i still works better! 1105 */ 1106 tmp |= DMA_WRITE_MAX_128; 1107 #endif 1108 writel(tmp, ®s->PciState); 1109 1110 #if 0 1111 /* 1112 * The Host PCI bus controller driver has to set FBB. 1113 * If all devices on that PCI bus support FBB, then the controller 1114 * can enable FBB support in the Host PCI Bus controller (or on 1115 * the PCI-PCI bridge if that applies). 1116 * -ggg 1117 */ 1118 /* 1119 * I have received reports from people having problems when this 1120 * bit is enabled. 1121 */ 1122 if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) { 1123 printk(KERN_INFO " Enabling PCI Fast Back to Back\n"); 1124 ap->pci_command |= PCI_COMMAND_FAST_BACK; 1125 pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command); 1126 } 1127 #endif 1128 1129 /* 1130 * Configure DMA attributes. 1131 */ 1132 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 1133 ap->pci_using_dac = 1; 1134 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 1135 ap->pci_using_dac = 0; 1136 } else { 1137 ecode = -ENODEV; 1138 goto init_error; 1139 } 1140 1141 /* 1142 * Initialize the generic info block and the command+event rings 1143 * and the control blocks for the transmit and receive rings 1144 * as they need to be setup once and for all. 1145 */ 1146 if (!(info = pci_alloc_consistent(ap->pdev, sizeof(struct ace_info), 1147 &ap->info_dma))) { 1148 ecode = -EAGAIN; 1149 goto init_error; 1150 } 1151 ap->info = info; 1152 1153 /* 1154 * Get the memory for the skb rings. 1155 */ 1156 if (!(ap->skb = kmalloc(sizeof(struct ace_skb), GFP_KERNEL))) { 1157 ecode = -EAGAIN; 1158 goto init_error; 1159 } 1160 1161 ecode = request_irq(pdev->irq, ace_interrupt, IRQF_SHARED, 1162 DRV_NAME, dev); 1163 if (ecode) { 1164 printk(KERN_WARNING "%s: Requested IRQ %d is busy\n", 1165 DRV_NAME, pdev->irq); 1166 goto init_error; 1167 } else 1168 dev->irq = pdev->irq; 1169 1170 #ifdef INDEX_DEBUG 1171 spin_lock_init(&ap->debug_lock); 1172 ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1; 1173 ap->last_std_rx = 0; 1174 ap->last_mini_rx = 0; 1175 #endif 1176 1177 memset(ap->info, 0, sizeof(struct ace_info)); 1178 memset(ap->skb, 0, sizeof(struct ace_skb)); 1179 1180 ecode = ace_load_firmware(dev); 1181 if (ecode) 1182 goto init_error; 1183 1184 ap->fw_running = 0; 1185 1186 tmp_ptr = ap->info_dma; 1187 writel(tmp_ptr >> 32, ®s->InfoPtrHi); 1188 writel(tmp_ptr & 0xffffffff, ®s->InfoPtrLo); 1189 1190 memset(ap->evt_ring, 0, EVT_RING_ENTRIES * sizeof(struct event)); 1191 1192 set_aceaddr(&info->evt_ctrl.rngptr, ap->evt_ring_dma); 1193 info->evt_ctrl.flags = 0; 1194 1195 *(ap->evt_prd) = 0; 1196 wmb(); 1197 set_aceaddr(&info->evt_prd_ptr, ap->evt_prd_dma); 1198 writel(0, ®s->EvtCsm); 1199 1200 set_aceaddr(&info->cmd_ctrl.rngptr, 0x100); 1201 info->cmd_ctrl.flags = 0; 1202 info->cmd_ctrl.max_len = 0; 1203 1204 for (i = 0; i < CMD_RING_ENTRIES; i++) 1205 writel(0, ®s->CmdRng[i]); 1206 1207 writel(0, ®s->CmdPrd); 1208 writel(0, ®s->CmdCsm); 1209 1210 tmp_ptr = ap->info_dma; 1211 tmp_ptr += (unsigned long) &(((struct ace_info *)0)->s.stats); 1212 set_aceaddr(&info->stats2_ptr, (dma_addr_t) tmp_ptr); 1213 1214 set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma); 1215 info->rx_std_ctrl.max_len = ACE_STD_BUFSIZE; 1216 info->rx_std_ctrl.flags = 1217 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST; 1218 1219 memset(ap->rx_std_ring, 0, 1220 RX_STD_RING_ENTRIES * sizeof(struct rx_desc)); 1221 1222 for (i = 0; i < RX_STD_RING_ENTRIES; i++) 1223 ap->rx_std_ring[i].flags = BD_FLG_TCP_UDP_SUM; 1224 1225 ap->rx_std_skbprd = 0; 1226 atomic_set(&ap->cur_rx_bufs, 0); 1227 1228 set_aceaddr(&info->rx_jumbo_ctrl.rngptr, 1229 (ap->rx_ring_base_dma + 1230 (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES))); 1231 info->rx_jumbo_ctrl.max_len = 0; 1232 info->rx_jumbo_ctrl.flags = 1233 RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST; 1234 1235 memset(ap->rx_jumbo_ring, 0, 1236 RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc)); 1237 1238 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) 1239 ap->rx_jumbo_ring[i].flags = BD_FLG_TCP_UDP_SUM | BD_FLG_JUMBO; 1240 1241 ap->rx_jumbo_skbprd = 0; 1242 atomic_set(&ap->cur_jumbo_bufs, 0); 1243 1244 memset(ap->rx_mini_ring, 0, 1245 RX_MINI_RING_ENTRIES * sizeof(struct rx_desc)); 1246 1247 if (ap->version >= 2) { 1248 set_aceaddr(&info->rx_mini_ctrl.rngptr, 1249 (ap->rx_ring_base_dma + 1250 (sizeof(struct rx_desc) * 1251 (RX_STD_RING_ENTRIES + 1252 RX_JUMBO_RING_ENTRIES)))); 1253 info->rx_mini_ctrl.max_len = ACE_MINI_SIZE; 1254 info->rx_mini_ctrl.flags = 1255 RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|RCB_FLG_VLAN_ASSIST; 1256 1257 for (i = 0; i < RX_MINI_RING_ENTRIES; i++) 1258 ap->rx_mini_ring[i].flags = 1259 BD_FLG_TCP_UDP_SUM | BD_FLG_MINI; 1260 } else { 1261 set_aceaddr(&info->rx_mini_ctrl.rngptr, 0); 1262 info->rx_mini_ctrl.flags = RCB_FLG_RNG_DISABLE; 1263 info->rx_mini_ctrl.max_len = 0; 1264 } 1265 1266 ap->rx_mini_skbprd = 0; 1267 atomic_set(&ap->cur_mini_bufs, 0); 1268 1269 set_aceaddr(&info->rx_return_ctrl.rngptr, 1270 (ap->rx_ring_base_dma + 1271 (sizeof(struct rx_desc) * 1272 (RX_STD_RING_ENTRIES + 1273 RX_JUMBO_RING_ENTRIES + 1274 RX_MINI_RING_ENTRIES)))); 1275 info->rx_return_ctrl.flags = 0; 1276 info->rx_return_ctrl.max_len = RX_RETURN_RING_ENTRIES; 1277 1278 memset(ap->rx_return_ring, 0, 1279 RX_RETURN_RING_ENTRIES * sizeof(struct rx_desc)); 1280 1281 set_aceaddr(&info->rx_ret_prd_ptr, ap->rx_ret_prd_dma); 1282 *(ap->rx_ret_prd) = 0; 1283 1284 writel(TX_RING_BASE, ®s->WinBase); 1285 1286 if (ACE_IS_TIGON_I(ap)) { 1287 ap->tx_ring = (__force struct tx_desc *) regs->Window; 1288 for (i = 0; i < (TIGON_I_TX_RING_ENTRIES 1289 * sizeof(struct tx_desc)) / sizeof(u32); i++) 1290 writel(0, (__force void __iomem *)ap->tx_ring + i * 4); 1291 1292 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE); 1293 } else { 1294 memset(ap->tx_ring, 0, 1295 MAX_TX_RING_ENTRIES * sizeof(struct tx_desc)); 1296 1297 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma); 1298 } 1299 1300 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap); 1301 tmp = RCB_FLG_TCP_UDP_SUM | RCB_FLG_NO_PSEUDO_HDR | RCB_FLG_VLAN_ASSIST; 1302 1303 /* 1304 * The Tigon I does not like having the TX ring in host memory ;-( 1305 */ 1306 if (!ACE_IS_TIGON_I(ap)) 1307 tmp |= RCB_FLG_TX_HOST_RING; 1308 #if TX_COAL_INTS_ONLY 1309 tmp |= RCB_FLG_COAL_INT_ONLY; 1310 #endif 1311 info->tx_ctrl.flags = tmp; 1312 1313 set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma); 1314 1315 /* 1316 * Potential item for tuning parameter 1317 */ 1318 #if 0 /* NO */ 1319 writel(DMA_THRESH_16W, ®s->DmaReadCfg); 1320 writel(DMA_THRESH_16W, ®s->DmaWriteCfg); 1321 #else 1322 writel(DMA_THRESH_8W, ®s->DmaReadCfg); 1323 writel(DMA_THRESH_8W, ®s->DmaWriteCfg); 1324 #endif 1325 1326 writel(0, ®s->MaskInt); 1327 writel(1, ®s->IfIdx); 1328 #if 0 1329 /* 1330 * McKinley boxes do not like us fiddling with AssistState 1331 * this early 1332 */ 1333 writel(1, ®s->AssistState); 1334 #endif 1335 1336 writel(DEF_STAT, ®s->TuneStatTicks); 1337 writel(DEF_TRACE, ®s->TuneTrace); 1338 1339 ace_set_rxtx_parms(dev, 0); 1340 1341 if (board_idx == BOARD_IDX_OVERFLOW) { 1342 printk(KERN_WARNING "%s: more than %i NICs detected, " 1343 "ignoring module parameters!\n", 1344 ap->name, ACE_MAX_MOD_PARMS); 1345 } else if (board_idx >= 0) { 1346 if (tx_coal_tick[board_idx]) 1347 writel(tx_coal_tick[board_idx], 1348 ®s->TuneTxCoalTicks); 1349 if (max_tx_desc[board_idx]) 1350 writel(max_tx_desc[board_idx], ®s->TuneMaxTxDesc); 1351 1352 if (rx_coal_tick[board_idx]) 1353 writel(rx_coal_tick[board_idx], 1354 ®s->TuneRxCoalTicks); 1355 if (max_rx_desc[board_idx]) 1356 writel(max_rx_desc[board_idx], ®s->TuneMaxRxDesc); 1357 1358 if (trace[board_idx]) 1359 writel(trace[board_idx], ®s->TuneTrace); 1360 1361 if ((tx_ratio[board_idx] > 0) && (tx_ratio[board_idx] < 64)) 1362 writel(tx_ratio[board_idx], ®s->TxBufRat); 1363 } 1364 1365 /* 1366 * Default link parameters 1367 */ 1368 tmp = LNK_ENABLE | LNK_FULL_DUPLEX | LNK_1000MB | LNK_100MB | 1369 LNK_10MB | LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL | LNK_NEGOTIATE; 1370 if(ap->version >= 2) 1371 tmp |= LNK_TX_FLOW_CTL_Y; 1372 1373 /* 1374 * Override link default parameters 1375 */ 1376 if ((board_idx >= 0) && link_state[board_idx]) { 1377 int option = link_state[board_idx]; 1378 1379 tmp = LNK_ENABLE; 1380 1381 if (option & 0x01) { 1382 printk(KERN_INFO "%s: Setting half duplex link\n", 1383 ap->name); 1384 tmp &= ~LNK_FULL_DUPLEX; 1385 } 1386 if (option & 0x02) 1387 tmp &= ~LNK_NEGOTIATE; 1388 if (option & 0x10) 1389 tmp |= LNK_10MB; 1390 if (option & 0x20) 1391 tmp |= LNK_100MB; 1392 if (option & 0x40) 1393 tmp |= LNK_1000MB; 1394 if ((option & 0x70) == 0) { 1395 printk(KERN_WARNING "%s: No media speed specified, " 1396 "forcing auto negotiation\n", ap->name); 1397 tmp |= LNK_NEGOTIATE | LNK_1000MB | 1398 LNK_100MB | LNK_10MB; 1399 } 1400 if ((option & 0x100) == 0) 1401 tmp |= LNK_NEG_FCTL; 1402 else 1403 printk(KERN_INFO "%s: Disabling flow control " 1404 "negotiation\n", ap->name); 1405 if (option & 0x200) 1406 tmp |= LNK_RX_FLOW_CTL_Y; 1407 if ((option & 0x400) && (ap->version >= 2)) { 1408 printk(KERN_INFO "%s: Enabling TX flow control\n", 1409 ap->name); 1410 tmp |= LNK_TX_FLOW_CTL_Y; 1411 } 1412 } 1413 1414 ap->link = tmp; 1415 writel(tmp, ®s->TuneLink); 1416 if (ap->version >= 2) 1417 writel(tmp, ®s->TuneFastLink); 1418 1419 writel(ap->firmware_start, ®s->Pc); 1420 1421 writel(0, ®s->Mb0Lo); 1422 1423 /* 1424 * Set tx_csm before we start receiving interrupts, otherwise 1425 * the interrupt handler might think it is supposed to process 1426 * tx ints before we are up and running, which may cause a null 1427 * pointer access in the int handler. 1428 */ 1429 ap->cur_rx = 0; 1430 ap->tx_prd = *(ap->tx_csm) = ap->tx_ret_csm = 0; 1431 1432 wmb(); 1433 ace_set_txprd(regs, ap, 0); 1434 writel(0, ®s->RxRetCsm); 1435 1436 /* 1437 * Enable DMA engine now. 1438 * If we do this sooner, Mckinley box pukes. 1439 * I assume it's because Tigon II DMA engine wants to check 1440 * *something* even before the CPU is started. 1441 */ 1442 writel(1, ®s->AssistState); /* enable DMA */ 1443 1444 /* 1445 * Start the NIC CPU 1446 */ 1447 writel(readl(®s->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), ®s->CpuCtrl); 1448 readl(®s->CpuCtrl); 1449 1450 /* 1451 * Wait for the firmware to spin up - max 3 seconds. 1452 */ 1453 myjif = jiffies + 3 * HZ; 1454 while (time_before(jiffies, myjif) && !ap->fw_running) 1455 cpu_relax(); 1456 1457 if (!ap->fw_running) { 1458 printk(KERN_ERR "%s: Firmware NOT running!\n", ap->name); 1459 1460 ace_dump_trace(ap); 1461 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); 1462 readl(®s->CpuCtrl); 1463 1464 /* aman@sgi.com - account for badly behaving firmware/NIC: 1465 * - have observed that the NIC may continue to generate 1466 * interrupts for some reason; attempt to stop it - halt 1467 * second CPU for Tigon II cards, and also clear Mb0 1468 * - if we're a module, we'll fail to load if this was 1469 * the only GbE card in the system => if the kernel does 1470 * see an interrupt from the NIC, code to handle it is 1471 * gone and OOps! - so free_irq also 1472 */ 1473 if (ap->version >= 2) 1474 writel(readl(®s->CpuBCtrl) | CPU_HALT, 1475 ®s->CpuBCtrl); 1476 writel(0, ®s->Mb0Lo); 1477 readl(®s->Mb0Lo); 1478 1479 ecode = -EBUSY; 1480 goto init_error; 1481 } 1482 1483 /* 1484 * We load the ring here as there seem to be no way to tell the 1485 * firmware to wipe the ring without re-initializing it. 1486 */ 1487 if (!test_and_set_bit(0, &ap->std_refill_busy)) 1488 ace_load_std_rx_ring(dev, RX_RING_SIZE); 1489 else 1490 printk(KERN_ERR "%s: Someone is busy refilling the RX ring\n", 1491 ap->name); 1492 if (ap->version >= 2) { 1493 if (!test_and_set_bit(0, &ap->mini_refill_busy)) 1494 ace_load_mini_rx_ring(dev, RX_MINI_SIZE); 1495 else 1496 printk(KERN_ERR "%s: Someone is busy refilling " 1497 "the RX mini ring\n", ap->name); 1498 } 1499 return 0; 1500 1501 init_error: 1502 ace_init_cleanup(dev); 1503 return ecode; 1504 } 1505 1506 1507 static void ace_set_rxtx_parms(struct net_device *dev, int jumbo) 1508 { 1509 struct ace_private *ap = netdev_priv(dev); 1510 struct ace_regs __iomem *regs = ap->regs; 1511 int board_idx = ap->board_idx; 1512 1513 if (board_idx >= 0) { 1514 if (!jumbo) { 1515 if (!tx_coal_tick[board_idx]) 1516 writel(DEF_TX_COAL, ®s->TuneTxCoalTicks); 1517 if (!max_tx_desc[board_idx]) 1518 writel(DEF_TX_MAX_DESC, ®s->TuneMaxTxDesc); 1519 if (!rx_coal_tick[board_idx]) 1520 writel(DEF_RX_COAL, ®s->TuneRxCoalTicks); 1521 if (!max_rx_desc[board_idx]) 1522 writel(DEF_RX_MAX_DESC, ®s->TuneMaxRxDesc); 1523 if (!tx_ratio[board_idx]) 1524 writel(DEF_TX_RATIO, ®s->TxBufRat); 1525 } else { 1526 if (!tx_coal_tick[board_idx]) 1527 writel(DEF_JUMBO_TX_COAL, 1528 ®s->TuneTxCoalTicks); 1529 if (!max_tx_desc[board_idx]) 1530 writel(DEF_JUMBO_TX_MAX_DESC, 1531 ®s->TuneMaxTxDesc); 1532 if (!rx_coal_tick[board_idx]) 1533 writel(DEF_JUMBO_RX_COAL, 1534 ®s->TuneRxCoalTicks); 1535 if (!max_rx_desc[board_idx]) 1536 writel(DEF_JUMBO_RX_MAX_DESC, 1537 ®s->TuneMaxRxDesc); 1538 if (!tx_ratio[board_idx]) 1539 writel(DEF_JUMBO_TX_RATIO, ®s->TxBufRat); 1540 } 1541 } 1542 } 1543 1544 1545 static void ace_watchdog(struct net_device *data) 1546 { 1547 struct net_device *dev = data; 1548 struct ace_private *ap = netdev_priv(dev); 1549 struct ace_regs __iomem *regs = ap->regs; 1550 1551 /* 1552 * We haven't received a stats update event for more than 2.5 1553 * seconds and there is data in the transmit queue, thus we 1554 * assume the card is stuck. 1555 */ 1556 if (*ap->tx_csm != ap->tx_ret_csm) { 1557 printk(KERN_WARNING "%s: Transmitter is stuck, %08x\n", 1558 dev->name, (unsigned int)readl(®s->HostCtrl)); 1559 /* This can happen due to ieee flow control. */ 1560 } else { 1561 printk(KERN_DEBUG "%s: BUG... transmitter died. Kicking it.\n", 1562 dev->name); 1563 #if 0 1564 netif_wake_queue(dev); 1565 #endif 1566 } 1567 } 1568 1569 1570 static void ace_tasklet(unsigned long arg) 1571 { 1572 struct net_device *dev = (struct net_device *) arg; 1573 struct ace_private *ap = netdev_priv(dev); 1574 int cur_size; 1575 1576 cur_size = atomic_read(&ap->cur_rx_bufs); 1577 if ((cur_size < RX_LOW_STD_THRES) && 1578 !test_and_set_bit(0, &ap->std_refill_busy)) { 1579 #ifdef DEBUG 1580 printk("refilling buffers (current %i)\n", cur_size); 1581 #endif 1582 ace_load_std_rx_ring(dev, RX_RING_SIZE - cur_size); 1583 } 1584 1585 if (ap->version >= 2) { 1586 cur_size = atomic_read(&ap->cur_mini_bufs); 1587 if ((cur_size < RX_LOW_MINI_THRES) && 1588 !test_and_set_bit(0, &ap->mini_refill_busy)) { 1589 #ifdef DEBUG 1590 printk("refilling mini buffers (current %i)\n", 1591 cur_size); 1592 #endif 1593 ace_load_mini_rx_ring(dev, RX_MINI_SIZE - cur_size); 1594 } 1595 } 1596 1597 cur_size = atomic_read(&ap->cur_jumbo_bufs); 1598 if (ap->jumbo && (cur_size < RX_LOW_JUMBO_THRES) && 1599 !test_and_set_bit(0, &ap->jumbo_refill_busy)) { 1600 #ifdef DEBUG 1601 printk("refilling jumbo buffers (current %i)\n", cur_size); 1602 #endif 1603 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE - cur_size); 1604 } 1605 ap->tasklet_pending = 0; 1606 } 1607 1608 1609 /* 1610 * Copy the contents of the NIC's trace buffer to kernel memory. 1611 */ 1612 static void ace_dump_trace(struct ace_private *ap) 1613 { 1614 #if 0 1615 if (!ap->trace_buf) 1616 if (!(ap->trace_buf = kmalloc(ACE_TRACE_SIZE, GFP_KERNEL))) 1617 return; 1618 #endif 1619 } 1620 1621 1622 /* 1623 * Load the standard rx ring. 1624 * 1625 * Loading rings is safe without holding the spin lock since this is 1626 * done only before the device is enabled, thus no interrupts are 1627 * generated and by the interrupt handler/tasklet handler. 1628 */ 1629 static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs) 1630 { 1631 struct ace_private *ap = netdev_priv(dev); 1632 struct ace_regs __iomem *regs = ap->regs; 1633 short i, idx; 1634 1635 1636 prefetchw(&ap->cur_rx_bufs); 1637 1638 idx = ap->rx_std_skbprd; 1639 1640 for (i = 0; i < nr_bufs; i++) { 1641 struct sk_buff *skb; 1642 struct rx_desc *rd; 1643 dma_addr_t mapping; 1644 1645 skb = netdev_alloc_skb_ip_align(dev, ACE_STD_BUFSIZE); 1646 if (!skb) 1647 break; 1648 1649 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data), 1650 offset_in_page(skb->data), 1651 ACE_STD_BUFSIZE, 1652 PCI_DMA_FROMDEVICE); 1653 ap->skb->rx_std_skbuff[idx].skb = skb; 1654 dma_unmap_addr_set(&ap->skb->rx_std_skbuff[idx], 1655 mapping, mapping); 1656 1657 rd = &ap->rx_std_ring[idx]; 1658 set_aceaddr(&rd->addr, mapping); 1659 rd->size = ACE_STD_BUFSIZE; 1660 rd->idx = idx; 1661 idx = (idx + 1) % RX_STD_RING_ENTRIES; 1662 } 1663 1664 if (!i) 1665 goto error_out; 1666 1667 atomic_add(i, &ap->cur_rx_bufs); 1668 ap->rx_std_skbprd = idx; 1669 1670 if (ACE_IS_TIGON_I(ap)) { 1671 struct cmd cmd; 1672 cmd.evt = C_SET_RX_PRD_IDX; 1673 cmd.code = 0; 1674 cmd.idx = ap->rx_std_skbprd; 1675 ace_issue_cmd(regs, &cmd); 1676 } else { 1677 writel(idx, ®s->RxStdPrd); 1678 wmb(); 1679 } 1680 1681 out: 1682 clear_bit(0, &ap->std_refill_busy); 1683 return; 1684 1685 error_out: 1686 printk(KERN_INFO "Out of memory when allocating " 1687 "standard receive buffers\n"); 1688 goto out; 1689 } 1690 1691 1692 static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs) 1693 { 1694 struct ace_private *ap = netdev_priv(dev); 1695 struct ace_regs __iomem *regs = ap->regs; 1696 short i, idx; 1697 1698 prefetchw(&ap->cur_mini_bufs); 1699 1700 idx = ap->rx_mini_skbprd; 1701 for (i = 0; i < nr_bufs; i++) { 1702 struct sk_buff *skb; 1703 struct rx_desc *rd; 1704 dma_addr_t mapping; 1705 1706 skb = netdev_alloc_skb_ip_align(dev, ACE_MINI_BUFSIZE); 1707 if (!skb) 1708 break; 1709 1710 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data), 1711 offset_in_page(skb->data), 1712 ACE_MINI_BUFSIZE, 1713 PCI_DMA_FROMDEVICE); 1714 ap->skb->rx_mini_skbuff[idx].skb = skb; 1715 dma_unmap_addr_set(&ap->skb->rx_mini_skbuff[idx], 1716 mapping, mapping); 1717 1718 rd = &ap->rx_mini_ring[idx]; 1719 set_aceaddr(&rd->addr, mapping); 1720 rd->size = ACE_MINI_BUFSIZE; 1721 rd->idx = idx; 1722 idx = (idx + 1) % RX_MINI_RING_ENTRIES; 1723 } 1724 1725 if (!i) 1726 goto error_out; 1727 1728 atomic_add(i, &ap->cur_mini_bufs); 1729 1730 ap->rx_mini_skbprd = idx; 1731 1732 writel(idx, ®s->RxMiniPrd); 1733 wmb(); 1734 1735 out: 1736 clear_bit(0, &ap->mini_refill_busy); 1737 return; 1738 error_out: 1739 printk(KERN_INFO "Out of memory when allocating " 1740 "mini receive buffers\n"); 1741 goto out; 1742 } 1743 1744 1745 /* 1746 * Load the jumbo rx ring, this may happen at any time if the MTU 1747 * is changed to a value > 1500. 1748 */ 1749 static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs) 1750 { 1751 struct ace_private *ap = netdev_priv(dev); 1752 struct ace_regs __iomem *regs = ap->regs; 1753 short i, idx; 1754 1755 idx = ap->rx_jumbo_skbprd; 1756 1757 for (i = 0; i < nr_bufs; i++) { 1758 struct sk_buff *skb; 1759 struct rx_desc *rd; 1760 dma_addr_t mapping; 1761 1762 skb = netdev_alloc_skb_ip_align(dev, ACE_JUMBO_BUFSIZE); 1763 if (!skb) 1764 break; 1765 1766 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data), 1767 offset_in_page(skb->data), 1768 ACE_JUMBO_BUFSIZE, 1769 PCI_DMA_FROMDEVICE); 1770 ap->skb->rx_jumbo_skbuff[idx].skb = skb; 1771 dma_unmap_addr_set(&ap->skb->rx_jumbo_skbuff[idx], 1772 mapping, mapping); 1773 1774 rd = &ap->rx_jumbo_ring[idx]; 1775 set_aceaddr(&rd->addr, mapping); 1776 rd->size = ACE_JUMBO_BUFSIZE; 1777 rd->idx = idx; 1778 idx = (idx + 1) % RX_JUMBO_RING_ENTRIES; 1779 } 1780 1781 if (!i) 1782 goto error_out; 1783 1784 atomic_add(i, &ap->cur_jumbo_bufs); 1785 ap->rx_jumbo_skbprd = idx; 1786 1787 if (ACE_IS_TIGON_I(ap)) { 1788 struct cmd cmd; 1789 cmd.evt = C_SET_RX_JUMBO_PRD_IDX; 1790 cmd.code = 0; 1791 cmd.idx = ap->rx_jumbo_skbprd; 1792 ace_issue_cmd(regs, &cmd); 1793 } else { 1794 writel(idx, ®s->RxJumboPrd); 1795 wmb(); 1796 } 1797 1798 out: 1799 clear_bit(0, &ap->jumbo_refill_busy); 1800 return; 1801 error_out: 1802 if (net_ratelimit()) 1803 printk(KERN_INFO "Out of memory when allocating " 1804 "jumbo receive buffers\n"); 1805 goto out; 1806 } 1807 1808 1809 /* 1810 * All events are considered to be slow (RX/TX ints do not generate 1811 * events) and are handled here, outside the main interrupt handler, 1812 * to reduce the size of the handler. 1813 */ 1814 static u32 ace_handle_event(struct net_device *dev, u32 evtcsm, u32 evtprd) 1815 { 1816 struct ace_private *ap; 1817 1818 ap = netdev_priv(dev); 1819 1820 while (evtcsm != evtprd) { 1821 switch (ap->evt_ring[evtcsm].evt) { 1822 case E_FW_RUNNING: 1823 printk(KERN_INFO "%s: Firmware up and running\n", 1824 ap->name); 1825 ap->fw_running = 1; 1826 wmb(); 1827 break; 1828 case E_STATS_UPDATED: 1829 break; 1830 case E_LNK_STATE: 1831 { 1832 u16 code = ap->evt_ring[evtcsm].code; 1833 switch (code) { 1834 case E_C_LINK_UP: 1835 { 1836 u32 state = readl(&ap->regs->GigLnkState); 1837 printk(KERN_WARNING "%s: Optical link UP " 1838 "(%s Duplex, Flow Control: %s%s)\n", 1839 ap->name, 1840 state & LNK_FULL_DUPLEX ? "Full":"Half", 1841 state & LNK_TX_FLOW_CTL_Y ? "TX " : "", 1842 state & LNK_RX_FLOW_CTL_Y ? "RX" : ""); 1843 break; 1844 } 1845 case E_C_LINK_DOWN: 1846 printk(KERN_WARNING "%s: Optical link DOWN\n", 1847 ap->name); 1848 break; 1849 case E_C_LINK_10_100: 1850 printk(KERN_WARNING "%s: 10/100BaseT link " 1851 "UP\n", ap->name); 1852 break; 1853 default: 1854 printk(KERN_ERR "%s: Unknown optical link " 1855 "state %02x\n", ap->name, code); 1856 } 1857 break; 1858 } 1859 case E_ERROR: 1860 switch(ap->evt_ring[evtcsm].code) { 1861 case E_C_ERR_INVAL_CMD: 1862 printk(KERN_ERR "%s: invalid command error\n", 1863 ap->name); 1864 break; 1865 case E_C_ERR_UNIMP_CMD: 1866 printk(KERN_ERR "%s: unimplemented command " 1867 "error\n", ap->name); 1868 break; 1869 case E_C_ERR_BAD_CFG: 1870 printk(KERN_ERR "%s: bad config error\n", 1871 ap->name); 1872 break; 1873 default: 1874 printk(KERN_ERR "%s: unknown error %02x\n", 1875 ap->name, ap->evt_ring[evtcsm].code); 1876 } 1877 break; 1878 case E_RESET_JUMBO_RNG: 1879 { 1880 int i; 1881 for (i = 0; i < RX_JUMBO_RING_ENTRIES; i++) { 1882 if (ap->skb->rx_jumbo_skbuff[i].skb) { 1883 ap->rx_jumbo_ring[i].size = 0; 1884 set_aceaddr(&ap->rx_jumbo_ring[i].addr, 0); 1885 dev_kfree_skb(ap->skb->rx_jumbo_skbuff[i].skb); 1886 ap->skb->rx_jumbo_skbuff[i].skb = NULL; 1887 } 1888 } 1889 1890 if (ACE_IS_TIGON_I(ap)) { 1891 struct cmd cmd; 1892 cmd.evt = C_SET_RX_JUMBO_PRD_IDX; 1893 cmd.code = 0; 1894 cmd.idx = 0; 1895 ace_issue_cmd(ap->regs, &cmd); 1896 } else { 1897 writel(0, &((ap->regs)->RxJumboPrd)); 1898 wmb(); 1899 } 1900 1901 ap->jumbo = 0; 1902 ap->rx_jumbo_skbprd = 0; 1903 printk(KERN_INFO "%s: Jumbo ring flushed\n", 1904 ap->name); 1905 clear_bit(0, &ap->jumbo_refill_busy); 1906 break; 1907 } 1908 default: 1909 printk(KERN_ERR "%s: Unhandled event 0x%02x\n", 1910 ap->name, ap->evt_ring[evtcsm].evt); 1911 } 1912 evtcsm = (evtcsm + 1) % EVT_RING_ENTRIES; 1913 } 1914 1915 return evtcsm; 1916 } 1917 1918 1919 static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm) 1920 { 1921 struct ace_private *ap = netdev_priv(dev); 1922 u32 idx; 1923 int mini_count = 0, std_count = 0; 1924 1925 idx = rxretcsm; 1926 1927 prefetchw(&ap->cur_rx_bufs); 1928 prefetchw(&ap->cur_mini_bufs); 1929 1930 while (idx != rxretprd) { 1931 struct ring_info *rip; 1932 struct sk_buff *skb; 1933 struct rx_desc *rxdesc, *retdesc; 1934 u32 skbidx; 1935 int bd_flags, desc_type, mapsize; 1936 u16 csum; 1937 1938 1939 /* make sure the rx descriptor isn't read before rxretprd */ 1940 if (idx == rxretcsm) 1941 rmb(); 1942 1943 retdesc = &ap->rx_return_ring[idx]; 1944 skbidx = retdesc->idx; 1945 bd_flags = retdesc->flags; 1946 desc_type = bd_flags & (BD_FLG_JUMBO | BD_FLG_MINI); 1947 1948 switch(desc_type) { 1949 /* 1950 * Normal frames do not have any flags set 1951 * 1952 * Mini and normal frames arrive frequently, 1953 * so use a local counter to avoid doing 1954 * atomic operations for each packet arriving. 1955 */ 1956 case 0: 1957 rip = &ap->skb->rx_std_skbuff[skbidx]; 1958 mapsize = ACE_STD_BUFSIZE; 1959 rxdesc = &ap->rx_std_ring[skbidx]; 1960 std_count++; 1961 break; 1962 case BD_FLG_JUMBO: 1963 rip = &ap->skb->rx_jumbo_skbuff[skbidx]; 1964 mapsize = ACE_JUMBO_BUFSIZE; 1965 rxdesc = &ap->rx_jumbo_ring[skbidx]; 1966 atomic_dec(&ap->cur_jumbo_bufs); 1967 break; 1968 case BD_FLG_MINI: 1969 rip = &ap->skb->rx_mini_skbuff[skbidx]; 1970 mapsize = ACE_MINI_BUFSIZE; 1971 rxdesc = &ap->rx_mini_ring[skbidx]; 1972 mini_count++; 1973 break; 1974 default: 1975 printk(KERN_INFO "%s: unknown frame type (0x%02x) " 1976 "returned by NIC\n", dev->name, 1977 retdesc->flags); 1978 goto error; 1979 } 1980 1981 skb = rip->skb; 1982 rip->skb = NULL; 1983 pci_unmap_page(ap->pdev, 1984 dma_unmap_addr(rip, mapping), 1985 mapsize, 1986 PCI_DMA_FROMDEVICE); 1987 skb_put(skb, retdesc->size); 1988 1989 /* 1990 * Fly baby, fly! 1991 */ 1992 csum = retdesc->tcp_udp_csum; 1993 1994 skb->protocol = eth_type_trans(skb, dev); 1995 1996 /* 1997 * Instead of forcing the poor tigon mips cpu to calculate 1998 * pseudo hdr checksum, we do this ourselves. 1999 */ 2000 if (bd_flags & BD_FLG_TCP_UDP_SUM) { 2001 skb->csum = htons(csum); 2002 skb->ip_summed = CHECKSUM_COMPLETE; 2003 } else { 2004 skb_checksum_none_assert(skb); 2005 } 2006 2007 /* send it up */ 2008 if ((bd_flags & BD_FLG_VLAN_TAG)) 2009 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), retdesc->vlan); 2010 netif_rx(skb); 2011 2012 dev->stats.rx_packets++; 2013 dev->stats.rx_bytes += retdesc->size; 2014 2015 idx = (idx + 1) % RX_RETURN_RING_ENTRIES; 2016 } 2017 2018 atomic_sub(std_count, &ap->cur_rx_bufs); 2019 if (!ACE_IS_TIGON_I(ap)) 2020 atomic_sub(mini_count, &ap->cur_mini_bufs); 2021 2022 out: 2023 /* 2024 * According to the documentation RxRetCsm is obsolete with 2025 * the 12.3.x Firmware - my Tigon I NICs seem to disagree! 2026 */ 2027 if (ACE_IS_TIGON_I(ap)) { 2028 writel(idx, &ap->regs->RxRetCsm); 2029 } 2030 ap->cur_rx = idx; 2031 2032 return; 2033 error: 2034 idx = rxretprd; 2035 goto out; 2036 } 2037 2038 2039 static inline void ace_tx_int(struct net_device *dev, 2040 u32 txcsm, u32 idx) 2041 { 2042 struct ace_private *ap = netdev_priv(dev); 2043 2044 do { 2045 struct sk_buff *skb; 2046 struct tx_ring_info *info; 2047 2048 info = ap->skb->tx_skbuff + idx; 2049 skb = info->skb; 2050 2051 if (dma_unmap_len(info, maplen)) { 2052 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping), 2053 dma_unmap_len(info, maplen), 2054 PCI_DMA_TODEVICE); 2055 dma_unmap_len_set(info, maplen, 0); 2056 } 2057 2058 if (skb) { 2059 dev->stats.tx_packets++; 2060 dev->stats.tx_bytes += skb->len; 2061 dev_kfree_skb_irq(skb); 2062 info->skb = NULL; 2063 } 2064 2065 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap); 2066 } while (idx != txcsm); 2067 2068 if (netif_queue_stopped(dev)) 2069 netif_wake_queue(dev); 2070 2071 wmb(); 2072 ap->tx_ret_csm = txcsm; 2073 2074 /* So... tx_ret_csm is advanced _after_ check for device wakeup. 2075 * 2076 * We could try to make it before. In this case we would get 2077 * the following race condition: hard_start_xmit on other cpu 2078 * enters after we advanced tx_ret_csm and fills space, 2079 * which we have just freed, so that we make illegal device wakeup. 2080 * There is no good way to workaround this (at entry 2081 * to ace_start_xmit detects this condition and prevents 2082 * ring corruption, but it is not a good workaround.) 2083 * 2084 * When tx_ret_csm is advanced after, we wake up device _only_ 2085 * if we really have some space in ring (though the core doing 2086 * hard_start_xmit can see full ring for some period and has to 2087 * synchronize.) Superb. 2088 * BUT! We get another subtle race condition. hard_start_xmit 2089 * may think that ring is full between wakeup and advancing 2090 * tx_ret_csm and will stop device instantly! It is not so bad. 2091 * We are guaranteed that there is something in ring, so that 2092 * the next irq will resume transmission. To speedup this we could 2093 * mark descriptor, which closes ring with BD_FLG_COAL_NOW 2094 * (see ace_start_xmit). 2095 * 2096 * Well, this dilemma exists in all lock-free devices. 2097 * We, following scheme used in drivers by Donald Becker, 2098 * select the least dangerous. 2099 * --ANK 2100 */ 2101 } 2102 2103 2104 static irqreturn_t ace_interrupt(int irq, void *dev_id) 2105 { 2106 struct net_device *dev = (struct net_device *)dev_id; 2107 struct ace_private *ap = netdev_priv(dev); 2108 struct ace_regs __iomem *regs = ap->regs; 2109 u32 idx; 2110 u32 txcsm, rxretcsm, rxretprd; 2111 u32 evtcsm, evtprd; 2112 2113 /* 2114 * In case of PCI shared interrupts or spurious interrupts, 2115 * we want to make sure it is actually our interrupt before 2116 * spending any time in here. 2117 */ 2118 if (!(readl(®s->HostCtrl) & IN_INT)) 2119 return IRQ_NONE; 2120 2121 /* 2122 * ACK intr now. Otherwise we will lose updates to rx_ret_prd, 2123 * which happened _after_ rxretprd = *ap->rx_ret_prd; but before 2124 * writel(0, ®s->Mb0Lo). 2125 * 2126 * "IRQ avoidance" recommended in docs applies to IRQs served 2127 * threads and it is wrong even for that case. 2128 */ 2129 writel(0, ®s->Mb0Lo); 2130 readl(®s->Mb0Lo); 2131 2132 /* 2133 * There is no conflict between transmit handling in 2134 * start_xmit and receive processing, thus there is no reason 2135 * to take a spin lock for RX handling. Wait until we start 2136 * working on the other stuff - hey we don't need a spin lock 2137 * anymore. 2138 */ 2139 rxretprd = *ap->rx_ret_prd; 2140 rxretcsm = ap->cur_rx; 2141 2142 if (rxretprd != rxretcsm) 2143 ace_rx_int(dev, rxretprd, rxretcsm); 2144 2145 txcsm = *ap->tx_csm; 2146 idx = ap->tx_ret_csm; 2147 2148 if (txcsm != idx) { 2149 /* 2150 * If each skb takes only one descriptor this check degenerates 2151 * to identity, because new space has just been opened. 2152 * But if skbs are fragmented we must check that this index 2153 * update releases enough of space, otherwise we just 2154 * wait for device to make more work. 2155 */ 2156 if (!tx_ring_full(ap, txcsm, ap->tx_prd)) 2157 ace_tx_int(dev, txcsm, idx); 2158 } 2159 2160 evtcsm = readl(®s->EvtCsm); 2161 evtprd = *ap->evt_prd; 2162 2163 if (evtcsm != evtprd) { 2164 evtcsm = ace_handle_event(dev, evtcsm, evtprd); 2165 writel(evtcsm, ®s->EvtCsm); 2166 } 2167 2168 /* 2169 * This has to go last in the interrupt handler and run with 2170 * the spin lock released ... what lock? 2171 */ 2172 if (netif_running(dev)) { 2173 int cur_size; 2174 int run_tasklet = 0; 2175 2176 cur_size = atomic_read(&ap->cur_rx_bufs); 2177 if (cur_size < RX_LOW_STD_THRES) { 2178 if ((cur_size < RX_PANIC_STD_THRES) && 2179 !test_and_set_bit(0, &ap->std_refill_busy)) { 2180 #ifdef DEBUG 2181 printk("low on std buffers %i\n", cur_size); 2182 #endif 2183 ace_load_std_rx_ring(dev, 2184 RX_RING_SIZE - cur_size); 2185 } else 2186 run_tasklet = 1; 2187 } 2188 2189 if (!ACE_IS_TIGON_I(ap)) { 2190 cur_size = atomic_read(&ap->cur_mini_bufs); 2191 if (cur_size < RX_LOW_MINI_THRES) { 2192 if ((cur_size < RX_PANIC_MINI_THRES) && 2193 !test_and_set_bit(0, 2194 &ap->mini_refill_busy)) { 2195 #ifdef DEBUG 2196 printk("low on mini buffers %i\n", 2197 cur_size); 2198 #endif 2199 ace_load_mini_rx_ring(dev, 2200 RX_MINI_SIZE - cur_size); 2201 } else 2202 run_tasklet = 1; 2203 } 2204 } 2205 2206 if (ap->jumbo) { 2207 cur_size = atomic_read(&ap->cur_jumbo_bufs); 2208 if (cur_size < RX_LOW_JUMBO_THRES) { 2209 if ((cur_size < RX_PANIC_JUMBO_THRES) && 2210 !test_and_set_bit(0, 2211 &ap->jumbo_refill_busy)){ 2212 #ifdef DEBUG 2213 printk("low on jumbo buffers %i\n", 2214 cur_size); 2215 #endif 2216 ace_load_jumbo_rx_ring(dev, 2217 RX_JUMBO_SIZE - cur_size); 2218 } else 2219 run_tasklet = 1; 2220 } 2221 } 2222 if (run_tasklet && !ap->tasklet_pending) { 2223 ap->tasklet_pending = 1; 2224 tasklet_schedule(&ap->ace_tasklet); 2225 } 2226 } 2227 2228 return IRQ_HANDLED; 2229 } 2230 2231 static int ace_open(struct net_device *dev) 2232 { 2233 struct ace_private *ap = netdev_priv(dev); 2234 struct ace_regs __iomem *regs = ap->regs; 2235 struct cmd cmd; 2236 2237 if (!(ap->fw_running)) { 2238 printk(KERN_WARNING "%s: Firmware not running!\n", dev->name); 2239 return -EBUSY; 2240 } 2241 2242 writel(dev->mtu + ETH_HLEN + 4, ®s->IfMtu); 2243 2244 cmd.evt = C_CLEAR_STATS; 2245 cmd.code = 0; 2246 cmd.idx = 0; 2247 ace_issue_cmd(regs, &cmd); 2248 2249 cmd.evt = C_HOST_STATE; 2250 cmd.code = C_C_STACK_UP; 2251 cmd.idx = 0; 2252 ace_issue_cmd(regs, &cmd); 2253 2254 if (ap->jumbo && 2255 !test_and_set_bit(0, &ap->jumbo_refill_busy)) 2256 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE); 2257 2258 if (dev->flags & IFF_PROMISC) { 2259 cmd.evt = C_SET_PROMISC_MODE; 2260 cmd.code = C_C_PROMISC_ENABLE; 2261 cmd.idx = 0; 2262 ace_issue_cmd(regs, &cmd); 2263 2264 ap->promisc = 1; 2265 }else 2266 ap->promisc = 0; 2267 ap->mcast_all = 0; 2268 2269 #if 0 2270 cmd.evt = C_LNK_NEGOTIATION; 2271 cmd.code = 0; 2272 cmd.idx = 0; 2273 ace_issue_cmd(regs, &cmd); 2274 #endif 2275 2276 netif_start_queue(dev); 2277 2278 /* 2279 * Setup the bottom half rx ring refill handler 2280 */ 2281 tasklet_init(&ap->ace_tasklet, ace_tasklet, (unsigned long)dev); 2282 return 0; 2283 } 2284 2285 2286 static int ace_close(struct net_device *dev) 2287 { 2288 struct ace_private *ap = netdev_priv(dev); 2289 struct ace_regs __iomem *regs = ap->regs; 2290 struct cmd cmd; 2291 unsigned long flags; 2292 short i; 2293 2294 /* 2295 * Without (or before) releasing irq and stopping hardware, this 2296 * is an absolute non-sense, by the way. It will be reset instantly 2297 * by the first irq. 2298 */ 2299 netif_stop_queue(dev); 2300 2301 2302 if (ap->promisc) { 2303 cmd.evt = C_SET_PROMISC_MODE; 2304 cmd.code = C_C_PROMISC_DISABLE; 2305 cmd.idx = 0; 2306 ace_issue_cmd(regs, &cmd); 2307 ap->promisc = 0; 2308 } 2309 2310 cmd.evt = C_HOST_STATE; 2311 cmd.code = C_C_STACK_DOWN; 2312 cmd.idx = 0; 2313 ace_issue_cmd(regs, &cmd); 2314 2315 tasklet_kill(&ap->ace_tasklet); 2316 2317 /* 2318 * Make sure one CPU is not processing packets while 2319 * buffers are being released by another. 2320 */ 2321 2322 local_irq_save(flags); 2323 ace_mask_irq(dev); 2324 2325 for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) { 2326 struct sk_buff *skb; 2327 struct tx_ring_info *info; 2328 2329 info = ap->skb->tx_skbuff + i; 2330 skb = info->skb; 2331 2332 if (dma_unmap_len(info, maplen)) { 2333 if (ACE_IS_TIGON_I(ap)) { 2334 /* NB: TIGON_1 is special, tx_ring is in io space */ 2335 struct tx_desc __iomem *tx; 2336 tx = (__force struct tx_desc __iomem *) &ap->tx_ring[i]; 2337 writel(0, &tx->addr.addrhi); 2338 writel(0, &tx->addr.addrlo); 2339 writel(0, &tx->flagsize); 2340 } else 2341 memset(ap->tx_ring + i, 0, 2342 sizeof(struct tx_desc)); 2343 pci_unmap_page(ap->pdev, dma_unmap_addr(info, mapping), 2344 dma_unmap_len(info, maplen), 2345 PCI_DMA_TODEVICE); 2346 dma_unmap_len_set(info, maplen, 0); 2347 } 2348 if (skb) { 2349 dev_kfree_skb(skb); 2350 info->skb = NULL; 2351 } 2352 } 2353 2354 if (ap->jumbo) { 2355 cmd.evt = C_RESET_JUMBO_RNG; 2356 cmd.code = 0; 2357 cmd.idx = 0; 2358 ace_issue_cmd(regs, &cmd); 2359 } 2360 2361 ace_unmask_irq(dev); 2362 local_irq_restore(flags); 2363 2364 return 0; 2365 } 2366 2367 2368 static inline dma_addr_t 2369 ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb, 2370 struct sk_buff *tail, u32 idx) 2371 { 2372 dma_addr_t mapping; 2373 struct tx_ring_info *info; 2374 2375 mapping = pci_map_page(ap->pdev, virt_to_page(skb->data), 2376 offset_in_page(skb->data), 2377 skb->len, PCI_DMA_TODEVICE); 2378 2379 info = ap->skb->tx_skbuff + idx; 2380 info->skb = tail; 2381 dma_unmap_addr_set(info, mapping, mapping); 2382 dma_unmap_len_set(info, maplen, skb->len); 2383 return mapping; 2384 } 2385 2386 2387 static inline void 2388 ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr, 2389 u32 flagsize, u32 vlan_tag) 2390 { 2391 #if !USE_TX_COAL_NOW 2392 flagsize &= ~BD_FLG_COAL_NOW; 2393 #endif 2394 2395 if (ACE_IS_TIGON_I(ap)) { 2396 struct tx_desc __iomem *io = (__force struct tx_desc __iomem *) desc; 2397 writel(addr >> 32, &io->addr.addrhi); 2398 writel(addr & 0xffffffff, &io->addr.addrlo); 2399 writel(flagsize, &io->flagsize); 2400 writel(vlan_tag, &io->vlanres); 2401 } else { 2402 desc->addr.addrhi = addr >> 32; 2403 desc->addr.addrlo = addr; 2404 desc->flagsize = flagsize; 2405 desc->vlanres = vlan_tag; 2406 } 2407 } 2408 2409 2410 static netdev_tx_t ace_start_xmit(struct sk_buff *skb, 2411 struct net_device *dev) 2412 { 2413 struct ace_private *ap = netdev_priv(dev); 2414 struct ace_regs __iomem *regs = ap->regs; 2415 struct tx_desc *desc; 2416 u32 idx, flagsize; 2417 unsigned long maxjiff = jiffies + 3*HZ; 2418 2419 restart: 2420 idx = ap->tx_prd; 2421 2422 if (tx_ring_full(ap, ap->tx_ret_csm, idx)) 2423 goto overflow; 2424 2425 if (!skb_shinfo(skb)->nr_frags) { 2426 dma_addr_t mapping; 2427 u32 vlan_tag = 0; 2428 2429 mapping = ace_map_tx_skb(ap, skb, skb, idx); 2430 flagsize = (skb->len << 16) | (BD_FLG_END); 2431 if (skb->ip_summed == CHECKSUM_PARTIAL) 2432 flagsize |= BD_FLG_TCP_UDP_SUM; 2433 if (vlan_tx_tag_present(skb)) { 2434 flagsize |= BD_FLG_VLAN_TAG; 2435 vlan_tag = vlan_tx_tag_get(skb); 2436 } 2437 desc = ap->tx_ring + idx; 2438 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap); 2439 2440 /* Look at ace_tx_int for explanations. */ 2441 if (tx_ring_full(ap, ap->tx_ret_csm, idx)) 2442 flagsize |= BD_FLG_COAL_NOW; 2443 2444 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag); 2445 } else { 2446 dma_addr_t mapping; 2447 u32 vlan_tag = 0; 2448 int i, len = 0; 2449 2450 mapping = ace_map_tx_skb(ap, skb, NULL, idx); 2451 flagsize = (skb_headlen(skb) << 16); 2452 if (skb->ip_summed == CHECKSUM_PARTIAL) 2453 flagsize |= BD_FLG_TCP_UDP_SUM; 2454 if (vlan_tx_tag_present(skb)) { 2455 flagsize |= BD_FLG_VLAN_TAG; 2456 vlan_tag = vlan_tx_tag_get(skb); 2457 } 2458 2459 ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag); 2460 2461 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap); 2462 2463 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2464 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2465 struct tx_ring_info *info; 2466 2467 len += skb_frag_size(frag); 2468 info = ap->skb->tx_skbuff + idx; 2469 desc = ap->tx_ring + idx; 2470 2471 mapping = skb_frag_dma_map(&ap->pdev->dev, frag, 0, 2472 skb_frag_size(frag), 2473 DMA_TO_DEVICE); 2474 2475 flagsize = skb_frag_size(frag) << 16; 2476 if (skb->ip_summed == CHECKSUM_PARTIAL) 2477 flagsize |= BD_FLG_TCP_UDP_SUM; 2478 idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap); 2479 2480 if (i == skb_shinfo(skb)->nr_frags - 1) { 2481 flagsize |= BD_FLG_END; 2482 if (tx_ring_full(ap, ap->tx_ret_csm, idx)) 2483 flagsize |= BD_FLG_COAL_NOW; 2484 2485 /* 2486 * Only the last fragment frees 2487 * the skb! 2488 */ 2489 info->skb = skb; 2490 } else { 2491 info->skb = NULL; 2492 } 2493 dma_unmap_addr_set(info, mapping, mapping); 2494 dma_unmap_len_set(info, maplen, skb_frag_size(frag)); 2495 ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag); 2496 } 2497 } 2498 2499 wmb(); 2500 ap->tx_prd = idx; 2501 ace_set_txprd(regs, ap, idx); 2502 2503 if (flagsize & BD_FLG_COAL_NOW) { 2504 netif_stop_queue(dev); 2505 2506 /* 2507 * A TX-descriptor producer (an IRQ) might have gotten 2508 * between, making the ring free again. Since xmit is 2509 * serialized, this is the only situation we have to 2510 * re-test. 2511 */ 2512 if (!tx_ring_full(ap, ap->tx_ret_csm, idx)) 2513 netif_wake_queue(dev); 2514 } 2515 2516 return NETDEV_TX_OK; 2517 2518 overflow: 2519 /* 2520 * This race condition is unavoidable with lock-free drivers. 2521 * We wake up the queue _before_ tx_prd is advanced, so that we can 2522 * enter hard_start_xmit too early, while tx ring still looks closed. 2523 * This happens ~1-4 times per 100000 packets, so that we can allow 2524 * to loop syncing to other CPU. Probably, we need an additional 2525 * wmb() in ace_tx_intr as well. 2526 * 2527 * Note that this race is relieved by reserving one more entry 2528 * in tx ring than it is necessary (see original non-SG driver). 2529 * However, with SG we need to reserve 2*MAX_SKB_FRAGS+1, which 2530 * is already overkill. 2531 * 2532 * Alternative is to return with 1 not throttling queue. In this 2533 * case loop becomes longer, no more useful effects. 2534 */ 2535 if (time_before(jiffies, maxjiff)) { 2536 barrier(); 2537 cpu_relax(); 2538 goto restart; 2539 } 2540 2541 /* The ring is stuck full. */ 2542 printk(KERN_WARNING "%s: Transmit ring stuck full\n", dev->name); 2543 return NETDEV_TX_BUSY; 2544 } 2545 2546 2547 static int ace_change_mtu(struct net_device *dev, int new_mtu) 2548 { 2549 struct ace_private *ap = netdev_priv(dev); 2550 struct ace_regs __iomem *regs = ap->regs; 2551 2552 if (new_mtu > ACE_JUMBO_MTU) 2553 return -EINVAL; 2554 2555 writel(new_mtu + ETH_HLEN + 4, ®s->IfMtu); 2556 dev->mtu = new_mtu; 2557 2558 if (new_mtu > ACE_STD_MTU) { 2559 if (!(ap->jumbo)) { 2560 printk(KERN_INFO "%s: Enabling Jumbo frame " 2561 "support\n", dev->name); 2562 ap->jumbo = 1; 2563 if (!test_and_set_bit(0, &ap->jumbo_refill_busy)) 2564 ace_load_jumbo_rx_ring(dev, RX_JUMBO_SIZE); 2565 ace_set_rxtx_parms(dev, 1); 2566 } 2567 } else { 2568 while (test_and_set_bit(0, &ap->jumbo_refill_busy)); 2569 ace_sync_irq(dev->irq); 2570 ace_set_rxtx_parms(dev, 0); 2571 if (ap->jumbo) { 2572 struct cmd cmd; 2573 2574 cmd.evt = C_RESET_JUMBO_RNG; 2575 cmd.code = 0; 2576 cmd.idx = 0; 2577 ace_issue_cmd(regs, &cmd); 2578 } 2579 } 2580 2581 return 0; 2582 } 2583 2584 static int ace_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 2585 { 2586 struct ace_private *ap = netdev_priv(dev); 2587 struct ace_regs __iomem *regs = ap->regs; 2588 u32 link; 2589 2590 memset(ecmd, 0, sizeof(struct ethtool_cmd)); 2591 ecmd->supported = 2592 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | 2593 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | 2594 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | 2595 SUPPORTED_Autoneg | SUPPORTED_FIBRE); 2596 2597 ecmd->port = PORT_FIBRE; 2598 ecmd->transceiver = XCVR_INTERNAL; 2599 2600 link = readl(®s->GigLnkState); 2601 if (link & LNK_1000MB) 2602 ethtool_cmd_speed_set(ecmd, SPEED_1000); 2603 else { 2604 link = readl(®s->FastLnkState); 2605 if (link & LNK_100MB) 2606 ethtool_cmd_speed_set(ecmd, SPEED_100); 2607 else if (link & LNK_10MB) 2608 ethtool_cmd_speed_set(ecmd, SPEED_10); 2609 else 2610 ethtool_cmd_speed_set(ecmd, 0); 2611 } 2612 if (link & LNK_FULL_DUPLEX) 2613 ecmd->duplex = DUPLEX_FULL; 2614 else 2615 ecmd->duplex = DUPLEX_HALF; 2616 2617 if (link & LNK_NEGOTIATE) 2618 ecmd->autoneg = AUTONEG_ENABLE; 2619 else 2620 ecmd->autoneg = AUTONEG_DISABLE; 2621 2622 #if 0 2623 /* 2624 * Current struct ethtool_cmd is insufficient 2625 */ 2626 ecmd->trace = readl(®s->TuneTrace); 2627 2628 ecmd->txcoal = readl(®s->TuneTxCoalTicks); 2629 ecmd->rxcoal = readl(®s->TuneRxCoalTicks); 2630 #endif 2631 ecmd->maxtxpkt = readl(®s->TuneMaxTxDesc); 2632 ecmd->maxrxpkt = readl(®s->TuneMaxRxDesc); 2633 2634 return 0; 2635 } 2636 2637 static int ace_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 2638 { 2639 struct ace_private *ap = netdev_priv(dev); 2640 struct ace_regs __iomem *regs = ap->regs; 2641 u32 link, speed; 2642 2643 link = readl(®s->GigLnkState); 2644 if (link & LNK_1000MB) 2645 speed = SPEED_1000; 2646 else { 2647 link = readl(®s->FastLnkState); 2648 if (link & LNK_100MB) 2649 speed = SPEED_100; 2650 else if (link & LNK_10MB) 2651 speed = SPEED_10; 2652 else 2653 speed = SPEED_100; 2654 } 2655 2656 link = LNK_ENABLE | LNK_1000MB | LNK_100MB | LNK_10MB | 2657 LNK_RX_FLOW_CTL_Y | LNK_NEG_FCTL; 2658 if (!ACE_IS_TIGON_I(ap)) 2659 link |= LNK_TX_FLOW_CTL_Y; 2660 if (ecmd->autoneg == AUTONEG_ENABLE) 2661 link |= LNK_NEGOTIATE; 2662 if (ethtool_cmd_speed(ecmd) != speed) { 2663 link &= ~(LNK_1000MB | LNK_100MB | LNK_10MB); 2664 switch (ethtool_cmd_speed(ecmd)) { 2665 case SPEED_1000: 2666 link |= LNK_1000MB; 2667 break; 2668 case SPEED_100: 2669 link |= LNK_100MB; 2670 break; 2671 case SPEED_10: 2672 link |= LNK_10MB; 2673 break; 2674 } 2675 } 2676 2677 if (ecmd->duplex == DUPLEX_FULL) 2678 link |= LNK_FULL_DUPLEX; 2679 2680 if (link != ap->link) { 2681 struct cmd cmd; 2682 printk(KERN_INFO "%s: Renegotiating link state\n", 2683 dev->name); 2684 2685 ap->link = link; 2686 writel(link, ®s->TuneLink); 2687 if (!ACE_IS_TIGON_I(ap)) 2688 writel(link, ®s->TuneFastLink); 2689 wmb(); 2690 2691 cmd.evt = C_LNK_NEGOTIATION; 2692 cmd.code = 0; 2693 cmd.idx = 0; 2694 ace_issue_cmd(regs, &cmd); 2695 } 2696 return 0; 2697 } 2698 2699 static void ace_get_drvinfo(struct net_device *dev, 2700 struct ethtool_drvinfo *info) 2701 { 2702 struct ace_private *ap = netdev_priv(dev); 2703 2704 strlcpy(info->driver, "acenic", sizeof(info->driver)); 2705 snprintf(info->version, sizeof(info->version), "%i.%i.%i", 2706 ap->firmware_major, ap->firmware_minor, 2707 ap->firmware_fix); 2708 2709 if (ap->pdev) 2710 strlcpy(info->bus_info, pci_name(ap->pdev), 2711 sizeof(info->bus_info)); 2712 2713 } 2714 2715 /* 2716 * Set the hardware MAC address. 2717 */ 2718 static int ace_set_mac_addr(struct net_device *dev, void *p) 2719 { 2720 struct ace_private *ap = netdev_priv(dev); 2721 struct ace_regs __iomem *regs = ap->regs; 2722 struct sockaddr *addr=p; 2723 u8 *da; 2724 struct cmd cmd; 2725 2726 if(netif_running(dev)) 2727 return -EBUSY; 2728 2729 memcpy(dev->dev_addr, addr->sa_data,dev->addr_len); 2730 2731 da = (u8 *)dev->dev_addr; 2732 2733 writel(da[0] << 8 | da[1], ®s->MacAddrHi); 2734 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5], 2735 ®s->MacAddrLo); 2736 2737 cmd.evt = C_SET_MAC_ADDR; 2738 cmd.code = 0; 2739 cmd.idx = 0; 2740 ace_issue_cmd(regs, &cmd); 2741 2742 return 0; 2743 } 2744 2745 2746 static void ace_set_multicast_list(struct net_device *dev) 2747 { 2748 struct ace_private *ap = netdev_priv(dev); 2749 struct ace_regs __iomem *regs = ap->regs; 2750 struct cmd cmd; 2751 2752 if ((dev->flags & IFF_ALLMULTI) && !(ap->mcast_all)) { 2753 cmd.evt = C_SET_MULTICAST_MODE; 2754 cmd.code = C_C_MCAST_ENABLE; 2755 cmd.idx = 0; 2756 ace_issue_cmd(regs, &cmd); 2757 ap->mcast_all = 1; 2758 } else if (ap->mcast_all) { 2759 cmd.evt = C_SET_MULTICAST_MODE; 2760 cmd.code = C_C_MCAST_DISABLE; 2761 cmd.idx = 0; 2762 ace_issue_cmd(regs, &cmd); 2763 ap->mcast_all = 0; 2764 } 2765 2766 if ((dev->flags & IFF_PROMISC) && !(ap->promisc)) { 2767 cmd.evt = C_SET_PROMISC_MODE; 2768 cmd.code = C_C_PROMISC_ENABLE; 2769 cmd.idx = 0; 2770 ace_issue_cmd(regs, &cmd); 2771 ap->promisc = 1; 2772 }else if (!(dev->flags & IFF_PROMISC) && (ap->promisc)) { 2773 cmd.evt = C_SET_PROMISC_MODE; 2774 cmd.code = C_C_PROMISC_DISABLE; 2775 cmd.idx = 0; 2776 ace_issue_cmd(regs, &cmd); 2777 ap->promisc = 0; 2778 } 2779 2780 /* 2781 * For the time being multicast relies on the upper layers 2782 * filtering it properly. The Firmware does not allow one to 2783 * set the entire multicast list at a time and keeping track of 2784 * it here is going to be messy. 2785 */ 2786 if (!netdev_mc_empty(dev) && !ap->mcast_all) { 2787 cmd.evt = C_SET_MULTICAST_MODE; 2788 cmd.code = C_C_MCAST_ENABLE; 2789 cmd.idx = 0; 2790 ace_issue_cmd(regs, &cmd); 2791 }else if (!ap->mcast_all) { 2792 cmd.evt = C_SET_MULTICAST_MODE; 2793 cmd.code = C_C_MCAST_DISABLE; 2794 cmd.idx = 0; 2795 ace_issue_cmd(regs, &cmd); 2796 } 2797 } 2798 2799 2800 static struct net_device_stats *ace_get_stats(struct net_device *dev) 2801 { 2802 struct ace_private *ap = netdev_priv(dev); 2803 struct ace_mac_stats __iomem *mac_stats = 2804 (struct ace_mac_stats __iomem *)ap->regs->Stats; 2805 2806 dev->stats.rx_missed_errors = readl(&mac_stats->drop_space); 2807 dev->stats.multicast = readl(&mac_stats->kept_mc); 2808 dev->stats.collisions = readl(&mac_stats->coll); 2809 2810 return &dev->stats; 2811 } 2812 2813 2814 static void ace_copy(struct ace_regs __iomem *regs, const __be32 *src, 2815 u32 dest, int size) 2816 { 2817 void __iomem *tdest; 2818 short tsize, i; 2819 2820 if (size <= 0) 2821 return; 2822 2823 while (size > 0) { 2824 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1), 2825 min_t(u32, size, ACE_WINDOW_SIZE)); 2826 tdest = (void __iomem *) ®s->Window + 2827 (dest & (ACE_WINDOW_SIZE - 1)); 2828 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase); 2829 for (i = 0; i < (tsize / 4); i++) { 2830 /* Firmware is big-endian */ 2831 writel(be32_to_cpup(src), tdest); 2832 src++; 2833 tdest += 4; 2834 dest += 4; 2835 size -= 4; 2836 } 2837 } 2838 } 2839 2840 2841 static void ace_clear(struct ace_regs __iomem *regs, u32 dest, int size) 2842 { 2843 void __iomem *tdest; 2844 short tsize = 0, i; 2845 2846 if (size <= 0) 2847 return; 2848 2849 while (size > 0) { 2850 tsize = min_t(u32, ((~dest & (ACE_WINDOW_SIZE - 1)) + 1), 2851 min_t(u32, size, ACE_WINDOW_SIZE)); 2852 tdest = (void __iomem *) ®s->Window + 2853 (dest & (ACE_WINDOW_SIZE - 1)); 2854 writel(dest & ~(ACE_WINDOW_SIZE - 1), ®s->WinBase); 2855 2856 for (i = 0; i < (tsize / 4); i++) { 2857 writel(0, tdest + i*4); 2858 } 2859 2860 dest += tsize; 2861 size -= tsize; 2862 } 2863 } 2864 2865 2866 /* 2867 * Download the firmware into the SRAM on the NIC 2868 * 2869 * This operation requires the NIC to be halted and is performed with 2870 * interrupts disabled and with the spinlock hold. 2871 */ 2872 static int ace_load_firmware(struct net_device *dev) 2873 { 2874 const struct firmware *fw; 2875 const char *fw_name = "acenic/tg2.bin"; 2876 struct ace_private *ap = netdev_priv(dev); 2877 struct ace_regs __iomem *regs = ap->regs; 2878 const __be32 *fw_data; 2879 u32 load_addr; 2880 int ret; 2881 2882 if (!(readl(®s->CpuCtrl) & CPU_HALTED)) { 2883 printk(KERN_ERR "%s: trying to download firmware while the " 2884 "CPU is running!\n", ap->name); 2885 return -EFAULT; 2886 } 2887 2888 if (ACE_IS_TIGON_I(ap)) 2889 fw_name = "acenic/tg1.bin"; 2890 2891 ret = request_firmware(&fw, fw_name, &ap->pdev->dev); 2892 if (ret) { 2893 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n", 2894 ap->name, fw_name); 2895 return ret; 2896 } 2897 2898 fw_data = (void *)fw->data; 2899 2900 /* Firmware blob starts with version numbers, followed by 2901 load and start address. Remainder is the blob to be loaded 2902 contiguously from load address. We don't bother to represent 2903 the BSS/SBSS sections any more, since we were clearing the 2904 whole thing anyway. */ 2905 ap->firmware_major = fw->data[0]; 2906 ap->firmware_minor = fw->data[1]; 2907 ap->firmware_fix = fw->data[2]; 2908 2909 ap->firmware_start = be32_to_cpu(fw_data[1]); 2910 if (ap->firmware_start < 0x4000 || ap->firmware_start >= 0x80000) { 2911 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n", 2912 ap->name, ap->firmware_start, fw_name); 2913 ret = -EINVAL; 2914 goto out; 2915 } 2916 2917 load_addr = be32_to_cpu(fw_data[2]); 2918 if (load_addr < 0x4000 || load_addr >= 0x80000) { 2919 printk(KERN_ERR "%s: bogus load address %08x in \"%s\"\n", 2920 ap->name, load_addr, fw_name); 2921 ret = -EINVAL; 2922 goto out; 2923 } 2924 2925 /* 2926 * Do not try to clear more than 512KiB or we end up seeing 2927 * funny things on NICs with only 512KiB SRAM 2928 */ 2929 ace_clear(regs, 0x2000, 0x80000-0x2000); 2930 ace_copy(regs, &fw_data[3], load_addr, fw->size-12); 2931 out: 2932 release_firmware(fw); 2933 return ret; 2934 } 2935 2936 2937 /* 2938 * The eeprom on the AceNIC is an Atmel i2c EEPROM. 2939 * 2940 * Accessing the EEPROM is `interesting' to say the least - don't read 2941 * this code right after dinner. 2942 * 2943 * This is all about black magic and bit-banging the device .... I 2944 * wonder in what hospital they have put the guy who designed the i2c 2945 * specs. 2946 * 2947 * Oh yes, this is only the beginning! 2948 * 2949 * Thanks to Stevarino Webinski for helping tracking down the bugs in the 2950 * code i2c readout code by beta testing all my hacks. 2951 */ 2952 static void eeprom_start(struct ace_regs __iomem *regs) 2953 { 2954 u32 local; 2955 2956 readl(®s->LocalCtrl); 2957 udelay(ACE_SHORT_DELAY); 2958 local = readl(®s->LocalCtrl); 2959 local |= EEPROM_DATA_OUT | EEPROM_WRITE_ENABLE; 2960 writel(local, ®s->LocalCtrl); 2961 readl(®s->LocalCtrl); 2962 mb(); 2963 udelay(ACE_SHORT_DELAY); 2964 local |= EEPROM_CLK_OUT; 2965 writel(local, ®s->LocalCtrl); 2966 readl(®s->LocalCtrl); 2967 mb(); 2968 udelay(ACE_SHORT_DELAY); 2969 local &= ~EEPROM_DATA_OUT; 2970 writel(local, ®s->LocalCtrl); 2971 readl(®s->LocalCtrl); 2972 mb(); 2973 udelay(ACE_SHORT_DELAY); 2974 local &= ~EEPROM_CLK_OUT; 2975 writel(local, ®s->LocalCtrl); 2976 readl(®s->LocalCtrl); 2977 mb(); 2978 } 2979 2980 2981 static void eeprom_prep(struct ace_regs __iomem *regs, u8 magic) 2982 { 2983 short i; 2984 u32 local; 2985 2986 udelay(ACE_SHORT_DELAY); 2987 local = readl(®s->LocalCtrl); 2988 local &= ~EEPROM_DATA_OUT; 2989 local |= EEPROM_WRITE_ENABLE; 2990 writel(local, ®s->LocalCtrl); 2991 readl(®s->LocalCtrl); 2992 mb(); 2993 2994 for (i = 0; i < 8; i++, magic <<= 1) { 2995 udelay(ACE_SHORT_DELAY); 2996 if (magic & 0x80) 2997 local |= EEPROM_DATA_OUT; 2998 else 2999 local &= ~EEPROM_DATA_OUT; 3000 writel(local, ®s->LocalCtrl); 3001 readl(®s->LocalCtrl); 3002 mb(); 3003 3004 udelay(ACE_SHORT_DELAY); 3005 local |= EEPROM_CLK_OUT; 3006 writel(local, ®s->LocalCtrl); 3007 readl(®s->LocalCtrl); 3008 mb(); 3009 udelay(ACE_SHORT_DELAY); 3010 local &= ~(EEPROM_CLK_OUT | EEPROM_DATA_OUT); 3011 writel(local, ®s->LocalCtrl); 3012 readl(®s->LocalCtrl); 3013 mb(); 3014 } 3015 } 3016 3017 3018 static int eeprom_check_ack(struct ace_regs __iomem *regs) 3019 { 3020 int state; 3021 u32 local; 3022 3023 local = readl(®s->LocalCtrl); 3024 local &= ~EEPROM_WRITE_ENABLE; 3025 writel(local, ®s->LocalCtrl); 3026 readl(®s->LocalCtrl); 3027 mb(); 3028 udelay(ACE_LONG_DELAY); 3029 local |= EEPROM_CLK_OUT; 3030 writel(local, ®s->LocalCtrl); 3031 readl(®s->LocalCtrl); 3032 mb(); 3033 udelay(ACE_SHORT_DELAY); 3034 /* sample data in middle of high clk */ 3035 state = (readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0; 3036 udelay(ACE_SHORT_DELAY); 3037 mb(); 3038 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl); 3039 readl(®s->LocalCtrl); 3040 mb(); 3041 3042 return state; 3043 } 3044 3045 3046 static void eeprom_stop(struct ace_regs __iomem *regs) 3047 { 3048 u32 local; 3049 3050 udelay(ACE_SHORT_DELAY); 3051 local = readl(®s->LocalCtrl); 3052 local |= EEPROM_WRITE_ENABLE; 3053 writel(local, ®s->LocalCtrl); 3054 readl(®s->LocalCtrl); 3055 mb(); 3056 udelay(ACE_SHORT_DELAY); 3057 local &= ~EEPROM_DATA_OUT; 3058 writel(local, ®s->LocalCtrl); 3059 readl(®s->LocalCtrl); 3060 mb(); 3061 udelay(ACE_SHORT_DELAY); 3062 local |= EEPROM_CLK_OUT; 3063 writel(local, ®s->LocalCtrl); 3064 readl(®s->LocalCtrl); 3065 mb(); 3066 udelay(ACE_SHORT_DELAY); 3067 local |= EEPROM_DATA_OUT; 3068 writel(local, ®s->LocalCtrl); 3069 readl(®s->LocalCtrl); 3070 mb(); 3071 udelay(ACE_LONG_DELAY); 3072 local &= ~EEPROM_CLK_OUT; 3073 writel(local, ®s->LocalCtrl); 3074 mb(); 3075 } 3076 3077 3078 /* 3079 * Read a whole byte from the EEPROM. 3080 */ 3081 static int read_eeprom_byte(struct net_device *dev, unsigned long offset) 3082 { 3083 struct ace_private *ap = netdev_priv(dev); 3084 struct ace_regs __iomem *regs = ap->regs; 3085 unsigned long flags; 3086 u32 local; 3087 int result = 0; 3088 short i; 3089 3090 /* 3091 * Don't take interrupts on this CPU will bit banging 3092 * the %#%#@$ I2C device 3093 */ 3094 local_irq_save(flags); 3095 3096 eeprom_start(regs); 3097 3098 eeprom_prep(regs, EEPROM_WRITE_SELECT); 3099 if (eeprom_check_ack(regs)) { 3100 local_irq_restore(flags); 3101 printk(KERN_ERR "%s: Unable to sync eeprom\n", ap->name); 3102 result = -EIO; 3103 goto eeprom_read_error; 3104 } 3105 3106 eeprom_prep(regs, (offset >> 8) & 0xff); 3107 if (eeprom_check_ack(regs)) { 3108 local_irq_restore(flags); 3109 printk(KERN_ERR "%s: Unable to set address byte 0\n", 3110 ap->name); 3111 result = -EIO; 3112 goto eeprom_read_error; 3113 } 3114 3115 eeprom_prep(regs, offset & 0xff); 3116 if (eeprom_check_ack(regs)) { 3117 local_irq_restore(flags); 3118 printk(KERN_ERR "%s: Unable to set address byte 1\n", 3119 ap->name); 3120 result = -EIO; 3121 goto eeprom_read_error; 3122 } 3123 3124 eeprom_start(regs); 3125 eeprom_prep(regs, EEPROM_READ_SELECT); 3126 if (eeprom_check_ack(regs)) { 3127 local_irq_restore(flags); 3128 printk(KERN_ERR "%s: Unable to set READ_SELECT\n", 3129 ap->name); 3130 result = -EIO; 3131 goto eeprom_read_error; 3132 } 3133 3134 for (i = 0; i < 8; i++) { 3135 local = readl(®s->LocalCtrl); 3136 local &= ~EEPROM_WRITE_ENABLE; 3137 writel(local, ®s->LocalCtrl); 3138 readl(®s->LocalCtrl); 3139 udelay(ACE_LONG_DELAY); 3140 mb(); 3141 local |= EEPROM_CLK_OUT; 3142 writel(local, ®s->LocalCtrl); 3143 readl(®s->LocalCtrl); 3144 mb(); 3145 udelay(ACE_SHORT_DELAY); 3146 /* sample data mid high clk */ 3147 result = (result << 1) | 3148 ((readl(®s->LocalCtrl) & EEPROM_DATA_IN) != 0); 3149 udelay(ACE_SHORT_DELAY); 3150 mb(); 3151 local = readl(®s->LocalCtrl); 3152 local &= ~EEPROM_CLK_OUT; 3153 writel(local, ®s->LocalCtrl); 3154 readl(®s->LocalCtrl); 3155 udelay(ACE_SHORT_DELAY); 3156 mb(); 3157 if (i == 7) { 3158 local |= EEPROM_WRITE_ENABLE; 3159 writel(local, ®s->LocalCtrl); 3160 readl(®s->LocalCtrl); 3161 mb(); 3162 udelay(ACE_SHORT_DELAY); 3163 } 3164 } 3165 3166 local |= EEPROM_DATA_OUT; 3167 writel(local, ®s->LocalCtrl); 3168 readl(®s->LocalCtrl); 3169 mb(); 3170 udelay(ACE_SHORT_DELAY); 3171 writel(readl(®s->LocalCtrl) | EEPROM_CLK_OUT, ®s->LocalCtrl); 3172 readl(®s->LocalCtrl); 3173 udelay(ACE_LONG_DELAY); 3174 writel(readl(®s->LocalCtrl) & ~EEPROM_CLK_OUT, ®s->LocalCtrl); 3175 readl(®s->LocalCtrl); 3176 mb(); 3177 udelay(ACE_SHORT_DELAY); 3178 eeprom_stop(regs); 3179 3180 local_irq_restore(flags); 3181 out: 3182 return result; 3183 3184 eeprom_read_error: 3185 printk(KERN_ERR "%s: Unable to read eeprom byte 0x%02lx\n", 3186 ap->name, offset); 3187 goto out; 3188 } 3189 3190 module_pci_driver(acenic_pci_driver); 3191