1 /* 2 * Allwinner EMAC Fast Ethernet driver for Linux. 3 * 4 * Copyright 2012-2013 Stefan Roese <sr@denx.de> 5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> 6 * 7 * Based on the Linux driver provided by Allwinner: 8 * Copyright (C) 1997 Sten Wang 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/gpio.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/mii.h> 22 #include <linux/module.h> 23 #include <linux/netdevice.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/phy.h> 31 #include <linux/soc/sunxi/sunxi_sram.h> 32 33 #include "sun4i-emac.h" 34 35 #define DRV_NAME "sun4i-emac" 36 #define DRV_VERSION "1.02" 37 38 #define EMAC_MAX_FRAME_LEN 0x0600 39 40 /* Transmit timeout, default 5 seconds. */ 41 static int watchdog = 5000; 42 module_param(watchdog, int, 0400); 43 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 44 45 /* EMAC register address locking. 46 * 47 * The EMAC uses an address register to control where data written 48 * to the data register goes. This means that the address register 49 * must be preserved over interrupts or similar calls. 50 * 51 * During interrupt and other critical calls, a spinlock is used to 52 * protect the system, but the calls themselves save the address 53 * in the address register in case they are interrupting another 54 * access to the device. 55 * 56 * For general accesses a lock is provided so that calls which are 57 * allowed to sleep are serialised so that the address register does 58 * not need to be saved. This lock also serves to serialise access 59 * to the EEPROM and PHY access registers which are shared between 60 * these two devices. 61 */ 62 63 /* The driver supports the original EMACE, and now the two newer 64 * devices, EMACA and EMACB. 65 */ 66 67 struct emac_board_info { 68 struct clk *clk; 69 struct device *dev; 70 struct platform_device *pdev; 71 spinlock_t lock; 72 void __iomem *membase; 73 u32 msg_enable; 74 struct net_device *ndev; 75 struct sk_buff *skb_last; 76 u16 tx_fifo_stat; 77 78 int emacrx_completed_flag; 79 80 struct device_node *phy_node; 81 unsigned int link; 82 unsigned int speed; 83 unsigned int duplex; 84 85 phy_interface_t phy_interface; 86 }; 87 88 static void emac_update_speed(struct net_device *dev) 89 { 90 struct emac_board_info *db = netdev_priv(dev); 91 unsigned int reg_val; 92 93 /* set EMAC SPEED, depend on PHY */ 94 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); 95 reg_val &= ~(0x1 << 8); 96 if (db->speed == SPEED_100) 97 reg_val |= 1 << 8; 98 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); 99 } 100 101 static void emac_update_duplex(struct net_device *dev) 102 { 103 struct emac_board_info *db = netdev_priv(dev); 104 unsigned int reg_val; 105 106 /* set duplex depend on phy */ 107 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); 108 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; 109 if (db->duplex) 110 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; 111 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); 112 } 113 114 static void emac_handle_link_change(struct net_device *dev) 115 { 116 struct emac_board_info *db = netdev_priv(dev); 117 struct phy_device *phydev = dev->phydev; 118 unsigned long flags; 119 int status_change = 0; 120 121 if (phydev->link) { 122 if (db->speed != phydev->speed) { 123 spin_lock_irqsave(&db->lock, flags); 124 db->speed = phydev->speed; 125 emac_update_speed(dev); 126 spin_unlock_irqrestore(&db->lock, flags); 127 status_change = 1; 128 } 129 130 if (db->duplex != phydev->duplex) { 131 spin_lock_irqsave(&db->lock, flags); 132 db->duplex = phydev->duplex; 133 emac_update_duplex(dev); 134 spin_unlock_irqrestore(&db->lock, flags); 135 status_change = 1; 136 } 137 } 138 139 if (phydev->link != db->link) { 140 if (!phydev->link) { 141 db->speed = 0; 142 db->duplex = -1; 143 } 144 db->link = phydev->link; 145 146 status_change = 1; 147 } 148 149 if (status_change) 150 phy_print_status(phydev); 151 } 152 153 static int emac_mdio_probe(struct net_device *dev) 154 { 155 struct emac_board_info *db = netdev_priv(dev); 156 struct phy_device *phydev; 157 158 /* to-do: PHY interrupts are currently not supported */ 159 160 /* attach the mac to the phy */ 161 phydev = of_phy_connect(db->ndev, db->phy_node, 162 &emac_handle_link_change, 0, 163 db->phy_interface); 164 if (!phydev) { 165 netdev_err(db->ndev, "could not find the PHY\n"); 166 return -ENODEV; 167 } 168 169 /* mask with MAC supported features */ 170 phydev->supported &= PHY_BASIC_FEATURES; 171 phydev->advertising = phydev->supported; 172 173 db->link = 0; 174 db->speed = 0; 175 db->duplex = -1; 176 177 return 0; 178 } 179 180 static void emac_mdio_remove(struct net_device *dev) 181 { 182 phy_disconnect(dev->phydev); 183 } 184 185 static void emac_reset(struct emac_board_info *db) 186 { 187 dev_dbg(db->dev, "resetting device\n"); 188 189 /* RESET device */ 190 writel(0, db->membase + EMAC_CTL_REG); 191 udelay(200); 192 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); 193 udelay(200); 194 } 195 196 static void emac_outblk_32bit(void __iomem *reg, void *data, int count) 197 { 198 writesl(reg, data, round_up(count, 4) / 4); 199 } 200 201 static void emac_inblk_32bit(void __iomem *reg, void *data, int count) 202 { 203 readsl(reg, data, round_up(count, 4) / 4); 204 } 205 206 static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 207 { 208 struct phy_device *phydev = dev->phydev; 209 210 if (!netif_running(dev)) 211 return -EINVAL; 212 213 if (!phydev) 214 return -ENODEV; 215 216 return phy_mii_ioctl(phydev, rq, cmd); 217 } 218 219 /* ethtool ops */ 220 static void emac_get_drvinfo(struct net_device *dev, 221 struct ethtool_drvinfo *info) 222 { 223 strlcpy(info->driver, DRV_NAME, sizeof(DRV_NAME)); 224 strlcpy(info->version, DRV_VERSION, sizeof(DRV_VERSION)); 225 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info)); 226 } 227 228 static const struct ethtool_ops emac_ethtool_ops = { 229 .get_drvinfo = emac_get_drvinfo, 230 .get_link = ethtool_op_get_link, 231 .get_link_ksettings = phy_ethtool_get_link_ksettings, 232 .set_link_ksettings = phy_ethtool_set_link_ksettings, 233 }; 234 235 static unsigned int emac_setup(struct net_device *ndev) 236 { 237 struct emac_board_info *db = netdev_priv(ndev); 238 unsigned int reg_val; 239 240 /* set up TX */ 241 reg_val = readl(db->membase + EMAC_TX_MODE_REG); 242 243 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN, 244 db->membase + EMAC_TX_MODE_REG); 245 246 /* set MAC */ 247 /* set MAC CTL0 */ 248 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); 249 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN | 250 EMAC_MAC_CTL0_TX_FLOW_CTL_EN, 251 db->membase + EMAC_MAC_CTL0_REG); 252 253 /* set MAC CTL1 */ 254 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); 255 reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN; 256 reg_val |= EMAC_MAC_CTL1_CRC_EN; 257 reg_val |= EMAC_MAC_CTL1_PAD_EN; 258 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); 259 260 /* set up IPGT */ 261 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG); 262 263 /* set up IPGR */ 264 writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2, 265 db->membase + EMAC_MAC_IPGR_REG); 266 267 /* set up Collison window */ 268 writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM, 269 db->membase + EMAC_MAC_CLRT_REG); 270 271 /* set up Max Frame Length */ 272 writel(EMAC_MAX_FRAME_LEN, 273 db->membase + EMAC_MAC_MAXF_REG); 274 275 return 0; 276 } 277 278 static void emac_set_rx_mode(struct net_device *ndev) 279 { 280 struct emac_board_info *db = netdev_priv(ndev); 281 unsigned int reg_val; 282 283 /* set up RX */ 284 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 285 286 if (ndev->flags & IFF_PROMISC) 287 reg_val |= EMAC_RX_CTL_PASS_ALL_EN; 288 else 289 reg_val &= ~EMAC_RX_CTL_PASS_ALL_EN; 290 291 writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN | 292 EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN | 293 EMAC_RX_CTL_ACCEPT_MULTICAST_EN | 294 EMAC_RX_CTL_ACCEPT_BROADCAST_EN, 295 db->membase + EMAC_RX_CTL_REG); 296 } 297 298 static unsigned int emac_powerup(struct net_device *ndev) 299 { 300 struct emac_board_info *db = netdev_priv(ndev); 301 unsigned int reg_val; 302 303 /* initial EMAC */ 304 /* flush RX FIFO */ 305 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 306 reg_val |= 0x8; 307 writel(reg_val, db->membase + EMAC_RX_CTL_REG); 308 udelay(1); 309 310 /* initial MAC */ 311 /* soft reset MAC */ 312 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); 313 reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET; 314 writel(reg_val, db->membase + EMAC_MAC_CTL0_REG); 315 316 /* set MII clock */ 317 reg_val = readl(db->membase + EMAC_MAC_MCFG_REG); 318 reg_val &= (~(0xf << 2)); 319 reg_val |= (0xD << 2); 320 writel(reg_val, db->membase + EMAC_MAC_MCFG_REG); 321 322 /* clear RX counter */ 323 writel(0x0, db->membase + EMAC_RX_FBC_REG); 324 325 /* disable all interrupt and clear interrupt status */ 326 writel(0, db->membase + EMAC_INT_CTL_REG); 327 reg_val = readl(db->membase + EMAC_INT_STA_REG); 328 writel(reg_val, db->membase + EMAC_INT_STA_REG); 329 330 udelay(1); 331 332 /* set up EMAC */ 333 emac_setup(ndev); 334 335 /* set mac_address to chip */ 336 writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev-> 337 dev_addr[2], db->membase + EMAC_MAC_A1_REG); 338 writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev-> 339 dev_addr[5], db->membase + EMAC_MAC_A0_REG); 340 341 mdelay(1); 342 343 return 0; 344 } 345 346 static int emac_set_mac_address(struct net_device *dev, void *p) 347 { 348 struct sockaddr *addr = p; 349 struct emac_board_info *db = netdev_priv(dev); 350 351 if (netif_running(dev)) 352 return -EBUSY; 353 354 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 355 356 writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev-> 357 dev_addr[2], db->membase + EMAC_MAC_A1_REG); 358 writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev-> 359 dev_addr[5], db->membase + EMAC_MAC_A0_REG); 360 361 return 0; 362 } 363 364 /* Initialize emac board */ 365 static void emac_init_device(struct net_device *dev) 366 { 367 struct emac_board_info *db = netdev_priv(dev); 368 unsigned long flags; 369 unsigned int reg_val; 370 371 spin_lock_irqsave(&db->lock, flags); 372 373 emac_update_speed(dev); 374 emac_update_duplex(dev); 375 376 /* enable RX/TX */ 377 reg_val = readl(db->membase + EMAC_CTL_REG); 378 writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN, 379 db->membase + EMAC_CTL_REG); 380 381 /* enable RX/TX0/RX Hlevel interrup */ 382 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 383 reg_val |= (0xf << 0) | (0x01 << 8); 384 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 385 386 spin_unlock_irqrestore(&db->lock, flags); 387 } 388 389 /* Our watchdog timed out. Called by the networking layer */ 390 static void emac_timeout(struct net_device *dev) 391 { 392 struct emac_board_info *db = netdev_priv(dev); 393 unsigned long flags; 394 395 if (netif_msg_timer(db)) 396 dev_err(db->dev, "tx time out.\n"); 397 398 /* Save previous register address */ 399 spin_lock_irqsave(&db->lock, flags); 400 401 netif_stop_queue(dev); 402 emac_reset(db); 403 emac_init_device(dev); 404 /* We can accept TX packets again */ 405 netif_trans_update(dev); 406 netif_wake_queue(dev); 407 408 /* Restore previous register address */ 409 spin_unlock_irqrestore(&db->lock, flags); 410 } 411 412 /* Hardware start transmission. 413 * Send a packet to media from the upper layer. 414 */ 415 static int emac_start_xmit(struct sk_buff *skb, struct net_device *dev) 416 { 417 struct emac_board_info *db = netdev_priv(dev); 418 unsigned long channel; 419 unsigned long flags; 420 421 channel = db->tx_fifo_stat & 3; 422 if (channel == 3) 423 return 1; 424 425 channel = (channel == 1 ? 1 : 0); 426 427 spin_lock_irqsave(&db->lock, flags); 428 429 writel(channel, db->membase + EMAC_TX_INS_REG); 430 431 emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG, 432 skb->data, skb->len); 433 dev->stats.tx_bytes += skb->len; 434 435 db->tx_fifo_stat |= 1 << channel; 436 /* TX control: First packet immediately send, second packet queue */ 437 if (channel == 0) { 438 /* set TX len */ 439 writel(skb->len, db->membase + EMAC_TX_PL0_REG); 440 /* start translate from fifo to phy */ 441 writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1, 442 db->membase + EMAC_TX_CTL0_REG); 443 444 /* save the time stamp */ 445 netif_trans_update(dev); 446 } else if (channel == 1) { 447 /* set TX len */ 448 writel(skb->len, db->membase + EMAC_TX_PL1_REG); 449 /* start translate from fifo to phy */ 450 writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1, 451 db->membase + EMAC_TX_CTL1_REG); 452 453 /* save the time stamp */ 454 netif_trans_update(dev); 455 } 456 457 if ((db->tx_fifo_stat & 3) == 3) { 458 /* Second packet */ 459 netif_stop_queue(dev); 460 } 461 462 spin_unlock_irqrestore(&db->lock, flags); 463 464 /* free this SKB */ 465 dev_consume_skb_any(skb); 466 467 return NETDEV_TX_OK; 468 } 469 470 /* EMAC interrupt handler 471 * receive the packet to upper layer, free the transmitted packet 472 */ 473 static void emac_tx_done(struct net_device *dev, struct emac_board_info *db, 474 unsigned int tx_status) 475 { 476 /* One packet sent complete */ 477 db->tx_fifo_stat &= ~(tx_status & 3); 478 if (3 == (tx_status & 3)) 479 dev->stats.tx_packets += 2; 480 else 481 dev->stats.tx_packets++; 482 483 if (netif_msg_tx_done(db)) 484 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); 485 486 netif_wake_queue(dev); 487 } 488 489 /* Received a packet and pass to upper layer 490 */ 491 static void emac_rx(struct net_device *dev) 492 { 493 struct emac_board_info *db = netdev_priv(dev); 494 struct sk_buff *skb; 495 u8 *rdptr; 496 bool good_packet; 497 static int rxlen_last; 498 unsigned int reg_val; 499 u32 rxhdr, rxstatus, rxcount, rxlen; 500 501 /* Check packet ready or not */ 502 while (1) { 503 /* race warning: the first packet might arrive with 504 * the interrupts disabled, but the second will fix 505 * it 506 */ 507 rxcount = readl(db->membase + EMAC_RX_FBC_REG); 508 509 if (netif_msg_rx_status(db)) 510 dev_dbg(db->dev, "RXCount: %x\n", rxcount); 511 512 if ((db->skb_last != NULL) && (rxlen_last > 0)) { 513 dev->stats.rx_bytes += rxlen_last; 514 515 /* Pass to upper layer */ 516 db->skb_last->protocol = eth_type_trans(db->skb_last, 517 dev); 518 netif_rx(db->skb_last); 519 dev->stats.rx_packets++; 520 db->skb_last = NULL; 521 rxlen_last = 0; 522 523 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 524 reg_val &= ~EMAC_RX_CTL_DMA_EN; 525 writel(reg_val, db->membase + EMAC_RX_CTL_REG); 526 } 527 528 if (!rxcount) { 529 db->emacrx_completed_flag = 1; 530 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 531 reg_val |= (0xf << 0) | (0x01 << 8); 532 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 533 534 /* had one stuck? */ 535 rxcount = readl(db->membase + EMAC_RX_FBC_REG); 536 if (!rxcount) 537 return; 538 } 539 540 reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG); 541 if (netif_msg_rx_status(db)) 542 dev_dbg(db->dev, "receive header: %x\n", reg_val); 543 if (reg_val != EMAC_UNDOCUMENTED_MAGIC) { 544 /* disable RX */ 545 reg_val = readl(db->membase + EMAC_CTL_REG); 546 writel(reg_val & ~EMAC_CTL_RX_EN, 547 db->membase + EMAC_CTL_REG); 548 549 /* Flush RX FIFO */ 550 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 551 writel(reg_val | (1 << 3), 552 db->membase + EMAC_RX_CTL_REG); 553 554 do { 555 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 556 } while (reg_val & (1 << 3)); 557 558 /* enable RX */ 559 reg_val = readl(db->membase + EMAC_CTL_REG); 560 writel(reg_val | EMAC_CTL_RX_EN, 561 db->membase + EMAC_CTL_REG); 562 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 563 reg_val |= (0xf << 0) | (0x01 << 8); 564 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 565 566 db->emacrx_completed_flag = 1; 567 568 return; 569 } 570 571 /* A packet ready now & Get status/length */ 572 good_packet = true; 573 574 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG, 575 &rxhdr, sizeof(rxhdr)); 576 577 if (netif_msg_rx_status(db)) 578 dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr))); 579 580 rxlen = EMAC_RX_IO_DATA_LEN(rxhdr); 581 rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr); 582 583 if (netif_msg_rx_status(db)) 584 dev_dbg(db->dev, "RX: status %02x, length %04x\n", 585 rxstatus, rxlen); 586 587 /* Packet Status check */ 588 if (rxlen < 0x40) { 589 good_packet = false; 590 if (netif_msg_rx_err(db)) 591 dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); 592 } 593 594 if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) { 595 good_packet = false; 596 597 if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) { 598 if (netif_msg_rx_err(db)) 599 dev_dbg(db->dev, "crc error\n"); 600 dev->stats.rx_crc_errors++; 601 } 602 603 if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) { 604 if (netif_msg_rx_err(db)) 605 dev_dbg(db->dev, "length error\n"); 606 dev->stats.rx_length_errors++; 607 } 608 } 609 610 /* Move data from EMAC */ 611 if (good_packet) { 612 skb = netdev_alloc_skb(dev, rxlen + 4); 613 if (!skb) 614 continue; 615 skb_reserve(skb, 2); 616 rdptr = (u8 *) skb_put(skb, rxlen - 4); 617 618 /* Read received packet from RX SRAM */ 619 if (netif_msg_rx_status(db)) 620 dev_dbg(db->dev, "RxLen %x\n", rxlen); 621 622 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG, 623 rdptr, rxlen); 624 dev->stats.rx_bytes += rxlen; 625 626 /* Pass to upper layer */ 627 skb->protocol = eth_type_trans(skb, dev); 628 netif_rx(skb); 629 dev->stats.rx_packets++; 630 } 631 } 632 } 633 634 static irqreturn_t emac_interrupt(int irq, void *dev_id) 635 { 636 struct net_device *dev = dev_id; 637 struct emac_board_info *db = netdev_priv(dev); 638 int int_status; 639 unsigned long flags; 640 unsigned int reg_val; 641 642 /* A real interrupt coming */ 643 644 /* holders of db->lock must always block IRQs */ 645 spin_lock_irqsave(&db->lock, flags); 646 647 /* Disable all interrupts */ 648 writel(0, db->membase + EMAC_INT_CTL_REG); 649 650 /* Got EMAC interrupt status */ 651 /* Got ISR */ 652 int_status = readl(db->membase + EMAC_INT_STA_REG); 653 /* Clear ISR status */ 654 writel(int_status, db->membase + EMAC_INT_STA_REG); 655 656 if (netif_msg_intr(db)) 657 dev_dbg(db->dev, "emac interrupt %02x\n", int_status); 658 659 /* Received the coming packet */ 660 if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) { 661 /* carrier lost */ 662 db->emacrx_completed_flag = 0; 663 emac_rx(dev); 664 } 665 666 /* Transmit Interrupt check */ 667 if (int_status & (0x01 | 0x02)) 668 emac_tx_done(dev, db, int_status); 669 670 if (int_status & (0x04 | 0x08)) 671 netdev_info(dev, " ab : %x\n", int_status); 672 673 /* Re-enable interrupt mask */ 674 if (db->emacrx_completed_flag == 1) { 675 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 676 reg_val |= (0xf << 0) | (0x01 << 8); 677 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 678 } 679 spin_unlock_irqrestore(&db->lock, flags); 680 681 return IRQ_HANDLED; 682 } 683 684 #ifdef CONFIG_NET_POLL_CONTROLLER 685 /* 686 * Used by netconsole 687 */ 688 static void emac_poll_controller(struct net_device *dev) 689 { 690 disable_irq(dev->irq); 691 emac_interrupt(dev->irq, dev); 692 enable_irq(dev->irq); 693 } 694 #endif 695 696 /* Open the interface. 697 * The interface is opened whenever "ifconfig" actives it. 698 */ 699 static int emac_open(struct net_device *dev) 700 { 701 struct emac_board_info *db = netdev_priv(dev); 702 int ret; 703 704 if (netif_msg_ifup(db)) 705 dev_dbg(db->dev, "enabling %s\n", dev->name); 706 707 if (request_irq(dev->irq, &emac_interrupt, 0, dev->name, dev)) 708 return -EAGAIN; 709 710 /* Initialize EMAC board */ 711 emac_reset(db); 712 emac_init_device(dev); 713 714 ret = emac_mdio_probe(dev); 715 if (ret < 0) { 716 free_irq(dev->irq, dev); 717 netdev_err(dev, "cannot probe MDIO bus\n"); 718 return ret; 719 } 720 721 phy_start(dev->phydev); 722 netif_start_queue(dev); 723 724 return 0; 725 } 726 727 static void emac_shutdown(struct net_device *dev) 728 { 729 unsigned int reg_val; 730 struct emac_board_info *db = netdev_priv(dev); 731 732 /* Disable all interrupt */ 733 writel(0, db->membase + EMAC_INT_CTL_REG); 734 735 /* clear interrupt status */ 736 reg_val = readl(db->membase + EMAC_INT_STA_REG); 737 writel(reg_val, db->membase + EMAC_INT_STA_REG); 738 739 /* Disable RX/TX */ 740 reg_val = readl(db->membase + EMAC_CTL_REG); 741 reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET); 742 writel(reg_val, db->membase + EMAC_CTL_REG); 743 } 744 745 /* Stop the interface. 746 * The interface is stopped when it is brought. 747 */ 748 static int emac_stop(struct net_device *ndev) 749 { 750 struct emac_board_info *db = netdev_priv(ndev); 751 752 if (netif_msg_ifdown(db)) 753 dev_dbg(db->dev, "shutting down %s\n", ndev->name); 754 755 netif_stop_queue(ndev); 756 netif_carrier_off(ndev); 757 758 phy_stop(ndev->phydev); 759 760 emac_mdio_remove(ndev); 761 762 emac_shutdown(ndev); 763 764 free_irq(ndev->irq, ndev); 765 766 return 0; 767 } 768 769 static const struct net_device_ops emac_netdev_ops = { 770 .ndo_open = emac_open, 771 .ndo_stop = emac_stop, 772 .ndo_start_xmit = emac_start_xmit, 773 .ndo_tx_timeout = emac_timeout, 774 .ndo_set_rx_mode = emac_set_rx_mode, 775 .ndo_do_ioctl = emac_ioctl, 776 .ndo_change_mtu = eth_change_mtu, 777 .ndo_validate_addr = eth_validate_addr, 778 .ndo_set_mac_address = emac_set_mac_address, 779 #ifdef CONFIG_NET_POLL_CONTROLLER 780 .ndo_poll_controller = emac_poll_controller, 781 #endif 782 }; 783 784 /* Search EMAC board, allocate space and register it 785 */ 786 static int emac_probe(struct platform_device *pdev) 787 { 788 struct device_node *np = pdev->dev.of_node; 789 struct emac_board_info *db; 790 struct net_device *ndev; 791 int ret = 0; 792 const char *mac_addr; 793 794 ndev = alloc_etherdev(sizeof(struct emac_board_info)); 795 if (!ndev) { 796 dev_err(&pdev->dev, "could not allocate device.\n"); 797 return -ENOMEM; 798 } 799 800 SET_NETDEV_DEV(ndev, &pdev->dev); 801 802 db = netdev_priv(ndev); 803 memset(db, 0, sizeof(*db)); 804 805 db->dev = &pdev->dev; 806 db->ndev = ndev; 807 db->pdev = pdev; 808 809 spin_lock_init(&db->lock); 810 811 db->membase = of_iomap(np, 0); 812 if (!db->membase) { 813 dev_err(&pdev->dev, "failed to remap registers\n"); 814 ret = -ENOMEM; 815 goto out; 816 } 817 818 /* fill in parameters for net-dev structure */ 819 ndev->base_addr = (unsigned long)db->membase; 820 ndev->irq = irq_of_parse_and_map(np, 0); 821 if (ndev->irq == -ENXIO) { 822 netdev_err(ndev, "No irq resource\n"); 823 ret = ndev->irq; 824 goto out_iounmap; 825 } 826 827 db->clk = devm_clk_get(&pdev->dev, NULL); 828 if (IS_ERR(db->clk)) { 829 ret = PTR_ERR(db->clk); 830 goto out_iounmap; 831 } 832 833 ret = clk_prepare_enable(db->clk); 834 if (ret) { 835 dev_err(&pdev->dev, "Error couldn't enable clock (%d)\n", ret); 836 goto out_iounmap; 837 } 838 839 ret = sunxi_sram_claim(&pdev->dev); 840 if (ret) { 841 dev_err(&pdev->dev, "Error couldn't map SRAM to device\n"); 842 goto out_clk_disable_unprepare; 843 } 844 845 db->phy_node = of_parse_phandle(np, "phy", 0); 846 if (!db->phy_node) { 847 dev_err(&pdev->dev, "no associated PHY\n"); 848 ret = -ENODEV; 849 goto out_release_sram; 850 } 851 852 /* Read MAC-address from DT */ 853 mac_addr = of_get_mac_address(np); 854 if (mac_addr) 855 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN); 856 857 /* Check if the MAC address is valid, if not get a random one */ 858 if (!is_valid_ether_addr(ndev->dev_addr)) { 859 eth_hw_addr_random(ndev); 860 dev_warn(&pdev->dev, "using random MAC address %pM\n", 861 ndev->dev_addr); 862 } 863 864 db->emacrx_completed_flag = 1; 865 emac_powerup(ndev); 866 emac_reset(db); 867 868 ndev->netdev_ops = &emac_netdev_ops; 869 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 870 ndev->ethtool_ops = &emac_ethtool_ops; 871 872 platform_set_drvdata(pdev, ndev); 873 874 /* Carrier starts down, phylib will bring it up */ 875 netif_carrier_off(ndev); 876 877 ret = register_netdev(ndev); 878 if (ret) { 879 dev_err(&pdev->dev, "Registering netdev failed!\n"); 880 ret = -ENODEV; 881 goto out_release_sram; 882 } 883 884 dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n", 885 ndev->name, db->membase, ndev->irq, ndev->dev_addr); 886 887 return 0; 888 889 out_release_sram: 890 sunxi_sram_release(&pdev->dev); 891 out_clk_disable_unprepare: 892 clk_disable_unprepare(db->clk); 893 out_iounmap: 894 iounmap(db->membase); 895 out: 896 dev_err(db->dev, "not found (%d).\n", ret); 897 898 free_netdev(ndev); 899 900 return ret; 901 } 902 903 static int emac_remove(struct platform_device *pdev) 904 { 905 struct net_device *ndev = platform_get_drvdata(pdev); 906 struct emac_board_info *db = netdev_priv(ndev); 907 908 unregister_netdev(ndev); 909 sunxi_sram_release(&pdev->dev); 910 clk_disable_unprepare(db->clk); 911 iounmap(db->membase); 912 free_netdev(ndev); 913 914 dev_dbg(&pdev->dev, "released and freed device\n"); 915 return 0; 916 } 917 918 static int emac_suspend(struct platform_device *dev, pm_message_t state) 919 { 920 struct net_device *ndev = platform_get_drvdata(dev); 921 922 netif_carrier_off(ndev); 923 netif_device_detach(ndev); 924 emac_shutdown(ndev); 925 926 return 0; 927 } 928 929 static int emac_resume(struct platform_device *dev) 930 { 931 struct net_device *ndev = platform_get_drvdata(dev); 932 struct emac_board_info *db = netdev_priv(ndev); 933 934 emac_reset(db); 935 emac_init_device(ndev); 936 netif_device_attach(ndev); 937 938 return 0; 939 } 940 941 static const struct of_device_id emac_of_match[] = { 942 {.compatible = "allwinner,sun4i-a10-emac",}, 943 944 /* Deprecated */ 945 {.compatible = "allwinner,sun4i-emac",}, 946 {}, 947 }; 948 949 MODULE_DEVICE_TABLE(of, emac_of_match); 950 951 static struct platform_driver emac_driver = { 952 .driver = { 953 .name = "sun4i-emac", 954 .of_match_table = emac_of_match, 955 }, 956 .probe = emac_probe, 957 .remove = emac_remove, 958 .suspend = emac_suspend, 959 .resume = emac_resume, 960 }; 961 962 module_platform_driver(emac_driver); 963 964 MODULE_AUTHOR("Stefan Roese <sr@denx.de>"); 965 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 966 MODULE_DESCRIPTION("Allwinner A10 emac network driver"); 967 MODULE_LICENSE("GPL"); 968