1 /* 2 * Allwinner EMAC Fast Ethernet driver for Linux. 3 * 4 * Copyright 2012-2013 Stefan Roese <sr@denx.de> 5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> 6 * 7 * Based on the Linux driver provided by Allwinner: 8 * Copyright (C) 1997 Sten Wang 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/gpio.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/irq.h> 22 #include <linux/mii.h> 23 #include <linux/module.h> 24 #include <linux/netdevice.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/of_net.h> 29 #include <linux/of_platform.h> 30 #include <linux/platform_device.h> 31 #include <linux/phy.h> 32 33 #include "sun4i-emac.h" 34 35 #define DRV_NAME "sun4i-emac" 36 #define DRV_VERSION "1.02" 37 38 #define EMAC_MAX_FRAME_LEN 0x0600 39 40 /* Transmit timeout, default 5 seconds. */ 41 static int watchdog = 5000; 42 module_param(watchdog, int, 0400); 43 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 44 45 /* EMAC register address locking. 46 * 47 * The EMAC uses an address register to control where data written 48 * to the data register goes. This means that the address register 49 * must be preserved over interrupts or similar calls. 50 * 51 * During interrupt and other critical calls, a spinlock is used to 52 * protect the system, but the calls themselves save the address 53 * in the address register in case they are interrupting another 54 * access to the device. 55 * 56 * For general accesses a lock is provided so that calls which are 57 * allowed to sleep are serialised so that the address register does 58 * not need to be saved. This lock also serves to serialise access 59 * to the EEPROM and PHY access registers which are shared between 60 * these two devices. 61 */ 62 63 /* The driver supports the original EMACE, and now the two newer 64 * devices, EMACA and EMACB. 65 */ 66 67 struct emac_board_info { 68 struct clk *clk; 69 struct device *dev; 70 struct platform_device *pdev; 71 spinlock_t lock; 72 void __iomem *membase; 73 u32 msg_enable; 74 struct net_device *ndev; 75 struct sk_buff *skb_last; 76 u16 tx_fifo_stat; 77 78 int emacrx_completed_flag; 79 80 struct phy_device *phy_dev; 81 struct device_node *phy_node; 82 unsigned int link; 83 unsigned int speed; 84 unsigned int duplex; 85 86 phy_interface_t phy_interface; 87 }; 88 89 static void emac_update_speed(struct net_device *dev) 90 { 91 struct emac_board_info *db = netdev_priv(dev); 92 unsigned int reg_val; 93 94 /* set EMAC SPEED, depend on PHY */ 95 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); 96 reg_val &= ~(0x1 << 8); 97 if (db->speed == SPEED_100) 98 reg_val |= 1 << 8; 99 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); 100 } 101 102 static void emac_update_duplex(struct net_device *dev) 103 { 104 struct emac_board_info *db = netdev_priv(dev); 105 unsigned int reg_val; 106 107 /* set duplex depend on phy */ 108 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); 109 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; 110 if (db->duplex) 111 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; 112 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); 113 } 114 115 static void emac_handle_link_change(struct net_device *dev) 116 { 117 struct emac_board_info *db = netdev_priv(dev); 118 struct phy_device *phydev = db->phy_dev; 119 unsigned long flags; 120 int status_change = 0; 121 122 if (phydev->link) { 123 if (db->speed != phydev->speed) { 124 spin_lock_irqsave(&db->lock, flags); 125 db->speed = phydev->speed; 126 emac_update_speed(dev); 127 spin_unlock_irqrestore(&db->lock, flags); 128 status_change = 1; 129 } 130 131 if (db->duplex != phydev->duplex) { 132 spin_lock_irqsave(&db->lock, flags); 133 db->duplex = phydev->duplex; 134 emac_update_duplex(dev); 135 spin_unlock_irqrestore(&db->lock, flags); 136 status_change = 1; 137 } 138 } 139 140 if (phydev->link != db->link) { 141 if (!phydev->link) { 142 db->speed = 0; 143 db->duplex = -1; 144 } 145 db->link = phydev->link; 146 147 status_change = 1; 148 } 149 150 if (status_change) 151 phy_print_status(phydev); 152 } 153 154 static int emac_mdio_probe(struct net_device *dev) 155 { 156 struct emac_board_info *db = netdev_priv(dev); 157 158 /* to-do: PHY interrupts are currently not supported */ 159 160 /* attach the mac to the phy */ 161 db->phy_dev = of_phy_connect(db->ndev, db->phy_node, 162 &emac_handle_link_change, 0, 163 db->phy_interface); 164 if (!db->phy_dev) { 165 netdev_err(db->ndev, "could not find the PHY\n"); 166 return -ENODEV; 167 } 168 169 /* mask with MAC supported features */ 170 db->phy_dev->supported &= PHY_BASIC_FEATURES; 171 db->phy_dev->advertising = db->phy_dev->supported; 172 173 db->link = 0; 174 db->speed = 0; 175 db->duplex = -1; 176 177 return 0; 178 } 179 180 static void emac_mdio_remove(struct net_device *dev) 181 { 182 struct emac_board_info *db = netdev_priv(dev); 183 184 phy_disconnect(db->phy_dev); 185 db->phy_dev = NULL; 186 } 187 188 static void emac_reset(struct emac_board_info *db) 189 { 190 dev_dbg(db->dev, "resetting device\n"); 191 192 /* RESET device */ 193 writel(0, db->membase + EMAC_CTL_REG); 194 udelay(200); 195 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); 196 udelay(200); 197 } 198 199 static void emac_outblk_32bit(void __iomem *reg, void *data, int count) 200 { 201 writesl(reg, data, round_up(count, 4) / 4); 202 } 203 204 static void emac_inblk_32bit(void __iomem *reg, void *data, int count) 205 { 206 readsl(reg, data, round_up(count, 4) / 4); 207 } 208 209 static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 210 { 211 struct emac_board_info *dm = netdev_priv(dev); 212 struct phy_device *phydev = dm->phy_dev; 213 214 if (!netif_running(dev)) 215 return -EINVAL; 216 217 if (!phydev) 218 return -ENODEV; 219 220 return phy_mii_ioctl(phydev, rq, cmd); 221 } 222 223 /* ethtool ops */ 224 static void emac_get_drvinfo(struct net_device *dev, 225 struct ethtool_drvinfo *info) 226 { 227 strlcpy(info->driver, DRV_NAME, sizeof(DRV_NAME)); 228 strlcpy(info->version, DRV_VERSION, sizeof(DRV_VERSION)); 229 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info)); 230 } 231 232 static int emac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 233 { 234 struct emac_board_info *dm = netdev_priv(dev); 235 struct phy_device *phydev = dm->phy_dev; 236 237 if (!phydev) 238 return -ENODEV; 239 240 return phy_ethtool_gset(phydev, cmd); 241 } 242 243 static int emac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 244 { 245 struct emac_board_info *dm = netdev_priv(dev); 246 struct phy_device *phydev = dm->phy_dev; 247 248 if (!phydev) 249 return -ENODEV; 250 251 return phy_ethtool_sset(phydev, cmd); 252 } 253 254 static const struct ethtool_ops emac_ethtool_ops = { 255 .get_drvinfo = emac_get_drvinfo, 256 .get_settings = emac_get_settings, 257 .set_settings = emac_set_settings, 258 .get_link = ethtool_op_get_link, 259 }; 260 261 static unsigned int emac_setup(struct net_device *ndev) 262 { 263 struct emac_board_info *db = netdev_priv(ndev); 264 unsigned int reg_val; 265 266 /* set up TX */ 267 reg_val = readl(db->membase + EMAC_TX_MODE_REG); 268 269 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN, 270 db->membase + EMAC_TX_MODE_REG); 271 272 /* set up RX */ 273 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 274 275 writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN | 276 EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN | 277 EMAC_RX_CTL_ACCEPT_MULTICAST_EN | 278 EMAC_RX_CTL_ACCEPT_BROADCAST_EN, 279 db->membase + EMAC_RX_CTL_REG); 280 281 /* set MAC */ 282 /* set MAC CTL0 */ 283 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); 284 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN | 285 EMAC_MAC_CTL0_TX_FLOW_CTL_EN, 286 db->membase + EMAC_MAC_CTL0_REG); 287 288 /* set MAC CTL1 */ 289 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); 290 reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN; 291 reg_val |= EMAC_MAC_CTL1_CRC_EN; 292 reg_val |= EMAC_MAC_CTL1_PAD_EN; 293 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); 294 295 /* set up IPGT */ 296 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG); 297 298 /* set up IPGR */ 299 writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2, 300 db->membase + EMAC_MAC_IPGR_REG); 301 302 /* set up Collison window */ 303 writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM, 304 db->membase + EMAC_MAC_CLRT_REG); 305 306 /* set up Max Frame Length */ 307 writel(EMAC_MAX_FRAME_LEN, 308 db->membase + EMAC_MAC_MAXF_REG); 309 310 return 0; 311 } 312 313 static unsigned int emac_powerup(struct net_device *ndev) 314 { 315 struct emac_board_info *db = netdev_priv(ndev); 316 unsigned int reg_val; 317 318 /* initial EMAC */ 319 /* flush RX FIFO */ 320 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 321 reg_val |= 0x8; 322 writel(reg_val, db->membase + EMAC_RX_CTL_REG); 323 udelay(1); 324 325 /* initial MAC */ 326 /* soft reset MAC */ 327 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); 328 reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET; 329 writel(reg_val, db->membase + EMAC_MAC_CTL0_REG); 330 331 /* set MII clock */ 332 reg_val = readl(db->membase + EMAC_MAC_MCFG_REG); 333 reg_val &= (~(0xf << 2)); 334 reg_val |= (0xD << 2); 335 writel(reg_val, db->membase + EMAC_MAC_MCFG_REG); 336 337 /* clear RX counter */ 338 writel(0x0, db->membase + EMAC_RX_FBC_REG); 339 340 /* disable all interrupt and clear interrupt status */ 341 writel(0, db->membase + EMAC_INT_CTL_REG); 342 reg_val = readl(db->membase + EMAC_INT_STA_REG); 343 writel(reg_val, db->membase + EMAC_INT_STA_REG); 344 345 udelay(1); 346 347 /* set up EMAC */ 348 emac_setup(ndev); 349 350 /* set mac_address to chip */ 351 writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev-> 352 dev_addr[2], db->membase + EMAC_MAC_A1_REG); 353 writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev-> 354 dev_addr[5], db->membase + EMAC_MAC_A0_REG); 355 356 mdelay(1); 357 358 return 0; 359 } 360 361 static int emac_set_mac_address(struct net_device *dev, void *p) 362 { 363 struct sockaddr *addr = p; 364 struct emac_board_info *db = netdev_priv(dev); 365 366 if (netif_running(dev)) 367 return -EBUSY; 368 369 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 370 371 writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev-> 372 dev_addr[2], db->membase + EMAC_MAC_A1_REG); 373 writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev-> 374 dev_addr[5], db->membase + EMAC_MAC_A0_REG); 375 376 return 0; 377 } 378 379 /* Initialize emac board */ 380 static void emac_init_device(struct net_device *dev) 381 { 382 struct emac_board_info *db = netdev_priv(dev); 383 unsigned long flags; 384 unsigned int reg_val; 385 386 spin_lock_irqsave(&db->lock, flags); 387 388 emac_update_speed(dev); 389 emac_update_duplex(dev); 390 391 /* enable RX/TX */ 392 reg_val = readl(db->membase + EMAC_CTL_REG); 393 writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN, 394 db->membase + EMAC_CTL_REG); 395 396 /* enable RX/TX0/RX Hlevel interrup */ 397 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 398 reg_val |= (0xf << 0) | (0x01 << 8); 399 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 400 401 spin_unlock_irqrestore(&db->lock, flags); 402 } 403 404 /* Our watchdog timed out. Called by the networking layer */ 405 static void emac_timeout(struct net_device *dev) 406 { 407 struct emac_board_info *db = netdev_priv(dev); 408 unsigned long flags; 409 410 if (netif_msg_timer(db)) 411 dev_err(db->dev, "tx time out.\n"); 412 413 /* Save previous register address */ 414 spin_lock_irqsave(&db->lock, flags); 415 416 netif_stop_queue(dev); 417 emac_reset(db); 418 emac_init_device(dev); 419 /* We can accept TX packets again */ 420 dev->trans_start = jiffies; 421 netif_wake_queue(dev); 422 423 /* Restore previous register address */ 424 spin_unlock_irqrestore(&db->lock, flags); 425 } 426 427 /* Hardware start transmission. 428 * Send a packet to media from the upper layer. 429 */ 430 static int emac_start_xmit(struct sk_buff *skb, struct net_device *dev) 431 { 432 struct emac_board_info *db = netdev_priv(dev); 433 unsigned long channel; 434 unsigned long flags; 435 436 channel = db->tx_fifo_stat & 3; 437 if (channel == 3) 438 return 1; 439 440 channel = (channel == 1 ? 1 : 0); 441 442 spin_lock_irqsave(&db->lock, flags); 443 444 writel(channel, db->membase + EMAC_TX_INS_REG); 445 446 emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG, 447 skb->data, skb->len); 448 dev->stats.tx_bytes += skb->len; 449 450 db->tx_fifo_stat |= 1 << channel; 451 /* TX control: First packet immediately send, second packet queue */ 452 if (channel == 0) { 453 /* set TX len */ 454 writel(skb->len, db->membase + EMAC_TX_PL0_REG); 455 /* start translate from fifo to phy */ 456 writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1, 457 db->membase + EMAC_TX_CTL0_REG); 458 459 /* save the time stamp */ 460 dev->trans_start = jiffies; 461 } else if (channel == 1) { 462 /* set TX len */ 463 writel(skb->len, db->membase + EMAC_TX_PL1_REG); 464 /* start translate from fifo to phy */ 465 writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1, 466 db->membase + EMAC_TX_CTL1_REG); 467 468 /* save the time stamp */ 469 dev->trans_start = jiffies; 470 } 471 472 if ((db->tx_fifo_stat & 3) == 3) { 473 /* Second packet */ 474 netif_stop_queue(dev); 475 } 476 477 spin_unlock_irqrestore(&db->lock, flags); 478 479 /* free this SKB */ 480 dev_kfree_skb(skb); 481 482 return NETDEV_TX_OK; 483 } 484 485 /* EMAC interrupt handler 486 * receive the packet to upper layer, free the transmitted packet 487 */ 488 static void emac_tx_done(struct net_device *dev, struct emac_board_info *db, 489 unsigned int tx_status) 490 { 491 /* One packet sent complete */ 492 db->tx_fifo_stat &= ~(tx_status & 3); 493 if (3 == (tx_status & 3)) 494 dev->stats.tx_packets += 2; 495 else 496 dev->stats.tx_packets++; 497 498 if (netif_msg_tx_done(db)) 499 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); 500 501 netif_wake_queue(dev); 502 } 503 504 /* Received a packet and pass to upper layer 505 */ 506 static void emac_rx(struct net_device *dev) 507 { 508 struct emac_board_info *db = netdev_priv(dev); 509 struct sk_buff *skb; 510 u8 *rdptr; 511 bool good_packet; 512 static int rxlen_last; 513 unsigned int reg_val; 514 u32 rxhdr, rxstatus, rxcount, rxlen; 515 516 /* Check packet ready or not */ 517 while (1) { 518 /* race warning: the first packet might arrive with 519 * the interrupts disabled, but the second will fix 520 * it 521 */ 522 rxcount = readl(db->membase + EMAC_RX_FBC_REG); 523 524 if (netif_msg_rx_status(db)) 525 dev_dbg(db->dev, "RXCount: %x\n", rxcount); 526 527 if ((db->skb_last != NULL) && (rxlen_last > 0)) { 528 dev->stats.rx_bytes += rxlen_last; 529 530 /* Pass to upper layer */ 531 db->skb_last->protocol = eth_type_trans(db->skb_last, 532 dev); 533 netif_rx(db->skb_last); 534 dev->stats.rx_packets++; 535 db->skb_last = NULL; 536 rxlen_last = 0; 537 538 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 539 reg_val &= ~EMAC_RX_CTL_DMA_EN; 540 writel(reg_val, db->membase + EMAC_RX_CTL_REG); 541 } 542 543 if (!rxcount) { 544 db->emacrx_completed_flag = 1; 545 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 546 reg_val |= (0xf << 0) | (0x01 << 8); 547 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 548 549 /* had one stuck? */ 550 rxcount = readl(db->membase + EMAC_RX_FBC_REG); 551 if (!rxcount) 552 return; 553 } 554 555 reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG); 556 if (netif_msg_rx_status(db)) 557 dev_dbg(db->dev, "receive header: %x\n", reg_val); 558 if (reg_val != EMAC_UNDOCUMENTED_MAGIC) { 559 /* disable RX */ 560 reg_val = readl(db->membase + EMAC_CTL_REG); 561 writel(reg_val & ~EMAC_CTL_RX_EN, 562 db->membase + EMAC_CTL_REG); 563 564 /* Flush RX FIFO */ 565 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 566 writel(reg_val | (1 << 3), 567 db->membase + EMAC_RX_CTL_REG); 568 569 do { 570 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 571 } while (reg_val & (1 << 3)); 572 573 /* enable RX */ 574 reg_val = readl(db->membase + EMAC_CTL_REG); 575 writel(reg_val | EMAC_CTL_RX_EN, 576 db->membase + EMAC_CTL_REG); 577 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 578 reg_val |= (0xf << 0) | (0x01 << 8); 579 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 580 581 db->emacrx_completed_flag = 1; 582 583 return; 584 } 585 586 /* A packet ready now & Get status/length */ 587 good_packet = true; 588 589 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG, 590 &rxhdr, sizeof(rxhdr)); 591 592 if (netif_msg_rx_status(db)) 593 dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr))); 594 595 rxlen = EMAC_RX_IO_DATA_LEN(rxhdr); 596 rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr); 597 598 if (netif_msg_rx_status(db)) 599 dev_dbg(db->dev, "RX: status %02x, length %04x\n", 600 rxstatus, rxlen); 601 602 /* Packet Status check */ 603 if (rxlen < 0x40) { 604 good_packet = false; 605 if (netif_msg_rx_err(db)) 606 dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); 607 } 608 609 if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) { 610 good_packet = false; 611 612 if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) { 613 if (netif_msg_rx_err(db)) 614 dev_dbg(db->dev, "crc error\n"); 615 dev->stats.rx_crc_errors++; 616 } 617 618 if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) { 619 if (netif_msg_rx_err(db)) 620 dev_dbg(db->dev, "length error\n"); 621 dev->stats.rx_length_errors++; 622 } 623 } 624 625 /* Move data from EMAC */ 626 skb = dev_alloc_skb(rxlen + 4); 627 if (good_packet && skb) { 628 skb_reserve(skb, 2); 629 rdptr = (u8 *) skb_put(skb, rxlen - 4); 630 631 /* Read received packet from RX SRAM */ 632 if (netif_msg_rx_status(db)) 633 dev_dbg(db->dev, "RxLen %x\n", rxlen); 634 635 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG, 636 rdptr, rxlen); 637 dev->stats.rx_bytes += rxlen; 638 639 /* Pass to upper layer */ 640 skb->protocol = eth_type_trans(skb, dev); 641 netif_rx(skb); 642 dev->stats.rx_packets++; 643 } 644 } 645 } 646 647 static irqreturn_t emac_interrupt(int irq, void *dev_id) 648 { 649 struct net_device *dev = dev_id; 650 struct emac_board_info *db = netdev_priv(dev); 651 int int_status; 652 unsigned long flags; 653 unsigned int reg_val; 654 655 /* A real interrupt coming */ 656 657 /* holders of db->lock must always block IRQs */ 658 spin_lock_irqsave(&db->lock, flags); 659 660 /* Disable all interrupts */ 661 writel(0, db->membase + EMAC_INT_CTL_REG); 662 663 /* Got EMAC interrupt status */ 664 /* Got ISR */ 665 int_status = readl(db->membase + EMAC_INT_STA_REG); 666 /* Clear ISR status */ 667 writel(int_status, db->membase + EMAC_INT_STA_REG); 668 669 if (netif_msg_intr(db)) 670 dev_dbg(db->dev, "emac interrupt %02x\n", int_status); 671 672 /* Received the coming packet */ 673 if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) { 674 /* carrier lost */ 675 db->emacrx_completed_flag = 0; 676 emac_rx(dev); 677 } 678 679 /* Transmit Interrupt check */ 680 if (int_status & (0x01 | 0x02)) 681 emac_tx_done(dev, db, int_status); 682 683 if (int_status & (0x04 | 0x08)) 684 netdev_info(dev, " ab : %x\n", int_status); 685 686 /* Re-enable interrupt mask */ 687 if (db->emacrx_completed_flag == 1) { 688 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 689 reg_val |= (0xf << 0) | (0x01 << 8); 690 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 691 } 692 spin_unlock_irqrestore(&db->lock, flags); 693 694 return IRQ_HANDLED; 695 } 696 697 #ifdef CONFIG_NET_POLL_CONTROLLER 698 /* 699 * Used by netconsole 700 */ 701 static void emac_poll_controller(struct net_device *dev) 702 { 703 disable_irq(dev->irq); 704 emac_interrupt(dev->irq, dev); 705 enable_irq(dev->irq); 706 } 707 #endif 708 709 /* Open the interface. 710 * The interface is opened whenever "ifconfig" actives it. 711 */ 712 static int emac_open(struct net_device *dev) 713 { 714 struct emac_board_info *db = netdev_priv(dev); 715 int ret; 716 717 if (netif_msg_ifup(db)) 718 dev_dbg(db->dev, "enabling %s\n", dev->name); 719 720 if (request_irq(dev->irq, &emac_interrupt, 0, dev->name, dev)) 721 return -EAGAIN; 722 723 /* Initialize EMAC board */ 724 emac_reset(db); 725 emac_init_device(dev); 726 727 ret = emac_mdio_probe(dev); 728 if (ret < 0) { 729 netdev_err(dev, "cannot probe MDIO bus\n"); 730 return ret; 731 } 732 733 phy_start(db->phy_dev); 734 netif_start_queue(dev); 735 736 return 0; 737 } 738 739 static void emac_shutdown(struct net_device *dev) 740 { 741 unsigned int reg_val; 742 struct emac_board_info *db = netdev_priv(dev); 743 744 /* Disable all interrupt */ 745 writel(0, db->membase + EMAC_INT_CTL_REG); 746 747 /* clear interupt status */ 748 reg_val = readl(db->membase + EMAC_INT_STA_REG); 749 writel(reg_val, db->membase + EMAC_INT_STA_REG); 750 751 /* Disable RX/TX */ 752 reg_val = readl(db->membase + EMAC_CTL_REG); 753 reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET); 754 writel(reg_val, db->membase + EMAC_CTL_REG); 755 } 756 757 /* Stop the interface. 758 * The interface is stopped when it is brought. 759 */ 760 static int emac_stop(struct net_device *ndev) 761 { 762 struct emac_board_info *db = netdev_priv(ndev); 763 764 if (netif_msg_ifdown(db)) 765 dev_dbg(db->dev, "shutting down %s\n", ndev->name); 766 767 netif_stop_queue(ndev); 768 netif_carrier_off(ndev); 769 770 phy_stop(db->phy_dev); 771 772 emac_mdio_remove(ndev); 773 774 emac_shutdown(ndev); 775 776 free_irq(ndev->irq, ndev); 777 778 return 0; 779 } 780 781 static const struct net_device_ops emac_netdev_ops = { 782 .ndo_open = emac_open, 783 .ndo_stop = emac_stop, 784 .ndo_start_xmit = emac_start_xmit, 785 .ndo_tx_timeout = emac_timeout, 786 .ndo_do_ioctl = emac_ioctl, 787 .ndo_change_mtu = eth_change_mtu, 788 .ndo_validate_addr = eth_validate_addr, 789 .ndo_set_mac_address = emac_set_mac_address, 790 #ifdef CONFIG_NET_POLL_CONTROLLER 791 .ndo_poll_controller = emac_poll_controller, 792 #endif 793 }; 794 795 /* Search EMAC board, allocate space and register it 796 */ 797 static int emac_probe(struct platform_device *pdev) 798 { 799 struct device_node *np = pdev->dev.of_node; 800 struct emac_board_info *db; 801 struct net_device *ndev; 802 int ret = 0; 803 const char *mac_addr; 804 805 ndev = alloc_etherdev(sizeof(struct emac_board_info)); 806 if (!ndev) { 807 dev_err(&pdev->dev, "could not allocate device.\n"); 808 return -ENOMEM; 809 } 810 811 SET_NETDEV_DEV(ndev, &pdev->dev); 812 813 db = netdev_priv(ndev); 814 memset(db, 0, sizeof(*db)); 815 816 db->dev = &pdev->dev; 817 db->ndev = ndev; 818 db->pdev = pdev; 819 820 spin_lock_init(&db->lock); 821 822 db->membase = of_iomap(np, 0); 823 if (!db->membase) { 824 dev_err(&pdev->dev, "failed to remap registers\n"); 825 ret = -ENOMEM; 826 goto out; 827 } 828 829 /* fill in parameters for net-dev structure */ 830 ndev->base_addr = (unsigned long)db->membase; 831 ndev->irq = irq_of_parse_and_map(np, 0); 832 if (ndev->irq == -ENXIO) { 833 netdev_err(ndev, "No irq resource\n"); 834 ret = ndev->irq; 835 goto out; 836 } 837 838 db->clk = devm_clk_get(&pdev->dev, NULL); 839 if (IS_ERR(db->clk)) 840 goto out; 841 842 clk_prepare_enable(db->clk); 843 844 db->phy_node = of_parse_phandle(np, "phy", 0); 845 if (!db->phy_node) { 846 dev_err(&pdev->dev, "no associated PHY\n"); 847 ret = -ENODEV; 848 goto out; 849 } 850 851 /* Read MAC-address from DT */ 852 mac_addr = of_get_mac_address(np); 853 if (mac_addr) 854 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN); 855 856 /* Check if the MAC address is valid, if not get a random one */ 857 if (!is_valid_ether_addr(ndev->dev_addr)) { 858 eth_hw_addr_random(ndev); 859 dev_warn(&pdev->dev, "using random MAC address %pM\n", 860 ndev->dev_addr); 861 } 862 863 db->emacrx_completed_flag = 1; 864 emac_powerup(ndev); 865 emac_reset(db); 866 867 ether_setup(ndev); 868 869 ndev->netdev_ops = &emac_netdev_ops; 870 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 871 ndev->ethtool_ops = &emac_ethtool_ops; 872 873 platform_set_drvdata(pdev, ndev); 874 875 /* Carrier starts down, phylib will bring it up */ 876 netif_carrier_off(ndev); 877 878 ret = register_netdev(ndev); 879 if (ret) { 880 dev_err(&pdev->dev, "Registering netdev failed!\n"); 881 ret = -ENODEV; 882 goto out; 883 } 884 885 dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n", 886 ndev->name, db->membase, ndev->irq, ndev->dev_addr); 887 888 return 0; 889 890 out: 891 dev_err(db->dev, "not found (%d).\n", ret); 892 893 free_netdev(ndev); 894 895 return ret; 896 } 897 898 static int emac_remove(struct platform_device *pdev) 899 { 900 struct net_device *ndev = platform_get_drvdata(pdev); 901 902 unregister_netdev(ndev); 903 free_netdev(ndev); 904 905 dev_dbg(&pdev->dev, "released and freed device\n"); 906 return 0; 907 } 908 909 static int emac_suspend(struct platform_device *dev, pm_message_t state) 910 { 911 struct net_device *ndev = platform_get_drvdata(dev); 912 913 netif_carrier_off(ndev); 914 netif_device_detach(ndev); 915 emac_shutdown(ndev); 916 917 return 0; 918 } 919 920 static int emac_resume(struct platform_device *dev) 921 { 922 struct net_device *ndev = platform_get_drvdata(dev); 923 struct emac_board_info *db = netdev_priv(ndev); 924 925 emac_reset(db); 926 emac_init_device(ndev); 927 netif_device_attach(ndev); 928 929 return 0; 930 } 931 932 static const struct of_device_id emac_of_match[] = { 933 {.compatible = "allwinner,sun4i-emac",}, 934 {}, 935 }; 936 937 MODULE_DEVICE_TABLE(of, emac_of_match); 938 939 static struct platform_driver emac_driver = { 940 .driver = { 941 .name = "sun4i-emac", 942 .of_match_table = emac_of_match, 943 }, 944 .probe = emac_probe, 945 .remove = emac_remove, 946 .suspend = emac_suspend, 947 .resume = emac_resume, 948 }; 949 950 module_platform_driver(emac_driver); 951 952 MODULE_AUTHOR("Stefan Roese <sr@denx.de>"); 953 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 954 MODULE_DESCRIPTION("Allwinner A10 emac network driver"); 955 MODULE_LICENSE("GPL"); 956