1 /* 2 * Allwinner EMAC Fast Ethernet driver for Linux. 3 * 4 * Copyright 2012-2013 Stefan Roese <sr@denx.de> 5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com> 6 * 7 * Based on the Linux driver provided by Allwinner: 8 * Copyright (C) 1997 Sten Wang 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/gpio.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/mii.h> 22 #include <linux/module.h> 23 #include <linux/netdevice.h> 24 #include <linux/of_address.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/of_net.h> 28 #include <linux/of_platform.h> 29 #include <linux/platform_device.h> 30 #include <linux/phy.h> 31 #include <linux/soc/sunxi/sunxi_sram.h> 32 #include <linux/dmaengine.h> 33 34 #include "sun4i-emac.h" 35 36 #define DRV_NAME "sun4i-emac" 37 38 #define EMAC_MAX_FRAME_LEN 0x0600 39 40 #define EMAC_DEFAULT_MSG_ENABLE 0x0000 41 static int debug = -1; /* defaults above */; 42 module_param(debug, int, 0); 43 MODULE_PARM_DESC(debug, "debug message flags"); 44 45 /* Transmit timeout, default 5 seconds. */ 46 static int watchdog = 5000; 47 module_param(watchdog, int, 0400); 48 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds"); 49 50 /* EMAC register address locking. 51 * 52 * The EMAC uses an address register to control where data written 53 * to the data register goes. This means that the address register 54 * must be preserved over interrupts or similar calls. 55 * 56 * During interrupt and other critical calls, a spinlock is used to 57 * protect the system, but the calls themselves save the address 58 * in the address register in case they are interrupting another 59 * access to the device. 60 * 61 * For general accesses a lock is provided so that calls which are 62 * allowed to sleep are serialised so that the address register does 63 * not need to be saved. This lock also serves to serialise access 64 * to the EEPROM and PHY access registers which are shared between 65 * these two devices. 66 */ 67 68 /* The driver supports the original EMACE, and now the two newer 69 * devices, EMACA and EMACB. 70 */ 71 72 struct emac_board_info { 73 struct clk *clk; 74 struct device *dev; 75 struct platform_device *pdev; 76 spinlock_t lock; 77 void __iomem *membase; 78 u32 msg_enable; 79 struct net_device *ndev; 80 u16 tx_fifo_stat; 81 82 int emacrx_completed_flag; 83 84 struct device_node *phy_node; 85 unsigned int link; 86 unsigned int speed; 87 unsigned int duplex; 88 89 phy_interface_t phy_interface; 90 struct dma_chan *rx_chan; 91 phys_addr_t emac_rx_fifo; 92 }; 93 94 struct emac_dma_req { 95 struct emac_board_info *db; 96 struct dma_async_tx_descriptor *desc; 97 struct sk_buff *skb; 98 dma_addr_t rxbuf; 99 int count; 100 }; 101 102 static void emac_update_speed(struct net_device *dev) 103 { 104 struct emac_board_info *db = netdev_priv(dev); 105 unsigned int reg_val; 106 107 /* set EMAC SPEED, depend on PHY */ 108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); 109 reg_val &= ~(0x1 << 8); 110 if (db->speed == SPEED_100) 111 reg_val |= 1 << 8; 112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); 113 } 114 115 static void emac_update_duplex(struct net_device *dev) 116 { 117 struct emac_board_info *db = netdev_priv(dev); 118 unsigned int reg_val; 119 120 /* set duplex depend on phy */ 121 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); 122 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; 123 if (db->duplex) 124 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; 125 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); 126 } 127 128 static void emac_handle_link_change(struct net_device *dev) 129 { 130 struct emac_board_info *db = netdev_priv(dev); 131 struct phy_device *phydev = dev->phydev; 132 unsigned long flags; 133 int status_change = 0; 134 135 if (phydev->link) { 136 if (db->speed != phydev->speed) { 137 spin_lock_irqsave(&db->lock, flags); 138 db->speed = phydev->speed; 139 emac_update_speed(dev); 140 spin_unlock_irqrestore(&db->lock, flags); 141 status_change = 1; 142 } 143 144 if (db->duplex != phydev->duplex) { 145 spin_lock_irqsave(&db->lock, flags); 146 db->duplex = phydev->duplex; 147 emac_update_duplex(dev); 148 spin_unlock_irqrestore(&db->lock, flags); 149 status_change = 1; 150 } 151 } 152 153 if (phydev->link != db->link) { 154 if (!phydev->link) { 155 db->speed = 0; 156 db->duplex = -1; 157 } 158 db->link = phydev->link; 159 160 status_change = 1; 161 } 162 163 if (status_change) 164 phy_print_status(phydev); 165 } 166 167 static int emac_mdio_probe(struct net_device *dev) 168 { 169 struct emac_board_info *db = netdev_priv(dev); 170 struct phy_device *phydev; 171 172 /* to-do: PHY interrupts are currently not supported */ 173 174 /* attach the mac to the phy */ 175 phydev = of_phy_connect(db->ndev, db->phy_node, 176 &emac_handle_link_change, 0, 177 db->phy_interface); 178 if (!phydev) { 179 netdev_err(db->ndev, "could not find the PHY\n"); 180 return -ENODEV; 181 } 182 183 /* mask with MAC supported features */ 184 phy_set_max_speed(phydev, SPEED_100); 185 186 db->link = 0; 187 db->speed = 0; 188 db->duplex = -1; 189 190 return 0; 191 } 192 193 static void emac_mdio_remove(struct net_device *dev) 194 { 195 phy_disconnect(dev->phydev); 196 } 197 198 static void emac_reset(struct emac_board_info *db) 199 { 200 dev_dbg(db->dev, "resetting device\n"); 201 202 /* RESET device */ 203 writel(0, db->membase + EMAC_CTL_REG); 204 udelay(200); 205 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); 206 udelay(200); 207 } 208 209 static void emac_outblk_32bit(void __iomem *reg, void *data, int count) 210 { 211 writesl(reg, data, round_up(count, 4) / 4); 212 } 213 214 static void emac_inblk_32bit(void __iomem *reg, void *data, int count) 215 { 216 readsl(reg, data, round_up(count, 4) / 4); 217 } 218 219 static struct emac_dma_req * 220 emac_alloc_dma_req(struct emac_board_info *db, 221 struct dma_async_tx_descriptor *desc, struct sk_buff *skb, 222 dma_addr_t rxbuf, int count) 223 { 224 struct emac_dma_req *req; 225 226 req = kzalloc(sizeof(struct emac_dma_req), GFP_ATOMIC); 227 if (!req) 228 return NULL; 229 230 req->db = db; 231 req->desc = desc; 232 req->skb = skb; 233 req->rxbuf = rxbuf; 234 req->count = count; 235 return req; 236 } 237 238 static void emac_free_dma_req(struct emac_dma_req *req) 239 { 240 kfree(req); 241 } 242 243 static void emac_dma_done_callback(void *arg) 244 { 245 struct emac_dma_req *req = arg; 246 struct emac_board_info *db = req->db; 247 struct sk_buff *skb = req->skb; 248 struct net_device *dev = db->ndev; 249 int rxlen = req->count; 250 u32 reg_val; 251 252 dma_unmap_single(db->dev, req->rxbuf, rxlen, DMA_FROM_DEVICE); 253 254 skb->protocol = eth_type_trans(skb, dev); 255 netif_rx(skb); 256 dev->stats.rx_bytes += rxlen; 257 /* Pass to upper layer */ 258 dev->stats.rx_packets++; 259 260 /* re enable cpu receive */ 261 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 262 reg_val &= ~EMAC_RX_CTL_DMA_EN; 263 writel(reg_val, db->membase + EMAC_RX_CTL_REG); 264 265 /* re enable interrupt */ 266 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 267 reg_val |= (0x01 << 8); 268 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 269 270 db->emacrx_completed_flag = 1; 271 emac_free_dma_req(req); 272 } 273 274 static int emac_dma_inblk_32bit(struct emac_board_info *db, 275 struct sk_buff *skb, void *rdptr, int count) 276 { 277 struct dma_async_tx_descriptor *desc; 278 dma_cookie_t cookie; 279 dma_addr_t rxbuf; 280 struct emac_dma_req *req; 281 int ret = 0; 282 283 rxbuf = dma_map_single(db->dev, rdptr, count, DMA_FROM_DEVICE); 284 ret = dma_mapping_error(db->dev, rxbuf); 285 if (ret) { 286 dev_err(db->dev, "dma mapping error.\n"); 287 return ret; 288 } 289 290 desc = dmaengine_prep_slave_single(db->rx_chan, rxbuf, count, 291 DMA_DEV_TO_MEM, 292 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 293 if (!desc) { 294 dev_err(db->dev, "prepare slave single failed\n"); 295 ret = -ENOMEM; 296 goto prepare_err; 297 } 298 299 req = emac_alloc_dma_req(db, desc, skb, rxbuf, count); 300 if (!req) { 301 dev_err(db->dev, "alloc emac dma req error.\n"); 302 ret = -ENOMEM; 303 goto alloc_req_err; 304 } 305 306 desc->callback_param = req; 307 desc->callback = emac_dma_done_callback; 308 309 cookie = dmaengine_submit(desc); 310 ret = dma_submit_error(cookie); 311 if (ret) { 312 dev_err(db->dev, "dma submit error.\n"); 313 goto submit_err; 314 } 315 316 dma_async_issue_pending(db->rx_chan); 317 return ret; 318 319 submit_err: 320 emac_free_dma_req(req); 321 322 alloc_req_err: 323 dmaengine_desc_free(desc); 324 325 prepare_err: 326 dma_unmap_single(db->dev, rxbuf, count, DMA_FROM_DEVICE); 327 return ret; 328 } 329 330 /* ethtool ops */ 331 static void emac_get_drvinfo(struct net_device *dev, 332 struct ethtool_drvinfo *info) 333 { 334 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 335 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info)); 336 } 337 338 static u32 emac_get_msglevel(struct net_device *dev) 339 { 340 struct emac_board_info *db = netdev_priv(dev); 341 342 return db->msg_enable; 343 } 344 345 static void emac_set_msglevel(struct net_device *dev, u32 value) 346 { 347 struct emac_board_info *db = netdev_priv(dev); 348 349 db->msg_enable = value; 350 } 351 352 static const struct ethtool_ops emac_ethtool_ops = { 353 .get_drvinfo = emac_get_drvinfo, 354 .get_link = ethtool_op_get_link, 355 .get_link_ksettings = phy_ethtool_get_link_ksettings, 356 .set_link_ksettings = phy_ethtool_set_link_ksettings, 357 .get_msglevel = emac_get_msglevel, 358 .set_msglevel = emac_set_msglevel, 359 }; 360 361 static unsigned int emac_setup(struct net_device *ndev) 362 { 363 struct emac_board_info *db = netdev_priv(ndev); 364 unsigned int reg_val; 365 366 /* set up TX */ 367 reg_val = readl(db->membase + EMAC_TX_MODE_REG); 368 369 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN, 370 db->membase + EMAC_TX_MODE_REG); 371 372 /* set MAC */ 373 /* set MAC CTL0 */ 374 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); 375 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN | 376 EMAC_MAC_CTL0_TX_FLOW_CTL_EN, 377 db->membase + EMAC_MAC_CTL0_REG); 378 379 /* set MAC CTL1 */ 380 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); 381 reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN; 382 reg_val |= EMAC_MAC_CTL1_CRC_EN; 383 reg_val |= EMAC_MAC_CTL1_PAD_EN; 384 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); 385 386 /* set up IPGT */ 387 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG); 388 389 /* set up IPGR */ 390 writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2, 391 db->membase + EMAC_MAC_IPGR_REG); 392 393 /* set up Collison window */ 394 writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM, 395 db->membase + EMAC_MAC_CLRT_REG); 396 397 /* set up Max Frame Length */ 398 writel(EMAC_MAX_FRAME_LEN, 399 db->membase + EMAC_MAC_MAXF_REG); 400 401 return 0; 402 } 403 404 static void emac_set_rx_mode(struct net_device *ndev) 405 { 406 struct emac_board_info *db = netdev_priv(ndev); 407 unsigned int reg_val; 408 409 /* set up RX */ 410 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 411 412 if (ndev->flags & IFF_PROMISC) 413 reg_val |= EMAC_RX_CTL_PASS_ALL_EN; 414 else 415 reg_val &= ~EMAC_RX_CTL_PASS_ALL_EN; 416 417 writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN | 418 EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN | 419 EMAC_RX_CTL_ACCEPT_MULTICAST_EN | 420 EMAC_RX_CTL_ACCEPT_BROADCAST_EN, 421 db->membase + EMAC_RX_CTL_REG); 422 } 423 424 static unsigned int emac_powerup(struct net_device *ndev) 425 { 426 struct emac_board_info *db = netdev_priv(ndev); 427 unsigned int reg_val; 428 429 /* initial EMAC */ 430 /* flush RX FIFO */ 431 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 432 reg_val |= 0x8; 433 writel(reg_val, db->membase + EMAC_RX_CTL_REG); 434 udelay(1); 435 436 /* initial MAC */ 437 /* soft reset MAC */ 438 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); 439 reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET; 440 writel(reg_val, db->membase + EMAC_MAC_CTL0_REG); 441 442 /* set MII clock */ 443 reg_val = readl(db->membase + EMAC_MAC_MCFG_REG); 444 reg_val &= (~(0xf << 2)); 445 reg_val |= (0xD << 2); 446 writel(reg_val, db->membase + EMAC_MAC_MCFG_REG); 447 448 /* clear RX counter */ 449 writel(0x0, db->membase + EMAC_RX_FBC_REG); 450 451 /* disable all interrupt and clear interrupt status */ 452 writel(0, db->membase + EMAC_INT_CTL_REG); 453 reg_val = readl(db->membase + EMAC_INT_STA_REG); 454 writel(reg_val, db->membase + EMAC_INT_STA_REG); 455 456 udelay(1); 457 458 /* set up EMAC */ 459 emac_setup(ndev); 460 461 /* set mac_address to chip */ 462 writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev-> 463 dev_addr[2], db->membase + EMAC_MAC_A1_REG); 464 writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev-> 465 dev_addr[5], db->membase + EMAC_MAC_A0_REG); 466 467 mdelay(1); 468 469 return 0; 470 } 471 472 static int emac_set_mac_address(struct net_device *dev, void *p) 473 { 474 struct sockaddr *addr = p; 475 struct emac_board_info *db = netdev_priv(dev); 476 477 if (netif_running(dev)) 478 return -EBUSY; 479 480 eth_hw_addr_set(dev, addr->sa_data); 481 482 writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev-> 483 dev_addr[2], db->membase + EMAC_MAC_A1_REG); 484 writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev-> 485 dev_addr[5], db->membase + EMAC_MAC_A0_REG); 486 487 return 0; 488 } 489 490 /* Initialize emac board */ 491 static void emac_init_device(struct net_device *dev) 492 { 493 struct emac_board_info *db = netdev_priv(dev); 494 unsigned long flags; 495 unsigned int reg_val; 496 497 spin_lock_irqsave(&db->lock, flags); 498 499 emac_update_speed(dev); 500 emac_update_duplex(dev); 501 502 /* enable RX/TX */ 503 reg_val = readl(db->membase + EMAC_CTL_REG); 504 writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN, 505 db->membase + EMAC_CTL_REG); 506 507 /* enable RX/TX0/RX Hlevel interrup */ 508 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 509 reg_val |= (0xf << 0) | (0x01 << 8); 510 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 511 512 spin_unlock_irqrestore(&db->lock, flags); 513 } 514 515 /* Our watchdog timed out. Called by the networking layer */ 516 static void emac_timeout(struct net_device *dev, unsigned int txqueue) 517 { 518 struct emac_board_info *db = netdev_priv(dev); 519 unsigned long flags; 520 521 if (netif_msg_timer(db)) 522 dev_err(db->dev, "tx time out.\n"); 523 524 /* Save previous register address */ 525 spin_lock_irqsave(&db->lock, flags); 526 527 netif_stop_queue(dev); 528 emac_reset(db); 529 emac_init_device(dev); 530 /* We can accept TX packets again */ 531 netif_trans_update(dev); 532 netif_wake_queue(dev); 533 534 /* Restore previous register address */ 535 spin_unlock_irqrestore(&db->lock, flags); 536 } 537 538 /* Hardware start transmission. 539 * Send a packet to media from the upper layer. 540 */ 541 static netdev_tx_t emac_start_xmit(struct sk_buff *skb, struct net_device *dev) 542 { 543 struct emac_board_info *db = netdev_priv(dev); 544 unsigned long channel; 545 unsigned long flags; 546 547 channel = db->tx_fifo_stat & 3; 548 if (channel == 3) 549 return NETDEV_TX_BUSY; 550 551 channel = (channel == 1 ? 1 : 0); 552 553 spin_lock_irqsave(&db->lock, flags); 554 555 writel(channel, db->membase + EMAC_TX_INS_REG); 556 557 emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG, 558 skb->data, skb->len); 559 dev->stats.tx_bytes += skb->len; 560 561 db->tx_fifo_stat |= 1 << channel; 562 /* TX control: First packet immediately send, second packet queue */ 563 if (channel == 0) { 564 /* set TX len */ 565 writel(skb->len, db->membase + EMAC_TX_PL0_REG); 566 /* start translate from fifo to phy */ 567 writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1, 568 db->membase + EMAC_TX_CTL0_REG); 569 570 /* save the time stamp */ 571 netif_trans_update(dev); 572 } else if (channel == 1) { 573 /* set TX len */ 574 writel(skb->len, db->membase + EMAC_TX_PL1_REG); 575 /* start translate from fifo to phy */ 576 writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1, 577 db->membase + EMAC_TX_CTL1_REG); 578 579 /* save the time stamp */ 580 netif_trans_update(dev); 581 } 582 583 if ((db->tx_fifo_stat & 3) == 3) { 584 /* Second packet */ 585 netif_stop_queue(dev); 586 } 587 588 spin_unlock_irqrestore(&db->lock, flags); 589 590 /* free this SKB */ 591 dev_consume_skb_any(skb); 592 593 return NETDEV_TX_OK; 594 } 595 596 /* EMAC interrupt handler 597 * receive the packet to upper layer, free the transmitted packet 598 */ 599 static void emac_tx_done(struct net_device *dev, struct emac_board_info *db, 600 unsigned int tx_status) 601 { 602 /* One packet sent complete */ 603 db->tx_fifo_stat &= ~(tx_status & 3); 604 if (3 == (tx_status & 3)) 605 dev->stats.tx_packets += 2; 606 else 607 dev->stats.tx_packets++; 608 609 if (netif_msg_tx_done(db)) 610 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status); 611 612 netif_wake_queue(dev); 613 } 614 615 /* Received a packet and pass to upper layer 616 */ 617 static void emac_rx(struct net_device *dev) 618 { 619 struct emac_board_info *db = netdev_priv(dev); 620 struct sk_buff *skb; 621 u8 *rdptr; 622 bool good_packet; 623 unsigned int reg_val; 624 u32 rxhdr, rxstatus, rxcount, rxlen; 625 626 /* Check packet ready or not */ 627 while (1) { 628 /* race warning: the first packet might arrive with 629 * the interrupts disabled, but the second will fix 630 * it 631 */ 632 rxcount = readl(db->membase + EMAC_RX_FBC_REG); 633 634 if (netif_msg_rx_status(db)) 635 dev_dbg(db->dev, "RXCount: %x\n", rxcount); 636 637 if (!rxcount) { 638 db->emacrx_completed_flag = 1; 639 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 640 reg_val |= (0xf << 0) | (0x01 << 8); 641 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 642 643 /* had one stuck? */ 644 rxcount = readl(db->membase + EMAC_RX_FBC_REG); 645 if (!rxcount) 646 return; 647 } 648 649 reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG); 650 if (netif_msg_rx_status(db)) 651 dev_dbg(db->dev, "receive header: %x\n", reg_val); 652 if (reg_val != EMAC_UNDOCUMENTED_MAGIC) { 653 /* disable RX */ 654 reg_val = readl(db->membase + EMAC_CTL_REG); 655 writel(reg_val & ~EMAC_CTL_RX_EN, 656 db->membase + EMAC_CTL_REG); 657 658 /* Flush RX FIFO */ 659 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 660 writel(reg_val | (1 << 3), 661 db->membase + EMAC_RX_CTL_REG); 662 663 do { 664 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 665 } while (reg_val & (1 << 3)); 666 667 /* enable RX */ 668 reg_val = readl(db->membase + EMAC_CTL_REG); 669 writel(reg_val | EMAC_CTL_RX_EN, 670 db->membase + EMAC_CTL_REG); 671 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 672 reg_val |= (0xf << 0) | (0x01 << 8); 673 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 674 675 db->emacrx_completed_flag = 1; 676 677 return; 678 } 679 680 /* A packet ready now & Get status/length */ 681 good_packet = true; 682 683 rxhdr = readl(db->membase + EMAC_RX_IO_DATA_REG); 684 685 if (netif_msg_rx_status(db)) 686 dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr))); 687 688 rxlen = EMAC_RX_IO_DATA_LEN(rxhdr); 689 rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr); 690 691 if (netif_msg_rx_status(db)) 692 dev_dbg(db->dev, "RX: status %02x, length %04x\n", 693 rxstatus, rxlen); 694 695 /* Packet Status check */ 696 if (rxlen < 0x40) { 697 good_packet = false; 698 if (netif_msg_rx_err(db)) 699 dev_dbg(db->dev, "RX: Bad Packet (runt)\n"); 700 } 701 702 if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) { 703 good_packet = false; 704 705 if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) { 706 if (netif_msg_rx_err(db)) 707 dev_dbg(db->dev, "crc error\n"); 708 dev->stats.rx_crc_errors++; 709 } 710 711 if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) { 712 if (netif_msg_rx_err(db)) 713 dev_dbg(db->dev, "length error\n"); 714 dev->stats.rx_length_errors++; 715 } 716 } 717 718 /* Move data from EMAC */ 719 if (good_packet) { 720 skb = netdev_alloc_skb(dev, rxlen + 4); 721 if (!skb) 722 continue; 723 skb_reserve(skb, 2); 724 rdptr = skb_put(skb, rxlen - 4); 725 726 /* Read received packet from RX SRAM */ 727 if (netif_msg_rx_status(db)) 728 dev_dbg(db->dev, "RxLen %x\n", rxlen); 729 730 if (rxlen >= dev->mtu && db->rx_chan) { 731 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 732 reg_val |= EMAC_RX_CTL_DMA_EN; 733 writel(reg_val, db->membase + EMAC_RX_CTL_REG); 734 if (!emac_dma_inblk_32bit(db, skb, rdptr, rxlen)) 735 break; 736 737 /* re enable cpu receive. then try to receive by emac_inblk_32bit */ 738 reg_val = readl(db->membase + EMAC_RX_CTL_REG); 739 reg_val &= ~EMAC_RX_CTL_DMA_EN; 740 writel(reg_val, db->membase + EMAC_RX_CTL_REG); 741 } 742 743 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG, 744 rdptr, rxlen); 745 dev->stats.rx_bytes += rxlen; 746 747 /* Pass to upper layer */ 748 skb->protocol = eth_type_trans(skb, dev); 749 netif_rx(skb); 750 dev->stats.rx_packets++; 751 } 752 } 753 } 754 755 static irqreturn_t emac_interrupt(int irq, void *dev_id) 756 { 757 struct net_device *dev = dev_id; 758 struct emac_board_info *db = netdev_priv(dev); 759 int int_status; 760 unsigned int reg_val; 761 762 /* A real interrupt coming */ 763 764 spin_lock(&db->lock); 765 766 /* Disable all interrupts */ 767 writel(0, db->membase + EMAC_INT_CTL_REG); 768 769 /* Got EMAC interrupt status */ 770 /* Got ISR */ 771 int_status = readl(db->membase + EMAC_INT_STA_REG); 772 /* Clear ISR status */ 773 writel(int_status, db->membase + EMAC_INT_STA_REG); 774 775 if (netif_msg_intr(db)) 776 dev_dbg(db->dev, "emac interrupt %02x\n", int_status); 777 778 /* Received the coming packet */ 779 if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) { 780 /* carrier lost */ 781 db->emacrx_completed_flag = 0; 782 emac_rx(dev); 783 } 784 785 /* Transmit Interrupt check */ 786 if (int_status & (0x01 | 0x02)) 787 emac_tx_done(dev, db, int_status); 788 789 if (int_status & (0x04 | 0x08)) 790 netdev_info(dev, " ab : %x\n", int_status); 791 792 /* Re-enable interrupt mask */ 793 if (db->emacrx_completed_flag == 1) { 794 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 795 reg_val |= (0xf << 0) | (0x01 << 8); 796 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 797 } else { 798 reg_val = readl(db->membase + EMAC_INT_CTL_REG); 799 reg_val |= (0xf << 0); 800 writel(reg_val, db->membase + EMAC_INT_CTL_REG); 801 } 802 803 spin_unlock(&db->lock); 804 805 return IRQ_HANDLED; 806 } 807 808 #ifdef CONFIG_NET_POLL_CONTROLLER 809 /* 810 * Used by netconsole 811 */ 812 static void emac_poll_controller(struct net_device *dev) 813 { 814 disable_irq(dev->irq); 815 emac_interrupt(dev->irq, dev); 816 enable_irq(dev->irq); 817 } 818 #endif 819 820 /* Open the interface. 821 * The interface is opened whenever "ifconfig" actives it. 822 */ 823 static int emac_open(struct net_device *dev) 824 { 825 struct emac_board_info *db = netdev_priv(dev); 826 int ret; 827 828 if (netif_msg_ifup(db)) 829 dev_dbg(db->dev, "enabling %s\n", dev->name); 830 831 if (request_irq(dev->irq, &emac_interrupt, 0, dev->name, dev)) 832 return -EAGAIN; 833 834 /* Initialize EMAC board */ 835 emac_reset(db); 836 emac_init_device(dev); 837 838 ret = emac_mdio_probe(dev); 839 if (ret < 0) { 840 free_irq(dev->irq, dev); 841 netdev_err(dev, "cannot probe MDIO bus\n"); 842 return ret; 843 } 844 845 phy_start(dev->phydev); 846 netif_start_queue(dev); 847 848 return 0; 849 } 850 851 static void emac_shutdown(struct net_device *dev) 852 { 853 unsigned int reg_val; 854 struct emac_board_info *db = netdev_priv(dev); 855 856 /* Disable all interrupt */ 857 writel(0, db->membase + EMAC_INT_CTL_REG); 858 859 /* clear interrupt status */ 860 reg_val = readl(db->membase + EMAC_INT_STA_REG); 861 writel(reg_val, db->membase + EMAC_INT_STA_REG); 862 863 /* Disable RX/TX */ 864 reg_val = readl(db->membase + EMAC_CTL_REG); 865 reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET); 866 writel(reg_val, db->membase + EMAC_CTL_REG); 867 } 868 869 /* Stop the interface. 870 * The interface is stopped when it is brought. 871 */ 872 static int emac_stop(struct net_device *ndev) 873 { 874 struct emac_board_info *db = netdev_priv(ndev); 875 876 if (netif_msg_ifdown(db)) 877 dev_dbg(db->dev, "shutting down %s\n", ndev->name); 878 879 netif_stop_queue(ndev); 880 netif_carrier_off(ndev); 881 882 phy_stop(ndev->phydev); 883 884 emac_mdio_remove(ndev); 885 886 emac_shutdown(ndev); 887 888 free_irq(ndev->irq, ndev); 889 890 return 0; 891 } 892 893 static const struct net_device_ops emac_netdev_ops = { 894 .ndo_open = emac_open, 895 .ndo_stop = emac_stop, 896 .ndo_start_xmit = emac_start_xmit, 897 .ndo_tx_timeout = emac_timeout, 898 .ndo_set_rx_mode = emac_set_rx_mode, 899 .ndo_eth_ioctl = phy_do_ioctl_running, 900 .ndo_validate_addr = eth_validate_addr, 901 .ndo_set_mac_address = emac_set_mac_address, 902 #ifdef CONFIG_NET_POLL_CONTROLLER 903 .ndo_poll_controller = emac_poll_controller, 904 #endif 905 }; 906 907 static int emac_configure_dma(struct emac_board_info *db) 908 { 909 struct platform_device *pdev = db->pdev; 910 struct net_device *ndev = db->ndev; 911 struct dma_slave_config conf = {}; 912 struct resource *regs; 913 int err = 0; 914 915 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 916 if (!regs) { 917 netdev_err(ndev, "get io resource from device failed.\n"); 918 err = -ENOMEM; 919 goto out_clear_chan; 920 } 921 922 netdev_info(ndev, "get io resource from device: %pa, size = %u\n", 923 ®s->start, (unsigned int)resource_size(regs)); 924 db->emac_rx_fifo = regs->start + EMAC_RX_IO_DATA_REG; 925 926 db->rx_chan = dma_request_chan(&pdev->dev, "rx"); 927 if (IS_ERR(db->rx_chan)) { 928 netdev_err(ndev, 929 "failed to request dma channel. dma is disabled\n"); 930 err = PTR_ERR(db->rx_chan); 931 goto out_clear_chan; 932 } 933 934 conf.direction = DMA_DEV_TO_MEM; 935 conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 936 conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 937 conf.src_addr = db->emac_rx_fifo; 938 conf.dst_maxburst = 4; 939 conf.src_maxburst = 4; 940 conf.device_fc = false; 941 942 err = dmaengine_slave_config(db->rx_chan, &conf); 943 if (err) { 944 netdev_err(ndev, "config dma slave failed\n"); 945 err = -EINVAL; 946 goto out_slave_configure_err; 947 } 948 949 return err; 950 951 out_slave_configure_err: 952 dma_release_channel(db->rx_chan); 953 954 out_clear_chan: 955 db->rx_chan = NULL; 956 return err; 957 } 958 959 /* Search EMAC board, allocate space and register it 960 */ 961 static int emac_probe(struct platform_device *pdev) 962 { 963 struct device_node *np = pdev->dev.of_node; 964 struct emac_board_info *db; 965 struct net_device *ndev; 966 int ret = 0; 967 968 ndev = alloc_etherdev(sizeof(struct emac_board_info)); 969 if (!ndev) { 970 dev_err(&pdev->dev, "could not allocate device.\n"); 971 return -ENOMEM; 972 } 973 974 SET_NETDEV_DEV(ndev, &pdev->dev); 975 976 db = netdev_priv(ndev); 977 978 db->dev = &pdev->dev; 979 db->ndev = ndev; 980 db->pdev = pdev; 981 db->msg_enable = netif_msg_init(debug, EMAC_DEFAULT_MSG_ENABLE); 982 983 spin_lock_init(&db->lock); 984 985 db->membase = of_iomap(np, 0); 986 if (!db->membase) { 987 dev_err(&pdev->dev, "failed to remap registers\n"); 988 ret = -ENOMEM; 989 goto out; 990 } 991 992 /* fill in parameters for net-dev structure */ 993 ndev->base_addr = (unsigned long)db->membase; 994 ndev->irq = irq_of_parse_and_map(np, 0); 995 if (ndev->irq == -ENXIO) { 996 netdev_err(ndev, "No irq resource\n"); 997 ret = ndev->irq; 998 goto out_iounmap; 999 } 1000 1001 if (emac_configure_dma(db)) 1002 netdev_info(ndev, "configure dma failed. disable dma.\n"); 1003 1004 db->clk = devm_clk_get(&pdev->dev, NULL); 1005 if (IS_ERR(db->clk)) { 1006 ret = PTR_ERR(db->clk); 1007 goto out_dispose_mapping; 1008 } 1009 1010 ret = clk_prepare_enable(db->clk); 1011 if (ret) { 1012 dev_err(&pdev->dev, "Error couldn't enable clock (%d)\n", ret); 1013 goto out_dispose_mapping; 1014 } 1015 1016 ret = sunxi_sram_claim(&pdev->dev); 1017 if (ret) { 1018 dev_err(&pdev->dev, "Error couldn't map SRAM to device\n"); 1019 goto out_clk_disable_unprepare; 1020 } 1021 1022 db->phy_node = of_parse_phandle(np, "phy-handle", 0); 1023 if (!db->phy_node) 1024 db->phy_node = of_parse_phandle(np, "phy", 0); 1025 if (!db->phy_node) { 1026 dev_err(&pdev->dev, "no associated PHY\n"); 1027 ret = -ENODEV; 1028 goto out_release_sram; 1029 } 1030 1031 /* Read MAC-address from DT */ 1032 ret = of_get_ethdev_address(np, ndev); 1033 if (ret) { 1034 /* if the MAC address is invalid get a random one */ 1035 eth_hw_addr_random(ndev); 1036 dev_warn(&pdev->dev, "using random MAC address %pM\n", 1037 ndev->dev_addr); 1038 } 1039 1040 db->emacrx_completed_flag = 1; 1041 emac_powerup(ndev); 1042 emac_reset(db); 1043 1044 ndev->netdev_ops = &emac_netdev_ops; 1045 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 1046 ndev->ethtool_ops = &emac_ethtool_ops; 1047 1048 platform_set_drvdata(pdev, ndev); 1049 1050 /* Carrier starts down, phylib will bring it up */ 1051 netif_carrier_off(ndev); 1052 1053 ret = register_netdev(ndev); 1054 if (ret) { 1055 dev_err(&pdev->dev, "Registering netdev failed!\n"); 1056 ret = -ENODEV; 1057 goto out_release_sram; 1058 } 1059 1060 dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n", 1061 ndev->name, db->membase, ndev->irq, ndev->dev_addr); 1062 1063 return 0; 1064 1065 out_release_sram: 1066 sunxi_sram_release(&pdev->dev); 1067 out_clk_disable_unprepare: 1068 clk_disable_unprepare(db->clk); 1069 out_dispose_mapping: 1070 irq_dispose_mapping(ndev->irq); 1071 out_iounmap: 1072 iounmap(db->membase); 1073 out: 1074 dev_err(db->dev, "not found (%d).\n", ret); 1075 1076 free_netdev(ndev); 1077 1078 return ret; 1079 } 1080 1081 static int emac_remove(struct platform_device *pdev) 1082 { 1083 struct net_device *ndev = platform_get_drvdata(pdev); 1084 struct emac_board_info *db = netdev_priv(ndev); 1085 1086 if (db->rx_chan) { 1087 dmaengine_terminate_all(db->rx_chan); 1088 dma_release_channel(db->rx_chan); 1089 } 1090 1091 unregister_netdev(ndev); 1092 sunxi_sram_release(&pdev->dev); 1093 clk_disable_unprepare(db->clk); 1094 irq_dispose_mapping(ndev->irq); 1095 iounmap(db->membase); 1096 free_netdev(ndev); 1097 1098 dev_dbg(&pdev->dev, "released and freed device\n"); 1099 return 0; 1100 } 1101 1102 static int emac_suspend(struct platform_device *dev, pm_message_t state) 1103 { 1104 struct net_device *ndev = platform_get_drvdata(dev); 1105 1106 netif_carrier_off(ndev); 1107 netif_device_detach(ndev); 1108 emac_shutdown(ndev); 1109 1110 return 0; 1111 } 1112 1113 static int emac_resume(struct platform_device *dev) 1114 { 1115 struct net_device *ndev = platform_get_drvdata(dev); 1116 struct emac_board_info *db = netdev_priv(ndev); 1117 1118 emac_reset(db); 1119 emac_init_device(ndev); 1120 netif_device_attach(ndev); 1121 1122 return 0; 1123 } 1124 1125 static const struct of_device_id emac_of_match[] = { 1126 {.compatible = "allwinner,sun4i-a10-emac",}, 1127 1128 /* Deprecated */ 1129 {.compatible = "allwinner,sun4i-emac",}, 1130 {}, 1131 }; 1132 1133 MODULE_DEVICE_TABLE(of, emac_of_match); 1134 1135 static struct platform_driver emac_driver = { 1136 .driver = { 1137 .name = "sun4i-emac", 1138 .of_match_table = emac_of_match, 1139 }, 1140 .probe = emac_probe, 1141 .remove = emac_remove, 1142 .suspend = emac_suspend, 1143 .resume = emac_resume, 1144 }; 1145 1146 module_platform_driver(emac_driver); 1147 1148 MODULE_AUTHOR("Stefan Roese <sr@denx.de>"); 1149 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1150 MODULE_DESCRIPTION("Allwinner A10 emac network driver"); 1151 MODULE_LICENSE("GPL"); 1152