1 /* Generic NS8390 register definitions. */ 2 /* This file is part of Donald Becker's 8390 drivers, and is distributed 3 under the same license. Auto-loading of 8390.o only in v2.2 - Paul G. 4 Some of these names and comments originated from the Crynwr 5 packet drivers, which are distributed under the GPL. */ 6 7 #ifndef _8390_h 8 #define _8390_h 9 10 #include <linux/if_ether.h> 11 #include <linux/ioport.h> 12 #include <linux/irqreturn.h> 13 #include <linux/skbuff.h> 14 15 #define TX_PAGES 12 /* Two Tx slots */ 16 17 /* The 8390 specific per-packet-header format. */ 18 struct e8390_pkt_hdr { 19 unsigned char status; /* status */ 20 unsigned char next; /* pointer to next packet. */ 21 unsigned short count; /* header + packet length in bytes */ 22 }; 23 24 #ifdef notdef 25 extern int ei_debug; 26 #else 27 #define ei_debug 1 28 #endif 29 30 #ifdef CONFIG_NET_POLL_CONTROLLER 31 extern void ei_poll(struct net_device *dev); 32 extern void eip_poll(struct net_device *dev); 33 #endif 34 35 36 /* Without I/O delay - non ISA or later chips */ 37 extern void NS8390_init(struct net_device *dev, int startp); 38 extern int ei_open(struct net_device *dev); 39 extern int ei_close(struct net_device *dev); 40 extern irqreturn_t ei_interrupt(int irq, void *dev_id); 41 extern void ei_tx_timeout(struct net_device *dev); 42 extern netdev_tx_t ei_start_xmit(struct sk_buff *skb, struct net_device *dev); 43 extern void ei_set_multicast_list(struct net_device *dev); 44 extern struct net_device_stats *ei_get_stats(struct net_device *dev); 45 46 extern const struct net_device_ops ei_netdev_ops; 47 48 extern struct net_device *__alloc_ei_netdev(int size); 49 static inline struct net_device *alloc_ei_netdev(void) 50 { 51 return __alloc_ei_netdev(0); 52 } 53 54 /* With I/O delay form */ 55 extern void NS8390p_init(struct net_device *dev, int startp); 56 extern int eip_open(struct net_device *dev); 57 extern int eip_close(struct net_device *dev); 58 extern irqreturn_t eip_interrupt(int irq, void *dev_id); 59 extern void eip_tx_timeout(struct net_device *dev); 60 extern netdev_tx_t eip_start_xmit(struct sk_buff *skb, struct net_device *dev); 61 extern void eip_set_multicast_list(struct net_device *dev); 62 extern struct net_device_stats *eip_get_stats(struct net_device *dev); 63 64 extern const struct net_device_ops eip_netdev_ops; 65 66 extern struct net_device *__alloc_eip_netdev(int size); 67 static inline struct net_device *alloc_eip_netdev(void) 68 { 69 return __alloc_eip_netdev(0); 70 } 71 72 /* You have one of these per-board */ 73 struct ei_device { 74 const char *name; 75 void (*reset_8390)(struct net_device *); 76 void (*get_8390_hdr)(struct net_device *, struct e8390_pkt_hdr *, int); 77 void (*block_output)(struct net_device *, int, const unsigned char *, int); 78 void (*block_input)(struct net_device *, int, struct sk_buff *, int); 79 unsigned long rmem_start; 80 unsigned long rmem_end; 81 void __iomem *mem; 82 unsigned char mcfilter[8]; 83 unsigned open:1; 84 unsigned word16:1; /* We have the 16-bit (vs 8-bit) version of the card. */ 85 unsigned bigendian:1; /* 16-bit big endian mode. Do NOT */ 86 /* set this on random 8390 clones! */ 87 unsigned txing:1; /* Transmit Active */ 88 unsigned irqlock:1; /* 8390's intrs disabled when '1'. */ 89 unsigned dmaing:1; /* Remote DMA Active */ 90 unsigned char tx_start_page, rx_start_page, stop_page; 91 unsigned char current_page; /* Read pointer in buffer */ 92 unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */ 93 unsigned char txqueue; /* Tx Packet buffer queue length. */ 94 short tx1, tx2; /* Packet lengths for ping-pong tx. */ 95 short lasttx; /* Alpha version consistency check. */ 96 unsigned char reg0; /* Register '0' in a WD8013 */ 97 unsigned char reg5; /* Register '5' in a WD8013 */ 98 unsigned char saved_irq; /* Original dev->irq value. */ 99 u32 *reg_offset; /* Register mapping table */ 100 spinlock_t page_lock; /* Page register locks */ 101 unsigned long priv; /* Private field to store bus IDs etc. */ 102 #ifdef AX88796_PLATFORM 103 unsigned char rxcr_base; /* default value for RXCR */ 104 #endif 105 }; 106 107 /* The maximum number of 8390 interrupt service routines called per IRQ. */ 108 #define MAX_SERVICE 12 109 110 /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */ 111 #define TX_TIMEOUT (20*HZ/100) 112 113 #define ei_status (*(struct ei_device *)netdev_priv(dev)) 114 115 /* Some generic ethernet register configurations. */ 116 #define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */ 117 #define E8390_RX_IRQ_MASK 0x5 118 119 #ifdef AX88796_PLATFORM 120 #define E8390_RXCONFIG (ei_status.rxcr_base | 0x04) 121 #define E8390_RXOFF (ei_status.rxcr_base | 0x20) 122 #else 123 #define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */ 124 #define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */ 125 #endif 126 127 #define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */ 128 #define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */ 129 130 131 /* Register accessed at EN_CMD, the 8390 base addr. */ 132 #define E8390_STOP 0x01 /* Stop and reset the chip */ 133 #define E8390_START 0x02 /* Start the chip, clear reset */ 134 #define E8390_TRANS 0x04 /* Transmit a frame */ 135 #define E8390_RREAD 0x08 /* Remote read */ 136 #define E8390_RWRITE 0x10 /* Remote write */ 137 #define E8390_NODMA 0x20 /* Remote DMA */ 138 #define E8390_PAGE0 0x00 /* Select page chip registers */ 139 #define E8390_PAGE1 0x40 /* using the two high-order bits */ 140 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ 141 142 /* 143 * Only generate indirect loads given a machine that needs them. 144 * - removed AMIGA_PCMCIA from this list, handled as ISA io now 145 * - the _p for generates no delay by default 8390p.c overrides this. 146 */ 147 148 #ifndef ei_inb 149 #define ei_inb(_p) inb(_p) 150 #define ei_outb(_v,_p) outb(_v,_p) 151 #define ei_inb_p(_p) inb(_p) 152 #define ei_outb_p(_v,_p) outb(_v,_p) 153 #endif 154 155 #ifndef EI_SHIFT 156 #define EI_SHIFT(x) (x) 157 #endif 158 159 #define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */ 160 /* Page 0 register offsets. */ 161 #define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */ 162 #define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */ 163 #define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */ 164 #define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */ 165 #define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */ 166 #define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */ 167 #define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */ 168 #define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */ 169 #define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */ 170 #define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */ 171 #define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */ 172 #define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */ 173 #define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */ 174 #define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */ 175 #define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */ 176 #define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */ 177 #define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */ 178 #define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */ 179 #define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */ 180 #define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */ 181 #define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */ 182 #define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */ 183 #define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */ 184 #define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */ 185 #define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */ 186 #define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */ 187 188 /* Bits in EN0_ISR - Interrupt status register */ 189 #define ENISR_RX 0x01 /* Receiver, no error */ 190 #define ENISR_TX 0x02 /* Transmitter, no error */ 191 #define ENISR_RX_ERR 0x04 /* Receiver, with error */ 192 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ 193 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ 194 #define ENISR_COUNTERS 0x20 /* Counters need emptying */ 195 #define ENISR_RDC 0x40 /* remote dma complete */ 196 #define ENISR_RESET 0x80 /* Reset completed */ 197 #define ENISR_ALL 0x3f /* Interrupts we will enable */ 198 199 /* Bits in EN0_DCFG - Data config register */ 200 #define ENDCFG_WTS 0x01 /* word transfer mode selection */ 201 #define ENDCFG_BOS 0x02 /* byte order selection */ 202 203 /* Page 1 register offsets. */ 204 #define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */ 205 #define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */ 206 #define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */ 207 #define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */ 208 #define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */ 209 210 /* Bits in received packet status byte and EN0_RSR*/ 211 #define ENRSR_RXOK 0x01 /* Received a good packet */ 212 #define ENRSR_CRC 0x02 /* CRC error */ 213 #define ENRSR_FAE 0x04 /* frame alignment error */ 214 #define ENRSR_FO 0x08 /* FIFO overrun */ 215 #define ENRSR_MPA 0x10 /* missed pkt */ 216 #define ENRSR_PHY 0x20 /* physical/multicast address */ 217 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ 218 #define ENRSR_DEF 0x80 /* deferring */ 219 220 /* Transmitted packet status, EN0_TSR. */ 221 #define ENTSR_PTX 0x01 /* Packet transmitted without error */ 222 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ 223 #define ENTSR_COL 0x04 /* The transmit collided at least once. */ 224 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ 225 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ 226 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ 227 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ 228 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ 229 230 #endif /* _8390_h */ 231