1*dc3eb2f4SBagas Sanjaya /* SPDX-License-Identifier: GPL-1.0+ */
2*dc3eb2f4SBagas Sanjaya
3644570b8SJeff Kirsher /* Generic NS8390 register definitions. */
4ac6a86a5SArmin Wolf
5644570b8SJeff Kirsher /* This file is part of Donald Becker's 8390 drivers, and is distributed
6ac6a86a5SArmin Wolf * under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
7ac6a86a5SArmin Wolf * Some of these names and comments originated from the Crynwr
8ac6a86a5SArmin Wolf * packet drivers, which are distributed under the GPL.
9ac6a86a5SArmin Wolf */
10644570b8SJeff Kirsher
11644570b8SJeff Kirsher #ifndef _8390_h
12644570b8SJeff Kirsher #define _8390_h
13644570b8SJeff Kirsher
14644570b8SJeff Kirsher #include <linux/if_ether.h>
15644570b8SJeff Kirsher #include <linux/ioport.h>
16644570b8SJeff Kirsher #include <linux/irqreturn.h>
17644570b8SJeff Kirsher #include <linux/skbuff.h>
18644570b8SJeff Kirsher
19644570b8SJeff Kirsher #define TX_PAGES 12 /* Two Tx slots */
20644570b8SJeff Kirsher
21644570b8SJeff Kirsher /* The 8390 specific per-packet-header format. */
22644570b8SJeff Kirsher struct e8390_pkt_hdr {
23644570b8SJeff Kirsher unsigned char status; /* status */
24644570b8SJeff Kirsher unsigned char next; /* pointer to next packet. */
25644570b8SJeff Kirsher unsigned short count; /* header + packet length in bytes */
26644570b8SJeff Kirsher };
27644570b8SJeff Kirsher
28644570b8SJeff Kirsher #ifdef CONFIG_NET_POLL_CONTROLLER
2968d34301SJoe Perches void ei_poll(struct net_device *dev);
3068d34301SJoe Perches void eip_poll(struct net_device *dev);
31644570b8SJeff Kirsher #endif
32644570b8SJeff Kirsher
33644570b8SJeff Kirsher
34644570b8SJeff Kirsher /* Without I/O delay - non ISA or later chips */
3568d34301SJoe Perches void NS8390_init(struct net_device *dev, int startp);
3668d34301SJoe Perches int ei_open(struct net_device *dev);
3768d34301SJoe Perches int ei_close(struct net_device *dev);
3868d34301SJoe Perches irqreturn_t ei_interrupt(int irq, void *dev_id);
390290bd29SMichael S. Tsirkin void ei_tx_timeout(struct net_device *dev, unsigned int txqueue);
4068d34301SJoe Perches netdev_tx_t ei_start_xmit(struct sk_buff *skb, struct net_device *dev);
4168d34301SJoe Perches void ei_set_multicast_list(struct net_device *dev);
4268d34301SJoe Perches struct net_device_stats *ei_get_stats(struct net_device *dev);
43644570b8SJeff Kirsher
44644570b8SJeff Kirsher extern const struct net_device_ops ei_netdev_ops;
45644570b8SJeff Kirsher
4668d34301SJoe Perches struct net_device *__alloc_ei_netdev(int size);
alloc_ei_netdev(void)47644570b8SJeff Kirsher static inline struct net_device *alloc_ei_netdev(void)
48644570b8SJeff Kirsher {
49644570b8SJeff Kirsher return __alloc_ei_netdev(0);
50644570b8SJeff Kirsher }
51644570b8SJeff Kirsher
52644570b8SJeff Kirsher /* With I/O delay form */
5368d34301SJoe Perches void NS8390p_init(struct net_device *dev, int startp);
5468d34301SJoe Perches int eip_open(struct net_device *dev);
5568d34301SJoe Perches int eip_close(struct net_device *dev);
5668d34301SJoe Perches irqreturn_t eip_interrupt(int irq, void *dev_id);
570290bd29SMichael S. Tsirkin void eip_tx_timeout(struct net_device *dev, unsigned int txqueue);
5868d34301SJoe Perches netdev_tx_t eip_start_xmit(struct sk_buff *skb, struct net_device *dev);
5968d34301SJoe Perches void eip_set_multicast_list(struct net_device *dev);
6068d34301SJoe Perches struct net_device_stats *eip_get_stats(struct net_device *dev);
61644570b8SJeff Kirsher
62644570b8SJeff Kirsher extern const struct net_device_ops eip_netdev_ops;
63644570b8SJeff Kirsher
6468d34301SJoe Perches struct net_device *__alloc_eip_netdev(int size);
alloc_eip_netdev(void)65644570b8SJeff Kirsher static inline struct net_device *alloc_eip_netdev(void)
66644570b8SJeff Kirsher {
67644570b8SJeff Kirsher return __alloc_eip_netdev(0);
68644570b8SJeff Kirsher }
69644570b8SJeff Kirsher
70644570b8SJeff Kirsher /* You have one of these per-board */
71644570b8SJeff Kirsher struct ei_device {
72644570b8SJeff Kirsher const char *name;
73ac6a86a5SArmin Wolf void (*reset_8390)(struct net_device *dev);
74ac6a86a5SArmin Wolf void (*get_8390_hdr)(struct net_device *dev,
75ac6a86a5SArmin Wolf struct e8390_pkt_hdr *hdr, int ring_page);
76ac6a86a5SArmin Wolf void (*block_output)(struct net_device *dev, int count,
77ac6a86a5SArmin Wolf const unsigned char *buf, int start_page);
78ac6a86a5SArmin Wolf void (*block_input)(struct net_device *dev, int count,
79ac6a86a5SArmin Wolf struct sk_buff *skb, int ring_offset);
80644570b8SJeff Kirsher unsigned long rmem_start;
81644570b8SJeff Kirsher unsigned long rmem_end;
82644570b8SJeff Kirsher void __iomem *mem;
83644570b8SJeff Kirsher unsigned char mcfilter[8];
84644570b8SJeff Kirsher unsigned open:1;
85ac6a86a5SArmin Wolf unsigned word16:1; /* We have the 16-bit (vs 8-bit)
86ac6a86a5SArmin Wolf * version of the card.
87ac6a86a5SArmin Wolf */
88ac6a86a5SArmin Wolf unsigned bigendian:1; /* 16-bit big endian mode. Do NOT
89ac6a86a5SArmin Wolf * set this on random 8390 clones!
90ac6a86a5SArmin Wolf */
91644570b8SJeff Kirsher unsigned txing:1; /* Transmit Active */
92644570b8SJeff Kirsher unsigned irqlock:1; /* 8390's intrs disabled when '1'. */
93644570b8SJeff Kirsher unsigned dmaing:1; /* Remote DMA Active */
94644570b8SJeff Kirsher unsigned char tx_start_page, rx_start_page, stop_page;
95644570b8SJeff Kirsher unsigned char current_page; /* Read pointer in buffer */
96644570b8SJeff Kirsher unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */
97644570b8SJeff Kirsher unsigned char txqueue; /* Tx Packet buffer queue length. */
98644570b8SJeff Kirsher short tx1, tx2; /* Packet lengths for ping-pong tx. */
99644570b8SJeff Kirsher short lasttx; /* Alpha version consistency check. */
100644570b8SJeff Kirsher unsigned char reg0; /* Register '0' in a WD8013 */
101644570b8SJeff Kirsher unsigned char reg5; /* Register '5' in a WD8013 */
102644570b8SJeff Kirsher unsigned char saved_irq; /* Original dev->irq value. */
103644570b8SJeff Kirsher u32 *reg_offset; /* Register mapping table */
104644570b8SJeff Kirsher spinlock_t page_lock; /* Page register locks */
105644570b8SJeff Kirsher unsigned long priv; /* Private field to store bus IDs etc. */
106c45f812fSMatthew Whitehead u32 msg_enable; /* debug message level */
107644570b8SJeff Kirsher #ifdef AX88796_PLATFORM
108644570b8SJeff Kirsher unsigned char rxcr_base; /* default value for RXCR */
109644570b8SJeff Kirsher #endif
110644570b8SJeff Kirsher };
111644570b8SJeff Kirsher
112644570b8SJeff Kirsher /* The maximum number of 8390 interrupt service routines called per IRQ. */
113644570b8SJeff Kirsher #define MAX_SERVICE 12
114644570b8SJeff Kirsher
115644570b8SJeff Kirsher /* The maximum time waited (in jiffies) before assuming a Tx failed. (20ms) */
116644570b8SJeff Kirsher #define TX_TIMEOUT (20*HZ/100)
117644570b8SJeff Kirsher
118644570b8SJeff Kirsher #define ei_status (*(struct ei_device *)netdev_priv(dev))
119644570b8SJeff Kirsher
120644570b8SJeff Kirsher /* Some generic ethernet register configurations. */
121644570b8SJeff Kirsher #define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */
122644570b8SJeff Kirsher #define E8390_RX_IRQ_MASK 0x5
123644570b8SJeff Kirsher
124644570b8SJeff Kirsher #ifdef AX88796_PLATFORM
125644570b8SJeff Kirsher #define E8390_RXCONFIG (ei_status.rxcr_base | 0x04)
126644570b8SJeff Kirsher #define E8390_RXOFF (ei_status.rxcr_base | 0x20)
127644570b8SJeff Kirsher #else
128ac6a86a5SArmin Wolf /* EN0_RXCR: broadcasts, no multicast,errors */
129ac6a86a5SArmin Wolf #define E8390_RXCONFIG 0x4
130ac6a86a5SArmin Wolf /* EN0_RXCR: Accept no packets */
131ac6a86a5SArmin Wolf #define E8390_RXOFF 0x20
132644570b8SJeff Kirsher #endif
133644570b8SJeff Kirsher
134ac6a86a5SArmin Wolf /* EN0_TXCR: Normal transmit mode */
135ac6a86a5SArmin Wolf #define E8390_TXCONFIG 0x00
136ac6a86a5SArmin Wolf /* EN0_TXCR: Transmitter off */
137ac6a86a5SArmin Wolf #define E8390_TXOFF 0x02
138644570b8SJeff Kirsher
139644570b8SJeff Kirsher
140644570b8SJeff Kirsher /* Register accessed at EN_CMD, the 8390 base addr. */
141644570b8SJeff Kirsher #define E8390_STOP 0x01 /* Stop and reset the chip */
142644570b8SJeff Kirsher #define E8390_START 0x02 /* Start the chip, clear reset */
143644570b8SJeff Kirsher #define E8390_TRANS 0x04 /* Transmit a frame */
144644570b8SJeff Kirsher #define E8390_RREAD 0x08 /* Remote read */
145644570b8SJeff Kirsher #define E8390_RWRITE 0x10 /* Remote write */
146644570b8SJeff Kirsher #define E8390_NODMA 0x20 /* Remote DMA */
147644570b8SJeff Kirsher #define E8390_PAGE0 0x00 /* Select page chip registers */
148644570b8SJeff Kirsher #define E8390_PAGE1 0x40 /* using the two high-order bits */
149644570b8SJeff Kirsher #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
150644570b8SJeff Kirsher
151ac6a86a5SArmin Wolf /* Only generate indirect loads given a machine that needs them.
152644570b8SJeff Kirsher * - removed AMIGA_PCMCIA from this list, handled as ISA io now
153644570b8SJeff Kirsher * - the _p for generates no delay by default 8390p.c overrides this.
154644570b8SJeff Kirsher */
155644570b8SJeff Kirsher
156644570b8SJeff Kirsher #ifndef ei_inb
157644570b8SJeff Kirsher #define ei_inb(_p) inb(_p)
158644570b8SJeff Kirsher #define ei_outb(_v, _p) outb(_v, _p)
159644570b8SJeff Kirsher #define ei_inb_p(_p) inb(_p)
160644570b8SJeff Kirsher #define ei_outb_p(_v, _p) outb(_v, _p)
161644570b8SJeff Kirsher #endif
162644570b8SJeff Kirsher
163644570b8SJeff Kirsher #ifndef EI_SHIFT
164644570b8SJeff Kirsher #define EI_SHIFT(x) (x)
165644570b8SJeff Kirsher #endif
166644570b8SJeff Kirsher
167644570b8SJeff Kirsher #define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */
168644570b8SJeff Kirsher /* Page 0 register offsets. */
169644570b8SJeff Kirsher #define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */
170644570b8SJeff Kirsher #define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */
171644570b8SJeff Kirsher #define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */
172644570b8SJeff Kirsher #define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */
173644570b8SJeff Kirsher #define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */
174644570b8SJeff Kirsher #define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */
175644570b8SJeff Kirsher #define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */
176644570b8SJeff Kirsher #define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */
177644570b8SJeff Kirsher #define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */
178644570b8SJeff Kirsher #define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */
179644570b8SJeff Kirsher #define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */
180644570b8SJeff Kirsher #define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */
181644570b8SJeff Kirsher #define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */
182644570b8SJeff Kirsher #define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */
183644570b8SJeff Kirsher #define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */
184644570b8SJeff Kirsher #define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */
185644570b8SJeff Kirsher #define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */
186644570b8SJeff Kirsher #define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */
187644570b8SJeff Kirsher #define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */
188644570b8SJeff Kirsher #define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */
189644570b8SJeff Kirsher #define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */
190644570b8SJeff Kirsher #define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */
191644570b8SJeff Kirsher #define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */
192644570b8SJeff Kirsher #define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */
193644570b8SJeff Kirsher #define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */
194644570b8SJeff Kirsher #define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */
195644570b8SJeff Kirsher
196644570b8SJeff Kirsher /* Bits in EN0_ISR - Interrupt status register */
197644570b8SJeff Kirsher #define ENISR_RX 0x01 /* Receiver, no error */
198644570b8SJeff Kirsher #define ENISR_TX 0x02 /* Transmitter, no error */
199644570b8SJeff Kirsher #define ENISR_RX_ERR 0x04 /* Receiver, with error */
200644570b8SJeff Kirsher #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
201644570b8SJeff Kirsher #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
202644570b8SJeff Kirsher #define ENISR_COUNTERS 0x20 /* Counters need emptying */
203644570b8SJeff Kirsher #define ENISR_RDC 0x40 /* remote dma complete */
204644570b8SJeff Kirsher #define ENISR_RESET 0x80 /* Reset completed */
205644570b8SJeff Kirsher #define ENISR_ALL 0x3f /* Interrupts we will enable */
206644570b8SJeff Kirsher
207644570b8SJeff Kirsher /* Bits in EN0_DCFG - Data config register */
208644570b8SJeff Kirsher #define ENDCFG_WTS 0x01 /* word transfer mode selection */
209644570b8SJeff Kirsher #define ENDCFG_BOS 0x02 /* byte order selection */
210644570b8SJeff Kirsher
211644570b8SJeff Kirsher /* Page 1 register offsets. */
212644570b8SJeff Kirsher #define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */
213644570b8SJeff Kirsher #define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */
214644570b8SJeff Kirsher #define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */
215644570b8SJeff Kirsher #define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */
216644570b8SJeff Kirsher #define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */
217644570b8SJeff Kirsher
218644570b8SJeff Kirsher /* Bits in received packet status byte and EN0_RSR*/
219644570b8SJeff Kirsher #define ENRSR_RXOK 0x01 /* Received a good packet */
220644570b8SJeff Kirsher #define ENRSR_CRC 0x02 /* CRC error */
221644570b8SJeff Kirsher #define ENRSR_FAE 0x04 /* frame alignment error */
222644570b8SJeff Kirsher #define ENRSR_FO 0x08 /* FIFO overrun */
223644570b8SJeff Kirsher #define ENRSR_MPA 0x10 /* missed pkt */
224644570b8SJeff Kirsher #define ENRSR_PHY 0x20 /* physical/multicast address */
225644570b8SJeff Kirsher #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
226644570b8SJeff Kirsher #define ENRSR_DEF 0x80 /* deferring */
227644570b8SJeff Kirsher
228644570b8SJeff Kirsher /* Transmitted packet status, EN0_TSR. */
229644570b8SJeff Kirsher #define ENTSR_PTX 0x01 /* Packet transmitted without error */
230644570b8SJeff Kirsher #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
231644570b8SJeff Kirsher #define ENTSR_COL 0x04 /* The transmit collided at least once. */
232644570b8SJeff Kirsher #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
233644570b8SJeff Kirsher #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
234644570b8SJeff Kirsher #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
235644570b8SJeff Kirsher #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
236644570b8SJeff Kirsher #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
237644570b8SJeff Kirsher
238644570b8SJeff Kirsher #endif /* _8390_h */
239