1ca7a8e85SJeff Kirsher /* typhoon.h: chip info for the 3Com 3CR990 family of controllers */ 2ca7a8e85SJeff Kirsher /* 3ca7a8e85SJeff Kirsher Written 2002-2003 by David Dillow <dave@thedillows.org> 4ca7a8e85SJeff Kirsher 5ca7a8e85SJeff Kirsher This software may be used and distributed according to the terms of 6ca7a8e85SJeff Kirsher the GNU General Public License (GPL), incorporated herein by reference. 7ca7a8e85SJeff Kirsher Drivers based on or derived from this code fall under the GPL and must 8ca7a8e85SJeff Kirsher retain the authorship, copyright and license notice. This file is not 9ca7a8e85SJeff Kirsher a complete program and may only be used when the entire operating 10ca7a8e85SJeff Kirsher system is licensed under the GPL. 11ca7a8e85SJeff Kirsher 12ca7a8e85SJeff Kirsher This software is available on a public web site. It may enable 13ca7a8e85SJeff Kirsher cryptographic capabilities of the 3Com hardware, and may be 14ca7a8e85SJeff Kirsher exported from the United States under License Exception "TSU" 15ca7a8e85SJeff Kirsher pursuant to 15 C.F.R. Section 740.13(e). 16ca7a8e85SJeff Kirsher 17ca7a8e85SJeff Kirsher This work was funded by the National Library of Medicine under 18ca7a8e85SJeff Kirsher the Department of Energy project number 0274DD06D1 and NLM project 19ca7a8e85SJeff Kirsher number Y1-LM-2015-01. 20ca7a8e85SJeff Kirsher */ 21ca7a8e85SJeff Kirsher 22ca7a8e85SJeff Kirsher /* All Typhoon ring positions are specificed in bytes, and point to the 23ca7a8e85SJeff Kirsher * first "clean" entry in the ring -- ie the next entry we use for whatever 24ca7a8e85SJeff Kirsher * purpose. 25ca7a8e85SJeff Kirsher */ 26ca7a8e85SJeff Kirsher 27ca7a8e85SJeff Kirsher /* The Typhoon basic ring 28ca7a8e85SJeff Kirsher * ringBase: where this ring lives (our virtual address) 29ca7a8e85SJeff Kirsher * lastWrite: the next entry we'll use 30ca7a8e85SJeff Kirsher */ 31ca7a8e85SJeff Kirsher struct basic_ring { 32ca7a8e85SJeff Kirsher u8 *ringBase; 33ca7a8e85SJeff Kirsher u32 lastWrite; 34ca7a8e85SJeff Kirsher }; 35ca7a8e85SJeff Kirsher 36790ca79dSChristophe JAILLET /* The Typhoon transmit ring -- same as a basic ring, plus: 37ca7a8e85SJeff Kirsher * lastRead: where we're at in regard to cleaning up the ring 38ca7a8e85SJeff Kirsher * writeRegister: register to use for writing (different for Hi & Lo rings) 39ca7a8e85SJeff Kirsher */ 40ca7a8e85SJeff Kirsher struct transmit_ring { 41ca7a8e85SJeff Kirsher u8 *ringBase; 42ca7a8e85SJeff Kirsher u32 lastWrite; 43ca7a8e85SJeff Kirsher u32 lastRead; 44ca7a8e85SJeff Kirsher int writeRegister; 45ca7a8e85SJeff Kirsher }; 46ca7a8e85SJeff Kirsher 47ca7a8e85SJeff Kirsher /* The host<->Typhoon ring index structure 48ca7a8e85SJeff Kirsher * This indicates the current positions in the rings 49ca7a8e85SJeff Kirsher * 50ca7a8e85SJeff Kirsher * All values must be in little endian format for the 3XP 51ca7a8e85SJeff Kirsher * 52ca7a8e85SJeff Kirsher * rxHiCleared: entry we've cleared to in the Hi receive ring 53ca7a8e85SJeff Kirsher * rxLoCleared: entry we've cleared to in the Lo receive ring 54ca7a8e85SJeff Kirsher * rxBuffReady: next entry we'll put a free buffer in 55ca7a8e85SJeff Kirsher * respCleared: entry we've cleared to in the response ring 56ca7a8e85SJeff Kirsher * 57ca7a8e85SJeff Kirsher * txLoCleared: entry the NIC has cleared to in the Lo transmit ring 58ca7a8e85SJeff Kirsher * txHiCleared: entry the NIC has cleared to in the Hi transmit ring 59ca7a8e85SJeff Kirsher * rxLoReady: entry the NIC has filled to in the Lo receive ring 60ca7a8e85SJeff Kirsher * rxBuffCleared: entry the NIC has cleared in the free buffer ring 61ca7a8e85SJeff Kirsher * cmdCleared: entry the NIC has cleared in the command ring 62ca7a8e85SJeff Kirsher * respReady: entry the NIC has filled to in the response ring 63ca7a8e85SJeff Kirsher * rxHiReady: entry the NIC has filled to in the Hi receive ring 64ca7a8e85SJeff Kirsher */ 65ca7a8e85SJeff Kirsher struct typhoon_indexes { 66ca7a8e85SJeff Kirsher /* The first four are written by the host, and read by the NIC */ 67ca7a8e85SJeff Kirsher volatile __le32 rxHiCleared; 68ca7a8e85SJeff Kirsher volatile __le32 rxLoCleared; 69ca7a8e85SJeff Kirsher volatile __le32 rxBuffReady; 70ca7a8e85SJeff Kirsher volatile __le32 respCleared; 71ca7a8e85SJeff Kirsher 72ca7a8e85SJeff Kirsher /* The remaining are written by the NIC, and read by the host */ 73ca7a8e85SJeff Kirsher volatile __le32 txLoCleared; 74ca7a8e85SJeff Kirsher volatile __le32 txHiCleared; 75ca7a8e85SJeff Kirsher volatile __le32 rxLoReady; 76ca7a8e85SJeff Kirsher volatile __le32 rxBuffCleared; 77ca7a8e85SJeff Kirsher volatile __le32 cmdCleared; 78ca7a8e85SJeff Kirsher volatile __le32 respReady; 79ca7a8e85SJeff Kirsher volatile __le32 rxHiReady; 80ca7a8e85SJeff Kirsher } __packed; 81ca7a8e85SJeff Kirsher 82ca7a8e85SJeff Kirsher /* The host<->Typhoon interface 83ca7a8e85SJeff Kirsher * Our means of communicating where things are 84ca7a8e85SJeff Kirsher * 85ca7a8e85SJeff Kirsher * All values must be in little endian format for the 3XP 86ca7a8e85SJeff Kirsher * 87ca7a8e85SJeff Kirsher * ringIndex: 64 bit bus address of the index structure 88ca7a8e85SJeff Kirsher * txLoAddr: 64 bit bus address of the Lo transmit ring 89ca7a8e85SJeff Kirsher * txLoSize: size (in bytes) of the Lo transmit ring 90ca7a8e85SJeff Kirsher * txHi*: as above for the Hi priority transmit ring 91ca7a8e85SJeff Kirsher * rxLo*: as above for the Lo priority receive ring 92ca7a8e85SJeff Kirsher * rxBuff*: as above for the free buffer ring 93ca7a8e85SJeff Kirsher * cmd*: as above for the command ring 94ca7a8e85SJeff Kirsher * resp*: as above for the response ring 95ca7a8e85SJeff Kirsher * zeroAddr: 64 bit bus address of a zero word (for DMA) 96ca7a8e85SJeff Kirsher * rxHi*: as above for the Hi Priority receive ring 97ca7a8e85SJeff Kirsher * 98ca7a8e85SJeff Kirsher * While there is room for 64 bit addresses, current versions of the 3XP 99ca7a8e85SJeff Kirsher * only do 32 bit addresses, so the *Hi for each of the above will always 100ca7a8e85SJeff Kirsher * be zero. 101ca7a8e85SJeff Kirsher */ 102ca7a8e85SJeff Kirsher struct typhoon_interface { 103ca7a8e85SJeff Kirsher __le32 ringIndex; 104ca7a8e85SJeff Kirsher __le32 ringIndexHi; 105ca7a8e85SJeff Kirsher __le32 txLoAddr; 106ca7a8e85SJeff Kirsher __le32 txLoAddrHi; 107ca7a8e85SJeff Kirsher __le32 txLoSize; 108ca7a8e85SJeff Kirsher __le32 txHiAddr; 109ca7a8e85SJeff Kirsher __le32 txHiAddrHi; 110ca7a8e85SJeff Kirsher __le32 txHiSize; 111ca7a8e85SJeff Kirsher __le32 rxLoAddr; 112ca7a8e85SJeff Kirsher __le32 rxLoAddrHi; 113ca7a8e85SJeff Kirsher __le32 rxLoSize; 114ca7a8e85SJeff Kirsher __le32 rxBuffAddr; 115ca7a8e85SJeff Kirsher __le32 rxBuffAddrHi; 116ca7a8e85SJeff Kirsher __le32 rxBuffSize; 117ca7a8e85SJeff Kirsher __le32 cmdAddr; 118ca7a8e85SJeff Kirsher __le32 cmdAddrHi; 119ca7a8e85SJeff Kirsher __le32 cmdSize; 120ca7a8e85SJeff Kirsher __le32 respAddr; 121ca7a8e85SJeff Kirsher __le32 respAddrHi; 122ca7a8e85SJeff Kirsher __le32 respSize; 123ca7a8e85SJeff Kirsher __le32 zeroAddr; 124ca7a8e85SJeff Kirsher __le32 zeroAddrHi; 125ca7a8e85SJeff Kirsher __le32 rxHiAddr; 126ca7a8e85SJeff Kirsher __le32 rxHiAddrHi; 127ca7a8e85SJeff Kirsher __le32 rxHiSize; 128ca7a8e85SJeff Kirsher } __packed; 129ca7a8e85SJeff Kirsher 130ca7a8e85SJeff Kirsher /* The Typhoon transmit/fragment descriptor 131ca7a8e85SJeff Kirsher * 132ca7a8e85SJeff Kirsher * A packet is described by a packet descriptor, followed by option descriptors, 133ca7a8e85SJeff Kirsher * if any, then one or more fragment descriptors. 134ca7a8e85SJeff Kirsher * 135ca7a8e85SJeff Kirsher * Packet descriptor: 136ca7a8e85SJeff Kirsher * flags: Descriptor type 137ca7a8e85SJeff Kirsher * len:i zero, or length of this packet 138ca7a8e85SJeff Kirsher * addr*: 8 bytes of opaque data to the firmware -- for skb pointer 139ca7a8e85SJeff Kirsher * processFlags: Determine offload tasks to perform on this packet. 140ca7a8e85SJeff Kirsher * 141ca7a8e85SJeff Kirsher * Fragment descriptor: 142ca7a8e85SJeff Kirsher * flags: Descriptor type 143ca7a8e85SJeff Kirsher * len:i length of this fragment 144ca7a8e85SJeff Kirsher * addr: low bytes of DMA address for this part of the packet 145ca7a8e85SJeff Kirsher * addrHi: hi bytes of DMA address for this part of the packet 146ca7a8e85SJeff Kirsher * processFlags: must be zero 147ca7a8e85SJeff Kirsher * 148ca7a8e85SJeff Kirsher * TYPHOON_DESC_VALID is not mentioned in their docs, but their Linux 149ca7a8e85SJeff Kirsher * driver uses it. 150ca7a8e85SJeff Kirsher */ 151ca7a8e85SJeff Kirsher struct tx_desc { 152ca7a8e85SJeff Kirsher u8 flags; 153ca7a8e85SJeff Kirsher #define TYPHOON_TYPE_MASK 0x07 154ca7a8e85SJeff Kirsher #define TYPHOON_FRAG_DESC 0x00 155ca7a8e85SJeff Kirsher #define TYPHOON_TX_DESC 0x01 156ca7a8e85SJeff Kirsher #define TYPHOON_CMD_DESC 0x02 157ca7a8e85SJeff Kirsher #define TYPHOON_OPT_DESC 0x03 158ca7a8e85SJeff Kirsher #define TYPHOON_RX_DESC 0x04 159ca7a8e85SJeff Kirsher #define TYPHOON_RESP_DESC 0x05 160ca7a8e85SJeff Kirsher #define TYPHOON_OPT_TYPE_MASK 0xf0 161ca7a8e85SJeff Kirsher #define TYPHOON_OPT_IPSEC 0x00 162ca7a8e85SJeff Kirsher #define TYPHOON_OPT_TCP_SEG 0x10 163ca7a8e85SJeff Kirsher #define TYPHOON_CMD_RESPOND 0x40 164ca7a8e85SJeff Kirsher #define TYPHOON_RESP_ERROR 0x40 165ca7a8e85SJeff Kirsher #define TYPHOON_RX_ERROR 0x40 166ca7a8e85SJeff Kirsher #define TYPHOON_DESC_VALID 0x80 167ca7a8e85SJeff Kirsher u8 numDesc; 168ca7a8e85SJeff Kirsher __le16 len; 169ca7a8e85SJeff Kirsher union { 170ca7a8e85SJeff Kirsher struct { 171ca7a8e85SJeff Kirsher __le32 addr; 172ca7a8e85SJeff Kirsher __le32 addrHi; 173ca7a8e85SJeff Kirsher } frag; 174ca7a8e85SJeff Kirsher u64 tx_addr; /* opaque for hardware, for TX_DESC */ 175ca7a8e85SJeff Kirsher }; 176ca7a8e85SJeff Kirsher __le32 processFlags; 177ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_NO_CRC cpu_to_le32(0x00000001) 178ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_IP_CHKSUM cpu_to_le32(0x00000002) 179ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_TCP_CHKSUM cpu_to_le32(0x00000004) 180ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_TCP_SEGMENT cpu_to_le32(0x00000008) 181ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_INSERT_VLAN cpu_to_le32(0x00000010) 182ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_IPSEC cpu_to_le32(0x00000020) 183ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_VLAN_PRIORITY cpu_to_le32(0x00000040) 184ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_UDP_CHKSUM cpu_to_le32(0x00000080) 185ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_PAD_FRAME cpu_to_le32(0x00000100) 186ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_RESERVED cpu_to_le32(0x00000e00) 187ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_VLAN_MASK cpu_to_le32(0x0ffff000) 188ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_INTERNAL cpu_to_le32(0xf0000000) 189ca7a8e85SJeff Kirsher #define TYPHOON_TX_PF_VLAN_TAG_SHIFT 12 190ca7a8e85SJeff Kirsher } __packed; 191ca7a8e85SJeff Kirsher 192ca7a8e85SJeff Kirsher /* The TCP Segmentation offload option descriptor 193ca7a8e85SJeff Kirsher * 194ca7a8e85SJeff Kirsher * flags: descriptor type 195ca7a8e85SJeff Kirsher * numDesc: must be 1 196ca7a8e85SJeff Kirsher * mss_flags: bits 0-11 (little endian) are MSS, 12 is first TSO descriptor 197ca7a8e85SJeff Kirsher * 13 is list TSO descriptor, set both if only one TSO 198ca7a8e85SJeff Kirsher * respAddrLo: low bytes of address of the bytesTx field of this descriptor 199ca7a8e85SJeff Kirsher * bytesTx: total number of bytes in this TSO request 200ca7a8e85SJeff Kirsher * status: 0 on completion 201ca7a8e85SJeff Kirsher */ 202ca7a8e85SJeff Kirsher struct tcpopt_desc { 203ca7a8e85SJeff Kirsher u8 flags; 204ca7a8e85SJeff Kirsher u8 numDesc; 205ca7a8e85SJeff Kirsher __le16 mss_flags; 206ca7a8e85SJeff Kirsher #define TYPHOON_TSO_FIRST cpu_to_le16(0x1000) 207ca7a8e85SJeff Kirsher #define TYPHOON_TSO_LAST cpu_to_le16(0x2000) 208ca7a8e85SJeff Kirsher __le32 respAddrLo; 209ca7a8e85SJeff Kirsher __le32 bytesTx; 210ca7a8e85SJeff Kirsher __le32 status; 211ca7a8e85SJeff Kirsher } __packed; 212ca7a8e85SJeff Kirsher 213ca7a8e85SJeff Kirsher /* The IPSEC Offload descriptor 214ca7a8e85SJeff Kirsher * 215ca7a8e85SJeff Kirsher * flags: descriptor type 216ca7a8e85SJeff Kirsher * numDesc: must be 1 217ca7a8e85SJeff Kirsher * ipsecFlags: bit 0: 0 -- generate IV, 1 -- use supplied IV 218ca7a8e85SJeff Kirsher * sa1, sa2: Security Association IDs for this packet 219ca7a8e85SJeff Kirsher * reserved: set to 0 220ca7a8e85SJeff Kirsher */ 221ca7a8e85SJeff Kirsher struct ipsec_desc { 222ca7a8e85SJeff Kirsher u8 flags; 223ca7a8e85SJeff Kirsher u8 numDesc; 224ca7a8e85SJeff Kirsher __le16 ipsecFlags; 225ca7a8e85SJeff Kirsher #define TYPHOON_IPSEC_GEN_IV cpu_to_le16(0x0000) 226ca7a8e85SJeff Kirsher #define TYPHOON_IPSEC_USE_IV cpu_to_le16(0x0001) 227ca7a8e85SJeff Kirsher __le32 sa1; 228ca7a8e85SJeff Kirsher __le32 sa2; 229ca7a8e85SJeff Kirsher __le32 reserved; 230ca7a8e85SJeff Kirsher } __packed; 231ca7a8e85SJeff Kirsher 232ca7a8e85SJeff Kirsher /* The Typhoon receive descriptor (Updated by NIC) 233ca7a8e85SJeff Kirsher * 234ca7a8e85SJeff Kirsher * flags: Descriptor type, error indication 235ca7a8e85SJeff Kirsher * numDesc: Always zero 236ca7a8e85SJeff Kirsher * frameLen: the size of the packet received 237ca7a8e85SJeff Kirsher * addr: low 32 bytes of the virtual addr passed in for this buffer 238ca7a8e85SJeff Kirsher * addrHi: high 32 bytes of the virtual addr passed in for this buffer 239ca7a8e85SJeff Kirsher * rxStatus: Error if set in flags, otherwise result of offload processing 240ca7a8e85SJeff Kirsher * filterResults: results of filtering on packet, not used 241ca7a8e85SJeff Kirsher * ipsecResults: Results of IPSEC processing 242ca7a8e85SJeff Kirsher * vlanTag: the 801.2q TCI from the packet 243ca7a8e85SJeff Kirsher */ 244ca7a8e85SJeff Kirsher struct rx_desc { 245ca7a8e85SJeff Kirsher u8 flags; 246ca7a8e85SJeff Kirsher u8 numDesc; 247ca7a8e85SJeff Kirsher __le16 frameLen; 248ca7a8e85SJeff Kirsher u32 addr; /* opaque, comes from virtAddr */ 249ca7a8e85SJeff Kirsher u32 addrHi; /* opaque, comes from virtAddrHi */ 250ca7a8e85SJeff Kirsher __le32 rxStatus; 251ca7a8e85SJeff Kirsher #define TYPHOON_RX_ERR_INTERNAL cpu_to_le32(0x00000000) 252ca7a8e85SJeff Kirsher #define TYPHOON_RX_ERR_FIFO_UNDERRUN cpu_to_le32(0x00000001) 253ca7a8e85SJeff Kirsher #define TYPHOON_RX_ERR_BAD_SSD cpu_to_le32(0x00000002) 254ca7a8e85SJeff Kirsher #define TYPHOON_RX_ERR_RUNT cpu_to_le32(0x00000003) 255ca7a8e85SJeff Kirsher #define TYPHOON_RX_ERR_CRC cpu_to_le32(0x00000004) 256ca7a8e85SJeff Kirsher #define TYPHOON_RX_ERR_OVERSIZE cpu_to_le32(0x00000005) 257ca7a8e85SJeff Kirsher #define TYPHOON_RX_ERR_ALIGN cpu_to_le32(0x00000006) 258ca7a8e85SJeff Kirsher #define TYPHOON_RX_ERR_DRIBBLE cpu_to_le32(0x00000007) 259ca7a8e85SJeff Kirsher #define TYPHOON_RX_PROTO_MASK cpu_to_le32(0x00000003) 260ca7a8e85SJeff Kirsher #define TYPHOON_RX_PROTO_UNKNOWN cpu_to_le32(0x00000000) 261ca7a8e85SJeff Kirsher #define TYPHOON_RX_PROTO_IP cpu_to_le32(0x00000001) 262ca7a8e85SJeff Kirsher #define TYPHOON_RX_PROTO_IPX cpu_to_le32(0x00000002) 263ca7a8e85SJeff Kirsher #define TYPHOON_RX_VLAN cpu_to_le32(0x00000004) 264ca7a8e85SJeff Kirsher #define TYPHOON_RX_IP_FRAG cpu_to_le32(0x00000008) 265ca7a8e85SJeff Kirsher #define TYPHOON_RX_IPSEC cpu_to_le32(0x00000010) 266ca7a8e85SJeff Kirsher #define TYPHOON_RX_IP_CHK_FAIL cpu_to_le32(0x00000020) 267ca7a8e85SJeff Kirsher #define TYPHOON_RX_TCP_CHK_FAIL cpu_to_le32(0x00000040) 268ca7a8e85SJeff Kirsher #define TYPHOON_RX_UDP_CHK_FAIL cpu_to_le32(0x00000080) 269ca7a8e85SJeff Kirsher #define TYPHOON_RX_IP_CHK_GOOD cpu_to_le32(0x00000100) 270ca7a8e85SJeff Kirsher #define TYPHOON_RX_TCP_CHK_GOOD cpu_to_le32(0x00000200) 271ca7a8e85SJeff Kirsher #define TYPHOON_RX_UDP_CHK_GOOD cpu_to_le32(0x00000400) 272ca7a8e85SJeff Kirsher __le16 filterResults; 273ca7a8e85SJeff Kirsher #define TYPHOON_RX_FILTER_MASK cpu_to_le16(0x7fff) 274ca7a8e85SJeff Kirsher #define TYPHOON_RX_FILTERED cpu_to_le16(0x8000) 275ca7a8e85SJeff Kirsher __le16 ipsecResults; 276ca7a8e85SJeff Kirsher #define TYPHOON_RX_OUTER_AH_GOOD cpu_to_le16(0x0001) 277ca7a8e85SJeff Kirsher #define TYPHOON_RX_OUTER_ESP_GOOD cpu_to_le16(0x0002) 278ca7a8e85SJeff Kirsher #define TYPHOON_RX_INNER_AH_GOOD cpu_to_le16(0x0004) 279ca7a8e85SJeff Kirsher #define TYPHOON_RX_INNER_ESP_GOOD cpu_to_le16(0x0008) 280ca7a8e85SJeff Kirsher #define TYPHOON_RX_OUTER_AH_FAIL cpu_to_le16(0x0010) 281ca7a8e85SJeff Kirsher #define TYPHOON_RX_OUTER_ESP_FAIL cpu_to_le16(0x0020) 282ca7a8e85SJeff Kirsher #define TYPHOON_RX_INNER_AH_FAIL cpu_to_le16(0x0040) 283ca7a8e85SJeff Kirsher #define TYPHOON_RX_INNER_ESP_FAIL cpu_to_le16(0x0080) 284ca7a8e85SJeff Kirsher #define TYPHOON_RX_UNKNOWN_SA cpu_to_le16(0x0100) 285ca7a8e85SJeff Kirsher #define TYPHOON_RX_ESP_FORMAT_ERR cpu_to_le16(0x0200) 286ca7a8e85SJeff Kirsher __be32 vlanTag; 287ca7a8e85SJeff Kirsher } __packed; 288ca7a8e85SJeff Kirsher 289ca7a8e85SJeff Kirsher /* The Typhoon free buffer descriptor, used to give a buffer to the NIC 290ca7a8e85SJeff Kirsher * 291ca7a8e85SJeff Kirsher * physAddr: low 32 bits of the bus address of the buffer 292ca7a8e85SJeff Kirsher * physAddrHi: high 32 bits of the bus address of the buffer, always zero 293ca7a8e85SJeff Kirsher * virtAddr: low 32 bits of the skb address 294ca7a8e85SJeff Kirsher * virtAddrHi: high 32 bits of the skb address, always zero 295ca7a8e85SJeff Kirsher * 296ca7a8e85SJeff Kirsher * the virt* address is basically two 32 bit cookies, just passed back 297ca7a8e85SJeff Kirsher * from the NIC 298ca7a8e85SJeff Kirsher */ 299ca7a8e85SJeff Kirsher struct rx_free { 300ca7a8e85SJeff Kirsher __le32 physAddr; 301ca7a8e85SJeff Kirsher __le32 physAddrHi; 302ca7a8e85SJeff Kirsher u32 virtAddr; 303ca7a8e85SJeff Kirsher u32 virtAddrHi; 304ca7a8e85SJeff Kirsher } __packed; 305ca7a8e85SJeff Kirsher 306ca7a8e85SJeff Kirsher /* The Typhoon command descriptor, used for commands and responses 307ca7a8e85SJeff Kirsher * 308ca7a8e85SJeff Kirsher * flags: descriptor type 309ca7a8e85SJeff Kirsher * numDesc: number of descriptors following in this command/response, 310ca7a8e85SJeff Kirsher * ie, zero for a one descriptor command 311ca7a8e85SJeff Kirsher * cmd: the command 312ca7a8e85SJeff Kirsher * seqNo: sequence number (unused) 313ca7a8e85SJeff Kirsher * parm1: use varies by command 314ca7a8e85SJeff Kirsher * parm2: use varies by command 315ca7a8e85SJeff Kirsher * parm3: use varies by command 316ca7a8e85SJeff Kirsher */ 317ca7a8e85SJeff Kirsher struct cmd_desc { 318ca7a8e85SJeff Kirsher u8 flags; 319ca7a8e85SJeff Kirsher u8 numDesc; 320ca7a8e85SJeff Kirsher __le16 cmd; 321ca7a8e85SJeff Kirsher #define TYPHOON_CMD_TX_ENABLE cpu_to_le16(0x0001) 322ca7a8e85SJeff Kirsher #define TYPHOON_CMD_TX_DISABLE cpu_to_le16(0x0002) 323ca7a8e85SJeff Kirsher #define TYPHOON_CMD_RX_ENABLE cpu_to_le16(0x0003) 324ca7a8e85SJeff Kirsher #define TYPHOON_CMD_RX_DISABLE cpu_to_le16(0x0004) 325ca7a8e85SJeff Kirsher #define TYPHOON_CMD_SET_RX_FILTER cpu_to_le16(0x0005) 326ca7a8e85SJeff Kirsher #define TYPHOON_CMD_READ_STATS cpu_to_le16(0x0007) 327ca7a8e85SJeff Kirsher #define TYPHOON_CMD_XCVR_SELECT cpu_to_le16(0x0013) 328ca7a8e85SJeff Kirsher #define TYPHOON_CMD_SET_MAX_PKT_SIZE cpu_to_le16(0x001a) 329ca7a8e85SJeff Kirsher #define TYPHOON_CMD_READ_MEDIA_STATUS cpu_to_le16(0x001b) 330ca7a8e85SJeff Kirsher #define TYPHOON_CMD_GOTO_SLEEP cpu_to_le16(0x0023) 331ca7a8e85SJeff Kirsher #define TYPHOON_CMD_SET_MULTICAST_HASH cpu_to_le16(0x0025) 332ca7a8e85SJeff Kirsher #define TYPHOON_CMD_SET_MAC_ADDRESS cpu_to_le16(0x0026) 333ca7a8e85SJeff Kirsher #define TYPHOON_CMD_READ_MAC_ADDRESS cpu_to_le16(0x0027) 334ca7a8e85SJeff Kirsher #define TYPHOON_CMD_VLAN_TYPE_WRITE cpu_to_le16(0x002b) 335ca7a8e85SJeff Kirsher #define TYPHOON_CMD_CREATE_SA cpu_to_le16(0x0034) 336ca7a8e85SJeff Kirsher #define TYPHOON_CMD_DELETE_SA cpu_to_le16(0x0035) 337ca7a8e85SJeff Kirsher #define TYPHOON_CMD_READ_VERSIONS cpu_to_le16(0x0043) 338ca7a8e85SJeff Kirsher #define TYPHOON_CMD_IRQ_COALESCE_CTRL cpu_to_le16(0x0045) 339ca7a8e85SJeff Kirsher #define TYPHOON_CMD_ENABLE_WAKE_EVENTS cpu_to_le16(0x0049) 340ca7a8e85SJeff Kirsher #define TYPHOON_CMD_SET_OFFLOAD_TASKS cpu_to_le16(0x004f) 341ca7a8e85SJeff Kirsher #define TYPHOON_CMD_HELLO_RESP cpu_to_le16(0x0057) 342ca7a8e85SJeff Kirsher #define TYPHOON_CMD_HALT cpu_to_le16(0x005d) 343ca7a8e85SJeff Kirsher #define TYPHOON_CMD_READ_IPSEC_INFO cpu_to_le16(0x005e) 344ca7a8e85SJeff Kirsher #define TYPHOON_CMD_GET_IPSEC_ENABLE cpu_to_le16(0x0067) 345ca7a8e85SJeff Kirsher #define TYPHOON_CMD_GET_CMD_LVL cpu_to_le16(0x0069) 346ca7a8e85SJeff Kirsher u16 seqNo; 347ca7a8e85SJeff Kirsher __le16 parm1; 348ca7a8e85SJeff Kirsher __le32 parm2; 349ca7a8e85SJeff Kirsher __le32 parm3; 350ca7a8e85SJeff Kirsher } __packed; 351ca7a8e85SJeff Kirsher 352ca7a8e85SJeff Kirsher /* The Typhoon response descriptor, see command descriptor for details 353ca7a8e85SJeff Kirsher */ 354ca7a8e85SJeff Kirsher struct resp_desc { 355ca7a8e85SJeff Kirsher u8 flags; 356ca7a8e85SJeff Kirsher u8 numDesc; 357ca7a8e85SJeff Kirsher __le16 cmd; 358ca7a8e85SJeff Kirsher __le16 seqNo; 359ca7a8e85SJeff Kirsher __le16 parm1; 360ca7a8e85SJeff Kirsher __le32 parm2; 361ca7a8e85SJeff Kirsher __le32 parm3; 362ca7a8e85SJeff Kirsher } __packed; 363ca7a8e85SJeff Kirsher 364ca7a8e85SJeff Kirsher #define INIT_COMMAND_NO_RESPONSE(x, command) \ 365ca7a8e85SJeff Kirsher do { struct cmd_desc *_ptr = (x); \ 366ca7a8e85SJeff Kirsher memset(_ptr, 0, sizeof(struct cmd_desc)); \ 367ca7a8e85SJeff Kirsher _ptr->flags = TYPHOON_CMD_DESC | TYPHOON_DESC_VALID; \ 368ca7a8e85SJeff Kirsher _ptr->cmd = command; \ 369ca7a8e85SJeff Kirsher } while (0) 370ca7a8e85SJeff Kirsher 371ca7a8e85SJeff Kirsher /* We set seqNo to 1 if we're expecting a response from this command */ 372ca7a8e85SJeff Kirsher #define INIT_COMMAND_WITH_RESPONSE(x, command) \ 373ca7a8e85SJeff Kirsher do { struct cmd_desc *_ptr = (x); \ 374ca7a8e85SJeff Kirsher memset(_ptr, 0, sizeof(struct cmd_desc)); \ 375ca7a8e85SJeff Kirsher _ptr->flags = TYPHOON_CMD_RESPOND | TYPHOON_CMD_DESC; \ 376ca7a8e85SJeff Kirsher _ptr->flags |= TYPHOON_DESC_VALID; \ 377ca7a8e85SJeff Kirsher _ptr->cmd = command; \ 378ca7a8e85SJeff Kirsher _ptr->seqNo = 1; \ 379ca7a8e85SJeff Kirsher } while (0) 380ca7a8e85SJeff Kirsher 381ca7a8e85SJeff Kirsher /* TYPHOON_CMD_SET_RX_FILTER filter bits (cmd.parm1) 382ca7a8e85SJeff Kirsher */ 383ca7a8e85SJeff Kirsher #define TYPHOON_RX_FILTER_DIRECTED cpu_to_le16(0x0001) 384ca7a8e85SJeff Kirsher #define TYPHOON_RX_FILTER_ALL_MCAST cpu_to_le16(0x0002) 385ca7a8e85SJeff Kirsher #define TYPHOON_RX_FILTER_BROADCAST cpu_to_le16(0x0004) 386ca7a8e85SJeff Kirsher #define TYPHOON_RX_FILTER_PROMISCOUS cpu_to_le16(0x0008) 387ca7a8e85SJeff Kirsher #define TYPHOON_RX_FILTER_MCAST_HASH cpu_to_le16(0x0010) 388ca7a8e85SJeff Kirsher 389ca7a8e85SJeff Kirsher /* TYPHOON_CMD_READ_STATS response format 390ca7a8e85SJeff Kirsher */ 391ca7a8e85SJeff Kirsher struct stats_resp { 392ca7a8e85SJeff Kirsher u8 flags; 393ca7a8e85SJeff Kirsher u8 numDesc; 394ca7a8e85SJeff Kirsher __le16 cmd; 395ca7a8e85SJeff Kirsher __le16 seqNo; 396ca7a8e85SJeff Kirsher __le16 unused; 397ca7a8e85SJeff Kirsher __le32 txPackets; 398ca7a8e85SJeff Kirsher __le64 txBytes; 399ca7a8e85SJeff Kirsher __le32 txDeferred; 400ca7a8e85SJeff Kirsher __le32 txLateCollisions; 401ca7a8e85SJeff Kirsher __le32 txCollisions; 402ca7a8e85SJeff Kirsher __le32 txCarrierLost; 403ca7a8e85SJeff Kirsher __le32 txMultipleCollisions; 404ca7a8e85SJeff Kirsher __le32 txExcessiveCollisions; 405ca7a8e85SJeff Kirsher __le32 txFifoUnderruns; 406ca7a8e85SJeff Kirsher __le32 txMulticastTxOverflows; 407ca7a8e85SJeff Kirsher __le32 txFiltered; 408ca7a8e85SJeff Kirsher __le32 rxPacketsGood; 409ca7a8e85SJeff Kirsher __le64 rxBytesGood; 410ca7a8e85SJeff Kirsher __le32 rxFifoOverruns; 411ca7a8e85SJeff Kirsher __le32 BadSSD; 412ca7a8e85SJeff Kirsher __le32 rxCrcErrors; 413ca7a8e85SJeff Kirsher __le32 rxOversized; 414ca7a8e85SJeff Kirsher __le32 rxBroadcast; 415ca7a8e85SJeff Kirsher __le32 rxMulticast; 416ca7a8e85SJeff Kirsher __le32 rxOverflow; 417ca7a8e85SJeff Kirsher __le32 rxFiltered; 418ca7a8e85SJeff Kirsher __le32 linkStatus; 419ca7a8e85SJeff Kirsher #define TYPHOON_LINK_STAT_MASK cpu_to_le32(0x00000001) 420ca7a8e85SJeff Kirsher #define TYPHOON_LINK_GOOD cpu_to_le32(0x00000001) 421ca7a8e85SJeff Kirsher #define TYPHOON_LINK_BAD cpu_to_le32(0x00000000) 422ca7a8e85SJeff Kirsher #define TYPHOON_LINK_SPEED_MASK cpu_to_le32(0x00000002) 423ca7a8e85SJeff Kirsher #define TYPHOON_LINK_100MBPS cpu_to_le32(0x00000002) 424ca7a8e85SJeff Kirsher #define TYPHOON_LINK_10MBPS cpu_to_le32(0x00000000) 425ca7a8e85SJeff Kirsher #define TYPHOON_LINK_DUPLEX_MASK cpu_to_le32(0x00000004) 426ca7a8e85SJeff Kirsher #define TYPHOON_LINK_FULL_DUPLEX cpu_to_le32(0x00000004) 427ca7a8e85SJeff Kirsher #define TYPHOON_LINK_HALF_DUPLEX cpu_to_le32(0x00000000) 428ca7a8e85SJeff Kirsher __le32 unused2; 429ca7a8e85SJeff Kirsher __le32 unused3; 430ca7a8e85SJeff Kirsher } __packed; 431ca7a8e85SJeff Kirsher 432ca7a8e85SJeff Kirsher /* TYPHOON_CMD_XCVR_SELECT xcvr values (resp.parm1) 433ca7a8e85SJeff Kirsher */ 434ca7a8e85SJeff Kirsher #define TYPHOON_XCVR_10HALF cpu_to_le16(0x0000) 435ca7a8e85SJeff Kirsher #define TYPHOON_XCVR_10FULL cpu_to_le16(0x0001) 436ca7a8e85SJeff Kirsher #define TYPHOON_XCVR_100HALF cpu_to_le16(0x0002) 437ca7a8e85SJeff Kirsher #define TYPHOON_XCVR_100FULL cpu_to_le16(0x0003) 438ca7a8e85SJeff Kirsher #define TYPHOON_XCVR_AUTONEG cpu_to_le16(0x0004) 439ca7a8e85SJeff Kirsher 440ca7a8e85SJeff Kirsher /* TYPHOON_CMD_READ_MEDIA_STATUS (resp.parm1) 441ca7a8e85SJeff Kirsher */ 442ca7a8e85SJeff Kirsher #define TYPHOON_MEDIA_STAT_CRC_STRIP_DISABLE cpu_to_le16(0x0004) 443ca7a8e85SJeff Kirsher #define TYPHOON_MEDIA_STAT_COLLISION_DETECT cpu_to_le16(0x0010) 444ca7a8e85SJeff Kirsher #define TYPHOON_MEDIA_STAT_CARRIER_SENSE cpu_to_le16(0x0020) 445ca7a8e85SJeff Kirsher #define TYPHOON_MEDIA_STAT_POLARITY_REV cpu_to_le16(0x0400) 446ca7a8e85SJeff Kirsher #define TYPHOON_MEDIA_STAT_NO_LINK cpu_to_le16(0x0800) 447ca7a8e85SJeff Kirsher 448ca7a8e85SJeff Kirsher /* TYPHOON_CMD_SET_MULTICAST_HASH enable values (cmd.parm1) 449ca7a8e85SJeff Kirsher */ 450ca7a8e85SJeff Kirsher #define TYPHOON_MCAST_HASH_DISABLE cpu_to_le16(0x0000) 451ca7a8e85SJeff Kirsher #define TYPHOON_MCAST_HASH_ENABLE cpu_to_le16(0x0001) 452ca7a8e85SJeff Kirsher #define TYPHOON_MCAST_HASH_SET cpu_to_le16(0x0002) 453ca7a8e85SJeff Kirsher 454ca7a8e85SJeff Kirsher /* TYPHOON_CMD_CREATE_SA descriptor and settings 455ca7a8e85SJeff Kirsher */ 456ca7a8e85SJeff Kirsher struct sa_descriptor { 457ca7a8e85SJeff Kirsher u8 flags; 458ca7a8e85SJeff Kirsher u8 numDesc; 459ca7a8e85SJeff Kirsher u16 cmd; 460ca7a8e85SJeff Kirsher u16 seqNo; 461ca7a8e85SJeff Kirsher u16 mode; 462ca7a8e85SJeff Kirsher #define TYPHOON_SA_MODE_NULL cpu_to_le16(0x0000) 463ca7a8e85SJeff Kirsher #define TYPHOON_SA_MODE_AH cpu_to_le16(0x0001) 464ca7a8e85SJeff Kirsher #define TYPHOON_SA_MODE_ESP cpu_to_le16(0x0002) 465ca7a8e85SJeff Kirsher u8 hashFlags; 466ca7a8e85SJeff Kirsher #define TYPHOON_SA_HASH_ENABLE 0x01 467ca7a8e85SJeff Kirsher #define TYPHOON_SA_HASH_SHA1 0x02 468ca7a8e85SJeff Kirsher #define TYPHOON_SA_HASH_MD5 0x04 469ca7a8e85SJeff Kirsher u8 direction; 470ca7a8e85SJeff Kirsher #define TYPHOON_SA_DIR_RX 0x00 471ca7a8e85SJeff Kirsher #define TYPHOON_SA_DIR_TX 0x01 472ca7a8e85SJeff Kirsher u8 encryptionFlags; 473ca7a8e85SJeff Kirsher #define TYPHOON_SA_ENCRYPT_ENABLE 0x01 474ca7a8e85SJeff Kirsher #define TYPHOON_SA_ENCRYPT_DES 0x02 475ca7a8e85SJeff Kirsher #define TYPHOON_SA_ENCRYPT_3DES 0x00 476ca7a8e85SJeff Kirsher #define TYPHOON_SA_ENCRYPT_3DES_2KEY 0x00 477ca7a8e85SJeff Kirsher #define TYPHOON_SA_ENCRYPT_3DES_3KEY 0x04 478ca7a8e85SJeff Kirsher #define TYPHOON_SA_ENCRYPT_CBC 0x08 479ca7a8e85SJeff Kirsher #define TYPHOON_SA_ENCRYPT_ECB 0x00 480ca7a8e85SJeff Kirsher u8 specifyIndex; 481ca7a8e85SJeff Kirsher #define TYPHOON_SA_SPECIFY_INDEX 0x01 482ca7a8e85SJeff Kirsher #define TYPHOON_SA_GENERATE_INDEX 0x00 483ca7a8e85SJeff Kirsher u32 SPI; 484ca7a8e85SJeff Kirsher u32 destAddr; 485ca7a8e85SJeff Kirsher u32 destMask; 486ca7a8e85SJeff Kirsher u8 integKey[20]; 487ca7a8e85SJeff Kirsher u8 confKey[24]; 488ca7a8e85SJeff Kirsher u32 index; 489ca7a8e85SJeff Kirsher u32 unused; 490ca7a8e85SJeff Kirsher u32 unused2; 491ca7a8e85SJeff Kirsher } __packed; 492ca7a8e85SJeff Kirsher 493ca7a8e85SJeff Kirsher /* TYPHOON_CMD_SET_OFFLOAD_TASKS bits (cmd.parm2 (Tx) & cmd.parm3 (Rx)) 494ca7a8e85SJeff Kirsher * This is all for IPv4. 495ca7a8e85SJeff Kirsher */ 496ca7a8e85SJeff Kirsher #define TYPHOON_OFFLOAD_TCP_CHKSUM cpu_to_le32(0x00000002) 497ca7a8e85SJeff Kirsher #define TYPHOON_OFFLOAD_UDP_CHKSUM cpu_to_le32(0x00000004) 498ca7a8e85SJeff Kirsher #define TYPHOON_OFFLOAD_IP_CHKSUM cpu_to_le32(0x00000008) 499ca7a8e85SJeff Kirsher #define TYPHOON_OFFLOAD_IPSEC cpu_to_le32(0x00000010) 500ca7a8e85SJeff Kirsher #define TYPHOON_OFFLOAD_BCAST_THROTTLE cpu_to_le32(0x00000020) 501ca7a8e85SJeff Kirsher #define TYPHOON_OFFLOAD_DHCP_PREVENT cpu_to_le32(0x00000040) 502ca7a8e85SJeff Kirsher #define TYPHOON_OFFLOAD_VLAN cpu_to_le32(0x00000080) 503ca7a8e85SJeff Kirsher #define TYPHOON_OFFLOAD_FILTERING cpu_to_le32(0x00000100) 504ca7a8e85SJeff Kirsher #define TYPHOON_OFFLOAD_TCP_SEGMENT cpu_to_le32(0x00000200) 505ca7a8e85SJeff Kirsher 506ca7a8e85SJeff Kirsher /* TYPHOON_CMD_ENABLE_WAKE_EVENTS bits (cmd.parm1) 507ca7a8e85SJeff Kirsher */ 508ca7a8e85SJeff Kirsher #define TYPHOON_WAKE_MAGIC_PKT cpu_to_le16(0x01) 509ca7a8e85SJeff Kirsher #define TYPHOON_WAKE_LINK_EVENT cpu_to_le16(0x02) 510ca7a8e85SJeff Kirsher #define TYPHOON_WAKE_ICMP_ECHO cpu_to_le16(0x04) 511ca7a8e85SJeff Kirsher #define TYPHOON_WAKE_ARP cpu_to_le16(0x08) 512ca7a8e85SJeff Kirsher 513ca7a8e85SJeff Kirsher /* These are used to load the firmware image on the NIC 514ca7a8e85SJeff Kirsher */ 515ca7a8e85SJeff Kirsher struct typhoon_file_header { 516ca7a8e85SJeff Kirsher u8 tag[8]; 517ca7a8e85SJeff Kirsher __le32 version; 518ca7a8e85SJeff Kirsher __le32 numSections; 519ca7a8e85SJeff Kirsher __le32 startAddr; 520ca7a8e85SJeff Kirsher __le32 hmacDigest[5]; 521ca7a8e85SJeff Kirsher } __packed; 522ca7a8e85SJeff Kirsher 523ca7a8e85SJeff Kirsher struct typhoon_section_header { 524ca7a8e85SJeff Kirsher __le32 len; 525ca7a8e85SJeff Kirsher u16 checksum; 526ca7a8e85SJeff Kirsher u16 reserved; 527ca7a8e85SJeff Kirsher __le32 startAddr; 528ca7a8e85SJeff Kirsher } __packed; 529ca7a8e85SJeff Kirsher 530ca7a8e85SJeff Kirsher /* The Typhoon Register offsets 531ca7a8e85SJeff Kirsher */ 532ca7a8e85SJeff Kirsher #define TYPHOON_REG_SOFT_RESET 0x00 533ca7a8e85SJeff Kirsher #define TYPHOON_REG_INTR_STATUS 0x04 534ca7a8e85SJeff Kirsher #define TYPHOON_REG_INTR_ENABLE 0x08 535ca7a8e85SJeff Kirsher #define TYPHOON_REG_INTR_MASK 0x0c 536ca7a8e85SJeff Kirsher #define TYPHOON_REG_SELF_INTERRUPT 0x10 537ca7a8e85SJeff Kirsher #define TYPHOON_REG_HOST2ARM7 0x14 538ca7a8e85SJeff Kirsher #define TYPHOON_REG_HOST2ARM6 0x18 539ca7a8e85SJeff Kirsher #define TYPHOON_REG_HOST2ARM5 0x1c 540ca7a8e85SJeff Kirsher #define TYPHOON_REG_HOST2ARM4 0x20 541ca7a8e85SJeff Kirsher #define TYPHOON_REG_HOST2ARM3 0x24 542ca7a8e85SJeff Kirsher #define TYPHOON_REG_HOST2ARM2 0x28 543ca7a8e85SJeff Kirsher #define TYPHOON_REG_HOST2ARM1 0x2c 544ca7a8e85SJeff Kirsher #define TYPHOON_REG_HOST2ARM0 0x30 545ca7a8e85SJeff Kirsher #define TYPHOON_REG_ARM2HOST3 0x34 546ca7a8e85SJeff Kirsher #define TYPHOON_REG_ARM2HOST2 0x38 547ca7a8e85SJeff Kirsher #define TYPHOON_REG_ARM2HOST1 0x3c 548ca7a8e85SJeff Kirsher #define TYPHOON_REG_ARM2HOST0 0x40 549ca7a8e85SJeff Kirsher 550ca7a8e85SJeff Kirsher #define TYPHOON_REG_BOOT_DATA_LO TYPHOON_REG_HOST2ARM5 551ca7a8e85SJeff Kirsher #define TYPHOON_REG_BOOT_DATA_HI TYPHOON_REG_HOST2ARM4 552ca7a8e85SJeff Kirsher #define TYPHOON_REG_BOOT_DEST_ADDR TYPHOON_REG_HOST2ARM3 553ca7a8e85SJeff Kirsher #define TYPHOON_REG_BOOT_CHECKSUM TYPHOON_REG_HOST2ARM2 554ca7a8e85SJeff Kirsher #define TYPHOON_REG_BOOT_LENGTH TYPHOON_REG_HOST2ARM1 555ca7a8e85SJeff Kirsher 556ca7a8e85SJeff Kirsher #define TYPHOON_REG_DOWNLOAD_BOOT_ADDR TYPHOON_REG_HOST2ARM1 557ca7a8e85SJeff Kirsher #define TYPHOON_REG_DOWNLOAD_HMAC_0 TYPHOON_REG_HOST2ARM2 558ca7a8e85SJeff Kirsher #define TYPHOON_REG_DOWNLOAD_HMAC_1 TYPHOON_REG_HOST2ARM3 559ca7a8e85SJeff Kirsher #define TYPHOON_REG_DOWNLOAD_HMAC_2 TYPHOON_REG_HOST2ARM4 560ca7a8e85SJeff Kirsher #define TYPHOON_REG_DOWNLOAD_HMAC_3 TYPHOON_REG_HOST2ARM5 561ca7a8e85SJeff Kirsher #define TYPHOON_REG_DOWNLOAD_HMAC_4 TYPHOON_REG_HOST2ARM6 562ca7a8e85SJeff Kirsher 563ca7a8e85SJeff Kirsher #define TYPHOON_REG_BOOT_RECORD_ADDR_HI TYPHOON_REG_HOST2ARM2 564ca7a8e85SJeff Kirsher #define TYPHOON_REG_BOOT_RECORD_ADDR_LO TYPHOON_REG_HOST2ARM1 565ca7a8e85SJeff Kirsher 566ca7a8e85SJeff Kirsher #define TYPHOON_REG_TX_LO_READY TYPHOON_REG_HOST2ARM3 567ca7a8e85SJeff Kirsher #define TYPHOON_REG_CMD_READY TYPHOON_REG_HOST2ARM2 568ca7a8e85SJeff Kirsher #define TYPHOON_REG_TX_HI_READY TYPHOON_REG_HOST2ARM1 569ca7a8e85SJeff Kirsher 570ca7a8e85SJeff Kirsher #define TYPHOON_REG_COMMAND TYPHOON_REG_HOST2ARM0 571ca7a8e85SJeff Kirsher #define TYPHOON_REG_HEARTBEAT TYPHOON_REG_ARM2HOST3 572ca7a8e85SJeff Kirsher #define TYPHOON_REG_STATUS TYPHOON_REG_ARM2HOST0 573ca7a8e85SJeff Kirsher 574ca7a8e85SJeff Kirsher /* 3XP Reset values (TYPHOON_REG_SOFT_RESET) 575ca7a8e85SJeff Kirsher */ 576ca7a8e85SJeff Kirsher #define TYPHOON_RESET_ALL 0x7f 577ca7a8e85SJeff Kirsher #define TYPHOON_RESET_NONE 0x00 578ca7a8e85SJeff Kirsher 579ca7a8e85SJeff Kirsher /* 3XP irq bits (TYPHOON_REG_INTR{STATUS,ENABLE,MASK}) 580ca7a8e85SJeff Kirsher * 581ca7a8e85SJeff Kirsher * Some of these came from OpenBSD, as the 3Com docs have it wrong 582ca7a8e85SJeff Kirsher * (INTR_SELF) or don't list it at all (INTR_*_ABORT) 583ca7a8e85SJeff Kirsher * 584ca7a8e85SJeff Kirsher * Enabling irqs on the Heartbeat reg (ArmToHost3) gets you an irq 585ca7a8e85SJeff Kirsher * about every 8ms, so don't do it. 586ca7a8e85SJeff Kirsher */ 587ca7a8e85SJeff Kirsher #define TYPHOON_INTR_HOST_INT 0x00000001 588ca7a8e85SJeff Kirsher #define TYPHOON_INTR_ARM2HOST0 0x00000002 589ca7a8e85SJeff Kirsher #define TYPHOON_INTR_ARM2HOST1 0x00000004 590ca7a8e85SJeff Kirsher #define TYPHOON_INTR_ARM2HOST2 0x00000008 591ca7a8e85SJeff Kirsher #define TYPHOON_INTR_ARM2HOST3 0x00000010 592ca7a8e85SJeff Kirsher #define TYPHOON_INTR_DMA0 0x00000020 593ca7a8e85SJeff Kirsher #define TYPHOON_INTR_DMA1 0x00000040 594ca7a8e85SJeff Kirsher #define TYPHOON_INTR_DMA2 0x00000080 595ca7a8e85SJeff Kirsher #define TYPHOON_INTR_DMA3 0x00000100 596ca7a8e85SJeff Kirsher #define TYPHOON_INTR_MASTER_ABORT 0x00000200 597ca7a8e85SJeff Kirsher #define TYPHOON_INTR_TARGET_ABORT 0x00000400 598ca7a8e85SJeff Kirsher #define TYPHOON_INTR_SELF 0x00000800 599ca7a8e85SJeff Kirsher #define TYPHOON_INTR_RESERVED 0xfffff000 600ca7a8e85SJeff Kirsher 601ca7a8e85SJeff Kirsher #define TYPHOON_INTR_BOOTCMD TYPHOON_INTR_ARM2HOST0 602ca7a8e85SJeff Kirsher 603ca7a8e85SJeff Kirsher #define TYPHOON_INTR_ENABLE_ALL 0xffffffef 604ca7a8e85SJeff Kirsher #define TYPHOON_INTR_ALL 0xffffffff 605ca7a8e85SJeff Kirsher #define TYPHOON_INTR_NONE 0x00000000 606ca7a8e85SJeff Kirsher 607ca7a8e85SJeff Kirsher /* The commands for the 3XP chip (TYPHOON_REG_COMMAND) 608ca7a8e85SJeff Kirsher */ 609ca7a8e85SJeff Kirsher #define TYPHOON_BOOTCMD_BOOT 0x00 610ca7a8e85SJeff Kirsher #define TYPHOON_BOOTCMD_WAKEUP 0xfa 611ca7a8e85SJeff Kirsher #define TYPHOON_BOOTCMD_DNLD_COMPLETE 0xfb 612ca7a8e85SJeff Kirsher #define TYPHOON_BOOTCMD_SEG_AVAILABLE 0xfc 613ca7a8e85SJeff Kirsher #define TYPHOON_BOOTCMD_RUNTIME_IMAGE 0xfd 614ca7a8e85SJeff Kirsher #define TYPHOON_BOOTCMD_REG_BOOT_RECORD 0xff 615ca7a8e85SJeff Kirsher 616ca7a8e85SJeff Kirsher /* 3XP Status values (TYPHOON_REG_STATUS) 617ca7a8e85SJeff Kirsher */ 618ca7a8e85SJeff Kirsher #define TYPHOON_STATUS_WAITING_FOR_BOOT 0x07 619ca7a8e85SJeff Kirsher #define TYPHOON_STATUS_SECOND_INIT 0x08 620ca7a8e85SJeff Kirsher #define TYPHOON_STATUS_RUNNING 0x09 621ca7a8e85SJeff Kirsher #define TYPHOON_STATUS_WAITING_FOR_HOST 0x0d 622ca7a8e85SJeff Kirsher #define TYPHOON_STATUS_WAITING_FOR_SEGMENT 0x10 623ca7a8e85SJeff Kirsher #define TYPHOON_STATUS_SLEEPING 0x11 624ca7a8e85SJeff Kirsher #define TYPHOON_STATUS_HALTED 0x14 625