1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */ 2 /* 3 Written 1996-1999 by Donald Becker. 4 5 This software may be used and distributed according to the terms 6 of the GNU General Public License, incorporated herein by reference. 7 8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards. 9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597 10 and the EtherLink XL 3c900 and 3c905 cards. 11 12 Problem reports and questions should be directed to 13 vortex@scyld.com 14 15 The author may be reached as becker@scyld.com, or C/O 16 Scyld Computing Corporation 17 410 Severn Ave., Suite 210 18 Annapolis MD 21403 19 20 */ 21 22 /* 23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation 24 * as well as other drivers 25 * 26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k 27 * due to dead code elimination. There will be some performance benefits from this due to 28 * elimination of all the tests and reduced cache footprint. 29 */ 30 31 32 #define DRV_NAME "3c59x" 33 34 35 36 /* A few values that may be tweaked. */ 37 /* Keep the ring sizes a power of two for efficiency. */ 38 #define TX_RING_SIZE 16 39 #define RX_RING_SIZE 32 40 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ 41 42 /* "Knobs" that adjust features and parameters. */ 43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. 44 Setting to > 1512 effectively disables this feature. */ 45 #ifndef __arm__ 46 static int rx_copybreak = 200; 47 #else 48 /* ARM systems perform better by disregarding the bus-master 49 transfer capability of these cards. -- rmk */ 50 static int rx_copybreak = 1513; 51 #endif 52 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */ 53 static const int mtu = 1500; 54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ 55 static int max_interrupt_work = 32; 56 /* Tx timeout interval (millisecs) */ 57 static int watchdog = 5000; 58 59 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost 60 * of possible Tx stalls if the system is blocking interrupts 61 * somewhere else. Undefine this to disable. 62 */ 63 #define tx_interrupt_mitigation 1 64 65 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */ 66 #define vortex_debug debug 67 #ifdef VORTEX_DEBUG 68 static int vortex_debug = VORTEX_DEBUG; 69 #else 70 static int vortex_debug = 1; 71 #endif 72 73 #include <linux/module.h> 74 #include <linux/kernel.h> 75 #include <linux/string.h> 76 #include <linux/timer.h> 77 #include <linux/errno.h> 78 #include <linux/in.h> 79 #include <linux/ioport.h> 80 #include <linux/interrupt.h> 81 #include <linux/pci.h> 82 #include <linux/mii.h> 83 #include <linux/init.h> 84 #include <linux/netdevice.h> 85 #include <linux/etherdevice.h> 86 #include <linux/skbuff.h> 87 #include <linux/ethtool.h> 88 #include <linux/highmem.h> 89 #include <linux/eisa.h> 90 #include <linux/bitops.h> 91 #include <linux/jiffies.h> 92 #include <linux/gfp.h> 93 #include <asm/irq.h> /* For nr_irqs only. */ 94 #include <asm/io.h> 95 #include <asm/uaccess.h> 96 97 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. 98 This is only in the support-all-kernels source code. */ 99 100 #define RUN_AT(x) (jiffies + (x)) 101 102 #include <linux/delay.h> 103 104 105 static const char version[] = 106 DRV_NAME ": Donald Becker and others.\n"; 107 108 MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); 109 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver "); 110 MODULE_LICENSE("GPL"); 111 112 113 /* Operational parameter that usually are not changed. */ 114 115 /* The Vortex size is twice that of the original EtherLinkIII series: the 116 runtime register window, window 1, is now always mapped in. 117 The Boomerang size is twice as large as the Vortex -- it has additional 118 bus master control registers. */ 119 #define VORTEX_TOTAL_SIZE 0x20 120 #define BOOMERANG_TOTAL_SIZE 0x40 121 122 /* Set iff a MII transceiver on any interface requires mdio preamble. 123 This only set with the original DP83840 on older 3c905 boards, so the extra 124 code size of a per-interface flag is not worthwhile. */ 125 static char mii_preamble_required; 126 127 #define PFX DRV_NAME ": " 128 129 130 131 /* 132 Theory of Operation 133 134 I. Board Compatibility 135 136 This device driver is designed for the 3Com FastEtherLink and FastEtherLink 137 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs 138 versions of the FastEtherLink cards. The supported product IDs are 139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905 140 141 The related ISA 3c515 is supported with a separate driver, 3c515.c, included 142 with the kernel source or available from 143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html 144 145 II. Board-specific settings 146 147 PCI bus devices are configured by the system at boot time, so no jumpers 148 need to be set on the board. The system BIOS should be set to assign the 149 PCI INTA signal to an otherwise unused system IRQ line. 150 151 The EEPROM settings for media type and forced-full-duplex are observed. 152 The EEPROM media type should be left at the default "autoselect" unless using 153 10base2 or AUI connections which cannot be reliably detected. 154 155 III. Driver operation 156 157 The 3c59x series use an interface that's very similar to the previous 3c5x9 158 series. The primary interface is two programmed-I/O FIFOs, with an 159 alternate single-contiguous-region bus-master transfer (see next). 160 161 The 3c900 "Boomerang" series uses a full-bus-master interface with separate 162 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet, 163 DEC Tulip and Intel Speedo3. The first chip version retains a compatible 164 programmed-I/O interface that has been removed in 'B' and subsequent board 165 revisions. 166 167 One extension that is advertised in a very large font is that the adapters 168 are capable of being bus masters. On the Vortex chip this capability was 169 only for a single contiguous region making it far less useful than the full 170 bus master capability. There is a significant performance impact of taking 171 an extra interrupt or polling for the completion of each transfer, as well 172 as difficulty sharing the single transfer engine between the transmit and 173 receive threads. Using DMA transfers is a win only with large blocks or 174 with the flawed versions of the Intel Orion motherboard PCI controller. 175 176 The Boomerang chip's full-bus-master interface is useful, and has the 177 currently-unused advantages over other similar chips that queued transmit 178 packets may be reordered and receive buffer groups are associated with a 179 single frame. 180 181 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme. 182 Rather than a fixed intermediate receive buffer, this scheme allocates 183 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as 184 the copying breakpoint: it is chosen to trade-off the memory wasted by 185 passing the full-sized skbuff to the queue layer for all frames vs. the 186 copying cost of copying a frame to a correctly-sized skbuff. 187 188 IIIC. Synchronization 189 The driver runs as two independent, single-threaded flows of control. One 190 is the send-packet routine, which enforces single-threaded use by the 191 dev->tbusy flag. The other thread is the interrupt handler, which is single 192 threaded by the hardware and other software. 193 194 IV. Notes 195 196 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development 197 3c590, 3c595, and 3c900 boards. 198 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and 199 the EISA version is called "Demon". According to Terry these names come 200 from rides at the local amusement park. 201 202 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes! 203 This driver only supports ethernet packets because of the skbuff allocation 204 limit of 4K. 205 */ 206 207 /* This table drives the PCI probe routines. It's mostly boilerplate in all 208 of the drivers, and will likely be provided by some future kernel. 209 */ 210 enum pci_flags_bit { 211 PCI_USES_MASTER=4, 212 }; 213 214 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8, 215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */ 216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100, 217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800, 218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000, 219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, }; 220 221 enum vortex_chips { 222 CH_3C590 = 0, 223 CH_3C592, 224 CH_3C597, 225 CH_3C595_1, 226 CH_3C595_2, 227 228 CH_3C595_3, 229 CH_3C900_1, 230 CH_3C900_2, 231 CH_3C900_3, 232 CH_3C900_4, 233 234 CH_3C900_5, 235 CH_3C900B_FL, 236 CH_3C905_1, 237 CH_3C905_2, 238 CH_3C905B_TX, 239 CH_3C905B_1, 240 241 CH_3C905B_2, 242 CH_3C905B_FX, 243 CH_3C905C, 244 CH_3C9202, 245 CH_3C980, 246 CH_3C9805, 247 248 CH_3CSOHO100_TX, 249 CH_3C555, 250 CH_3C556, 251 CH_3C556B, 252 CH_3C575, 253 254 CH_3C575_1, 255 CH_3CCFE575, 256 CH_3CCFE575CT, 257 CH_3CCFE656, 258 CH_3CCFEM656, 259 260 CH_3CCFEM656_1, 261 CH_3C450, 262 CH_3C920, 263 CH_3C982A, 264 CH_3C982B, 265 266 CH_905BT4, 267 CH_920B_EMB_WNM, 268 }; 269 270 271 /* note: this array directly indexed by above enums, and MUST 272 * be kept in sync with both the enums above, and the PCI device 273 * table below 274 */ 275 static struct vortex_chip_info { 276 const char *name; 277 int flags; 278 int drv_flags; 279 int io_size; 280 } vortex_info_tbl[] = { 281 {"3c590 Vortex 10Mbps", 282 PCI_USES_MASTER, IS_VORTEX, 32, }, 283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */ 284 PCI_USES_MASTER, IS_VORTEX, 32, }, 285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */ 286 PCI_USES_MASTER, IS_VORTEX, 32, }, 287 {"3c595 Vortex 100baseTx", 288 PCI_USES_MASTER, IS_VORTEX, 32, }, 289 {"3c595 Vortex 100baseT4", 290 PCI_USES_MASTER, IS_VORTEX, 32, }, 291 292 {"3c595 Vortex 100base-MII", 293 PCI_USES_MASTER, IS_VORTEX, 32, }, 294 {"3c900 Boomerang 10baseT", 295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, }, 296 {"3c900 Boomerang 10Mbps Combo", 297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, }, 298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */ 299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, }, 300 {"3c900 Cyclone 10Mbps Combo", 301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, }, 302 303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */ 304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, }, 305 {"3c900B-FL Cyclone 10base-FL", 306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, }, 307 {"3c905 Boomerang 100baseTx", 308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, }, 309 {"3c905 Boomerang 100baseT4", 310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, }, 311 {"3C905B-TX Fast Etherlink XL PCI", 312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, 313 {"3c905B Cyclone 100baseTx", 314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, 315 316 {"3c905B Cyclone 10/100/BNC", 317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, }, 318 {"3c905B-FX Cyclone 100baseFx", 319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, }, 320 {"3c905C Tornado", 321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, 322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)", 323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, }, 324 {"3c980 Cyclone", 325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, 326 327 {"3c980C Python-T", 328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, }, 329 {"3cSOHO100-TX Hurricane", 330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, 331 {"3c555 Laptop Hurricane", 332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, }, 333 {"3c556 Laptop Tornado", 334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR| 335 HAS_HWCKSM, 128, }, 336 {"3c556B Laptop Hurricane", 337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR| 338 WNO_XCVR_PWR|HAS_HWCKSM, 128, }, 339 340 {"3c575 [Megahertz] 10/100 LAN CardBus", 341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, }, 342 {"3c575 Boomerang CardBus", 343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, }, 344 {"3CCFE575BT Cyclone CardBus", 345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT| 346 INVERT_LED_PWR|HAS_HWCKSM, 128, }, 347 {"3CCFE575CT Tornado CardBus", 348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR| 349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, }, 350 {"3CCFE656 Cyclone CardBus", 351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR| 352 INVERT_LED_PWR|HAS_HWCKSM, 128, }, 353 354 {"3CCFEM656B Cyclone+Winmodem CardBus", 355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR| 356 INVERT_LED_PWR|HAS_HWCKSM, 128, }, 357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */ 358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR| 359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, }, 360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */ 361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, }, 362 {"3c920 Tornado", 363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, }, 364 {"3c982 Hydra Dual Port A", 365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, }, 366 367 {"3c982 Hydra Dual Port B", 368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, }, 369 {"3c905B-T4", 370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, }, 371 {"3c920B-EMB-WNM Tornado", 372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, }, 373 374 {NULL,}, /* NULL terminated list. */ 375 }; 376 377 378 static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = { 379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 }, 380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 }, 381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 }, 382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 }, 383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 }, 384 385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 }, 386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 }, 387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 }, 388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 }, 389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 }, 390 391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 }, 392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL }, 393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 }, 394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 }, 395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX }, 396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 }, 397 398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 }, 399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX }, 400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C }, 401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 }, 402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 }, 403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 }, 404 405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX }, 406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 }, 407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 }, 408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B }, 409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 }, 410 411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 }, 412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 }, 413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT }, 414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 }, 415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 }, 416 417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 }, 418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 }, 419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 }, 420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A }, 421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B }, 422 423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 }, 424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM }, 425 426 {0,} /* 0 terminated list. */ 427 }; 428 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl); 429 430 431 /* Operational definitions. 432 These are not used by other compilation units and thus are not 433 exported in a ".h" file. 434 435 First the windows. There are eight register windows, with the command 436 and status registers available in each. 437 */ 438 #define EL3_CMD 0x0e 439 #define EL3_STATUS 0x0e 440 441 /* The top five bits written to EL3_CMD are a command, the lower 442 11 bits are the parameter, if applicable. 443 Note that 11 parameters bits was fine for ethernet, but the new chip 444 can handle FDDI length frames (~4500 octets) and now parameters count 445 32-bit 'Dwords' rather than octets. */ 446 447 enum vortex_cmd { 448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11, 449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, 450 UpStall = 6<<11, UpUnstall = (6<<11)+1, 451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3, 452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11, 453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11, 454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11, 455 SetTxThreshold = 18<<11, SetTxStart = 19<<11, 456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11, 457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,}; 458 459 /* The SetRxFilter command accepts the following classes: */ 460 enum RxFilter { 461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 }; 462 463 /* Bits in the general status register. */ 464 enum vortex_status { 465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004, 466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, 467 IntReq = 0x0040, StatsFull = 0x0080, 468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10, 469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/ 470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/ 471 }; 472 473 /* Register window 1 offsets, the window used in normal operation. 474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */ 475 enum Window1 { 476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14, 477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B, 478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */ 479 }; 480 enum Window0 { 481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */ 482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */ 483 IntrStatus=0x0E, /* Valid in all windows. */ 484 }; 485 enum Win0_EEPROM_bits { 486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0, 487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */ 488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */ 489 }; 490 /* EEPROM locations. */ 491 enum eeprom_offset { 492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3, 493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9, 494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12, 495 DriverTune=13, Checksum=15}; 496 497 enum Window2 { /* Window 2. */ 498 Wn2_ResetOptions=12, 499 }; 500 enum Window3 { /* Window 3: MAC/config bits. */ 501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8, 502 }; 503 504 #define BFEXT(value, offset, bitcount) \ 505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1)) 506 507 #define BFINS(lhs, rhs, offset, bitcount) \ 508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \ 509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset))) 510 511 #define RAM_SIZE(v) BFEXT(v, 0, 3) 512 #define RAM_WIDTH(v) BFEXT(v, 3, 1) 513 #define RAM_SPEED(v) BFEXT(v, 4, 2) 514 #define ROM_SIZE(v) BFEXT(v, 6, 2) 515 #define RAM_SPLIT(v) BFEXT(v, 16, 2) 516 #define XCVR(v) BFEXT(v, 20, 4) 517 #define AUTOSELECT(v) BFEXT(v, 24, 1) 518 519 enum Window4 { /* Window 4: Xcvr/media bits. */ 520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10, 521 }; 522 enum Win4_Media_bits { 523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */ 524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */ 525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */ 526 Media_LnkBeat = 0x0800, 527 }; 528 enum Window7 { /* Window 7: Bus Master control. */ 529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6, 530 Wn7_MasterStatus = 12, 531 }; 532 /* Boomerang bus master control registers. */ 533 enum MasterCtrl { 534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c, 535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38, 536 }; 537 538 /* The Rx and Tx descriptor lists. 539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte 540 alignment contraint on tx_ring[] and rx_ring[]. */ 541 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */ 542 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */ 543 struct boom_rx_desc { 544 __le32 next; /* Last entry points to 0. */ 545 __le32 status; 546 __le32 addr; /* Up to 63 addr/len pairs possible. */ 547 __le32 length; /* Set LAST_FRAG to indicate last pair. */ 548 }; 549 /* Values for the Rx status entry. */ 550 enum rx_desc_status { 551 RxDComplete=0x00008000, RxDError=0x4000, 552 /* See boomerang_rx() for actual error bits */ 553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27, 554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31, 555 }; 556 557 #ifdef MAX_SKB_FRAGS 558 #define DO_ZEROCOPY 1 559 #else 560 #define DO_ZEROCOPY 0 561 #endif 562 563 struct boom_tx_desc { 564 __le32 next; /* Last entry points to 0. */ 565 __le32 status; /* bits 0:12 length, others see below. */ 566 #if DO_ZEROCOPY 567 struct { 568 __le32 addr; 569 __le32 length; 570 } frag[1+MAX_SKB_FRAGS]; 571 #else 572 __le32 addr; 573 __le32 length; 574 #endif 575 }; 576 577 /* Values for the Tx status entry. */ 578 enum tx_desc_status { 579 CRCDisable=0x2000, TxDComplete=0x8000, 580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000, 581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */ 582 }; 583 584 /* Chip features we care about in vp->capabilities, read from the EEPROM. */ 585 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 }; 586 587 struct vortex_extra_stats { 588 unsigned long tx_deferred; 589 unsigned long tx_max_collisions; 590 unsigned long tx_multiple_collisions; 591 unsigned long tx_single_collisions; 592 unsigned long rx_bad_ssd; 593 }; 594 595 struct vortex_private { 596 /* The Rx and Tx rings should be quad-word-aligned. */ 597 struct boom_rx_desc* rx_ring; 598 struct boom_tx_desc* tx_ring; 599 dma_addr_t rx_ring_dma; 600 dma_addr_t tx_ring_dma; 601 /* The addresses of transmit- and receive-in-place skbuffs. */ 602 struct sk_buff* rx_skbuff[RX_RING_SIZE]; 603 struct sk_buff* tx_skbuff[TX_RING_SIZE]; 604 unsigned int cur_rx, cur_tx; /* The next free ring entry */ 605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */ 606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */ 607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */ 608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */ 609 610 /* PCI configuration space information. */ 611 struct device *gendev; 612 void __iomem *ioaddr; /* IO address space */ 613 void __iomem *cb_fn_base; /* CardBus function status addr space. */ 614 615 /* Some values here only for performance evaluation and path-coverage */ 616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits; 617 int card_idx; 618 619 /* The remainder are related to chip state, mostly media selection. */ 620 struct timer_list timer; /* Media selection timer. */ 621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */ 622 int options; /* User-settable misc. driver options. */ 623 unsigned int media_override:4, /* Passed-in media type. */ 624 default_media:4, /* Read from the EEPROM/Wn3_Config. */ 625 full_duplex:1, autoselect:1, 626 bus_master:1, /* Vortex can only do a fragment bus-m. */ 627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */ 628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */ 629 partner_flow_ctrl:1, /* Partner supports flow control */ 630 has_nway:1, 631 enable_wol:1, /* Wake-on-LAN is enabled */ 632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */ 633 open:1, 634 medialock:1, 635 large_frames:1, /* accept large frames */ 636 handling_irq:1; /* private in_irq indicator */ 637 /* {get|set}_wol operations are already serialized by rtnl. 638 * no additional locking is required for the enable_wol and acpi_set_WOL() 639 */ 640 int drv_flags; 641 u16 status_enable; 642 u16 intr_enable; 643 u16 available_media; /* From Wn3_Options. */ 644 u16 capabilities, info1, info2; /* Various, from EEPROM. */ 645 u16 advertising; /* NWay media advertisement */ 646 unsigned char phys[2]; /* MII device addresses. */ 647 u16 deferred; /* Resend these interrupts when we 648 * bale from the ISR */ 649 u16 io_size; /* Size of PCI region (for release_region) */ 650 651 /* Serialises access to hardware other than MII and variables below. 652 * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */ 653 spinlock_t lock; 654 655 spinlock_t mii_lock; /* Serialises access to MII */ 656 struct mii_if_info mii; /* MII lib hooks/info */ 657 spinlock_t window_lock; /* Serialises access to windowed regs */ 658 int window; /* Register window */ 659 }; 660 661 static void window_set(struct vortex_private *vp, int window) 662 { 663 if (window != vp->window) { 664 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD); 665 vp->window = window; 666 } 667 } 668 669 #define DEFINE_WINDOW_IO(size) \ 670 static u ## size \ 671 window_read ## size(struct vortex_private *vp, int window, int addr) \ 672 { \ 673 unsigned long flags; \ 674 u ## size ret; \ 675 spin_lock_irqsave(&vp->window_lock, flags); \ 676 window_set(vp, window); \ 677 ret = ioread ## size(vp->ioaddr + addr); \ 678 spin_unlock_irqrestore(&vp->window_lock, flags); \ 679 return ret; \ 680 } \ 681 static void \ 682 window_write ## size(struct vortex_private *vp, u ## size value, \ 683 int window, int addr) \ 684 { \ 685 unsigned long flags; \ 686 spin_lock_irqsave(&vp->window_lock, flags); \ 687 window_set(vp, window); \ 688 iowrite ## size(value, vp->ioaddr + addr); \ 689 spin_unlock_irqrestore(&vp->window_lock, flags); \ 690 } 691 DEFINE_WINDOW_IO(8) 692 DEFINE_WINDOW_IO(16) 693 DEFINE_WINDOW_IO(32) 694 695 #ifdef CONFIG_PCI 696 #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL) 697 #else 698 #define DEVICE_PCI(dev) NULL 699 #endif 700 701 #define VORTEX_PCI(vp) \ 702 ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)) 703 704 #ifdef CONFIG_EISA 705 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL) 706 #else 707 #define DEVICE_EISA(dev) NULL 708 #endif 709 710 #define VORTEX_EISA(vp) \ 711 ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)) 712 713 /* The action to take with a media selection timer tick. 714 Note that we deviate from the 3Com order by checking 10base2 before AUI. 715 */ 716 enum xcvr_types { 717 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx, 718 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10, 719 }; 720 721 static const struct media_table { 722 char *name; 723 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */ 724 mask:8, /* The transceiver-present bit in Wn3_Config.*/ 725 next:8; /* The media type to try next. */ 726 int wait; /* Time before we check media status. */ 727 } media_tbl[] = { 728 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10}, 729 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10}, 730 { "undefined", 0, 0x80, XCVR_10baseT, 10000}, 731 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10}, 732 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10}, 733 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10}, 734 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ }, 735 { "undefined", 0, 0x01, XCVR_10baseT, 10000}, 736 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ}, 737 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ }, 738 { "Default", 0, 0xFF, XCVR_10baseT, 10000}, 739 }; 740 741 static struct { 742 const char str[ETH_GSTRING_LEN]; 743 } ethtool_stats_keys[] = { 744 { "tx_deferred" }, 745 { "tx_max_collisions" }, 746 { "tx_multiple_collisions" }, 747 { "tx_single_collisions" }, 748 { "rx_bad_ssd" }, 749 }; 750 751 /* number of ETHTOOL_GSTATS u64's */ 752 #define VORTEX_NUM_STATS 5 753 754 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq, 755 int chip_idx, int card_idx); 756 static int vortex_up(struct net_device *dev); 757 static void vortex_down(struct net_device *dev, int final); 758 static int vortex_open(struct net_device *dev); 759 static void mdio_sync(struct vortex_private *vp, int bits); 760 static int mdio_read(struct net_device *dev, int phy_id, int location); 761 static void mdio_write(struct net_device *vp, int phy_id, int location, int value); 762 static void vortex_timer(unsigned long arg); 763 static void rx_oom_timer(unsigned long arg); 764 static netdev_tx_t vortex_start_xmit(struct sk_buff *skb, 765 struct net_device *dev); 766 static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb, 767 struct net_device *dev); 768 static int vortex_rx(struct net_device *dev); 769 static int boomerang_rx(struct net_device *dev); 770 static irqreturn_t vortex_interrupt(int irq, void *dev_id); 771 static irqreturn_t boomerang_interrupt(int irq, void *dev_id); 772 static int vortex_close(struct net_device *dev); 773 static void dump_tx_ring(struct net_device *dev); 774 static void update_stats(void __iomem *ioaddr, struct net_device *dev); 775 static struct net_device_stats *vortex_get_stats(struct net_device *dev); 776 static void set_rx_mode(struct net_device *dev); 777 #ifdef CONFIG_PCI 778 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 779 #endif 780 static void vortex_tx_timeout(struct net_device *dev); 781 static void acpi_set_WOL(struct net_device *dev); 782 static const struct ethtool_ops vortex_ethtool_ops; 783 static void set_8021q_mode(struct net_device *dev, int enable); 784 785 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */ 786 /* Option count limit only -- unlimited interfaces are supported. */ 787 #define MAX_UNITS 8 788 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 }; 789 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 }; 790 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 }; 791 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 }; 792 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 }; 793 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 }; 794 static int global_options = -1; 795 static int global_full_duplex = -1; 796 static int global_enable_wol = -1; 797 static int global_use_mmio = -1; 798 799 /* Variables to work-around the Compaq PCI BIOS32 problem. */ 800 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900; 801 static struct net_device *compaq_net_device; 802 803 static int vortex_cards_found; 804 805 module_param(debug, int, 0); 806 module_param(global_options, int, 0); 807 module_param_array(options, int, NULL, 0); 808 module_param(global_full_duplex, int, 0); 809 module_param_array(full_duplex, int, NULL, 0); 810 module_param_array(hw_checksums, int, NULL, 0); 811 module_param_array(flow_ctrl, int, NULL, 0); 812 module_param(global_enable_wol, int, 0); 813 module_param_array(enable_wol, int, NULL, 0); 814 module_param(rx_copybreak, int, 0); 815 module_param(max_interrupt_work, int, 0); 816 module_param(compaq_ioaddr, int, 0); 817 module_param(compaq_irq, int, 0); 818 module_param(compaq_device_id, int, 0); 819 module_param(watchdog, int, 0); 820 module_param(global_use_mmio, int, 0); 821 module_param_array(use_mmio, int, NULL, 0); 822 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)"); 823 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex"); 824 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset"); 825 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)"); 826 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset"); 827 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)"); 828 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)"); 829 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)"); 830 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset"); 831 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames"); 832 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt"); 833 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)"); 834 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)"); 835 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)"); 836 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds"); 837 MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset"); 838 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)"); 839 840 #ifdef CONFIG_NET_POLL_CONTROLLER 841 static void poll_vortex(struct net_device *dev) 842 { 843 struct vortex_private *vp = netdev_priv(dev); 844 unsigned long flags; 845 local_irq_save(flags); 846 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev); 847 local_irq_restore(flags); 848 } 849 #endif 850 851 #ifdef CONFIG_PM 852 853 static int vortex_suspend(struct device *dev) 854 { 855 struct pci_dev *pdev = to_pci_dev(dev); 856 struct net_device *ndev = pci_get_drvdata(pdev); 857 858 if (!ndev || !netif_running(ndev)) 859 return 0; 860 861 netif_device_detach(ndev); 862 vortex_down(ndev, 1); 863 864 return 0; 865 } 866 867 static int vortex_resume(struct device *dev) 868 { 869 struct pci_dev *pdev = to_pci_dev(dev); 870 struct net_device *ndev = pci_get_drvdata(pdev); 871 int err; 872 873 if (!ndev || !netif_running(ndev)) 874 return 0; 875 876 err = vortex_up(ndev); 877 if (err) 878 return err; 879 880 netif_device_attach(ndev); 881 882 return 0; 883 } 884 885 static const struct dev_pm_ops vortex_pm_ops = { 886 .suspend = vortex_suspend, 887 .resume = vortex_resume, 888 .freeze = vortex_suspend, 889 .thaw = vortex_resume, 890 .poweroff = vortex_suspend, 891 .restore = vortex_resume, 892 }; 893 894 #define VORTEX_PM_OPS (&vortex_pm_ops) 895 896 #else /* !CONFIG_PM */ 897 898 #define VORTEX_PM_OPS NULL 899 900 #endif /* !CONFIG_PM */ 901 902 #ifdef CONFIG_EISA 903 static struct eisa_device_id vortex_eisa_ids[] = { 904 { "TCM5920", CH_3C592 }, 905 { "TCM5970", CH_3C597 }, 906 { "" } 907 }; 908 MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids); 909 910 static int __init vortex_eisa_probe(struct device *device) 911 { 912 void __iomem *ioaddr; 913 struct eisa_device *edev; 914 915 edev = to_eisa_device(device); 916 917 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME)) 918 return -EBUSY; 919 920 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE); 921 922 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12, 923 edev->id.driver_data, vortex_cards_found)) { 924 release_region(edev->base_addr, VORTEX_TOTAL_SIZE); 925 return -ENODEV; 926 } 927 928 vortex_cards_found++; 929 930 return 0; 931 } 932 933 static int vortex_eisa_remove(struct device *device) 934 { 935 struct eisa_device *edev; 936 struct net_device *dev; 937 struct vortex_private *vp; 938 void __iomem *ioaddr; 939 940 edev = to_eisa_device(device); 941 dev = eisa_get_drvdata(edev); 942 943 if (!dev) { 944 pr_err("vortex_eisa_remove called for Compaq device!\n"); 945 BUG(); 946 } 947 948 vp = netdev_priv(dev); 949 ioaddr = vp->ioaddr; 950 951 unregister_netdev(dev); 952 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD); 953 release_region(edev->base_addr, VORTEX_TOTAL_SIZE); 954 955 free_netdev(dev); 956 return 0; 957 } 958 959 static struct eisa_driver vortex_eisa_driver = { 960 .id_table = vortex_eisa_ids, 961 .driver = { 962 .name = "3c59x", 963 .probe = vortex_eisa_probe, 964 .remove = vortex_eisa_remove 965 } 966 }; 967 968 #endif /* CONFIG_EISA */ 969 970 /* returns count found (>= 0), or negative on error */ 971 static int __init vortex_eisa_init(void) 972 { 973 int eisa_found = 0; 974 int orig_cards_found = vortex_cards_found; 975 976 #ifdef CONFIG_EISA 977 int err; 978 979 err = eisa_driver_register (&vortex_eisa_driver); 980 if (!err) { 981 /* 982 * Because of the way EISA bus is probed, we cannot assume 983 * any device have been found when we exit from 984 * eisa_driver_register (the bus root driver may not be 985 * initialized yet). So we blindly assume something was 986 * found, and let the sysfs magic happened... 987 */ 988 eisa_found = 1; 989 } 990 #endif 991 992 /* Special code to work-around the Compaq PCI BIOS32 problem. */ 993 if (compaq_ioaddr) { 994 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE), 995 compaq_irq, compaq_device_id, vortex_cards_found++); 996 } 997 998 return vortex_cards_found - orig_cards_found + eisa_found; 999 } 1000 1001 /* returns count (>= 0), or negative on error */ 1002 static int vortex_init_one(struct pci_dev *pdev, 1003 const struct pci_device_id *ent) 1004 { 1005 int rc, unit, pci_bar; 1006 struct vortex_chip_info *vci; 1007 void __iomem *ioaddr; 1008 1009 /* wake up and enable device */ 1010 rc = pci_enable_device(pdev); 1011 if (rc < 0) 1012 goto out; 1013 1014 rc = pci_request_regions(pdev, DRV_NAME); 1015 if (rc < 0) 1016 goto out_disable; 1017 1018 unit = vortex_cards_found; 1019 1020 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) { 1021 /* Determine the default if the user didn't override us */ 1022 vci = &vortex_info_tbl[ent->driver_data]; 1023 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0; 1024 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0) 1025 pci_bar = use_mmio[unit] ? 1 : 0; 1026 else 1027 pci_bar = global_use_mmio ? 1 : 0; 1028 1029 ioaddr = pci_iomap(pdev, pci_bar, 0); 1030 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */ 1031 ioaddr = pci_iomap(pdev, 0, 0); 1032 if (!ioaddr) { 1033 rc = -ENOMEM; 1034 goto out_release; 1035 } 1036 1037 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq, 1038 ent->driver_data, unit); 1039 if (rc < 0) 1040 goto out_iounmap; 1041 1042 vortex_cards_found++; 1043 goto out; 1044 1045 out_iounmap: 1046 pci_iounmap(pdev, ioaddr); 1047 out_release: 1048 pci_release_regions(pdev); 1049 out_disable: 1050 pci_disable_device(pdev); 1051 out: 1052 return rc; 1053 } 1054 1055 static const struct net_device_ops boomrang_netdev_ops = { 1056 .ndo_open = vortex_open, 1057 .ndo_stop = vortex_close, 1058 .ndo_start_xmit = boomerang_start_xmit, 1059 .ndo_tx_timeout = vortex_tx_timeout, 1060 .ndo_get_stats = vortex_get_stats, 1061 #ifdef CONFIG_PCI 1062 .ndo_do_ioctl = vortex_ioctl, 1063 #endif 1064 .ndo_set_rx_mode = set_rx_mode, 1065 .ndo_change_mtu = eth_change_mtu, 1066 .ndo_set_mac_address = eth_mac_addr, 1067 .ndo_validate_addr = eth_validate_addr, 1068 #ifdef CONFIG_NET_POLL_CONTROLLER 1069 .ndo_poll_controller = poll_vortex, 1070 #endif 1071 }; 1072 1073 static const struct net_device_ops vortex_netdev_ops = { 1074 .ndo_open = vortex_open, 1075 .ndo_stop = vortex_close, 1076 .ndo_start_xmit = vortex_start_xmit, 1077 .ndo_tx_timeout = vortex_tx_timeout, 1078 .ndo_get_stats = vortex_get_stats, 1079 #ifdef CONFIG_PCI 1080 .ndo_do_ioctl = vortex_ioctl, 1081 #endif 1082 .ndo_set_rx_mode = set_rx_mode, 1083 .ndo_change_mtu = eth_change_mtu, 1084 .ndo_set_mac_address = eth_mac_addr, 1085 .ndo_validate_addr = eth_validate_addr, 1086 #ifdef CONFIG_NET_POLL_CONTROLLER 1087 .ndo_poll_controller = poll_vortex, 1088 #endif 1089 }; 1090 1091 /* 1092 * Start up the PCI/EISA device which is described by *gendev. 1093 * Return 0 on success. 1094 * 1095 * NOTE: pdev can be NULL, for the case of a Compaq device 1096 */ 1097 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq, 1098 int chip_idx, int card_idx) 1099 { 1100 struct vortex_private *vp; 1101 int option; 1102 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */ 1103 int i, step; 1104 struct net_device *dev; 1105 static int printed_version; 1106 int retval, print_info; 1107 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx]; 1108 const char *print_name = "3c59x"; 1109 struct pci_dev *pdev = NULL; 1110 struct eisa_device *edev = NULL; 1111 1112 if (!printed_version) { 1113 pr_info("%s", version); 1114 printed_version = 1; 1115 } 1116 1117 if (gendev) { 1118 if ((pdev = DEVICE_PCI(gendev))) { 1119 print_name = pci_name(pdev); 1120 } 1121 1122 if ((edev = DEVICE_EISA(gendev))) { 1123 print_name = dev_name(&edev->dev); 1124 } 1125 } 1126 1127 dev = alloc_etherdev(sizeof(*vp)); 1128 retval = -ENOMEM; 1129 if (!dev) 1130 goto out; 1131 1132 SET_NETDEV_DEV(dev, gendev); 1133 vp = netdev_priv(dev); 1134 1135 option = global_options; 1136 1137 /* The lower four bits are the media type. */ 1138 if (dev->mem_start) { 1139 /* 1140 * The 'options' param is passed in as the third arg to the 1141 * LILO 'ether=' argument for non-modular use 1142 */ 1143 option = dev->mem_start; 1144 } 1145 else if (card_idx < MAX_UNITS) { 1146 if (options[card_idx] >= 0) 1147 option = options[card_idx]; 1148 } 1149 1150 if (option > 0) { 1151 if (option & 0x8000) 1152 vortex_debug = 7; 1153 if (option & 0x4000) 1154 vortex_debug = 2; 1155 if (option & 0x0400) 1156 vp->enable_wol = 1; 1157 } 1158 1159 print_info = (vortex_debug > 1); 1160 if (print_info) 1161 pr_info("See Documentation/networking/vortex.txt\n"); 1162 1163 pr_info("%s: 3Com %s %s at %p.\n", 1164 print_name, 1165 pdev ? "PCI" : "EISA", 1166 vci->name, 1167 ioaddr); 1168 1169 dev->base_addr = (unsigned long)ioaddr; 1170 dev->irq = irq; 1171 dev->mtu = mtu; 1172 vp->ioaddr = ioaddr; 1173 vp->large_frames = mtu > 1500; 1174 vp->drv_flags = vci->drv_flags; 1175 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0; 1176 vp->io_size = vci->io_size; 1177 vp->card_idx = card_idx; 1178 vp->window = -1; 1179 1180 /* module list only for Compaq device */ 1181 if (gendev == NULL) { 1182 compaq_net_device = dev; 1183 } 1184 1185 /* PCI-only startup logic */ 1186 if (pdev) { 1187 /* enable bus-mastering if necessary */ 1188 if (vci->flags & PCI_USES_MASTER) 1189 pci_set_master(pdev); 1190 1191 if (vci->drv_flags & IS_VORTEX) { 1192 u8 pci_latency; 1193 u8 new_latency = 248; 1194 1195 /* Check the PCI latency value. On the 3c590 series the latency timer 1196 must be set to the maximum value to avoid data corruption that occurs 1197 when the timer expires during a transfer. This bug exists the Vortex 1198 chip only. */ 1199 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency); 1200 if (pci_latency < new_latency) { 1201 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n", 1202 print_name, pci_latency, new_latency); 1203 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency); 1204 } 1205 } 1206 } 1207 1208 spin_lock_init(&vp->lock); 1209 spin_lock_init(&vp->mii_lock); 1210 spin_lock_init(&vp->window_lock); 1211 vp->gendev = gendev; 1212 vp->mii.dev = dev; 1213 vp->mii.mdio_read = mdio_read; 1214 vp->mii.mdio_write = mdio_write; 1215 vp->mii.phy_id_mask = 0x1f; 1216 vp->mii.reg_num_mask = 0x1f; 1217 1218 /* Makes sure rings are at least 16 byte aligned. */ 1219 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE 1220 + sizeof(struct boom_tx_desc) * TX_RING_SIZE, 1221 &vp->rx_ring_dma); 1222 retval = -ENOMEM; 1223 if (!vp->rx_ring) 1224 goto free_device; 1225 1226 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE); 1227 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE; 1228 1229 /* if we are a PCI driver, we store info in pdev->driver_data 1230 * instead of a module list */ 1231 if (pdev) 1232 pci_set_drvdata(pdev, dev); 1233 if (edev) 1234 eisa_set_drvdata(edev, dev); 1235 1236 vp->media_override = 7; 1237 if (option >= 0) { 1238 vp->media_override = ((option & 7) == 2) ? 0 : option & 15; 1239 if (vp->media_override != 7) 1240 vp->medialock = 1; 1241 vp->full_duplex = (option & 0x200) ? 1 : 0; 1242 vp->bus_master = (option & 16) ? 1 : 0; 1243 } 1244 1245 if (global_full_duplex > 0) 1246 vp->full_duplex = 1; 1247 if (global_enable_wol > 0) 1248 vp->enable_wol = 1; 1249 1250 if (card_idx < MAX_UNITS) { 1251 if (full_duplex[card_idx] > 0) 1252 vp->full_duplex = 1; 1253 if (flow_ctrl[card_idx] > 0) 1254 vp->flow_ctrl = 1; 1255 if (enable_wol[card_idx] > 0) 1256 vp->enable_wol = 1; 1257 } 1258 1259 vp->mii.force_media = vp->full_duplex; 1260 vp->options = option; 1261 /* Read the station address from the EEPROM. */ 1262 { 1263 int base; 1264 1265 if (vci->drv_flags & EEPROM_8BIT) 1266 base = 0x230; 1267 else if (vci->drv_flags & EEPROM_OFFSET) 1268 base = EEPROM_Read + 0x30; 1269 else 1270 base = EEPROM_Read; 1271 1272 for (i = 0; i < 0x40; i++) { 1273 int timer; 1274 window_write16(vp, base + i, 0, Wn0EepromCmd); 1275 /* Pause for at least 162 us. for the read to take place. */ 1276 for (timer = 10; timer >= 0; timer--) { 1277 udelay(162); 1278 if ((window_read16(vp, 0, Wn0EepromCmd) & 1279 0x8000) == 0) 1280 break; 1281 } 1282 eeprom[i] = window_read16(vp, 0, Wn0EepromData); 1283 } 1284 } 1285 for (i = 0; i < 0x18; i++) 1286 checksum ^= eeprom[i]; 1287 checksum = (checksum ^ (checksum >> 8)) & 0xff; 1288 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */ 1289 while (i < 0x21) 1290 checksum ^= eeprom[i++]; 1291 checksum = (checksum ^ (checksum >> 8)) & 0xff; 1292 } 1293 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO)) 1294 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum); 1295 for (i = 0; i < 3; i++) 1296 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]); 1297 if (print_info) 1298 pr_cont(" %pM", dev->dev_addr); 1299 /* Unfortunately an all zero eeprom passes the checksum and this 1300 gets found in the wild in failure cases. Crypto is hard 8) */ 1301 if (!is_valid_ether_addr(dev->dev_addr)) { 1302 retval = -EINVAL; 1303 pr_err("*** EEPROM MAC address is invalid.\n"); 1304 goto free_ring; /* With every pack */ 1305 } 1306 for (i = 0; i < 6; i++) 1307 window_write8(vp, dev->dev_addr[i], 2, i); 1308 1309 if (print_info) 1310 pr_cont(", IRQ %d\n", dev->irq); 1311 /* Tell them about an invalid IRQ. */ 1312 if (dev->irq <= 0 || dev->irq >= nr_irqs) 1313 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n", 1314 dev->irq); 1315 1316 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1; 1317 if (print_info) { 1318 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n", 1319 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14], 1320 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9); 1321 } 1322 1323 1324 if (pdev && vci->drv_flags & HAS_CB_FNS) { 1325 unsigned short n; 1326 1327 vp->cb_fn_base = pci_iomap(pdev, 2, 0); 1328 if (!vp->cb_fn_base) { 1329 retval = -ENOMEM; 1330 goto free_ring; 1331 } 1332 1333 if (print_info) { 1334 pr_info("%s: CardBus functions mapped %16.16llx->%p\n", 1335 print_name, 1336 (unsigned long long)pci_resource_start(pdev, 2), 1337 vp->cb_fn_base); 1338 } 1339 1340 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010; 1341 if (vp->drv_flags & INVERT_LED_PWR) 1342 n |= 0x10; 1343 if (vp->drv_flags & INVERT_MII_PWR) 1344 n |= 0x4000; 1345 window_write16(vp, n, 2, Wn2_ResetOptions); 1346 if (vp->drv_flags & WNO_XCVR_PWR) { 1347 window_write16(vp, 0x0800, 0, 0); 1348 } 1349 } 1350 1351 /* Extract our information from the EEPROM data. */ 1352 vp->info1 = eeprom[13]; 1353 vp->info2 = eeprom[15]; 1354 vp->capabilities = eeprom[16]; 1355 1356 if (vp->info1 & 0x8000) { 1357 vp->full_duplex = 1; 1358 if (print_info) 1359 pr_info("Full duplex capable\n"); 1360 } 1361 1362 { 1363 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"}; 1364 unsigned int config; 1365 vp->available_media = window_read16(vp, 3, Wn3_Options); 1366 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */ 1367 vp->available_media = 0x40; 1368 config = window_read32(vp, 3, Wn3_Config); 1369 if (print_info) { 1370 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n", 1371 config, window_read16(vp, 3, Wn3_Options)); 1372 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n", 1373 8 << RAM_SIZE(config), 1374 RAM_WIDTH(config) ? "word" : "byte", 1375 ram_split[RAM_SPLIT(config)], 1376 AUTOSELECT(config) ? "autoselect/" : "", 1377 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" : 1378 media_tbl[XCVR(config)].name); 1379 } 1380 vp->default_media = XCVR(config); 1381 if (vp->default_media == XCVR_NWAY) 1382 vp->has_nway = 1; 1383 vp->autoselect = AUTOSELECT(config); 1384 } 1385 1386 if (vp->media_override != 7) { 1387 pr_info("%s: Media override to transceiver type %d (%s).\n", 1388 print_name, vp->media_override, 1389 media_tbl[vp->media_override].name); 1390 dev->if_port = vp->media_override; 1391 } else 1392 dev->if_port = vp->default_media; 1393 1394 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) || 1395 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) { 1396 int phy, phy_idx = 0; 1397 mii_preamble_required++; 1398 if (vp->drv_flags & EXTRA_PREAMBLE) 1399 mii_preamble_required++; 1400 mdio_sync(vp, 32); 1401 mdio_read(dev, 24, MII_BMSR); 1402 for (phy = 0; phy < 32 && phy_idx < 1; phy++) { 1403 int mii_status, phyx; 1404 1405 /* 1406 * For the 3c905CX we look at index 24 first, because it bogusly 1407 * reports an external PHY at all indices 1408 */ 1409 if (phy == 0) 1410 phyx = 24; 1411 else if (phy <= 24) 1412 phyx = phy - 1; 1413 else 1414 phyx = phy; 1415 mii_status = mdio_read(dev, phyx, MII_BMSR); 1416 if (mii_status && mii_status != 0xffff) { 1417 vp->phys[phy_idx++] = phyx; 1418 if (print_info) { 1419 pr_info(" MII transceiver found at address %d, status %4x.\n", 1420 phyx, mii_status); 1421 } 1422 if ((mii_status & 0x0040) == 0) 1423 mii_preamble_required++; 1424 } 1425 } 1426 mii_preamble_required--; 1427 if (phy_idx == 0) { 1428 pr_warning(" ***WARNING*** No MII transceivers found!\n"); 1429 vp->phys[0] = 24; 1430 } else { 1431 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE); 1432 if (vp->full_duplex) { 1433 /* Only advertise the FD media types. */ 1434 vp->advertising &= ~0x02A0; 1435 mdio_write(dev, vp->phys[0], 4, vp->advertising); 1436 } 1437 } 1438 vp->mii.phy_id = vp->phys[0]; 1439 } 1440 1441 if (vp->capabilities & CapBusMaster) { 1442 vp->full_bus_master_tx = 1; 1443 if (print_info) { 1444 pr_info(" Enabling bus-master transmits and %s receives.\n", 1445 (vp->info2 & 1) ? "early" : "whole-frame" ); 1446 } 1447 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2; 1448 vp->bus_master = 0; /* AKPM: vortex only */ 1449 } 1450 1451 /* The 3c59x-specific entries in the device structure. */ 1452 if (vp->full_bus_master_tx) { 1453 dev->netdev_ops = &boomrang_netdev_ops; 1454 /* Actually, it still should work with iommu. */ 1455 if (card_idx < MAX_UNITS && 1456 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) || 1457 hw_checksums[card_idx] == 1)) { 1458 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; 1459 } 1460 } else 1461 dev->netdev_ops = &vortex_netdev_ops; 1462 1463 if (print_info) { 1464 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n", 1465 print_name, 1466 (dev->features & NETIF_F_SG) ? "en":"dis", 1467 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis"); 1468 } 1469 1470 dev->ethtool_ops = &vortex_ethtool_ops; 1471 dev->watchdog_timeo = (watchdog * HZ) / 1000; 1472 1473 if (pdev) { 1474 vp->pm_state_valid = 1; 1475 pci_save_state(pdev); 1476 acpi_set_WOL(dev); 1477 } 1478 retval = register_netdev(dev); 1479 if (retval == 0) 1480 return 0; 1481 1482 free_ring: 1483 pci_free_consistent(pdev, 1484 sizeof(struct boom_rx_desc) * RX_RING_SIZE 1485 + sizeof(struct boom_tx_desc) * TX_RING_SIZE, 1486 vp->rx_ring, 1487 vp->rx_ring_dma); 1488 free_device: 1489 free_netdev(dev); 1490 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval); 1491 out: 1492 return retval; 1493 } 1494 1495 static void 1496 issue_and_wait(struct net_device *dev, int cmd) 1497 { 1498 struct vortex_private *vp = netdev_priv(dev); 1499 void __iomem *ioaddr = vp->ioaddr; 1500 int i; 1501 1502 iowrite16(cmd, ioaddr + EL3_CMD); 1503 for (i = 0; i < 2000; i++) { 1504 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) 1505 return; 1506 } 1507 1508 /* OK, that didn't work. Do it the slow way. One second */ 1509 for (i = 0; i < 100000; i++) { 1510 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) { 1511 if (vortex_debug > 1) 1512 pr_info("%s: command 0x%04x took %d usecs\n", 1513 dev->name, cmd, i * 10); 1514 return; 1515 } 1516 udelay(10); 1517 } 1518 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n", 1519 dev->name, cmd, ioread16(ioaddr + EL3_STATUS)); 1520 } 1521 1522 static void 1523 vortex_set_duplex(struct net_device *dev) 1524 { 1525 struct vortex_private *vp = netdev_priv(dev); 1526 1527 pr_info("%s: setting %s-duplex.\n", 1528 dev->name, (vp->full_duplex) ? "full" : "half"); 1529 1530 /* Set the full-duplex bit. */ 1531 window_write16(vp, 1532 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) | 1533 (vp->large_frames ? 0x40 : 0) | 1534 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ? 1535 0x100 : 0), 1536 3, Wn3_MAC_Ctrl); 1537 } 1538 1539 static void vortex_check_media(struct net_device *dev, unsigned int init) 1540 { 1541 struct vortex_private *vp = netdev_priv(dev); 1542 unsigned int ok_to_print = 0; 1543 1544 if (vortex_debug > 3) 1545 ok_to_print = 1; 1546 1547 if (mii_check_media(&vp->mii, ok_to_print, init)) { 1548 vp->full_duplex = vp->mii.full_duplex; 1549 vortex_set_duplex(dev); 1550 } else if (init) { 1551 vortex_set_duplex(dev); 1552 } 1553 } 1554 1555 static int 1556 vortex_up(struct net_device *dev) 1557 { 1558 struct vortex_private *vp = netdev_priv(dev); 1559 void __iomem *ioaddr = vp->ioaddr; 1560 unsigned int config; 1561 int i, mii_reg1, mii_reg5, err = 0; 1562 1563 if (VORTEX_PCI(vp)) { 1564 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */ 1565 if (vp->pm_state_valid) 1566 pci_restore_state(VORTEX_PCI(vp)); 1567 err = pci_enable_device(VORTEX_PCI(vp)); 1568 if (err) { 1569 pr_warning("%s: Could not enable device\n", 1570 dev->name); 1571 goto err_out; 1572 } 1573 } 1574 1575 /* Before initializing select the active media port. */ 1576 config = window_read32(vp, 3, Wn3_Config); 1577 1578 if (vp->media_override != 7) { 1579 pr_info("%s: Media override to transceiver %d (%s).\n", 1580 dev->name, vp->media_override, 1581 media_tbl[vp->media_override].name); 1582 dev->if_port = vp->media_override; 1583 } else if (vp->autoselect) { 1584 if (vp->has_nway) { 1585 if (vortex_debug > 1) 1586 pr_info("%s: using NWAY device table, not %d\n", 1587 dev->name, dev->if_port); 1588 dev->if_port = XCVR_NWAY; 1589 } else { 1590 /* Find first available media type, starting with 100baseTx. */ 1591 dev->if_port = XCVR_100baseTx; 1592 while (! (vp->available_media & media_tbl[dev->if_port].mask)) 1593 dev->if_port = media_tbl[dev->if_port].next; 1594 if (vortex_debug > 1) 1595 pr_info("%s: first available media type: %s\n", 1596 dev->name, media_tbl[dev->if_port].name); 1597 } 1598 } else { 1599 dev->if_port = vp->default_media; 1600 if (vortex_debug > 1) 1601 pr_info("%s: using default media %s\n", 1602 dev->name, media_tbl[dev->if_port].name); 1603 } 1604 1605 init_timer(&vp->timer); 1606 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait); 1607 vp->timer.data = (unsigned long)dev; 1608 vp->timer.function = vortex_timer; /* timer handler */ 1609 add_timer(&vp->timer); 1610 1611 init_timer(&vp->rx_oom_timer); 1612 vp->rx_oom_timer.data = (unsigned long)dev; 1613 vp->rx_oom_timer.function = rx_oom_timer; 1614 1615 if (vortex_debug > 1) 1616 pr_debug("%s: Initial media type %s.\n", 1617 dev->name, media_tbl[dev->if_port].name); 1618 1619 vp->full_duplex = vp->mii.force_media; 1620 config = BFINS(config, dev->if_port, 20, 4); 1621 if (vortex_debug > 6) 1622 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config); 1623 window_write32(vp, config, 3, Wn3_Config); 1624 1625 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) { 1626 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR); 1627 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA); 1628 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0); 1629 vp->mii.full_duplex = vp->full_duplex; 1630 1631 vortex_check_media(dev, 1); 1632 } 1633 else 1634 vortex_set_duplex(dev); 1635 1636 issue_and_wait(dev, TxReset); 1637 /* 1638 * Don't reset the PHY - that upsets autonegotiation during DHCP operations. 1639 */ 1640 issue_and_wait(dev, RxReset|0x04); 1641 1642 1643 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD); 1644 1645 if (vortex_debug > 1) { 1646 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n", 1647 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media)); 1648 } 1649 1650 /* Set the station address and mask in window 2 each time opened. */ 1651 for (i = 0; i < 6; i++) 1652 window_write8(vp, dev->dev_addr[i], 2, i); 1653 for (; i < 12; i+=2) 1654 window_write16(vp, 0, 2, i); 1655 1656 if (vp->cb_fn_base) { 1657 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010; 1658 if (vp->drv_flags & INVERT_LED_PWR) 1659 n |= 0x10; 1660 if (vp->drv_flags & INVERT_MII_PWR) 1661 n |= 0x4000; 1662 window_write16(vp, n, 2, Wn2_ResetOptions); 1663 } 1664 1665 if (dev->if_port == XCVR_10base2) 1666 /* Start the thinnet transceiver. We should really wait 50ms...*/ 1667 iowrite16(StartCoax, ioaddr + EL3_CMD); 1668 if (dev->if_port != XCVR_NWAY) { 1669 window_write16(vp, 1670 (window_read16(vp, 4, Wn4_Media) & 1671 ~(Media_10TP|Media_SQE)) | 1672 media_tbl[dev->if_port].media_bits, 1673 4, Wn4_Media); 1674 } 1675 1676 /* Switch to the stats window, and clear all stats by reading. */ 1677 iowrite16(StatsDisable, ioaddr + EL3_CMD); 1678 for (i = 0; i < 10; i++) 1679 window_read8(vp, 6, i); 1680 window_read16(vp, 6, 10); 1681 window_read16(vp, 6, 12); 1682 /* New: On the Vortex we must also clear the BadSSD counter. */ 1683 window_read8(vp, 4, 12); 1684 /* ..and on the Boomerang we enable the extra statistics bits. */ 1685 window_write16(vp, 0x0040, 4, Wn4_NetDiag); 1686 1687 if (vp->full_bus_master_rx) { /* Boomerang bus master. */ 1688 vp->cur_rx = vp->dirty_rx = 0; 1689 /* Initialize the RxEarly register as recommended. */ 1690 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD); 1691 iowrite32(0x0020, ioaddr + PktStatus); 1692 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr); 1693 } 1694 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */ 1695 vp->cur_tx = vp->dirty_tx = 0; 1696 if (vp->drv_flags & IS_BOOMERANG) 1697 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */ 1698 /* Clear the Rx, Tx rings. */ 1699 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */ 1700 vp->rx_ring[i].status = 0; 1701 for (i = 0; i < TX_RING_SIZE; i++) 1702 vp->tx_skbuff[i] = NULL; 1703 iowrite32(0, ioaddr + DownListPtr); 1704 } 1705 /* Set receiver mode: presumably accept b-case and phys addr only. */ 1706 set_rx_mode(dev); 1707 /* enable 802.1q tagged frames */ 1708 set_8021q_mode(dev, 1); 1709 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */ 1710 1711 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */ 1712 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */ 1713 /* Allow status bits to be seen. */ 1714 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete| 1715 (vp->full_bus_master_tx ? DownComplete : TxAvailable) | 1716 (vp->full_bus_master_rx ? UpComplete : RxComplete) | 1717 (vp->bus_master ? DMADone : 0); 1718 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable | 1719 (vp->full_bus_master_rx ? 0 : RxComplete) | 1720 StatsFull | HostError | TxComplete | IntReq 1721 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete; 1722 iowrite16(vp->status_enable, ioaddr + EL3_CMD); 1723 /* Ack all pending events, and set active indicator mask. */ 1724 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq, 1725 ioaddr + EL3_CMD); 1726 iowrite16(vp->intr_enable, ioaddr + EL3_CMD); 1727 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */ 1728 iowrite32(0x8000, vp->cb_fn_base + 4); 1729 netif_start_queue (dev); 1730 err_out: 1731 return err; 1732 } 1733 1734 static int 1735 vortex_open(struct net_device *dev) 1736 { 1737 struct vortex_private *vp = netdev_priv(dev); 1738 int i; 1739 int retval; 1740 1741 /* Use the now-standard shared IRQ implementation. */ 1742 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ? 1743 boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) { 1744 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq); 1745 goto err; 1746 } 1747 1748 if (vp->full_bus_master_rx) { /* Boomerang bus master. */ 1749 if (vortex_debug > 2) 1750 pr_debug("%s: Filling in the Rx ring.\n", dev->name); 1751 for (i = 0; i < RX_RING_SIZE; i++) { 1752 struct sk_buff *skb; 1753 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1)); 1754 vp->rx_ring[i].status = 0; /* Clear complete bit. */ 1755 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG); 1756 1757 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN, 1758 GFP_KERNEL); 1759 vp->rx_skbuff[i] = skb; 1760 if (skb == NULL) 1761 break; /* Bad news! */ 1762 1763 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */ 1764 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE)); 1765 } 1766 if (i != RX_RING_SIZE) { 1767 int j; 1768 pr_emerg("%s: no memory for rx ring\n", dev->name); 1769 for (j = 0; j < i; j++) { 1770 if (vp->rx_skbuff[j]) { 1771 dev_kfree_skb(vp->rx_skbuff[j]); 1772 vp->rx_skbuff[j] = NULL; 1773 } 1774 } 1775 retval = -ENOMEM; 1776 goto err_free_irq; 1777 } 1778 /* Wrap the ring. */ 1779 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma); 1780 } 1781 1782 retval = vortex_up(dev); 1783 if (!retval) 1784 goto out; 1785 1786 err_free_irq: 1787 free_irq(dev->irq, dev); 1788 err: 1789 if (vortex_debug > 1) 1790 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval); 1791 out: 1792 return retval; 1793 } 1794 1795 static void 1796 vortex_timer(unsigned long data) 1797 { 1798 struct net_device *dev = (struct net_device *)data; 1799 struct vortex_private *vp = netdev_priv(dev); 1800 void __iomem *ioaddr = vp->ioaddr; 1801 int next_tick = 60*HZ; 1802 int ok = 0; 1803 int media_status; 1804 1805 if (vortex_debug > 2) { 1806 pr_debug("%s: Media selection timer tick happened, %s.\n", 1807 dev->name, media_tbl[dev->if_port].name); 1808 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo); 1809 } 1810 1811 media_status = window_read16(vp, 4, Wn4_Media); 1812 switch (dev->if_port) { 1813 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx: 1814 if (media_status & Media_LnkBeat) { 1815 netif_carrier_on(dev); 1816 ok = 1; 1817 if (vortex_debug > 1) 1818 pr_debug("%s: Media %s has link beat, %x.\n", 1819 dev->name, media_tbl[dev->if_port].name, media_status); 1820 } else { 1821 netif_carrier_off(dev); 1822 if (vortex_debug > 1) { 1823 pr_debug("%s: Media %s has no link beat, %x.\n", 1824 dev->name, media_tbl[dev->if_port].name, media_status); 1825 } 1826 } 1827 break; 1828 case XCVR_MII: case XCVR_NWAY: 1829 { 1830 ok = 1; 1831 vortex_check_media(dev, 0); 1832 } 1833 break; 1834 default: /* Other media types handled by Tx timeouts. */ 1835 if (vortex_debug > 1) 1836 pr_debug("%s: Media %s has no indication, %x.\n", 1837 dev->name, media_tbl[dev->if_port].name, media_status); 1838 ok = 1; 1839 } 1840 1841 if (dev->flags & IFF_SLAVE || !netif_carrier_ok(dev)) 1842 next_tick = 5*HZ; 1843 1844 if (vp->medialock) 1845 goto leave_media_alone; 1846 1847 if (!ok) { 1848 unsigned int config; 1849 1850 spin_lock_irq(&vp->lock); 1851 1852 do { 1853 dev->if_port = media_tbl[dev->if_port].next; 1854 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask)); 1855 if (dev->if_port == XCVR_Default) { /* Go back to default. */ 1856 dev->if_port = vp->default_media; 1857 if (vortex_debug > 1) 1858 pr_debug("%s: Media selection failing, using default %s port.\n", 1859 dev->name, media_tbl[dev->if_port].name); 1860 } else { 1861 if (vortex_debug > 1) 1862 pr_debug("%s: Media selection failed, now trying %s port.\n", 1863 dev->name, media_tbl[dev->if_port].name); 1864 next_tick = media_tbl[dev->if_port].wait; 1865 } 1866 window_write16(vp, 1867 (media_status & ~(Media_10TP|Media_SQE)) | 1868 media_tbl[dev->if_port].media_bits, 1869 4, Wn4_Media); 1870 1871 config = window_read32(vp, 3, Wn3_Config); 1872 config = BFINS(config, dev->if_port, 20, 4); 1873 window_write32(vp, config, 3, Wn3_Config); 1874 1875 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax, 1876 ioaddr + EL3_CMD); 1877 if (vortex_debug > 1) 1878 pr_debug("wrote 0x%08x to Wn3_Config\n", config); 1879 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */ 1880 1881 spin_unlock_irq(&vp->lock); 1882 } 1883 1884 leave_media_alone: 1885 if (vortex_debug > 2) 1886 pr_debug("%s: Media selection timer finished, %s.\n", 1887 dev->name, media_tbl[dev->if_port].name); 1888 1889 mod_timer(&vp->timer, RUN_AT(next_tick)); 1890 if (vp->deferred) 1891 iowrite16(FakeIntr, ioaddr + EL3_CMD); 1892 } 1893 1894 static void vortex_tx_timeout(struct net_device *dev) 1895 { 1896 struct vortex_private *vp = netdev_priv(dev); 1897 void __iomem *ioaddr = vp->ioaddr; 1898 1899 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n", 1900 dev->name, ioread8(ioaddr + TxStatus), 1901 ioread16(ioaddr + EL3_STATUS)); 1902 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n", 1903 window_read16(vp, 4, Wn4_NetDiag), 1904 window_read16(vp, 4, Wn4_Media), 1905 ioread32(ioaddr + PktStatus), 1906 window_read16(vp, 4, Wn4_FIFODiag)); 1907 /* Slight code bloat to be user friendly. */ 1908 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88) 1909 pr_err("%s: Transmitter encountered 16 collisions --" 1910 " network cable problem?\n", dev->name); 1911 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) { 1912 pr_err("%s: Interrupt posted but not delivered --" 1913 " IRQ blocked by another device?\n", dev->name); 1914 /* Bad idea here.. but we might as well handle a few events. */ 1915 { 1916 /* 1917 * Block interrupts because vortex_interrupt does a bare spin_lock() 1918 */ 1919 unsigned long flags; 1920 local_irq_save(flags); 1921 if (vp->full_bus_master_tx) 1922 boomerang_interrupt(dev->irq, dev); 1923 else 1924 vortex_interrupt(dev->irq, dev); 1925 local_irq_restore(flags); 1926 } 1927 } 1928 1929 if (vortex_debug > 0) 1930 dump_tx_ring(dev); 1931 1932 issue_and_wait(dev, TxReset); 1933 1934 dev->stats.tx_errors++; 1935 if (vp->full_bus_master_tx) { 1936 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name); 1937 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0) 1938 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc), 1939 ioaddr + DownListPtr); 1940 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE) 1941 netif_wake_queue (dev); 1942 if (vp->drv_flags & IS_BOOMERANG) 1943 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); 1944 iowrite16(DownUnstall, ioaddr + EL3_CMD); 1945 } else { 1946 dev->stats.tx_dropped++; 1947 netif_wake_queue(dev); 1948 } 1949 1950 /* Issue Tx Enable */ 1951 iowrite16(TxEnable, ioaddr + EL3_CMD); 1952 dev->trans_start = jiffies; /* prevent tx timeout */ 1953 } 1954 1955 /* 1956 * Handle uncommon interrupt sources. This is a separate routine to minimize 1957 * the cache impact. 1958 */ 1959 static void 1960 vortex_error(struct net_device *dev, int status) 1961 { 1962 struct vortex_private *vp = netdev_priv(dev); 1963 void __iomem *ioaddr = vp->ioaddr; 1964 int do_tx_reset = 0, reset_mask = 0; 1965 unsigned char tx_status = 0; 1966 1967 if (vortex_debug > 2) { 1968 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status); 1969 } 1970 1971 if (status & TxComplete) { /* Really "TxError" for us. */ 1972 tx_status = ioread8(ioaddr + TxStatus); 1973 /* Presumably a tx-timeout. We must merely re-enable. */ 1974 if (vortex_debug > 2 || 1975 (tx_status != 0x88 && vortex_debug > 0)) { 1976 pr_err("%s: Transmit error, Tx status register %2.2x.\n", 1977 dev->name, tx_status); 1978 if (tx_status == 0x82) { 1979 pr_err("Probably a duplex mismatch. See " 1980 "Documentation/networking/vortex.txt\n"); 1981 } 1982 dump_tx_ring(dev); 1983 } 1984 if (tx_status & 0x14) dev->stats.tx_fifo_errors++; 1985 if (tx_status & 0x38) dev->stats.tx_aborted_errors++; 1986 if (tx_status & 0x08) vp->xstats.tx_max_collisions++; 1987 iowrite8(0, ioaddr + TxStatus); 1988 if (tx_status & 0x30) { /* txJabber or txUnderrun */ 1989 do_tx_reset = 1; 1990 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */ 1991 do_tx_reset = 1; 1992 reset_mask = 0x0108; /* Reset interface logic, but not download logic */ 1993 } else { /* Merely re-enable the transmitter. */ 1994 iowrite16(TxEnable, ioaddr + EL3_CMD); 1995 } 1996 } 1997 1998 if (status & RxEarly) /* Rx early is unused. */ 1999 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD); 2000 2001 if (status & StatsFull) { /* Empty statistics. */ 2002 static int DoneDidThat; 2003 if (vortex_debug > 4) 2004 pr_debug("%s: Updating stats.\n", dev->name); 2005 update_stats(ioaddr, dev); 2006 /* HACK: Disable statistics as an interrupt source. */ 2007 /* This occurs when we have the wrong media type! */ 2008 if (DoneDidThat == 0 && 2009 ioread16(ioaddr + EL3_STATUS) & StatsFull) { 2010 pr_warning("%s: Updating statistics failed, disabling " 2011 "stats as an interrupt source.\n", dev->name); 2012 iowrite16(SetIntrEnb | 2013 (window_read16(vp, 5, 10) & ~StatsFull), 2014 ioaddr + EL3_CMD); 2015 vp->intr_enable &= ~StatsFull; 2016 DoneDidThat++; 2017 } 2018 } 2019 if (status & IntReq) { /* Restore all interrupt sources. */ 2020 iowrite16(vp->status_enable, ioaddr + EL3_CMD); 2021 iowrite16(vp->intr_enable, ioaddr + EL3_CMD); 2022 } 2023 if (status & HostError) { 2024 u16 fifo_diag; 2025 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag); 2026 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n", 2027 dev->name, fifo_diag); 2028 /* Adapter failure requires Tx/Rx reset and reinit. */ 2029 if (vp->full_bus_master_tx) { 2030 int bus_status = ioread32(ioaddr + PktStatus); 2031 /* 0x80000000 PCI master abort. */ 2032 /* 0x40000000 PCI target abort. */ 2033 if (vortex_debug) 2034 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status); 2035 2036 /* In this case, blow the card away */ 2037 /* Must not enter D3 or we can't legally issue the reset! */ 2038 vortex_down(dev, 0); 2039 issue_and_wait(dev, TotalReset | 0xff); 2040 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */ 2041 } else if (fifo_diag & 0x0400) 2042 do_tx_reset = 1; 2043 if (fifo_diag & 0x3000) { 2044 /* Reset Rx fifo and upload logic */ 2045 issue_and_wait(dev, RxReset|0x07); 2046 /* Set the Rx filter to the current state. */ 2047 set_rx_mode(dev); 2048 /* enable 802.1q VLAN tagged frames */ 2049 set_8021q_mode(dev, 1); 2050 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */ 2051 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD); 2052 } 2053 } 2054 2055 if (do_tx_reset) { 2056 issue_and_wait(dev, TxReset|reset_mask); 2057 iowrite16(TxEnable, ioaddr + EL3_CMD); 2058 if (!vp->full_bus_master_tx) 2059 netif_wake_queue(dev); 2060 } 2061 } 2062 2063 static netdev_tx_t 2064 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev) 2065 { 2066 struct vortex_private *vp = netdev_priv(dev); 2067 void __iomem *ioaddr = vp->ioaddr; 2068 2069 /* Put out the doubleword header... */ 2070 iowrite32(skb->len, ioaddr + TX_FIFO); 2071 if (vp->bus_master) { 2072 /* Set the bus-master controller to transfer the packet. */ 2073 int len = (skb->len + 3) & ~3; 2074 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, 2075 PCI_DMA_TODEVICE); 2076 spin_lock_irq(&vp->window_lock); 2077 window_set(vp, 7); 2078 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr); 2079 iowrite16(len, ioaddr + Wn7_MasterLen); 2080 spin_unlock_irq(&vp->window_lock); 2081 vp->tx_skb = skb; 2082 iowrite16(StartDMADown, ioaddr + EL3_CMD); 2083 /* netif_wake_queue() will be called at the DMADone interrupt. */ 2084 } else { 2085 /* ... and the packet rounded to a doubleword. */ 2086 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2); 2087 dev_kfree_skb (skb); 2088 if (ioread16(ioaddr + TxFree) > 1536) { 2089 netif_start_queue (dev); /* AKPM: redundant? */ 2090 } else { 2091 /* Interrupt us when the FIFO has room for max-sized packet. */ 2092 netif_stop_queue(dev); 2093 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD); 2094 } 2095 } 2096 2097 2098 /* Clear the Tx status stack. */ 2099 { 2100 int tx_status; 2101 int i = 32; 2102 2103 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) { 2104 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */ 2105 if (vortex_debug > 2) 2106 pr_debug("%s: Tx error, status %2.2x.\n", 2107 dev->name, tx_status); 2108 if (tx_status & 0x04) dev->stats.tx_fifo_errors++; 2109 if (tx_status & 0x38) dev->stats.tx_aborted_errors++; 2110 if (tx_status & 0x30) { 2111 issue_and_wait(dev, TxReset); 2112 } 2113 iowrite16(TxEnable, ioaddr + EL3_CMD); 2114 } 2115 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */ 2116 } 2117 } 2118 return NETDEV_TX_OK; 2119 } 2120 2121 static netdev_tx_t 2122 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev) 2123 { 2124 struct vortex_private *vp = netdev_priv(dev); 2125 void __iomem *ioaddr = vp->ioaddr; 2126 /* Calculate the next Tx descriptor entry. */ 2127 int entry = vp->cur_tx % TX_RING_SIZE; 2128 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE]; 2129 unsigned long flags; 2130 2131 if (vortex_debug > 6) { 2132 pr_debug("boomerang_start_xmit()\n"); 2133 pr_debug("%s: Trying to send a packet, Tx index %d.\n", 2134 dev->name, vp->cur_tx); 2135 } 2136 2137 /* 2138 * We can't allow a recursion from our interrupt handler back into the 2139 * tx routine, as they take the same spin lock, and that causes 2140 * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in 2141 * a bit 2142 */ 2143 if (vp->handling_irq) 2144 return NETDEV_TX_BUSY; 2145 2146 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) { 2147 if (vortex_debug > 0) 2148 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n", 2149 dev->name); 2150 netif_stop_queue(dev); 2151 return NETDEV_TX_BUSY; 2152 } 2153 2154 vp->tx_skbuff[entry] = skb; 2155 2156 vp->tx_ring[entry].next = 0; 2157 #if DO_ZEROCOPY 2158 if (skb->ip_summed != CHECKSUM_PARTIAL) 2159 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded); 2160 else 2161 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum); 2162 2163 if (!skb_shinfo(skb)->nr_frags) { 2164 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, 2165 skb->len, PCI_DMA_TODEVICE)); 2166 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG); 2167 } else { 2168 int i; 2169 2170 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, 2171 skb_headlen(skb), PCI_DMA_TODEVICE)); 2172 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb)); 2173 2174 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 2175 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2176 2177 vp->tx_ring[entry].frag[i+1].addr = 2178 cpu_to_le32(pci_map_single( 2179 VORTEX_PCI(vp), 2180 (void *)skb_frag_address(frag), 2181 skb_frag_size(frag), PCI_DMA_TODEVICE)); 2182 2183 if (i == skb_shinfo(skb)->nr_frags-1) 2184 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG); 2185 else 2186 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)); 2187 } 2188 } 2189 #else 2190 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE)); 2191 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG); 2192 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded); 2193 #endif 2194 2195 spin_lock_irqsave(&vp->lock, flags); 2196 /* Wait for the stall to complete. */ 2197 issue_and_wait(dev, DownStall); 2198 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc)); 2199 if (ioread32(ioaddr + DownListPtr) == 0) { 2200 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr); 2201 vp->queued_packet++; 2202 } 2203 2204 vp->cur_tx++; 2205 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) { 2206 netif_stop_queue (dev); 2207 } else { /* Clear previous interrupt enable. */ 2208 #if defined(tx_interrupt_mitigation) 2209 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef 2210 * were selected, this would corrupt DN_COMPLETE. No? 2211 */ 2212 prev_entry->status &= cpu_to_le32(~TxIntrUploaded); 2213 #endif 2214 } 2215 iowrite16(DownUnstall, ioaddr + EL3_CMD); 2216 spin_unlock_irqrestore(&vp->lock, flags); 2217 return NETDEV_TX_OK; 2218 } 2219 2220 /* The interrupt handler does all of the Rx thread work and cleans up 2221 after the Tx thread. */ 2222 2223 /* 2224 * This is the ISR for the vortex series chips. 2225 * full_bus_master_tx == 0 && full_bus_master_rx == 0 2226 */ 2227 2228 static irqreturn_t 2229 vortex_interrupt(int irq, void *dev_id) 2230 { 2231 struct net_device *dev = dev_id; 2232 struct vortex_private *vp = netdev_priv(dev); 2233 void __iomem *ioaddr; 2234 int status; 2235 int work_done = max_interrupt_work; 2236 int handled = 0; 2237 2238 ioaddr = vp->ioaddr; 2239 spin_lock(&vp->lock); 2240 2241 status = ioread16(ioaddr + EL3_STATUS); 2242 2243 if (vortex_debug > 6) 2244 pr_debug("vortex_interrupt(). status=0x%4x\n", status); 2245 2246 if ((status & IntLatch) == 0) 2247 goto handler_exit; /* No interrupt: shared IRQs cause this */ 2248 handled = 1; 2249 2250 if (status & IntReq) { 2251 status |= vp->deferred; 2252 vp->deferred = 0; 2253 } 2254 2255 if (status == 0xffff) /* h/w no longer present (hotplug)? */ 2256 goto handler_exit; 2257 2258 if (vortex_debug > 4) 2259 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n", 2260 dev->name, status, ioread8(ioaddr + Timer)); 2261 2262 spin_lock(&vp->window_lock); 2263 window_set(vp, 7); 2264 2265 do { 2266 if (vortex_debug > 5) 2267 pr_debug("%s: In interrupt loop, status %4.4x.\n", 2268 dev->name, status); 2269 if (status & RxComplete) 2270 vortex_rx(dev); 2271 2272 if (status & TxAvailable) { 2273 if (vortex_debug > 5) 2274 pr_debug(" TX room bit was handled.\n"); 2275 /* There's room in the FIFO for a full-sized packet. */ 2276 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD); 2277 netif_wake_queue (dev); 2278 } 2279 2280 if (status & DMADone) { 2281 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) { 2282 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */ 2283 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE); 2284 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */ 2285 if (ioread16(ioaddr + TxFree) > 1536) { 2286 /* 2287 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to 2288 * insufficient FIFO room, the TxAvailable test will succeed and call 2289 * netif_wake_queue() 2290 */ 2291 netif_wake_queue(dev); 2292 } else { /* Interrupt when FIFO has room for max-sized packet. */ 2293 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD); 2294 netif_stop_queue(dev); 2295 } 2296 } 2297 } 2298 /* Check for all uncommon interrupts at once. */ 2299 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) { 2300 if (status == 0xffff) 2301 break; 2302 if (status & RxEarly) 2303 vortex_rx(dev); 2304 spin_unlock(&vp->window_lock); 2305 vortex_error(dev, status); 2306 spin_lock(&vp->window_lock); 2307 window_set(vp, 7); 2308 } 2309 2310 if (--work_done < 0) { 2311 pr_warning("%s: Too much work in interrupt, status %4.4x.\n", 2312 dev->name, status); 2313 /* Disable all pending interrupts. */ 2314 do { 2315 vp->deferred |= status; 2316 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable), 2317 ioaddr + EL3_CMD); 2318 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD); 2319 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch); 2320 /* The timer will reenable interrupts. */ 2321 mod_timer(&vp->timer, jiffies + 1*HZ); 2322 break; 2323 } 2324 /* Acknowledge the IRQ. */ 2325 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD); 2326 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete)); 2327 2328 spin_unlock(&vp->window_lock); 2329 2330 if (vortex_debug > 4) 2331 pr_debug("%s: exiting interrupt, status %4.4x.\n", 2332 dev->name, status); 2333 handler_exit: 2334 spin_unlock(&vp->lock); 2335 return IRQ_RETVAL(handled); 2336 } 2337 2338 /* 2339 * This is the ISR for the boomerang series chips. 2340 * full_bus_master_tx == 1 && full_bus_master_rx == 1 2341 */ 2342 2343 static irqreturn_t 2344 boomerang_interrupt(int irq, void *dev_id) 2345 { 2346 struct net_device *dev = dev_id; 2347 struct vortex_private *vp = netdev_priv(dev); 2348 void __iomem *ioaddr; 2349 int status; 2350 int work_done = max_interrupt_work; 2351 2352 ioaddr = vp->ioaddr; 2353 2354 2355 /* 2356 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout 2357 * and boomerang_start_xmit 2358 */ 2359 spin_lock(&vp->lock); 2360 vp->handling_irq = 1; 2361 2362 status = ioread16(ioaddr + EL3_STATUS); 2363 2364 if (vortex_debug > 6) 2365 pr_debug("boomerang_interrupt. status=0x%4x\n", status); 2366 2367 if ((status & IntLatch) == 0) 2368 goto handler_exit; /* No interrupt: shared IRQs can cause this */ 2369 2370 if (status == 0xffff) { /* h/w no longer present (hotplug)? */ 2371 if (vortex_debug > 1) 2372 pr_debug("boomerang_interrupt(1): status = 0xffff\n"); 2373 goto handler_exit; 2374 } 2375 2376 if (status & IntReq) { 2377 status |= vp->deferred; 2378 vp->deferred = 0; 2379 } 2380 2381 if (vortex_debug > 4) 2382 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n", 2383 dev->name, status, ioread8(ioaddr + Timer)); 2384 do { 2385 if (vortex_debug > 5) 2386 pr_debug("%s: In interrupt loop, status %4.4x.\n", 2387 dev->name, status); 2388 if (status & UpComplete) { 2389 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD); 2390 if (vortex_debug > 5) 2391 pr_debug("boomerang_interrupt->boomerang_rx\n"); 2392 boomerang_rx(dev); 2393 } 2394 2395 if (status & DownComplete) { 2396 unsigned int dirty_tx = vp->dirty_tx; 2397 2398 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD); 2399 while (vp->cur_tx - dirty_tx > 0) { 2400 int entry = dirty_tx % TX_RING_SIZE; 2401 #if 1 /* AKPM: the latter is faster, but cyclone-only */ 2402 if (ioread32(ioaddr + DownListPtr) == 2403 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc)) 2404 break; /* It still hasn't been processed. */ 2405 #else 2406 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0) 2407 break; /* It still hasn't been processed. */ 2408 #endif 2409 2410 if (vp->tx_skbuff[entry]) { 2411 struct sk_buff *skb = vp->tx_skbuff[entry]; 2412 #if DO_ZEROCOPY 2413 int i; 2414 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++) 2415 pci_unmap_single(VORTEX_PCI(vp), 2416 le32_to_cpu(vp->tx_ring[entry].frag[i].addr), 2417 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF, 2418 PCI_DMA_TODEVICE); 2419 #else 2420 pci_unmap_single(VORTEX_PCI(vp), 2421 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE); 2422 #endif 2423 dev_kfree_skb_irq(skb); 2424 vp->tx_skbuff[entry] = NULL; 2425 } else { 2426 pr_debug("boomerang_interrupt: no skb!\n"); 2427 } 2428 /* dev->stats.tx_packets++; Counted below. */ 2429 dirty_tx++; 2430 } 2431 vp->dirty_tx = dirty_tx; 2432 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) { 2433 if (vortex_debug > 6) 2434 pr_debug("boomerang_interrupt: wake queue\n"); 2435 netif_wake_queue (dev); 2436 } 2437 } 2438 2439 /* Check for all uncommon interrupts at once. */ 2440 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) 2441 vortex_error(dev, status); 2442 2443 if (--work_done < 0) { 2444 pr_warning("%s: Too much work in interrupt, status %4.4x.\n", 2445 dev->name, status); 2446 /* Disable all pending interrupts. */ 2447 do { 2448 vp->deferred |= status; 2449 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable), 2450 ioaddr + EL3_CMD); 2451 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD); 2452 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch); 2453 /* The timer will reenable interrupts. */ 2454 mod_timer(&vp->timer, jiffies + 1*HZ); 2455 break; 2456 } 2457 /* Acknowledge the IRQ. */ 2458 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD); 2459 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */ 2460 iowrite32(0x8000, vp->cb_fn_base + 4); 2461 2462 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch); 2463 2464 if (vortex_debug > 4) 2465 pr_debug("%s: exiting interrupt, status %4.4x.\n", 2466 dev->name, status); 2467 handler_exit: 2468 vp->handling_irq = 0; 2469 spin_unlock(&vp->lock); 2470 return IRQ_HANDLED; 2471 } 2472 2473 static int vortex_rx(struct net_device *dev) 2474 { 2475 struct vortex_private *vp = netdev_priv(dev); 2476 void __iomem *ioaddr = vp->ioaddr; 2477 int i; 2478 short rx_status; 2479 2480 if (vortex_debug > 5) 2481 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n", 2482 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus)); 2483 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) { 2484 if (rx_status & 0x4000) { /* Error, update stats. */ 2485 unsigned char rx_error = ioread8(ioaddr + RxErrors); 2486 if (vortex_debug > 2) 2487 pr_debug(" Rx error: status %2.2x.\n", rx_error); 2488 dev->stats.rx_errors++; 2489 if (rx_error & 0x01) dev->stats.rx_over_errors++; 2490 if (rx_error & 0x02) dev->stats.rx_length_errors++; 2491 if (rx_error & 0x04) dev->stats.rx_frame_errors++; 2492 if (rx_error & 0x08) dev->stats.rx_crc_errors++; 2493 if (rx_error & 0x10) dev->stats.rx_length_errors++; 2494 } else { 2495 /* The packet length: up to 4.5K!. */ 2496 int pkt_len = rx_status & 0x1fff; 2497 struct sk_buff *skb; 2498 2499 skb = netdev_alloc_skb(dev, pkt_len + 5); 2500 if (vortex_debug > 4) 2501 pr_debug("Receiving packet size %d status %4.4x.\n", 2502 pkt_len, rx_status); 2503 if (skb != NULL) { 2504 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ 2505 /* 'skb_put()' points to the start of sk_buff data area. */ 2506 if (vp->bus_master && 2507 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) { 2508 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len), 2509 pkt_len, PCI_DMA_FROMDEVICE); 2510 iowrite32(dma, ioaddr + Wn7_MasterAddr); 2511 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen); 2512 iowrite16(StartDMAUp, ioaddr + EL3_CMD); 2513 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000) 2514 ; 2515 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE); 2516 } else { 2517 ioread32_rep(ioaddr + RX_FIFO, 2518 skb_put(skb, pkt_len), 2519 (pkt_len + 3) >> 2); 2520 } 2521 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */ 2522 skb->protocol = eth_type_trans(skb, dev); 2523 netif_rx(skb); 2524 dev->stats.rx_packets++; 2525 /* Wait a limited time to go to next packet. */ 2526 for (i = 200; i >= 0; i--) 2527 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) 2528 break; 2529 continue; 2530 } else if (vortex_debug > 0) 2531 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n", 2532 dev->name, pkt_len); 2533 dev->stats.rx_dropped++; 2534 } 2535 issue_and_wait(dev, RxDiscard); 2536 } 2537 2538 return 0; 2539 } 2540 2541 static int 2542 boomerang_rx(struct net_device *dev) 2543 { 2544 struct vortex_private *vp = netdev_priv(dev); 2545 int entry = vp->cur_rx % RX_RING_SIZE; 2546 void __iomem *ioaddr = vp->ioaddr; 2547 int rx_status; 2548 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx; 2549 2550 if (vortex_debug > 5) 2551 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS)); 2552 2553 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){ 2554 if (--rx_work_limit < 0) 2555 break; 2556 if (rx_status & RxDError) { /* Error, update stats. */ 2557 unsigned char rx_error = rx_status >> 16; 2558 if (vortex_debug > 2) 2559 pr_debug(" Rx error: status %2.2x.\n", rx_error); 2560 dev->stats.rx_errors++; 2561 if (rx_error & 0x01) dev->stats.rx_over_errors++; 2562 if (rx_error & 0x02) dev->stats.rx_length_errors++; 2563 if (rx_error & 0x04) dev->stats.rx_frame_errors++; 2564 if (rx_error & 0x08) dev->stats.rx_crc_errors++; 2565 if (rx_error & 0x10) dev->stats.rx_length_errors++; 2566 } else { 2567 /* The packet length: up to 4.5K!. */ 2568 int pkt_len = rx_status & 0x1fff; 2569 struct sk_buff *skb; 2570 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr); 2571 2572 if (vortex_debug > 4) 2573 pr_debug("Receiving packet size %d status %4.4x.\n", 2574 pkt_len, rx_status); 2575 2576 /* Check if the packet is long enough to just accept without 2577 copying to a properly sized skbuff. */ 2578 if (pkt_len < rx_copybreak && 2579 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) { 2580 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ 2581 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 2582 /* 'skb_put()' points to the start of sk_buff data area. */ 2583 memcpy(skb_put(skb, pkt_len), 2584 vp->rx_skbuff[entry]->data, 2585 pkt_len); 2586 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 2587 vp->rx_copy++; 2588 } else { 2589 /* Pass up the skbuff already on the Rx ring. */ 2590 skb = vp->rx_skbuff[entry]; 2591 vp->rx_skbuff[entry] = NULL; 2592 skb_put(skb, pkt_len); 2593 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 2594 vp->rx_nocopy++; 2595 } 2596 skb->protocol = eth_type_trans(skb, dev); 2597 { /* Use hardware checksum info. */ 2598 int csum_bits = rx_status & 0xee000000; 2599 if (csum_bits && 2600 (csum_bits == (IPChksumValid | TCPChksumValid) || 2601 csum_bits == (IPChksumValid | UDPChksumValid))) { 2602 skb->ip_summed = CHECKSUM_UNNECESSARY; 2603 vp->rx_csumhits++; 2604 } 2605 } 2606 netif_rx(skb); 2607 dev->stats.rx_packets++; 2608 } 2609 entry = (++vp->cur_rx) % RX_RING_SIZE; 2610 } 2611 /* Refill the Rx ring buffers. */ 2612 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) { 2613 struct sk_buff *skb; 2614 entry = vp->dirty_rx % RX_RING_SIZE; 2615 if (vp->rx_skbuff[entry] == NULL) { 2616 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ); 2617 if (skb == NULL) { 2618 static unsigned long last_jif; 2619 if (time_after(jiffies, last_jif + 10 * HZ)) { 2620 pr_warning("%s: memory shortage\n", dev->name); 2621 last_jif = jiffies; 2622 } 2623 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) 2624 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1)); 2625 break; /* Bad news! */ 2626 } 2627 2628 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE)); 2629 vp->rx_skbuff[entry] = skb; 2630 } 2631 vp->rx_ring[entry].status = 0; /* Clear complete bit. */ 2632 iowrite16(UpUnstall, ioaddr + EL3_CMD); 2633 } 2634 return 0; 2635 } 2636 2637 /* 2638 * If we've hit a total OOM refilling the Rx ring we poll once a second 2639 * for some memory. Otherwise there is no way to restart the rx process. 2640 */ 2641 static void 2642 rx_oom_timer(unsigned long arg) 2643 { 2644 struct net_device *dev = (struct net_device *)arg; 2645 struct vortex_private *vp = netdev_priv(dev); 2646 2647 spin_lock_irq(&vp->lock); 2648 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */ 2649 boomerang_rx(dev); 2650 if (vortex_debug > 1) { 2651 pr_debug("%s: rx_oom_timer %s\n", dev->name, 2652 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying"); 2653 } 2654 spin_unlock_irq(&vp->lock); 2655 } 2656 2657 static void 2658 vortex_down(struct net_device *dev, int final_down) 2659 { 2660 struct vortex_private *vp = netdev_priv(dev); 2661 void __iomem *ioaddr = vp->ioaddr; 2662 2663 netif_stop_queue (dev); 2664 2665 del_timer_sync(&vp->rx_oom_timer); 2666 del_timer_sync(&vp->timer); 2667 2668 /* Turn off statistics ASAP. We update dev->stats below. */ 2669 iowrite16(StatsDisable, ioaddr + EL3_CMD); 2670 2671 /* Disable the receiver and transmitter. */ 2672 iowrite16(RxDisable, ioaddr + EL3_CMD); 2673 iowrite16(TxDisable, ioaddr + EL3_CMD); 2674 2675 /* Disable receiving 802.1q tagged frames */ 2676 set_8021q_mode(dev, 0); 2677 2678 if (dev->if_port == XCVR_10base2) 2679 /* Turn off thinnet power. Green! */ 2680 iowrite16(StopCoax, ioaddr + EL3_CMD); 2681 2682 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD); 2683 2684 update_stats(ioaddr, dev); 2685 if (vp->full_bus_master_rx) 2686 iowrite32(0, ioaddr + UpListPtr); 2687 if (vp->full_bus_master_tx) 2688 iowrite32(0, ioaddr + DownListPtr); 2689 2690 if (final_down && VORTEX_PCI(vp)) { 2691 vp->pm_state_valid = 1; 2692 pci_save_state(VORTEX_PCI(vp)); 2693 acpi_set_WOL(dev); 2694 } 2695 } 2696 2697 static int 2698 vortex_close(struct net_device *dev) 2699 { 2700 struct vortex_private *vp = netdev_priv(dev); 2701 void __iomem *ioaddr = vp->ioaddr; 2702 int i; 2703 2704 if (netif_device_present(dev)) 2705 vortex_down(dev, 1); 2706 2707 if (vortex_debug > 1) { 2708 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n", 2709 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus)); 2710 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d" 2711 " tx_queued %d Rx pre-checksummed %d.\n", 2712 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits); 2713 } 2714 2715 #if DO_ZEROCOPY 2716 if (vp->rx_csumhits && 2717 (vp->drv_flags & HAS_HWCKSM) == 0 && 2718 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) { 2719 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name); 2720 } 2721 #endif 2722 2723 free_irq(dev->irq, dev); 2724 2725 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */ 2726 for (i = 0; i < RX_RING_SIZE; i++) 2727 if (vp->rx_skbuff[i]) { 2728 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr), 2729 PKT_BUF_SZ, PCI_DMA_FROMDEVICE); 2730 dev_kfree_skb(vp->rx_skbuff[i]); 2731 vp->rx_skbuff[i] = NULL; 2732 } 2733 } 2734 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */ 2735 for (i = 0; i < TX_RING_SIZE; i++) { 2736 if (vp->tx_skbuff[i]) { 2737 struct sk_buff *skb = vp->tx_skbuff[i]; 2738 #if DO_ZEROCOPY 2739 int k; 2740 2741 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++) 2742 pci_unmap_single(VORTEX_PCI(vp), 2743 le32_to_cpu(vp->tx_ring[i].frag[k].addr), 2744 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF, 2745 PCI_DMA_TODEVICE); 2746 #else 2747 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE); 2748 #endif 2749 dev_kfree_skb(skb); 2750 vp->tx_skbuff[i] = NULL; 2751 } 2752 } 2753 } 2754 2755 return 0; 2756 } 2757 2758 static void 2759 dump_tx_ring(struct net_device *dev) 2760 { 2761 if (vortex_debug > 0) { 2762 struct vortex_private *vp = netdev_priv(dev); 2763 void __iomem *ioaddr = vp->ioaddr; 2764 2765 if (vp->full_bus_master_tx) { 2766 int i; 2767 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */ 2768 2769 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n", 2770 vp->full_bus_master_tx, 2771 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE, 2772 vp->cur_tx, vp->cur_tx % TX_RING_SIZE); 2773 pr_err(" Transmit list %8.8x vs. %p.\n", 2774 ioread32(ioaddr + DownListPtr), 2775 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]); 2776 issue_and_wait(dev, DownStall); 2777 for (i = 0; i < TX_RING_SIZE; i++) { 2778 unsigned int length; 2779 2780 #if DO_ZEROCOPY 2781 length = le32_to_cpu(vp->tx_ring[i].frag[0].length); 2782 #else 2783 length = le32_to_cpu(vp->tx_ring[i].length); 2784 #endif 2785 pr_err(" %d: @%p length %8.8x status %8.8x\n", 2786 i, &vp->tx_ring[i], length, 2787 le32_to_cpu(vp->tx_ring[i].status)); 2788 } 2789 if (!stalled) 2790 iowrite16(DownUnstall, ioaddr + EL3_CMD); 2791 } 2792 } 2793 } 2794 2795 static struct net_device_stats *vortex_get_stats(struct net_device *dev) 2796 { 2797 struct vortex_private *vp = netdev_priv(dev); 2798 void __iomem *ioaddr = vp->ioaddr; 2799 unsigned long flags; 2800 2801 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */ 2802 spin_lock_irqsave (&vp->lock, flags); 2803 update_stats(ioaddr, dev); 2804 spin_unlock_irqrestore (&vp->lock, flags); 2805 } 2806 return &dev->stats; 2807 } 2808 2809 /* Update statistics. 2810 Unlike with the EL3 we need not worry about interrupts changing 2811 the window setting from underneath us, but we must still guard 2812 against a race condition with a StatsUpdate interrupt updating the 2813 table. This is done by checking that the ASM (!) code generated uses 2814 atomic updates with '+='. 2815 */ 2816 static void update_stats(void __iomem *ioaddr, struct net_device *dev) 2817 { 2818 struct vortex_private *vp = netdev_priv(dev); 2819 2820 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */ 2821 /* Switch to the stats window, and read everything. */ 2822 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0); 2823 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1); 2824 dev->stats.tx_window_errors += window_read8(vp, 6, 4); 2825 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5); 2826 dev->stats.tx_packets += window_read8(vp, 6, 6); 2827 dev->stats.tx_packets += (window_read8(vp, 6, 9) & 2828 0x30) << 4; 2829 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */ 2830 /* Don't bother with register 9, an extension of registers 6&7. 2831 If we do use the 6&7 values the atomic update assumption above 2832 is invalid. */ 2833 dev->stats.rx_bytes += window_read16(vp, 6, 10); 2834 dev->stats.tx_bytes += window_read16(vp, 6, 12); 2835 /* Extra stats for get_ethtool_stats() */ 2836 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2); 2837 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3); 2838 vp->xstats.tx_deferred += window_read8(vp, 6, 8); 2839 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12); 2840 2841 dev->stats.collisions = vp->xstats.tx_multiple_collisions 2842 + vp->xstats.tx_single_collisions 2843 + vp->xstats.tx_max_collisions; 2844 2845 { 2846 u8 up = window_read8(vp, 4, 13); 2847 dev->stats.rx_bytes += (up & 0x0f) << 16; 2848 dev->stats.tx_bytes += (up & 0xf0) << 12; 2849 } 2850 } 2851 2852 static int vortex_nway_reset(struct net_device *dev) 2853 { 2854 struct vortex_private *vp = netdev_priv(dev); 2855 2856 return mii_nway_restart(&vp->mii); 2857 } 2858 2859 static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2860 { 2861 struct vortex_private *vp = netdev_priv(dev); 2862 2863 return mii_ethtool_gset(&vp->mii, cmd); 2864 } 2865 2866 static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2867 { 2868 struct vortex_private *vp = netdev_priv(dev); 2869 2870 return mii_ethtool_sset(&vp->mii, cmd); 2871 } 2872 2873 static u32 vortex_get_msglevel(struct net_device *dev) 2874 { 2875 return vortex_debug; 2876 } 2877 2878 static void vortex_set_msglevel(struct net_device *dev, u32 dbg) 2879 { 2880 vortex_debug = dbg; 2881 } 2882 2883 static int vortex_get_sset_count(struct net_device *dev, int sset) 2884 { 2885 switch (sset) { 2886 case ETH_SS_STATS: 2887 return VORTEX_NUM_STATS; 2888 default: 2889 return -EOPNOTSUPP; 2890 } 2891 } 2892 2893 static void vortex_get_ethtool_stats(struct net_device *dev, 2894 struct ethtool_stats *stats, u64 *data) 2895 { 2896 struct vortex_private *vp = netdev_priv(dev); 2897 void __iomem *ioaddr = vp->ioaddr; 2898 unsigned long flags; 2899 2900 spin_lock_irqsave(&vp->lock, flags); 2901 update_stats(ioaddr, dev); 2902 spin_unlock_irqrestore(&vp->lock, flags); 2903 2904 data[0] = vp->xstats.tx_deferred; 2905 data[1] = vp->xstats.tx_max_collisions; 2906 data[2] = vp->xstats.tx_multiple_collisions; 2907 data[3] = vp->xstats.tx_single_collisions; 2908 data[4] = vp->xstats.rx_bad_ssd; 2909 } 2910 2911 2912 static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2913 { 2914 switch (stringset) { 2915 case ETH_SS_STATS: 2916 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys)); 2917 break; 2918 default: 2919 WARN_ON(1); 2920 break; 2921 } 2922 } 2923 2924 static void vortex_get_drvinfo(struct net_device *dev, 2925 struct ethtool_drvinfo *info) 2926 { 2927 struct vortex_private *vp = netdev_priv(dev); 2928 2929 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 2930 if (VORTEX_PCI(vp)) { 2931 strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)), 2932 sizeof(info->bus_info)); 2933 } else { 2934 if (VORTEX_EISA(vp)) 2935 strlcpy(info->bus_info, dev_name(vp->gendev), 2936 sizeof(info->bus_info)); 2937 else 2938 snprintf(info->bus_info, sizeof(info->bus_info), 2939 "EISA 0x%lx %d", dev->base_addr, dev->irq); 2940 } 2941 } 2942 2943 static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2944 { 2945 struct vortex_private *vp = netdev_priv(dev); 2946 2947 if (!VORTEX_PCI(vp)) 2948 return; 2949 2950 wol->supported = WAKE_MAGIC; 2951 2952 wol->wolopts = 0; 2953 if (vp->enable_wol) 2954 wol->wolopts |= WAKE_MAGIC; 2955 } 2956 2957 static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2958 { 2959 struct vortex_private *vp = netdev_priv(dev); 2960 2961 if (!VORTEX_PCI(vp)) 2962 return -EOPNOTSUPP; 2963 2964 if (wol->wolopts & ~WAKE_MAGIC) 2965 return -EINVAL; 2966 2967 if (wol->wolopts & WAKE_MAGIC) 2968 vp->enable_wol = 1; 2969 else 2970 vp->enable_wol = 0; 2971 acpi_set_WOL(dev); 2972 2973 return 0; 2974 } 2975 2976 static const struct ethtool_ops vortex_ethtool_ops = { 2977 .get_drvinfo = vortex_get_drvinfo, 2978 .get_strings = vortex_get_strings, 2979 .get_msglevel = vortex_get_msglevel, 2980 .set_msglevel = vortex_set_msglevel, 2981 .get_ethtool_stats = vortex_get_ethtool_stats, 2982 .get_sset_count = vortex_get_sset_count, 2983 .get_settings = vortex_get_settings, 2984 .set_settings = vortex_set_settings, 2985 .get_link = ethtool_op_get_link, 2986 .nway_reset = vortex_nway_reset, 2987 .get_wol = vortex_get_wol, 2988 .set_wol = vortex_set_wol, 2989 }; 2990 2991 #ifdef CONFIG_PCI 2992 /* 2993 * Must power the device up to do MDIO operations 2994 */ 2995 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2996 { 2997 int err; 2998 struct vortex_private *vp = netdev_priv(dev); 2999 pci_power_t state = 0; 3000 3001 if(VORTEX_PCI(vp)) 3002 state = VORTEX_PCI(vp)->current_state; 3003 3004 /* The kernel core really should have pci_get_power_state() */ 3005 3006 if(state != 0) 3007 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); 3008 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL); 3009 if(state != 0) 3010 pci_set_power_state(VORTEX_PCI(vp), state); 3011 3012 return err; 3013 } 3014 #endif 3015 3016 3017 /* Pre-Cyclone chips have no documented multicast filter, so the only 3018 multicast setting is to receive all multicast frames. At least 3019 the chip has a very clean way to set the mode, unlike many others. */ 3020 static void set_rx_mode(struct net_device *dev) 3021 { 3022 struct vortex_private *vp = netdev_priv(dev); 3023 void __iomem *ioaddr = vp->ioaddr; 3024 int new_mode; 3025 3026 if (dev->flags & IFF_PROMISC) { 3027 if (vortex_debug > 3) 3028 pr_notice("%s: Setting promiscuous mode.\n", dev->name); 3029 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm; 3030 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) { 3031 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast; 3032 } else 3033 new_mode = SetRxFilter | RxStation | RxBroadcast; 3034 3035 iowrite16(new_mode, ioaddr + EL3_CMD); 3036 } 3037 3038 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 3039 /* Setup the card so that it can receive frames with an 802.1q VLAN tag. 3040 Note that this must be done after each RxReset due to some backwards 3041 compatibility logic in the Cyclone and Tornado ASICs */ 3042 3043 /* The Ethernet Type used for 802.1q tagged frames */ 3044 #define VLAN_ETHER_TYPE 0x8100 3045 3046 static void set_8021q_mode(struct net_device *dev, int enable) 3047 { 3048 struct vortex_private *vp = netdev_priv(dev); 3049 int mac_ctrl; 3050 3051 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) { 3052 /* cyclone and tornado chipsets can recognize 802.1q 3053 * tagged frames and treat them correctly */ 3054 3055 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */ 3056 if (enable) 3057 max_pkt_size += 4; /* 802.1Q VLAN tag */ 3058 3059 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize); 3060 3061 /* set VlanEtherType to let the hardware checksumming 3062 treat tagged frames correctly */ 3063 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType); 3064 } else { 3065 /* on older cards we have to enable large frames */ 3066 3067 vp->large_frames = dev->mtu > 1500 || enable; 3068 3069 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl); 3070 if (vp->large_frames) 3071 mac_ctrl |= 0x40; 3072 else 3073 mac_ctrl &= ~0x40; 3074 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl); 3075 } 3076 } 3077 #else 3078 3079 static void set_8021q_mode(struct net_device *dev, int enable) 3080 { 3081 } 3082 3083 3084 #endif 3085 3086 /* MII transceiver control section. 3087 Read and write the MII registers using software-generated serial 3088 MDIO protocol. See the MII specifications or DP83840A data sheet 3089 for details. */ 3090 3091 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually 3092 met by back-to-back PCI I/O cycles, but we insert a delay to avoid 3093 "overclocking" issues. */ 3094 static void mdio_delay(struct vortex_private *vp) 3095 { 3096 window_read32(vp, 4, Wn4_PhysicalMgmt); 3097 } 3098 3099 #define MDIO_SHIFT_CLK 0x01 3100 #define MDIO_DIR_WRITE 0x04 3101 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE) 3102 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE) 3103 #define MDIO_DATA_READ 0x02 3104 #define MDIO_ENB_IN 0x00 3105 3106 /* Generate the preamble required for initial synchronization and 3107 a few older transceivers. */ 3108 static void mdio_sync(struct vortex_private *vp, int bits) 3109 { 3110 /* Establish sync by sending at least 32 logic ones. */ 3111 while (-- bits >= 0) { 3112 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt); 3113 mdio_delay(vp); 3114 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, 3115 4, Wn4_PhysicalMgmt); 3116 mdio_delay(vp); 3117 } 3118 } 3119 3120 static int mdio_read(struct net_device *dev, int phy_id, int location) 3121 { 3122 int i; 3123 struct vortex_private *vp = netdev_priv(dev); 3124 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location; 3125 unsigned int retval = 0; 3126 3127 spin_lock_bh(&vp->mii_lock); 3128 3129 if (mii_preamble_required) 3130 mdio_sync(vp, 32); 3131 3132 /* Shift the read command bits out. */ 3133 for (i = 14; i >= 0; i--) { 3134 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0; 3135 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt); 3136 mdio_delay(vp); 3137 window_write16(vp, dataval | MDIO_SHIFT_CLK, 3138 4, Wn4_PhysicalMgmt); 3139 mdio_delay(vp); 3140 } 3141 /* Read the two transition, 16 data, and wire-idle bits. */ 3142 for (i = 19; i > 0; i--) { 3143 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt); 3144 mdio_delay(vp); 3145 retval = (retval << 1) | 3146 ((window_read16(vp, 4, Wn4_PhysicalMgmt) & 3147 MDIO_DATA_READ) ? 1 : 0); 3148 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK, 3149 4, Wn4_PhysicalMgmt); 3150 mdio_delay(vp); 3151 } 3152 3153 spin_unlock_bh(&vp->mii_lock); 3154 3155 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff; 3156 } 3157 3158 static void mdio_write(struct net_device *dev, int phy_id, int location, int value) 3159 { 3160 struct vortex_private *vp = netdev_priv(dev); 3161 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value; 3162 int i; 3163 3164 spin_lock_bh(&vp->mii_lock); 3165 3166 if (mii_preamble_required) 3167 mdio_sync(vp, 32); 3168 3169 /* Shift the command bits out. */ 3170 for (i = 31; i >= 0; i--) { 3171 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0; 3172 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt); 3173 mdio_delay(vp); 3174 window_write16(vp, dataval | MDIO_SHIFT_CLK, 3175 4, Wn4_PhysicalMgmt); 3176 mdio_delay(vp); 3177 } 3178 /* Leave the interface idle. */ 3179 for (i = 1; i >= 0; i--) { 3180 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt); 3181 mdio_delay(vp); 3182 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK, 3183 4, Wn4_PhysicalMgmt); 3184 mdio_delay(vp); 3185 } 3186 3187 spin_unlock_bh(&vp->mii_lock); 3188 } 3189 3190 /* ACPI: Advanced Configuration and Power Interface. */ 3191 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */ 3192 static void acpi_set_WOL(struct net_device *dev) 3193 { 3194 struct vortex_private *vp = netdev_priv(dev); 3195 void __iomem *ioaddr = vp->ioaddr; 3196 3197 device_set_wakeup_enable(vp->gendev, vp->enable_wol); 3198 3199 if (vp->enable_wol) { 3200 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */ 3201 window_write16(vp, 2, 7, 0x0c); 3202 /* The RxFilter must accept the WOL frames. */ 3203 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD); 3204 iowrite16(RxEnable, ioaddr + EL3_CMD); 3205 3206 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) { 3207 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp))); 3208 3209 vp->enable_wol = 0; 3210 return; 3211 } 3212 3213 if (VORTEX_PCI(vp)->current_state < PCI_D3hot) 3214 return; 3215 3216 /* Change the power state to D3; RxEnable doesn't take effect. */ 3217 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot); 3218 } 3219 } 3220 3221 3222 static void vortex_remove_one(struct pci_dev *pdev) 3223 { 3224 struct net_device *dev = pci_get_drvdata(pdev); 3225 struct vortex_private *vp; 3226 3227 if (!dev) { 3228 pr_err("vortex_remove_one called for Compaq device!\n"); 3229 BUG(); 3230 } 3231 3232 vp = netdev_priv(dev); 3233 3234 if (vp->cb_fn_base) 3235 pci_iounmap(pdev, vp->cb_fn_base); 3236 3237 unregister_netdev(dev); 3238 3239 pci_set_power_state(pdev, PCI_D0); /* Go active */ 3240 if (vp->pm_state_valid) 3241 pci_restore_state(pdev); 3242 pci_disable_device(pdev); 3243 3244 /* Should really use issue_and_wait() here */ 3245 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14), 3246 vp->ioaddr + EL3_CMD); 3247 3248 pci_iounmap(pdev, vp->ioaddr); 3249 3250 pci_free_consistent(pdev, 3251 sizeof(struct boom_rx_desc) * RX_RING_SIZE 3252 + sizeof(struct boom_tx_desc) * TX_RING_SIZE, 3253 vp->rx_ring, 3254 vp->rx_ring_dma); 3255 3256 pci_release_regions(pdev); 3257 3258 free_netdev(dev); 3259 } 3260 3261 3262 static struct pci_driver vortex_driver = { 3263 .name = "3c59x", 3264 .probe = vortex_init_one, 3265 .remove = vortex_remove_one, 3266 .id_table = vortex_pci_tbl, 3267 .driver.pm = VORTEX_PM_OPS, 3268 }; 3269 3270 3271 static int vortex_have_pci; 3272 static int vortex_have_eisa; 3273 3274 3275 static int __init vortex_init(void) 3276 { 3277 int pci_rc, eisa_rc; 3278 3279 pci_rc = pci_register_driver(&vortex_driver); 3280 eisa_rc = vortex_eisa_init(); 3281 3282 if (pci_rc == 0) 3283 vortex_have_pci = 1; 3284 if (eisa_rc > 0) 3285 vortex_have_eisa = 1; 3286 3287 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV; 3288 } 3289 3290 3291 static void __exit vortex_eisa_cleanup(void) 3292 { 3293 struct vortex_private *vp; 3294 void __iomem *ioaddr; 3295 3296 #ifdef CONFIG_EISA 3297 /* Take care of the EISA devices */ 3298 eisa_driver_unregister(&vortex_eisa_driver); 3299 #endif 3300 3301 if (compaq_net_device) { 3302 vp = netdev_priv(compaq_net_device); 3303 ioaddr = ioport_map(compaq_net_device->base_addr, 3304 VORTEX_TOTAL_SIZE); 3305 3306 unregister_netdev(compaq_net_device); 3307 iowrite16(TotalReset, ioaddr + EL3_CMD); 3308 release_region(compaq_net_device->base_addr, 3309 VORTEX_TOTAL_SIZE); 3310 3311 free_netdev(compaq_net_device); 3312 } 3313 } 3314 3315 3316 static void __exit vortex_cleanup(void) 3317 { 3318 if (vortex_have_pci) 3319 pci_unregister_driver(&vortex_driver); 3320 if (vortex_have_eisa) 3321 vortex_eisa_cleanup(); 3322 } 3323 3324 3325 module_init(vortex_init); 3326 module_exit(vortex_cleanup); 3327