1 // SPDX-License-Identifier: GPL-2.0 2 /* DSA driver for: 3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch 4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch 5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch 6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch 7 * 8 * These switches have a built-in 8051 CPU and can download and execute a 9 * firmware in this CPU. They can also be configured to use an external CPU 10 * handling the switch in a memory-mapped manner by connecting to that external 11 * CPU's memory bus. 12 * 13 * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org> 14 * Includes portions of code from the firmware uploader by: 15 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org> 16 */ 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/iopoll.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/bitops.h> 24 #include <linux/if_bridge.h> 25 #include <linux/etherdevice.h> 26 #include <linux/gpio/consumer.h> 27 #include <linux/gpio/driver.h> 28 #include <linux/random.h> 29 #include <net/dsa.h> 30 31 #include "vitesse-vsc73xx.h" 32 33 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */ 34 #define VSC73XX_BLOCK_ANALYZER 0x2 /* Only subblock 0 */ 35 #define VSC73XX_BLOCK_MII 0x3 /* Subblocks 0 and 1 */ 36 #define VSC73XX_BLOCK_MEMINIT 0x3 /* Only subblock 2 */ 37 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Only subblock 2 */ 38 #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */ 39 #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */ 40 41 /* MII Block subblock */ 42 #define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */ 43 #define VSC73XX_BLOCK_MII_EXTERNAL 0x1 /* External MDIO subblock */ 44 45 #define CPU_PORT 6 /* CPU port */ 46 47 /* MAC Block registers */ 48 #define VSC73XX_MAC_CFG 0x00 49 #define VSC73XX_MACHDXGAP 0x02 50 #define VSC73XX_FCCONF 0x04 51 #define VSC73XX_FCMACHI 0x08 52 #define VSC73XX_FCMACLO 0x0c 53 #define VSC73XX_MAXLEN 0x10 54 #define VSC73XX_ADVPORTM 0x19 55 #define VSC73XX_TXUPDCFG 0x24 56 #define VSC73XX_TXQ_SELECT_CFG 0x28 57 #define VSC73XX_RXOCT 0x50 58 #define VSC73XX_TXOCT 0x51 59 #define VSC73XX_C_RX0 0x52 60 #define VSC73XX_C_RX1 0x53 61 #define VSC73XX_C_RX2 0x54 62 #define VSC73XX_C_TX0 0x55 63 #define VSC73XX_C_TX1 0x56 64 #define VSC73XX_C_TX2 0x57 65 #define VSC73XX_C_CFG 0x58 66 #define VSC73XX_CAT_DROP 0x6e 67 #define VSC73XX_CAT_PR_MISC_L2 0x6f 68 #define VSC73XX_CAT_PR_USR_PRIO 0x75 69 #define VSC73XX_Q_MISC_CONF 0xdf 70 71 /* MAC_CFG register bits */ 72 #define VSC73XX_MAC_CFG_WEXC_DIS BIT(31) 73 #define VSC73XX_MAC_CFG_PORT_RST BIT(29) 74 #define VSC73XX_MAC_CFG_TX_EN BIT(28) 75 #define VSC73XX_MAC_CFG_SEED_LOAD BIT(27) 76 #define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19) 77 #define VSC73XX_MAC_CFG_SEED_OFFSET 19 78 #define VSC73XX_MAC_CFG_FDX BIT(18) 79 #define VSC73XX_MAC_CFG_GIGA_MODE BIT(17) 80 #define VSC73XX_MAC_CFG_RX_EN BIT(16) 81 #define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15) 82 #define VSC73XX_MAC_CFG_VLAN_AWR BIT(14) 83 #define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */ 84 #define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6) 85 #define VSC73XX_MAC_CFG_TX_IPG_OFFSET 6 86 #define VSC73XX_MAC_CFG_TX_IPG_1000M (6 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 87 #define VSC73XX_MAC_CFG_TX_IPG_100_10M (17 << VSC73XX_MAC_CFG_TX_IPG_OFFSET) 88 #define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5) 89 #define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4) 90 #define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0) 91 #define VSC73XX_MAC_CFG_CLK_SEL_OFFSET 0 92 #define VSC73XX_MAC_CFG_CLK_SEL_1000M 1 93 #define VSC73XX_MAC_CFG_CLK_SEL_100M 2 94 #define VSC73XX_MAC_CFG_CLK_SEL_10M 3 95 #define VSC73XX_MAC_CFG_CLK_SEL_EXT 4 96 97 #define VSC73XX_MAC_CFG_1000M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 98 VSC73XX_MAC_CFG_GIGA_MODE | \ 99 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 100 VSC73XX_MAC_CFG_CLK_SEL_EXT) 101 #define VSC73XX_MAC_CFG_100_10M_F_PHY (VSC73XX_MAC_CFG_FDX | \ 102 VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 103 VSC73XX_MAC_CFG_CLK_SEL_EXT) 104 #define VSC73XX_MAC_CFG_100_10M_H_PHY (VSC73XX_MAC_CFG_TX_IPG_100_10M | \ 105 VSC73XX_MAC_CFG_CLK_SEL_EXT) 106 #define VSC73XX_MAC_CFG_1000M_F_RGMII (VSC73XX_MAC_CFG_FDX | \ 107 VSC73XX_MAC_CFG_GIGA_MODE | \ 108 VSC73XX_MAC_CFG_TX_IPG_1000M | \ 109 VSC73XX_MAC_CFG_CLK_SEL_1000M) 110 #define VSC73XX_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ 111 VSC73XX_MAC_CFG_MAC_RX_RST | \ 112 VSC73XX_MAC_CFG_MAC_TX_RST) 113 114 /* Flow control register bits */ 115 #define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17) 116 #define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16) 117 #define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0) 118 119 /* ADVPORTM advanced port setup register bits */ 120 #define VSC73XX_ADVPORTM_IFG_PPM BIT(7) 121 #define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6) 122 #define VSC73XX_ADVPORTM_EXT_PORT BIT(5) 123 #define VSC73XX_ADVPORTM_INV_GTX BIT(4) 124 #define VSC73XX_ADVPORTM_ENA_GTX BIT(3) 125 #define VSC73XX_ADVPORTM_DDR_MODE BIT(2) 126 #define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1) 127 #define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0) 128 129 /* CAT_DROP categorizer frame dropping register bits */ 130 #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6) 131 #define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4) 132 #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3) 133 #define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2) 134 #define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1) 135 #define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0) 136 137 #define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31) 138 #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1) 139 #define VSC73XX_Q_MISC_CONF_EARLY_TX_512 (1 << 1) 140 #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0) 141 142 /* Frame analyzer block 2 registers */ 143 #define VSC73XX_STORMLIMIT 0x02 144 #define VSC73XX_ADVLEARN 0x03 145 #define VSC73XX_IFLODMSK 0x04 146 #define VSC73XX_VLANMASK 0x05 147 #define VSC73XX_MACHDATA 0x06 148 #define VSC73XX_MACLDATA 0x07 149 #define VSC73XX_ANMOVED 0x08 150 #define VSC73XX_ANAGEFIL 0x09 151 #define VSC73XX_ANEVENTS 0x0a 152 #define VSC73XX_ANCNTMASK 0x0b 153 #define VSC73XX_ANCNTVAL 0x0c 154 #define VSC73XX_LEARNMASK 0x0d 155 #define VSC73XX_UFLODMASK 0x0e 156 #define VSC73XX_MFLODMASK 0x0f 157 #define VSC73XX_RECVMASK 0x10 158 #define VSC73XX_AGGRCTRL 0x20 159 #define VSC73XX_AGGRMSKS 0x30 /* Until 0x3f */ 160 #define VSC73XX_DSTMASKS 0x40 /* Until 0x7f */ 161 #define VSC73XX_SRCMASKS 0x80 /* Until 0x87 */ 162 #define VSC73XX_CAPENAB 0xa0 163 #define VSC73XX_MACACCESS 0xb0 164 #define VSC73XX_IPMCACCESS 0xb1 165 #define VSC73XX_MACTINDX 0xc0 166 #define VSC73XX_VLANACCESS 0xd0 167 #define VSC73XX_VLANTIDX 0xe0 168 #define VSC73XX_AGENCTRL 0xf0 169 #define VSC73XX_CAPRST 0xff 170 171 #define VSC73XX_MACACCESS_CPU_COPY BIT(14) 172 #define VSC73XX_MACACCESS_FWD_KILL BIT(13) 173 #define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12) 174 #define VSC73XX_MACACCESS_AGED_FLAG BIT(11) 175 #define VSC73XX_MACACCESS_VALID BIT(10) 176 #define VSC73XX_MACACCESS_LOCKED BIT(9) 177 #define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3) 178 #define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0) 179 #define VSC73XX_MACACCESS_CMD_IDLE 0 180 #define VSC73XX_MACACCESS_CMD_LEARN 1 181 #define VSC73XX_MACACCESS_CMD_FORGET 2 182 #define VSC73XX_MACACCESS_CMD_AGE_TABLE 3 183 #define VSC73XX_MACACCESS_CMD_FLUSH_TABLE 4 184 #define VSC73XX_MACACCESS_CMD_CLEAR_TABLE 5 185 #define VSC73XX_MACACCESS_CMD_READ_ENTRY 6 186 #define VSC73XX_MACACCESS_CMD_WRITE_ENTRY 7 187 188 #define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30) 189 #define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29) 190 #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28) 191 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2) 192 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(2, 0) 193 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE 0 194 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY 1 195 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY 2 196 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3 197 198 /* MII block 3 registers */ 199 #define VSC73XX_MII_STAT 0x0 200 #define VSC73XX_MII_CMD 0x1 201 #define VSC73XX_MII_DATA 0x2 202 203 #define VSC73XX_MII_STAT_BUSY BIT(3) 204 205 /* Arbiter block 5 registers */ 206 #define VSC73XX_ARBEMPTY 0x0c 207 #define VSC73XX_ARBDISC 0x0e 208 #define VSC73XX_SBACKWDROP 0x12 209 #define VSC73XX_DBACKWDROP 0x13 210 #define VSC73XX_ARBBURSTPROB 0x15 211 212 /* System block 7 registers */ 213 #define VSC73XX_ICPU_SIPAD 0x01 214 #define VSC73XX_GMIIDELAY 0x05 215 #define VSC73XX_ICPU_CTRL 0x10 216 #define VSC73XX_ICPU_ADDR 0x11 217 #define VSC73XX_ICPU_SRAM 0x12 218 #define VSC73XX_HWSEM 0x13 219 #define VSC73XX_GLORESET 0x14 220 #define VSC73XX_ICPU_MBOX_VAL 0x15 221 #define VSC73XX_ICPU_MBOX_SET 0x16 222 #define VSC73XX_ICPU_MBOX_CLR 0x17 223 #define VSC73XX_CHIPID 0x18 224 #define VSC73XX_GPIO 0x34 225 226 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE 0 227 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS 1 228 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS 2 229 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS 3 230 231 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE (0 << 4) 232 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS (1 << 4) 233 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS (2 << 4) 234 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS (3 << 4) 235 236 #define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31) 237 #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8) 238 #define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7) 239 #define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6) 240 #define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3) 241 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2) 242 #define VSC73XX_ICPU_CTRL_CLK_EN BIT(1) 243 #define VSC73XX_ICPU_CTRL_SRST BIT(0) 244 245 #define VSC73XX_CHIPID_ID_SHIFT 12 246 #define VSC73XX_CHIPID_ID_MASK 0xffff 247 #define VSC73XX_CHIPID_REV_SHIFT 28 248 #define VSC73XX_CHIPID_REV_MASK 0xf 249 #define VSC73XX_CHIPID_ID_7385 0x7385 250 #define VSC73XX_CHIPID_ID_7388 0x7388 251 #define VSC73XX_CHIPID_ID_7395 0x7395 252 #define VSC73XX_CHIPID_ID_7398 0x7398 253 254 #define VSC73XX_GLORESET_STROBE BIT(4) 255 #define VSC73XX_GLORESET_ICPU_LOCK BIT(3) 256 #define VSC73XX_GLORESET_MEM_LOCK BIT(2) 257 #define VSC73XX_GLORESET_PHY_RESET BIT(1) 258 #define VSC73XX_GLORESET_MASTER_RESET BIT(0) 259 260 #define VSC7385_CLOCK_DELAY ((3 << 4) | 3) 261 #define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) 262 263 #define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ 264 VSC73XX_ICPU_CTRL_BOOT_EN | \ 265 VSC73XX_ICPU_CTRL_EXT_ACC_EN) 266 267 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ 268 VSC73XX_ICPU_CTRL_BOOT_EN | \ 269 VSC73XX_ICPU_CTRL_CLK_EN | \ 270 VSC73XX_ICPU_CTRL_SRST) 271 272 #define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385) 273 #define IS_7388(a) ((a)->chipid == VSC73XX_CHIPID_ID_7388) 274 #define IS_7395(a) ((a)->chipid == VSC73XX_CHIPID_ID_7395) 275 #define IS_7398(a) ((a)->chipid == VSC73XX_CHIPID_ID_7398) 276 #define IS_739X(a) (IS_7395(a) || IS_7398(a)) 277 278 #define VSC73XX_POLL_SLEEP_US 1000 279 #define VSC73XX_MDIO_POLL_SLEEP_US 5 280 #define VSC73XX_POLL_TIMEOUT_US 10000 281 282 struct vsc73xx_counter { 283 u8 counter; 284 const char *name; 285 }; 286 287 /* Counters are named according to the MIB standards where applicable. 288 * Some counters are custom, non-standard. The standard counters are 289 * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex 290 * 30A Counters. 291 */ 292 static const struct vsc73xx_counter vsc73xx_rx_counters[] = { 293 { 0, "RxEtherStatsPkts" }, 294 { 1, "RxBroadcast+MulticastPkts" }, /* non-standard counter */ 295 { 2, "RxTotalErrorPackets" }, /* non-standard counter */ 296 { 3, "RxEtherStatsBroadcastPkts" }, 297 { 4, "RxEtherStatsMulticastPkts" }, 298 { 5, "RxEtherStatsPkts64Octets" }, 299 { 6, "RxEtherStatsPkts65to127Octets" }, 300 { 7, "RxEtherStatsPkts128to255Octets" }, 301 { 8, "RxEtherStatsPkts256to511Octets" }, 302 { 9, "RxEtherStatsPkts512to1023Octets" }, 303 { 10, "RxEtherStatsPkts1024to1518Octets" }, 304 { 11, "RxJumboFrames" }, /* non-standard counter */ 305 { 12, "RxaPauseMACControlFramesTransmitted" }, 306 { 13, "RxFIFODrops" }, /* non-standard counter */ 307 { 14, "RxBackwardDrops" }, /* non-standard counter */ 308 { 15, "RxClassifierDrops" }, /* non-standard counter */ 309 { 16, "RxEtherStatsCRCAlignErrors" }, 310 { 17, "RxEtherStatsUndersizePkts" }, 311 { 18, "RxEtherStatsOversizePkts" }, 312 { 19, "RxEtherStatsFragments" }, 313 { 20, "RxEtherStatsJabbers" }, 314 { 21, "RxaMACControlFramesReceived" }, 315 /* 22-24 are undefined */ 316 { 25, "RxaFramesReceivedOK" }, 317 { 26, "RxQoSClass0" }, /* non-standard counter */ 318 { 27, "RxQoSClass1" }, /* non-standard counter */ 319 { 28, "RxQoSClass2" }, /* non-standard counter */ 320 { 29, "RxQoSClass3" }, /* non-standard counter */ 321 }; 322 323 static const struct vsc73xx_counter vsc73xx_tx_counters[] = { 324 { 0, "TxEtherStatsPkts" }, 325 { 1, "TxBroadcast+MulticastPkts" }, /* non-standard counter */ 326 { 2, "TxTotalErrorPackets" }, /* non-standard counter */ 327 { 3, "TxEtherStatsBroadcastPkts" }, 328 { 4, "TxEtherStatsMulticastPkts" }, 329 { 5, "TxEtherStatsPkts64Octets" }, 330 { 6, "TxEtherStatsPkts65to127Octets" }, 331 { 7, "TxEtherStatsPkts128to255Octets" }, 332 { 8, "TxEtherStatsPkts256to511Octets" }, 333 { 9, "TxEtherStatsPkts512to1023Octets" }, 334 { 10, "TxEtherStatsPkts1024to1518Octets" }, 335 { 11, "TxJumboFrames" }, /* non-standard counter */ 336 { 12, "TxaPauseMACControlFramesTransmitted" }, 337 { 13, "TxFIFODrops" }, /* non-standard counter */ 338 { 14, "TxDrops" }, /* non-standard counter */ 339 { 15, "TxEtherStatsCollisions" }, 340 { 16, "TxEtherStatsCRCAlignErrors" }, 341 { 17, "TxEtherStatsUndersizePkts" }, 342 { 18, "TxEtherStatsOversizePkts" }, 343 { 19, "TxEtherStatsFragments" }, 344 { 20, "TxEtherStatsJabbers" }, 345 /* 21-24 are undefined */ 346 { 25, "TxaFramesReceivedOK" }, 347 { 26, "TxQoSClass0" }, /* non-standard counter */ 348 { 27, "TxQoSClass1" }, /* non-standard counter */ 349 { 28, "TxQoSClass2" }, /* non-standard counter */ 350 { 29, "TxQoSClass3" }, /* non-standard counter */ 351 }; 352 353 int vsc73xx_is_addr_valid(u8 block, u8 subblock) 354 { 355 switch (block) { 356 case VSC73XX_BLOCK_MAC: 357 switch (subblock) { 358 case 0 ... 4: 359 case 6: 360 return 1; 361 } 362 break; 363 364 case VSC73XX_BLOCK_ANALYZER: 365 case VSC73XX_BLOCK_SYSTEM: 366 switch (subblock) { 367 case 0: 368 return 1; 369 } 370 break; 371 372 case VSC73XX_BLOCK_MII: 373 case VSC73XX_BLOCK_CAPTURE: 374 case VSC73XX_BLOCK_ARBITER: 375 switch (subblock) { 376 case 0 ... 1: 377 return 1; 378 } 379 break; 380 } 381 382 return 0; 383 } 384 EXPORT_SYMBOL(vsc73xx_is_addr_valid); 385 386 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 387 u32 *val) 388 { 389 return vsc->ops->read(vsc, block, subblock, reg, val); 390 } 391 392 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, 393 u32 val) 394 { 395 return vsc->ops->write(vsc, block, subblock, reg, val); 396 } 397 398 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock, 399 u8 reg, u32 mask, u32 val) 400 { 401 u32 tmp, orig; 402 int ret; 403 404 /* Same read-modify-write algorithm as e.g. regmap */ 405 ret = vsc73xx_read(vsc, block, subblock, reg, &orig); 406 if (ret) 407 return ret; 408 tmp = orig & ~mask; 409 tmp |= val & mask; 410 return vsc73xx_write(vsc, block, subblock, reg, tmp); 411 } 412 413 static int vsc73xx_detect(struct vsc73xx *vsc) 414 { 415 bool icpu_si_boot_en; 416 bool icpu_pi_en; 417 u32 val; 418 u32 rev; 419 int ret; 420 u32 id; 421 422 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 423 VSC73XX_ICPU_MBOX_VAL, &val); 424 if (ret) { 425 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret); 426 return ret; 427 } 428 429 if (val == 0xffffffff) { 430 dev_info(vsc->dev, "chip seems dead.\n"); 431 return -EAGAIN; 432 } 433 434 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 435 VSC73XX_CHIPID, &val); 436 if (ret) { 437 dev_err(vsc->dev, "unable to read chip id (%d)\n", ret); 438 return ret; 439 } 440 441 id = (val >> VSC73XX_CHIPID_ID_SHIFT) & 442 VSC73XX_CHIPID_ID_MASK; 443 switch (id) { 444 case VSC73XX_CHIPID_ID_7385: 445 case VSC73XX_CHIPID_ID_7388: 446 case VSC73XX_CHIPID_ID_7395: 447 case VSC73XX_CHIPID_ID_7398: 448 break; 449 default: 450 dev_err(vsc->dev, "unsupported chip, id=%04x\n", id); 451 return -ENODEV; 452 } 453 454 vsc->chipid = id; 455 rev = (val >> VSC73XX_CHIPID_REV_SHIFT) & 456 VSC73XX_CHIPID_REV_MASK; 457 dev_info(vsc->dev, "VSC%04X (rev: %d) switch found\n", id, rev); 458 459 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 460 VSC73XX_ICPU_CTRL, &val); 461 if (ret) { 462 dev_err(vsc->dev, "unable to read iCPU control\n"); 463 return ret; 464 } 465 466 /* The iCPU can always be used but can boot in different ways. 467 * If it is initially disabled and has no external memory, 468 * we are in control and can do whatever we like, else we 469 * are probably in trouble (we need some way to communicate 470 * with the running firmware) so we bail out for now. 471 */ 472 icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN); 473 icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN); 474 if (icpu_si_boot_en && icpu_pi_en) { 475 dev_err(vsc->dev, 476 "iCPU enabled boots from SI, has external memory\n"); 477 dev_err(vsc->dev, "no idea how to deal with this\n"); 478 return -ENODEV; 479 } 480 if (icpu_si_boot_en && !icpu_pi_en) { 481 dev_err(vsc->dev, 482 "iCPU enabled boots from PI/SI, no external memory\n"); 483 return -EAGAIN; 484 } 485 if (!icpu_si_boot_en && icpu_pi_en) { 486 dev_err(vsc->dev, 487 "iCPU enabled, boots from PI external memory\n"); 488 dev_err(vsc->dev, "no idea how to deal with this\n"); 489 return -ENODEV; 490 } 491 /* !icpu_si_boot_en && !cpu_pi_en */ 492 dev_info(vsc->dev, "iCPU disabled, no external memory\n"); 493 494 return 0; 495 } 496 497 static int vsc73xx_mdio_busy_check(struct vsc73xx *vsc) 498 { 499 int ret, err; 500 u32 val; 501 502 ret = read_poll_timeout(vsc73xx_read, err, 503 err < 0 || !(val & VSC73XX_MII_STAT_BUSY), 504 VSC73XX_MDIO_POLL_SLEEP_US, 505 VSC73XX_POLL_TIMEOUT_US, false, vsc, 506 VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL, 507 VSC73XX_MII_STAT, &val); 508 if (ret) 509 return ret; 510 return err; 511 } 512 513 static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum) 514 { 515 struct vsc73xx *vsc = ds->priv; 516 u32 cmd; 517 u32 val; 518 int ret; 519 520 ret = vsc73xx_mdio_busy_check(vsc); 521 if (ret) 522 return ret; 523 524 /* Setting bit 26 means "read" */ 525 cmd = BIT(26) | (phy << 21) | (regnum << 16); 526 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 527 if (ret) 528 return ret; 529 530 ret = vsc73xx_mdio_busy_check(vsc); 531 if (ret) 532 return ret; 533 534 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val); 535 if (ret) 536 return ret; 537 if (val & BIT(16)) { 538 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n", 539 regnum, phy); 540 return -EIO; 541 } 542 val &= 0xFFFFU; 543 544 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n", 545 regnum, phy, val); 546 547 return val; 548 } 549 550 static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum, 551 u16 val) 552 { 553 struct vsc73xx *vsc = ds->priv; 554 u32 cmd; 555 int ret; 556 557 ret = vsc73xx_mdio_busy_check(vsc); 558 if (ret) 559 return ret; 560 561 /* It was found through tedious experiments that this router 562 * chip really hates to have it's PHYs reset. They 563 * never recover if that happens: autonegotiation stops 564 * working after a reset. Just filter out this command. 565 * (Resetting the whole chip is OK.) 566 */ 567 if (regnum == 0 && (val & BIT(15))) { 568 dev_info(vsc->dev, "reset PHY - disallowed\n"); 569 return 0; 570 } 571 572 cmd = (phy << 21) | (regnum << 16) | val; 573 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd); 574 if (ret) 575 return ret; 576 577 dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n", 578 val, regnum, phy); 579 return 0; 580 } 581 582 static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds, 583 int port, 584 enum dsa_tag_protocol mp) 585 { 586 /* The switch internally uses a 8 byte header with length, 587 * source port, tag, LPA and priority. This is supposedly 588 * only accessible when operating the switch using the internal 589 * CPU or with an external CPU mapping the device in, but not 590 * when operating the switch over SPI and putting frames in/out 591 * on port 6 (the CPU port). So far we must assume that we 592 * cannot access the tag. (See "Internal frame header" section 593 * 3.9.1 in the manual.) 594 */ 595 return DSA_TAG_PROTO_NONE; 596 } 597 598 static int vsc73xx_setup(struct dsa_switch *ds) 599 { 600 struct vsc73xx *vsc = ds->priv; 601 int i; 602 603 dev_info(vsc->dev, "set up the switch\n"); 604 605 /* Issue RESET */ 606 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 607 VSC73XX_GLORESET_MASTER_RESET); 608 usleep_range(125, 200); 609 610 /* Initialize memory, initialize RAM bank 0..15 except 6 and 7 611 * This sequence appears in the 612 * VSC7385 SparX-G5 datasheet section 6.6.1 613 * VSC7395 SparX-G5e datasheet section 6.6.1 614 * "initialization sequence". 615 * No explanation is given to the 0x1010400 magic number. 616 */ 617 for (i = 0; i <= 15; i++) { 618 if (i != 6 && i != 7) { 619 vsc73xx_write(vsc, VSC73XX_BLOCK_MEMINIT, 620 2, 621 0, 0x1010400 + i); 622 mdelay(1); 623 } 624 } 625 mdelay(30); 626 627 /* Clear MAC table */ 628 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 629 VSC73XX_MACACCESS, 630 VSC73XX_MACACCESS_CMD_CLEAR_TABLE); 631 632 /* Clear VLAN table */ 633 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, 634 VSC73XX_VLANACCESS, 635 VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE); 636 637 msleep(40); 638 639 /* Use 20KiB buffers on all ports on VSC7395 640 * The VSC7385 has 16KiB buffers and that is the 641 * default if we don't set this up explicitly. 642 * Port "31" is "all ports". 643 */ 644 if (IS_739X(vsc)) 645 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 0x1f, 646 VSC73XX_Q_MISC_CONF, 647 VSC73XX_Q_MISC_CONF_EXTENT_MEM); 648 649 /* Put all ports into reset until enabled */ 650 for (i = 0; i < 7; i++) { 651 if (i == 5) 652 continue; 653 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 4, 654 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 655 } 656 657 /* MII delay, set both GTX and RX delay to 2 ns */ 658 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GMIIDELAY, 659 VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS | 660 VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS); 661 /* Enable reception of frames on all ports */ 662 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_RECVMASK, 663 0x5f); 664 /* IP multicast flood mask (table 144) */ 665 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_IFLODMSK, 666 0xff); 667 668 mdelay(50); 669 670 /* Release reset from the internal PHYs */ 671 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET, 672 VSC73XX_GLORESET_PHY_RESET); 673 674 udelay(4); 675 676 return 0; 677 } 678 679 static void vsc73xx_init_port(struct vsc73xx *vsc, int port) 680 { 681 u32 val; 682 683 /* MAC configure, first reset the port and then write defaults */ 684 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 685 port, 686 VSC73XX_MAC_CFG, 687 VSC73XX_MAC_CFG_RESET); 688 689 /* Take up the port in 1Gbit mode by default, this will be 690 * augmented after auto-negotiation on the PHY-facing 691 * ports. 692 */ 693 if (port == CPU_PORT) 694 val = VSC73XX_MAC_CFG_1000M_F_RGMII; 695 else 696 val = VSC73XX_MAC_CFG_1000M_F_PHY; 697 698 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 699 port, 700 VSC73XX_MAC_CFG, 701 val | 702 VSC73XX_MAC_CFG_TX_EN | 703 VSC73XX_MAC_CFG_RX_EN); 704 705 /* Flow control for the CPU port: 706 * Use a zero delay pause frame when pause condition is left 707 * Obey pause control frames 708 */ 709 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 710 port, 711 VSC73XX_FCCONF, 712 VSC73XX_FCCONF_ZERO_PAUSE_EN | 713 VSC73XX_FCCONF_FLOW_CTRL_OBEY); 714 715 /* Issue pause control frames on PHY facing ports. 716 * Allow early initiation of MAC transmission if the amount 717 * of egress data is below 512 bytes on CPU port. 718 * FIXME: enable 20KiB buffers? 719 */ 720 if (port == CPU_PORT) 721 val = VSC73XX_Q_MISC_CONF_EARLY_TX_512; 722 else 723 val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE; 724 val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM; 725 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 726 port, 727 VSC73XX_Q_MISC_CONF, 728 val); 729 730 /* Flow control MAC: a MAC address used in flow control frames */ 731 val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]); 732 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 733 port, 734 VSC73XX_FCMACHI, 735 val); 736 val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]); 737 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 738 port, 739 VSC73XX_FCMACLO, 740 val); 741 742 /* Tell the categorizer to forward pause frames, not control 743 * frame. Do not drop anything. 744 */ 745 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 746 port, 747 VSC73XX_CAT_DROP, 748 VSC73XX_CAT_DROP_FWD_PAUSE_ENA); 749 750 /* Clear all counters */ 751 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 752 port, VSC73XX_C_RX0, 0); 753 } 754 755 static void vsc73xx_adjust_enable_port(struct vsc73xx *vsc, 756 int port, struct phy_device *phydev, 757 u32 initval) 758 { 759 u32 val = initval; 760 u8 seed; 761 762 /* Reset this port FIXME: break out subroutine */ 763 val |= VSC73XX_MAC_CFG_RESET; 764 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); 765 766 /* Seed the port randomness with randomness */ 767 get_random_bytes(&seed, 1); 768 val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET; 769 val |= VSC73XX_MAC_CFG_SEED_LOAD; 770 val |= VSC73XX_MAC_CFG_WEXC_DIS; 771 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val); 772 773 /* Flow control for the PHY facing ports: 774 * Use a zero delay pause frame when pause condition is left 775 * Obey pause control frames 776 * When generating pause frames, use 0xff as pause value 777 */ 778 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF, 779 VSC73XX_FCCONF_ZERO_PAUSE_EN | 780 VSC73XX_FCCONF_FLOW_CTRL_OBEY | 781 0xff); 782 783 /* Disallow backward dropping of frames from this port */ 784 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 785 VSC73XX_SBACKWDROP, BIT(port), 0); 786 787 /* Enable TX, RX, deassert reset, stop loading seed */ 788 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 789 VSC73XX_MAC_CFG, 790 VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD | 791 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN, 792 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN); 793 } 794 795 static void vsc73xx_adjust_link(struct dsa_switch *ds, int port, 796 struct phy_device *phydev) 797 { 798 struct vsc73xx *vsc = ds->priv; 799 u32 val; 800 801 /* Special handling of the CPU-facing port */ 802 if (port == CPU_PORT) { 803 /* Other ports are already initialized but not this one */ 804 vsc73xx_init_port(vsc, CPU_PORT); 805 /* Select the external port for this interface (EXT_PORT) 806 * Enable the GMII GTX external clock 807 * Use double data rate (DDR mode) 808 */ 809 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 810 CPU_PORT, 811 VSC73XX_ADVPORTM, 812 VSC73XX_ADVPORTM_EXT_PORT | 813 VSC73XX_ADVPORTM_ENA_GTX | 814 VSC73XX_ADVPORTM_DDR_MODE); 815 } 816 817 /* This is the MAC confiuration that always need to happen 818 * after a PHY or the CPU port comes up or down. 819 */ 820 if (!phydev->link) { 821 int ret, err; 822 823 dev_dbg(vsc->dev, "port %d: went down\n", 824 port); 825 826 /* Disable RX on this port */ 827 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port, 828 VSC73XX_MAC_CFG, 829 VSC73XX_MAC_CFG_RX_EN, 0); 830 831 /* Discard packets */ 832 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 833 VSC73XX_ARBDISC, BIT(port), BIT(port)); 834 835 /* Wait until queue is empty */ 836 ret = read_poll_timeout(vsc73xx_read, err, 837 err < 0 || (val & BIT(port)), 838 VSC73XX_POLL_SLEEP_US, 839 VSC73XX_POLL_TIMEOUT_US, false, 840 vsc, VSC73XX_BLOCK_ARBITER, 0, 841 VSC73XX_ARBEMPTY, &val); 842 if (ret) 843 dev_err(vsc->dev, 844 "timeout waiting for block arbiter\n"); 845 else if (err < 0) 846 dev_err(vsc->dev, "error reading arbiter\n"); 847 848 /* Put this port into reset */ 849 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, 850 VSC73XX_MAC_CFG_RESET); 851 852 /* Accept packets again */ 853 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 854 VSC73XX_ARBDISC, BIT(port), 0); 855 856 /* Allow backward dropping of frames from this port */ 857 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0, 858 VSC73XX_SBACKWDROP, BIT(port), BIT(port)); 859 860 /* Receive mask (disable forwarding) */ 861 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 862 VSC73XX_RECVMASK, BIT(port), 0); 863 864 return; 865 } 866 867 /* Figure out what speed was negotiated */ 868 if (phydev->speed == SPEED_1000) { 869 dev_dbg(vsc->dev, "port %d: 1000 Mbit mode full duplex\n", 870 port); 871 872 /* Set up default for internal port or external RGMII */ 873 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) 874 val = VSC73XX_MAC_CFG_1000M_F_RGMII; 875 else 876 val = VSC73XX_MAC_CFG_1000M_F_PHY; 877 vsc73xx_adjust_enable_port(vsc, port, phydev, val); 878 } else if (phydev->speed == SPEED_100) { 879 if (phydev->duplex == DUPLEX_FULL) { 880 val = VSC73XX_MAC_CFG_100_10M_F_PHY; 881 dev_dbg(vsc->dev, 882 "port %d: 100 Mbit full duplex mode\n", 883 port); 884 } else { 885 val = VSC73XX_MAC_CFG_100_10M_H_PHY; 886 dev_dbg(vsc->dev, 887 "port %d: 100 Mbit half duplex mode\n", 888 port); 889 } 890 vsc73xx_adjust_enable_port(vsc, port, phydev, val); 891 } else if (phydev->speed == SPEED_10) { 892 if (phydev->duplex == DUPLEX_FULL) { 893 val = VSC73XX_MAC_CFG_100_10M_F_PHY; 894 dev_dbg(vsc->dev, 895 "port %d: 10 Mbit full duplex mode\n", 896 port); 897 } else { 898 val = VSC73XX_MAC_CFG_100_10M_H_PHY; 899 dev_dbg(vsc->dev, 900 "port %d: 10 Mbit half duplex mode\n", 901 port); 902 } 903 vsc73xx_adjust_enable_port(vsc, port, phydev, val); 904 } else { 905 dev_err(vsc->dev, 906 "could not adjust link: unknown speed\n"); 907 } 908 909 /* Enable port (forwarding) in the receieve mask */ 910 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0, 911 VSC73XX_RECVMASK, BIT(port), BIT(port)); 912 } 913 914 static int vsc73xx_port_enable(struct dsa_switch *ds, int port, 915 struct phy_device *phy) 916 { 917 struct vsc73xx *vsc = ds->priv; 918 919 dev_info(vsc->dev, "enable port %d\n", port); 920 vsc73xx_init_port(vsc, port); 921 922 return 0; 923 } 924 925 static void vsc73xx_port_disable(struct dsa_switch *ds, int port) 926 { 927 struct vsc73xx *vsc = ds->priv; 928 929 /* Just put the port into reset */ 930 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 931 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET); 932 } 933 934 static const struct vsc73xx_counter * 935 vsc73xx_find_counter(struct vsc73xx *vsc, 936 u8 counter, 937 bool tx) 938 { 939 const struct vsc73xx_counter *cnts; 940 int num_cnts; 941 int i; 942 943 if (tx) { 944 cnts = vsc73xx_tx_counters; 945 num_cnts = ARRAY_SIZE(vsc73xx_tx_counters); 946 } else { 947 cnts = vsc73xx_rx_counters; 948 num_cnts = ARRAY_SIZE(vsc73xx_rx_counters); 949 } 950 951 for (i = 0; i < num_cnts; i++) { 952 const struct vsc73xx_counter *cnt; 953 954 cnt = &cnts[i]; 955 if (cnt->counter == counter) 956 return cnt; 957 } 958 959 return NULL; 960 } 961 962 static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset, 963 uint8_t *data) 964 { 965 const struct vsc73xx_counter *cnt; 966 struct vsc73xx *vsc = ds->priv; 967 u8 indices[6]; 968 int i, j; 969 u32 val; 970 int ret; 971 972 if (stringset != ETH_SS_STATS) 973 return; 974 975 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 976 VSC73XX_C_CFG, &val); 977 if (ret) 978 return; 979 980 indices[0] = (val & 0x1f); /* RX counter 0 */ 981 indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */ 982 indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */ 983 indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */ 984 indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */ 985 indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */ 986 987 /* The first counters is the RX octets */ 988 j = 0; 989 strncpy(data + j * ETH_GSTRING_LEN, 990 "RxEtherStatsOctets", ETH_GSTRING_LEN); 991 j++; 992 993 /* Each port supports recording 3 RX counters and 3 TX counters, 994 * figure out what counters we use in this set-up and return the 995 * names of them. The hardware default counters will be number of 996 * packets on RX/TX, combined broadcast+multicast packets RX/TX and 997 * total error packets RX/TX. 998 */ 999 for (i = 0; i < 3; i++) { 1000 cnt = vsc73xx_find_counter(vsc, indices[i], false); 1001 if (cnt) 1002 strncpy(data + j * ETH_GSTRING_LEN, 1003 cnt->name, ETH_GSTRING_LEN); 1004 j++; 1005 } 1006 1007 /* TX stats begins with the number of TX octets */ 1008 strncpy(data + j * ETH_GSTRING_LEN, 1009 "TxEtherStatsOctets", ETH_GSTRING_LEN); 1010 j++; 1011 1012 for (i = 3; i < 6; i++) { 1013 cnt = vsc73xx_find_counter(vsc, indices[i], true); 1014 if (cnt) 1015 strncpy(data + j * ETH_GSTRING_LEN, 1016 cnt->name, ETH_GSTRING_LEN); 1017 j++; 1018 } 1019 } 1020 1021 static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1022 { 1023 /* We only support SS_STATS */ 1024 if (sset != ETH_SS_STATS) 1025 return 0; 1026 /* RX and TX packets, then 3 RX counters, 3 TX counters */ 1027 return 8; 1028 } 1029 1030 static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port, 1031 uint64_t *data) 1032 { 1033 struct vsc73xx *vsc = ds->priv; 1034 u8 regs[] = { 1035 VSC73XX_RXOCT, 1036 VSC73XX_C_RX0, 1037 VSC73XX_C_RX1, 1038 VSC73XX_C_RX2, 1039 VSC73XX_TXOCT, 1040 VSC73XX_C_TX0, 1041 VSC73XX_C_TX1, 1042 VSC73XX_C_TX2, 1043 }; 1044 u32 val; 1045 int ret; 1046 int i; 1047 1048 for (i = 0; i < ARRAY_SIZE(regs); i++) { 1049 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port, 1050 regs[i], &val); 1051 if (ret) { 1052 dev_err(vsc->dev, "error reading counter %d\n", i); 1053 return; 1054 } 1055 data[i] = val; 1056 } 1057 } 1058 1059 static int vsc73xx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1060 { 1061 struct vsc73xx *vsc = ds->priv; 1062 1063 return vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, 1064 VSC73XX_MAXLEN, new_mtu + ETH_HLEN + ETH_FCS_LEN); 1065 } 1066 1067 /* According to application not "VSC7398 Jumbo Frames" setting 1068 * up the frame size to 9.6 KB does not affect the performance on standard 1069 * frames. It is clear from the application note that 1070 * "9.6 kilobytes" == 9600 bytes. 1071 */ 1072 static int vsc73xx_get_max_mtu(struct dsa_switch *ds, int port) 1073 { 1074 return 9600 - ETH_HLEN - ETH_FCS_LEN; 1075 } 1076 1077 static const struct dsa_switch_ops vsc73xx_ds_ops = { 1078 .get_tag_protocol = vsc73xx_get_tag_protocol, 1079 .setup = vsc73xx_setup, 1080 .phy_read = vsc73xx_phy_read, 1081 .phy_write = vsc73xx_phy_write, 1082 .adjust_link = vsc73xx_adjust_link, 1083 .get_strings = vsc73xx_get_strings, 1084 .get_ethtool_stats = vsc73xx_get_ethtool_stats, 1085 .get_sset_count = vsc73xx_get_sset_count, 1086 .port_enable = vsc73xx_port_enable, 1087 .port_disable = vsc73xx_port_disable, 1088 .port_change_mtu = vsc73xx_change_mtu, 1089 .port_max_mtu = vsc73xx_get_max_mtu, 1090 }; 1091 1092 static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 1093 { 1094 struct vsc73xx *vsc = gpiochip_get_data(chip); 1095 u32 val; 1096 int ret; 1097 1098 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1099 VSC73XX_GPIO, &val); 1100 if (ret) 1101 return ret; 1102 1103 return !!(val & BIT(offset)); 1104 } 1105 1106 static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 1107 int val) 1108 { 1109 struct vsc73xx *vsc = gpiochip_get_data(chip); 1110 u32 tmp = val ? BIT(offset) : 0; 1111 1112 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1113 VSC73XX_GPIO, BIT(offset), tmp); 1114 } 1115 1116 static int vsc73xx_gpio_direction_output(struct gpio_chip *chip, 1117 unsigned int offset, int val) 1118 { 1119 struct vsc73xx *vsc = gpiochip_get_data(chip); 1120 u32 tmp = val ? BIT(offset) : 0; 1121 1122 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1123 VSC73XX_GPIO, BIT(offset + 4) | BIT(offset), 1124 BIT(offset + 4) | tmp); 1125 } 1126 1127 static int vsc73xx_gpio_direction_input(struct gpio_chip *chip, 1128 unsigned int offset) 1129 { 1130 struct vsc73xx *vsc = gpiochip_get_data(chip); 1131 1132 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1133 VSC73XX_GPIO, BIT(offset + 4), 1134 0); 1135 } 1136 1137 static int vsc73xx_gpio_get_direction(struct gpio_chip *chip, 1138 unsigned int offset) 1139 { 1140 struct vsc73xx *vsc = gpiochip_get_data(chip); 1141 u32 val; 1142 int ret; 1143 1144 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, 1145 VSC73XX_GPIO, &val); 1146 if (ret) 1147 return ret; 1148 1149 return !(val & BIT(offset + 4)); 1150 } 1151 1152 static int vsc73xx_gpio_probe(struct vsc73xx *vsc) 1153 { 1154 int ret; 1155 1156 vsc->gc.label = devm_kasprintf(vsc->dev, GFP_KERNEL, "VSC%04x", 1157 vsc->chipid); 1158 if (!vsc->gc.label) 1159 return -ENOMEM; 1160 vsc->gc.ngpio = 4; 1161 vsc->gc.owner = THIS_MODULE; 1162 vsc->gc.parent = vsc->dev; 1163 vsc->gc.base = -1; 1164 vsc->gc.get = vsc73xx_gpio_get; 1165 vsc->gc.set = vsc73xx_gpio_set; 1166 vsc->gc.direction_input = vsc73xx_gpio_direction_input; 1167 vsc->gc.direction_output = vsc73xx_gpio_direction_output; 1168 vsc->gc.get_direction = vsc73xx_gpio_get_direction; 1169 vsc->gc.can_sleep = true; 1170 ret = devm_gpiochip_add_data(vsc->dev, &vsc->gc, vsc); 1171 if (ret) { 1172 dev_err(vsc->dev, "unable to register GPIO chip\n"); 1173 return ret; 1174 } 1175 return 0; 1176 } 1177 1178 int vsc73xx_probe(struct vsc73xx *vsc) 1179 { 1180 struct device *dev = vsc->dev; 1181 int ret; 1182 1183 /* Release reset, if any */ 1184 vsc->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1185 if (IS_ERR(vsc->reset)) { 1186 dev_err(dev, "failed to get RESET GPIO\n"); 1187 return PTR_ERR(vsc->reset); 1188 } 1189 if (vsc->reset) 1190 /* Wait 20ms according to datasheet table 245 */ 1191 msleep(20); 1192 1193 ret = vsc73xx_detect(vsc); 1194 if (ret == -EAGAIN) { 1195 dev_err(vsc->dev, 1196 "Chip seems to be out of control. Assert reset and try again.\n"); 1197 gpiod_set_value_cansleep(vsc->reset, 1); 1198 /* Reset pulse should be 20ns minimum, according to datasheet 1199 * table 245, so 10us should be fine 1200 */ 1201 usleep_range(10, 100); 1202 gpiod_set_value_cansleep(vsc->reset, 0); 1203 /* Wait 20ms according to datasheet table 245 */ 1204 msleep(20); 1205 ret = vsc73xx_detect(vsc); 1206 } 1207 if (ret) { 1208 dev_err(dev, "no chip found (%d)\n", ret); 1209 return -ENODEV; 1210 } 1211 1212 eth_random_addr(vsc->addr); 1213 dev_info(vsc->dev, 1214 "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n", 1215 vsc->addr[0], vsc->addr[1], vsc->addr[2], 1216 vsc->addr[3], vsc->addr[4], vsc->addr[5]); 1217 1218 /* The VSC7395 switch chips have 5+1 ports which means 5 1219 * ordinary ports and a sixth CPU port facing the processor 1220 * with an RGMII interface. These ports are numbered 0..4 1221 * and 6, so they leave a "hole" in the port map for port 5, 1222 * which is invalid. 1223 * 1224 * The VSC7398 has 8 ports, port 7 is again the CPU port. 1225 * 1226 * We allocate 8 ports and avoid access to the nonexistant 1227 * ports. 1228 */ 1229 vsc->ds = devm_kzalloc(dev, sizeof(*vsc->ds), GFP_KERNEL); 1230 if (!vsc->ds) 1231 return -ENOMEM; 1232 1233 vsc->ds->dev = dev; 1234 vsc->ds->num_ports = 8; 1235 vsc->ds->priv = vsc; 1236 1237 vsc->ds->ops = &vsc73xx_ds_ops; 1238 ret = dsa_register_switch(vsc->ds); 1239 if (ret) { 1240 dev_err(dev, "unable to register switch (%d)\n", ret); 1241 return ret; 1242 } 1243 1244 ret = vsc73xx_gpio_probe(vsc); 1245 if (ret) { 1246 dsa_unregister_switch(vsc->ds); 1247 return ret; 1248 } 1249 1250 return 0; 1251 } 1252 EXPORT_SYMBOL(vsc73xx_probe); 1253 1254 void vsc73xx_remove(struct vsc73xx *vsc) 1255 { 1256 dsa_unregister_switch(vsc->ds); 1257 gpiod_set_value(vsc->reset, 1); 1258 } 1259 EXPORT_SYMBOL(vsc73xx_remove); 1260 1261 void vsc73xx_shutdown(struct vsc73xx *vsc) 1262 { 1263 dsa_switch_shutdown(vsc->ds); 1264 } 1265 EXPORT_SYMBOL(vsc73xx_shutdown); 1266 1267 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>"); 1268 MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver"); 1269 MODULE_LICENSE("GPL v2"); 1270