1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright (c) 2016-2018, NXP Semiconductors 3 * Copyright (c) 2018, Sensor-Technik Wiedemann GmbH 4 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 5 */ 6 #include <linux/spi/spi.h> 7 #include <linux/packing.h> 8 #include "sja1105.h" 9 10 struct sja1105_chunk { 11 u8 *buf; 12 size_t len; 13 u64 reg_addr; 14 }; 15 16 static void 17 sja1105_spi_message_pack(void *buf, const struct sja1105_spi_message *msg) 18 { 19 const int size = SJA1105_SIZE_SPI_MSG_HEADER; 20 21 memset(buf, 0, size); 22 23 sja1105_pack(buf, &msg->access, 31, 31, size); 24 sja1105_pack(buf, &msg->read_count, 30, 25, size); 25 sja1105_pack(buf, &msg->address, 24, 4, size); 26 } 27 28 /* If @rw is: 29 * - SPI_WRITE: creates and sends an SPI write message at absolute 30 * address reg_addr, taking @len bytes from *buf 31 * - SPI_READ: creates and sends an SPI read message from absolute 32 * address reg_addr, writing @len bytes into *buf 33 */ 34 static int sja1105_xfer(const struct sja1105_private *priv, 35 sja1105_spi_rw_mode_t rw, u64 reg_addr, u8 *buf, 36 size_t len, struct ptp_system_timestamp *ptp_sts) 37 { 38 u8 hdr_buf[SJA1105_SIZE_SPI_MSG_HEADER] = {0}; 39 struct spi_device *spi = priv->spidev; 40 struct spi_transfer xfers[2] = {0}; 41 struct spi_transfer *chunk_xfer; 42 struct spi_transfer *hdr_xfer; 43 struct sja1105_chunk chunk; 44 int num_chunks; 45 int rc, i = 0; 46 47 num_chunks = DIV_ROUND_UP(len, priv->max_xfer_len); 48 49 chunk.reg_addr = reg_addr; 50 chunk.buf = buf; 51 chunk.len = min_t(size_t, len, priv->max_xfer_len); 52 53 hdr_xfer = &xfers[0]; 54 chunk_xfer = &xfers[1]; 55 56 for (i = 0; i < num_chunks; i++) { 57 struct spi_transfer *ptp_sts_xfer; 58 struct sja1105_spi_message msg; 59 60 /* Populate the transfer's header buffer */ 61 msg.address = chunk.reg_addr; 62 msg.access = rw; 63 if (rw == SPI_READ) 64 msg.read_count = chunk.len / 4; 65 else 66 /* Ignored */ 67 msg.read_count = 0; 68 sja1105_spi_message_pack(hdr_buf, &msg); 69 hdr_xfer->tx_buf = hdr_buf; 70 hdr_xfer->len = SJA1105_SIZE_SPI_MSG_HEADER; 71 72 /* Populate the transfer's data buffer */ 73 if (rw == SPI_READ) 74 chunk_xfer->rx_buf = chunk.buf; 75 else 76 chunk_xfer->tx_buf = chunk.buf; 77 chunk_xfer->len = chunk.len; 78 79 /* Request timestamping for the transfer. Instead of letting 80 * callers specify which byte they want to timestamp, we can 81 * make certain assumptions: 82 * - A read operation will request a software timestamp when 83 * what's being read is the PTP time. That is snapshotted by 84 * the switch hardware at the end of the command portion 85 * (hdr_xfer). 86 * - A write operation will request a software timestamp on 87 * actions that modify the PTP time. Taking clock stepping as 88 * an example, the switch writes the PTP time at the end of 89 * the data portion (chunk_xfer). 90 */ 91 if (rw == SPI_READ) 92 ptp_sts_xfer = hdr_xfer; 93 else 94 ptp_sts_xfer = chunk_xfer; 95 ptp_sts_xfer->ptp_sts_word_pre = ptp_sts_xfer->len - 1; 96 ptp_sts_xfer->ptp_sts_word_post = ptp_sts_xfer->len - 1; 97 ptp_sts_xfer->ptp_sts = ptp_sts; 98 99 /* Calculate next chunk */ 100 chunk.buf += chunk.len; 101 chunk.reg_addr += chunk.len / 4; 102 chunk.len = min_t(size_t, (ptrdiff_t)(buf + len - chunk.buf), 103 priv->max_xfer_len); 104 105 rc = spi_sync_transfer(spi, xfers, 2); 106 if (rc < 0) { 107 dev_err(&spi->dev, "SPI transfer failed: %d\n", rc); 108 return rc; 109 } 110 } 111 112 return 0; 113 } 114 115 int sja1105_xfer_buf(const struct sja1105_private *priv, 116 sja1105_spi_rw_mode_t rw, u64 reg_addr, 117 u8 *buf, size_t len) 118 { 119 return sja1105_xfer(priv, rw, reg_addr, buf, len, NULL); 120 } 121 122 /* If @rw is: 123 * - SPI_WRITE: creates and sends an SPI write message at absolute 124 * address reg_addr 125 * - SPI_READ: creates and sends an SPI read message from absolute 126 * address reg_addr 127 * 128 * The u64 *value is unpacked, meaning that it's stored in the native 129 * CPU endianness and directly usable by software running on the core. 130 */ 131 int sja1105_xfer_u64(const struct sja1105_private *priv, 132 sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value, 133 struct ptp_system_timestamp *ptp_sts) 134 { 135 u8 packed_buf[8]; 136 int rc; 137 138 if (rw == SPI_WRITE) 139 sja1105_pack(packed_buf, value, 63, 0, 8); 140 141 rc = sja1105_xfer(priv, rw, reg_addr, packed_buf, 8, ptp_sts); 142 143 if (rw == SPI_READ) 144 sja1105_unpack(packed_buf, value, 63, 0, 8); 145 146 return rc; 147 } 148 149 /* Same as above, but transfers only a 4 byte word */ 150 int sja1105_xfer_u32(const struct sja1105_private *priv, 151 sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value, 152 struct ptp_system_timestamp *ptp_sts) 153 { 154 u8 packed_buf[4]; 155 u64 tmp; 156 int rc; 157 158 if (rw == SPI_WRITE) { 159 /* The packing API only supports u64 as CPU word size, 160 * so we need to convert. 161 */ 162 tmp = *value; 163 sja1105_pack(packed_buf, &tmp, 31, 0, 4); 164 } 165 166 rc = sja1105_xfer(priv, rw, reg_addr, packed_buf, 4, ptp_sts); 167 168 if (rw == SPI_READ) { 169 sja1105_unpack(packed_buf, &tmp, 31, 0, 4); 170 *value = tmp; 171 } 172 173 return rc; 174 } 175 176 static int sja1105et_reset_cmd(struct dsa_switch *ds) 177 { 178 struct sja1105_private *priv = ds->priv; 179 const struct sja1105_regs *regs = priv->info->regs; 180 u32 cold_reset = BIT(3); 181 182 /* Cold reset */ 183 return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &cold_reset, NULL); 184 } 185 186 static int sja1105pqrs_reset_cmd(struct dsa_switch *ds) 187 { 188 struct sja1105_private *priv = ds->priv; 189 const struct sja1105_regs *regs = priv->info->regs; 190 u32 cold_reset = BIT(2); 191 192 /* Cold reset */ 193 return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &cold_reset, NULL); 194 } 195 196 static int sja1110_reset_cmd(struct dsa_switch *ds) 197 { 198 struct sja1105_private *priv = ds->priv; 199 const struct sja1105_regs *regs = priv->info->regs; 200 u32 switch_reset = BIT(20); 201 202 /* Switch core reset */ 203 return sja1105_xfer_u32(priv, SPI_WRITE, regs->rgu, &switch_reset, NULL); 204 } 205 206 int sja1105_inhibit_tx(const struct sja1105_private *priv, 207 unsigned long port_bitmap, bool tx_inhibited) 208 { 209 const struct sja1105_regs *regs = priv->info->regs; 210 u32 inhibit_cmd; 211 int rc; 212 213 rc = sja1105_xfer_u32(priv, SPI_READ, regs->port_control, 214 &inhibit_cmd, NULL); 215 if (rc < 0) 216 return rc; 217 218 if (tx_inhibited) 219 inhibit_cmd |= port_bitmap; 220 else 221 inhibit_cmd &= ~port_bitmap; 222 223 return sja1105_xfer_u32(priv, SPI_WRITE, regs->port_control, 224 &inhibit_cmd, NULL); 225 } 226 227 struct sja1105_status { 228 u64 configs; 229 u64 crcchkl; 230 u64 ids; 231 u64 crcchkg; 232 }; 233 234 /* This is not reading the entire General Status area, which is also 235 * divergent between E/T and P/Q/R/S, but only the relevant bits for 236 * ensuring that the static config upload procedure was successful. 237 */ 238 static void sja1105_status_unpack(void *buf, struct sja1105_status *status) 239 { 240 /* So that addition translates to 4 bytes */ 241 u32 *p = buf; 242 243 /* device_id is missing from the buffer, but we don't 244 * want to diverge from the manual definition of the 245 * register addresses, so we'll back off one step with 246 * the register pointer, and never access p[0]. 247 */ 248 p--; 249 sja1105_unpack(p + 0x1, &status->configs, 31, 31, 4); 250 sja1105_unpack(p + 0x1, &status->crcchkl, 30, 30, 4); 251 sja1105_unpack(p + 0x1, &status->ids, 29, 29, 4); 252 sja1105_unpack(p + 0x1, &status->crcchkg, 28, 28, 4); 253 } 254 255 static int sja1105_status_get(struct sja1105_private *priv, 256 struct sja1105_status *status) 257 { 258 const struct sja1105_regs *regs = priv->info->regs; 259 u8 packed_buf[4]; 260 int rc; 261 262 rc = sja1105_xfer_buf(priv, SPI_READ, regs->status, packed_buf, 4); 263 if (rc < 0) 264 return rc; 265 266 sja1105_status_unpack(packed_buf, status); 267 268 return 0; 269 } 270 271 /* Not const because unpacking priv->static_config into buffers and preparing 272 * for upload requires the recalculation of table CRCs and updating the 273 * structures with these. 274 */ 275 int static_config_buf_prepare_for_upload(struct sja1105_private *priv, 276 void *config_buf, int buf_len) 277 { 278 struct sja1105_static_config *config = &priv->static_config; 279 struct sja1105_table_header final_header; 280 sja1105_config_valid_t valid; 281 char *final_header_ptr; 282 int crc_len; 283 284 valid = sja1105_static_config_check_valid(config, 285 priv->info->max_frame_mem); 286 if (valid != SJA1105_CONFIG_OK) { 287 dev_err(&priv->spidev->dev, 288 sja1105_static_config_error_msg[valid]); 289 return -EINVAL; 290 } 291 292 /* Write Device ID and config tables to config_buf */ 293 sja1105_static_config_pack(config_buf, config); 294 /* Recalculate CRC of the last header (right now 0xDEADBEEF). 295 * Don't include the CRC field itself. 296 */ 297 crc_len = buf_len - 4; 298 /* Read the whole table header */ 299 final_header_ptr = config_buf + buf_len - SJA1105_SIZE_TABLE_HEADER; 300 sja1105_table_header_packing(final_header_ptr, &final_header, UNPACK); 301 /* Modify */ 302 final_header.crc = sja1105_crc32(config_buf, crc_len); 303 /* Rewrite */ 304 sja1105_table_header_packing(final_header_ptr, &final_header, PACK); 305 306 return 0; 307 } 308 309 #define RETRIES 10 310 311 int sja1105_static_config_upload(struct sja1105_private *priv) 312 { 313 struct sja1105_static_config *config = &priv->static_config; 314 const struct sja1105_regs *regs = priv->info->regs; 315 struct device *dev = &priv->spidev->dev; 316 struct dsa_switch *ds = priv->ds; 317 struct sja1105_status status; 318 int rc, retries = RETRIES; 319 u8 *config_buf; 320 int buf_len; 321 322 buf_len = sja1105_static_config_get_length(config); 323 config_buf = kcalloc(buf_len, sizeof(char), GFP_KERNEL); 324 if (!config_buf) 325 return -ENOMEM; 326 327 rc = static_config_buf_prepare_for_upload(priv, config_buf, buf_len); 328 if (rc < 0) { 329 dev_err(dev, "Invalid config, cannot upload\n"); 330 rc = -EINVAL; 331 goto out; 332 } 333 /* Prevent PHY jabbering during switch reset by inhibiting 334 * Tx on all ports and waiting for current packet to drain. 335 * Otherwise, the PHY will see an unterminated Ethernet packet. 336 */ 337 rc = sja1105_inhibit_tx(priv, GENMASK_ULL(ds->num_ports - 1, 0), true); 338 if (rc < 0) { 339 dev_err(dev, "Failed to inhibit Tx on ports\n"); 340 rc = -ENXIO; 341 goto out; 342 } 343 /* Wait for an eventual egress packet to finish transmission 344 * (reach IFG). It is guaranteed that a second one will not 345 * follow, and that switch cold reset is thus safe 346 */ 347 usleep_range(500, 1000); 348 do { 349 /* Put the SJA1105 in programming mode */ 350 rc = priv->info->reset_cmd(priv->ds); 351 if (rc < 0) { 352 dev_err(dev, "Failed to reset switch, retrying...\n"); 353 continue; 354 } 355 /* Wait for the switch to come out of reset */ 356 usleep_range(1000, 5000); 357 /* Upload the static config to the device */ 358 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->config, 359 config_buf, buf_len); 360 if (rc < 0) { 361 dev_err(dev, "Failed to upload config, retrying...\n"); 362 continue; 363 } 364 /* Check that SJA1105 responded well to the config upload */ 365 rc = sja1105_status_get(priv, &status); 366 if (rc < 0) 367 continue; 368 369 if (status.ids == 1) { 370 dev_err(dev, "Mismatch between hardware and static config " 371 "device id. Wrote 0x%llx, wants 0x%llx\n", 372 config->device_id, priv->info->device_id); 373 continue; 374 } 375 if (status.crcchkl == 1) { 376 dev_err(dev, "Switch reported invalid local CRC on " 377 "the uploaded config, retrying...\n"); 378 continue; 379 } 380 if (status.crcchkg == 1) { 381 dev_err(dev, "Switch reported invalid global CRC on " 382 "the uploaded config, retrying...\n"); 383 continue; 384 } 385 if (status.configs == 0) { 386 dev_err(dev, "Switch reported that configuration is " 387 "invalid, retrying...\n"); 388 continue; 389 } 390 /* Success! */ 391 break; 392 } while (--retries); 393 394 if (!retries) { 395 rc = -EIO; 396 dev_err(dev, "Failed to upload config to device, giving up\n"); 397 goto out; 398 } else if (retries != RETRIES) { 399 dev_info(dev, "Succeeded after %d tried\n", RETRIES - retries); 400 } 401 402 out: 403 kfree(config_buf); 404 return rc; 405 } 406 407 static struct sja1105_regs sja1105et_regs = { 408 .device_id = 0x0, 409 .prod_id = 0x100BC3, 410 .status = 0x1, 411 .port_control = 0x11, 412 .vl_status = 0x10000, 413 .config = 0x020000, 414 .rgu = 0x100440, 415 /* UM10944.pdf, Table 86, ACU Register overview */ 416 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808}, 417 .pad_mii_rx = {0x100801, 0x100803, 0x100805, 0x100807, 0x100809}, 418 .rmii_pll1 = 0x10000A, 419 .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F}, 420 .stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208}, 421 .stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440}, 422 .stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640}, 423 /* UM10944.pdf, Table 78, CGU Register overview */ 424 .mii_tx_clk = {0x100013, 0x10001A, 0x100021, 0x100028, 0x10002F}, 425 .mii_rx_clk = {0x100014, 0x10001B, 0x100022, 0x100029, 0x100030}, 426 .mii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034}, 427 .mii_ext_rx_clk = {0x100019, 0x100020, 0x100027, 0x10002E, 0x100035}, 428 .rgmii_tx_clk = {0x100016, 0x10001D, 0x100024, 0x10002B, 0x100032}, 429 .rmii_ref_clk = {0x100015, 0x10001C, 0x100023, 0x10002A, 0x100031}, 430 .rmii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034}, 431 .ptpegr_ts = {0xC0, 0xC2, 0xC4, 0xC6, 0xC8}, 432 .ptpschtm = 0x12, /* Spans 0x12 to 0x13 */ 433 .ptppinst = 0x14, 434 .ptppindur = 0x16, 435 .ptp_control = 0x17, 436 .ptpclkval = 0x18, /* Spans 0x18 to 0x19 */ 437 .ptpclkrate = 0x1A, 438 .ptpclkcorp = 0x1D, 439 .mdio_100base_tx = SJA1105_RSV_ADDR, 440 .mdio_100base_t1 = SJA1105_RSV_ADDR, 441 }; 442 443 static struct sja1105_regs sja1105pqrs_regs = { 444 .device_id = 0x0, 445 .prod_id = 0x100BC3, 446 .status = 0x1, 447 .port_control = 0x12, 448 .vl_status = 0x10000, 449 .config = 0x020000, 450 .rgu = 0x100440, 451 /* UM10944.pdf, Table 86, ACU Register overview */ 452 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808}, 453 .pad_mii_rx = {0x100801, 0x100803, 0x100805, 0x100807, 0x100809}, 454 .pad_mii_id = {0x100810, 0x100811, 0x100812, 0x100813, 0x100814}, 455 .rmii_pll1 = 0x10000A, 456 .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F}, 457 .stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208}, 458 .stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440}, 459 .stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640}, 460 .stats[ETHER] = {0x1400, 0x1418, 0x1430, 0x1448, 0x1460}, 461 /* UM11040.pdf, Table 114 */ 462 .mii_tx_clk = {0x100013, 0x100019, 0x10001F, 0x100025, 0x10002B}, 463 .mii_rx_clk = {0x100014, 0x10001A, 0x100020, 0x100026, 0x10002C}, 464 .mii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F}, 465 .mii_ext_rx_clk = {0x100018, 0x10001E, 0x100024, 0x10002A, 0x100030}, 466 .rgmii_tx_clk = {0x100016, 0x10001C, 0x100022, 0x100028, 0x10002E}, 467 .rmii_ref_clk = {0x100015, 0x10001B, 0x100021, 0x100027, 0x10002D}, 468 .rmii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F}, 469 .ptpegr_ts = {0xC0, 0xC4, 0xC8, 0xCC, 0xD0}, 470 .ptpschtm = 0x13, /* Spans 0x13 to 0x14 */ 471 .ptppinst = 0x15, 472 .ptppindur = 0x17, 473 .ptp_control = 0x18, 474 .ptpclkval = 0x19, 475 .ptpclkrate = 0x1B, 476 .ptpclkcorp = 0x1E, 477 .ptpsyncts = 0x1F, 478 .mdio_100base_tx = SJA1105_RSV_ADDR, 479 .mdio_100base_t1 = SJA1105_RSV_ADDR, 480 }; 481 482 static struct sja1105_regs sja1110_regs = { 483 .device_id = SJA1110_SPI_ADDR(0x0), 484 .prod_id = SJA1110_ACU_ADDR(0xf00), 485 .status = SJA1110_SPI_ADDR(0x4), 486 .port_control = SJA1110_SPI_ADDR(0x50), /* actually INHIB_TX */ 487 .vl_status = 0x10000, 488 .config = 0x020000, 489 .rgu = SJA1110_RGU_ADDR(0x100), /* Reset Control Register 0 */ 490 /* Ports 2 and 3 are capable of xMII, but there isn't anything to 491 * configure in the CGU/ACU for them. 492 */ 493 .pad_mii_tx = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 494 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 495 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 496 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 497 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 498 SJA1105_RSV_ADDR}, 499 .pad_mii_rx = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 500 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 501 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 502 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 503 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 504 SJA1105_RSV_ADDR}, 505 .pad_mii_id = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 506 SJA1110_ACU_ADDR(0x18), SJA1110_ACU_ADDR(0x28), 507 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 508 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 509 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 510 SJA1105_RSV_ADDR}, 511 .rmii_pll1 = SJA1105_RSV_ADDR, 512 .cgu_idiv = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 513 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 514 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 515 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR}, 516 .stats[MAC] = {0x200, 0x202, 0x204, 0x206, 0x208, 0x20a, 517 0x20c, 0x20e, 0x210, 0x212, 0x214}, 518 .stats[HL1] = {0x400, 0x410, 0x420, 0x430, 0x440, 0x450, 519 0x460, 0x470, 0x480, 0x490, 0x4a0}, 520 .stats[HL2] = {0x600, 0x610, 0x620, 0x630, 0x640, 0x650, 521 0x660, 0x670, 0x680, 0x690, 0x6a0}, 522 .stats[ETHER] = {0x1400, 0x1418, 0x1430, 0x1448, 0x1460, 0x1478, 523 0x1490, 0x14a8, 0x14c0, 0x14d8, 0x14f0}, 524 .mii_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 525 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 526 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 527 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR}, 528 .mii_rx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 529 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 530 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 531 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR}, 532 .mii_ext_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 533 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 534 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 535 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR}, 536 .mii_ext_rx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 537 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 538 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 539 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR}, 540 .rgmii_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 541 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 542 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 543 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR}, 544 .rmii_ref_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 545 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 546 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 547 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR}, 548 .rmii_ext_tx_clk = {SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 549 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 550 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 551 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 552 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 553 SJA1105_RSV_ADDR}, 554 .ptpschtm = SJA1110_SPI_ADDR(0x54), 555 .ptppinst = SJA1110_SPI_ADDR(0x5c), 556 .ptppindur = SJA1110_SPI_ADDR(0x64), 557 .ptp_control = SJA1110_SPI_ADDR(0x68), 558 .ptpclkval = SJA1110_SPI_ADDR(0x6c), 559 .ptpclkrate = SJA1110_SPI_ADDR(0x74), 560 .ptpclkcorp = SJA1110_SPI_ADDR(0x80), 561 .ptpsyncts = SJA1110_SPI_ADDR(0x84), 562 .mdio_100base_tx = 0x1c2400, 563 .mdio_100base_t1 = 0x1c1000, 564 .pcs_base = {SJA1105_RSV_ADDR, 0x1c1400, 0x1c1800, 0x1c1c00, 0x1c2000, 565 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, 566 SJA1105_RSV_ADDR, SJA1105_RSV_ADDR, SJA1105_RSV_ADDR}, 567 }; 568 569 const struct sja1105_info sja1105e_info = { 570 .device_id = SJA1105E_DEVICE_ID, 571 .part_no = SJA1105ET_PART_NO, 572 .static_ops = sja1105e_table_ops, 573 .dyn_ops = sja1105et_dyn_ops, 574 .qinq_tpid = ETH_P_8021Q, 575 .tag_proto = DSA_TAG_PROTO_SJA1105, 576 .can_limit_mcast_flood = false, 577 .ptp_ts_bits = 24, 578 .ptpegr_ts_bytes = 4, 579 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY, 580 .num_ports = SJA1105_NUM_PORTS, 581 .num_cbs_shapers = SJA1105ET_MAX_CBS_COUNT, 582 .reset_cmd = sja1105et_reset_cmd, 583 .fdb_add_cmd = sja1105et_fdb_add, 584 .fdb_del_cmd = sja1105et_fdb_del, 585 .ptp_cmd_packing = sja1105et_ptp_cmd_packing, 586 .rxtstamp = sja1105_rxtstamp, 587 .clocking_setup = sja1105_clocking_setup, 588 .regs = &sja1105et_regs, 589 .port_speed = { 590 [SJA1105_SPEED_AUTO] = 0, 591 [SJA1105_SPEED_10MBPS] = 3, 592 [SJA1105_SPEED_100MBPS] = 2, 593 [SJA1105_SPEED_1000MBPS] = 1, 594 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */ 595 }, 596 .supports_mii = {true, true, true, true, true}, 597 .supports_rmii = {true, true, true, true, true}, 598 .supports_rgmii = {true, true, true, true, true}, 599 .name = "SJA1105E", 600 }; 601 602 const struct sja1105_info sja1105t_info = { 603 .device_id = SJA1105T_DEVICE_ID, 604 .part_no = SJA1105ET_PART_NO, 605 .static_ops = sja1105t_table_ops, 606 .dyn_ops = sja1105et_dyn_ops, 607 .qinq_tpid = ETH_P_8021Q, 608 .tag_proto = DSA_TAG_PROTO_SJA1105, 609 .can_limit_mcast_flood = false, 610 .ptp_ts_bits = 24, 611 .ptpegr_ts_bytes = 4, 612 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY, 613 .num_ports = SJA1105_NUM_PORTS, 614 .num_cbs_shapers = SJA1105ET_MAX_CBS_COUNT, 615 .reset_cmd = sja1105et_reset_cmd, 616 .fdb_add_cmd = sja1105et_fdb_add, 617 .fdb_del_cmd = sja1105et_fdb_del, 618 .ptp_cmd_packing = sja1105et_ptp_cmd_packing, 619 .rxtstamp = sja1105_rxtstamp, 620 .clocking_setup = sja1105_clocking_setup, 621 .regs = &sja1105et_regs, 622 .port_speed = { 623 [SJA1105_SPEED_AUTO] = 0, 624 [SJA1105_SPEED_10MBPS] = 3, 625 [SJA1105_SPEED_100MBPS] = 2, 626 [SJA1105_SPEED_1000MBPS] = 1, 627 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */ 628 }, 629 .supports_mii = {true, true, true, true, true}, 630 .supports_rmii = {true, true, true, true, true}, 631 .supports_rgmii = {true, true, true, true, true}, 632 .name = "SJA1105T", 633 }; 634 635 const struct sja1105_info sja1105p_info = { 636 .device_id = SJA1105PR_DEVICE_ID, 637 .part_no = SJA1105P_PART_NO, 638 .static_ops = sja1105p_table_ops, 639 .dyn_ops = sja1105pqrs_dyn_ops, 640 .qinq_tpid = ETH_P_8021AD, 641 .tag_proto = DSA_TAG_PROTO_SJA1105, 642 .can_limit_mcast_flood = true, 643 .ptp_ts_bits = 32, 644 .ptpegr_ts_bytes = 8, 645 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY, 646 .num_ports = SJA1105_NUM_PORTS, 647 .num_cbs_shapers = SJA1105PQRS_MAX_CBS_COUNT, 648 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay, 649 .reset_cmd = sja1105pqrs_reset_cmd, 650 .fdb_add_cmd = sja1105pqrs_fdb_add, 651 .fdb_del_cmd = sja1105pqrs_fdb_del, 652 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing, 653 .rxtstamp = sja1105_rxtstamp, 654 .clocking_setup = sja1105_clocking_setup, 655 .regs = &sja1105pqrs_regs, 656 .port_speed = { 657 [SJA1105_SPEED_AUTO] = 0, 658 [SJA1105_SPEED_10MBPS] = 3, 659 [SJA1105_SPEED_100MBPS] = 2, 660 [SJA1105_SPEED_1000MBPS] = 1, 661 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */ 662 }, 663 .supports_mii = {true, true, true, true, true}, 664 .supports_rmii = {true, true, true, true, true}, 665 .supports_rgmii = {true, true, true, true, true}, 666 .name = "SJA1105P", 667 }; 668 669 const struct sja1105_info sja1105q_info = { 670 .device_id = SJA1105QS_DEVICE_ID, 671 .part_no = SJA1105Q_PART_NO, 672 .static_ops = sja1105q_table_ops, 673 .dyn_ops = sja1105pqrs_dyn_ops, 674 .qinq_tpid = ETH_P_8021AD, 675 .tag_proto = DSA_TAG_PROTO_SJA1105, 676 .can_limit_mcast_flood = true, 677 .ptp_ts_bits = 32, 678 .ptpegr_ts_bytes = 8, 679 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY, 680 .num_ports = SJA1105_NUM_PORTS, 681 .num_cbs_shapers = SJA1105PQRS_MAX_CBS_COUNT, 682 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay, 683 .reset_cmd = sja1105pqrs_reset_cmd, 684 .fdb_add_cmd = sja1105pqrs_fdb_add, 685 .fdb_del_cmd = sja1105pqrs_fdb_del, 686 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing, 687 .rxtstamp = sja1105_rxtstamp, 688 .clocking_setup = sja1105_clocking_setup, 689 .regs = &sja1105pqrs_regs, 690 .port_speed = { 691 [SJA1105_SPEED_AUTO] = 0, 692 [SJA1105_SPEED_10MBPS] = 3, 693 [SJA1105_SPEED_100MBPS] = 2, 694 [SJA1105_SPEED_1000MBPS] = 1, 695 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */ 696 }, 697 .supports_mii = {true, true, true, true, true}, 698 .supports_rmii = {true, true, true, true, true}, 699 .supports_rgmii = {true, true, true, true, true}, 700 .name = "SJA1105Q", 701 }; 702 703 const struct sja1105_info sja1105r_info = { 704 .device_id = SJA1105PR_DEVICE_ID, 705 .part_no = SJA1105R_PART_NO, 706 .static_ops = sja1105r_table_ops, 707 .dyn_ops = sja1105pqrs_dyn_ops, 708 .qinq_tpid = ETH_P_8021AD, 709 .tag_proto = DSA_TAG_PROTO_SJA1105, 710 .can_limit_mcast_flood = true, 711 .ptp_ts_bits = 32, 712 .ptpegr_ts_bytes = 8, 713 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY, 714 .num_ports = SJA1105_NUM_PORTS, 715 .num_cbs_shapers = SJA1105PQRS_MAX_CBS_COUNT, 716 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay, 717 .reset_cmd = sja1105pqrs_reset_cmd, 718 .fdb_add_cmd = sja1105pqrs_fdb_add, 719 .fdb_del_cmd = sja1105pqrs_fdb_del, 720 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing, 721 .rxtstamp = sja1105_rxtstamp, 722 .clocking_setup = sja1105_clocking_setup, 723 .pcs_mdio_read = sja1105_pcs_mdio_read, 724 .pcs_mdio_write = sja1105_pcs_mdio_write, 725 .regs = &sja1105pqrs_regs, 726 .port_speed = { 727 [SJA1105_SPEED_AUTO] = 0, 728 [SJA1105_SPEED_10MBPS] = 3, 729 [SJA1105_SPEED_100MBPS] = 2, 730 [SJA1105_SPEED_1000MBPS] = 1, 731 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */ 732 }, 733 .supports_mii = {true, true, true, true, true}, 734 .supports_rmii = {true, true, true, true, true}, 735 .supports_rgmii = {true, true, true, true, true}, 736 .supports_sgmii = {false, false, false, false, true}, 737 .name = "SJA1105R", 738 }; 739 740 const struct sja1105_info sja1105s_info = { 741 .device_id = SJA1105QS_DEVICE_ID, 742 .part_no = SJA1105S_PART_NO, 743 .static_ops = sja1105s_table_ops, 744 .dyn_ops = sja1105pqrs_dyn_ops, 745 .regs = &sja1105pqrs_regs, 746 .qinq_tpid = ETH_P_8021AD, 747 .tag_proto = DSA_TAG_PROTO_SJA1105, 748 .can_limit_mcast_flood = true, 749 .ptp_ts_bits = 32, 750 .ptpegr_ts_bytes = 8, 751 .max_frame_mem = SJA1105_MAX_FRAME_MEMORY, 752 .num_ports = SJA1105_NUM_PORTS, 753 .num_cbs_shapers = SJA1105PQRS_MAX_CBS_COUNT, 754 .setup_rgmii_delay = sja1105pqrs_setup_rgmii_delay, 755 .reset_cmd = sja1105pqrs_reset_cmd, 756 .fdb_add_cmd = sja1105pqrs_fdb_add, 757 .fdb_del_cmd = sja1105pqrs_fdb_del, 758 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing, 759 .rxtstamp = sja1105_rxtstamp, 760 .clocking_setup = sja1105_clocking_setup, 761 .pcs_mdio_read = sja1105_pcs_mdio_read, 762 .pcs_mdio_write = sja1105_pcs_mdio_write, 763 .port_speed = { 764 [SJA1105_SPEED_AUTO] = 0, 765 [SJA1105_SPEED_10MBPS] = 3, 766 [SJA1105_SPEED_100MBPS] = 2, 767 [SJA1105_SPEED_1000MBPS] = 1, 768 [SJA1105_SPEED_2500MBPS] = 0, /* Not supported */ 769 }, 770 .supports_mii = {true, true, true, true, true}, 771 .supports_rmii = {true, true, true, true, true}, 772 .supports_rgmii = {true, true, true, true, true}, 773 .supports_sgmii = {false, false, false, false, true}, 774 .name = "SJA1105S", 775 }; 776 777 const struct sja1105_info sja1110a_info = { 778 .device_id = SJA1110_DEVICE_ID, 779 .part_no = SJA1110A_PART_NO, 780 .static_ops = sja1110_table_ops, 781 .dyn_ops = sja1110_dyn_ops, 782 .regs = &sja1110_regs, 783 .qinq_tpid = ETH_P_8021AD, 784 .tag_proto = DSA_TAG_PROTO_SJA1110, 785 .can_limit_mcast_flood = true, 786 .multiple_cascade_ports = true, 787 .ptp_ts_bits = 32, 788 .ptpegr_ts_bytes = 8, 789 .max_frame_mem = SJA1110_MAX_FRAME_MEMORY, 790 .num_ports = SJA1110_NUM_PORTS, 791 .num_cbs_shapers = SJA1110_MAX_CBS_COUNT, 792 .setup_rgmii_delay = sja1110_setup_rgmii_delay, 793 .reset_cmd = sja1110_reset_cmd, 794 .fdb_add_cmd = sja1105pqrs_fdb_add, 795 .fdb_del_cmd = sja1105pqrs_fdb_del, 796 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing, 797 .rxtstamp = sja1110_rxtstamp, 798 .txtstamp = sja1110_txtstamp, 799 .clocking_setup = sja1110_clocking_setup, 800 .pcs_mdio_read = sja1110_pcs_mdio_read, 801 .pcs_mdio_write = sja1110_pcs_mdio_write, 802 .port_speed = { 803 [SJA1105_SPEED_AUTO] = 0, 804 [SJA1105_SPEED_10MBPS] = 4, 805 [SJA1105_SPEED_100MBPS] = 3, 806 [SJA1105_SPEED_1000MBPS] = 2, 807 [SJA1105_SPEED_2500MBPS] = 1, 808 }, 809 .supports_mii = {true, true, true, true, false, 810 true, true, true, true, true, true}, 811 .supports_rmii = {false, false, true, true, false, 812 false, false, false, false, false, false}, 813 .supports_rgmii = {false, false, true, true, false, 814 false, false, false, false, false, false}, 815 .supports_sgmii = {false, true, true, true, true, 816 false, false, false, false, false, false}, 817 .supports_2500basex = {false, false, false, true, true, 818 false, false, false, false, false, false}, 819 .internal_phy = {SJA1105_NO_PHY, SJA1105_PHY_BASE_TX, 820 SJA1105_NO_PHY, SJA1105_NO_PHY, 821 SJA1105_NO_PHY, SJA1105_PHY_BASE_T1, 822 SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1, 823 SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1, 824 SJA1105_PHY_BASE_T1}, 825 .name = "SJA1110A", 826 }; 827 828 const struct sja1105_info sja1110b_info = { 829 .device_id = SJA1110_DEVICE_ID, 830 .part_no = SJA1110B_PART_NO, 831 .static_ops = sja1110_table_ops, 832 .dyn_ops = sja1110_dyn_ops, 833 .regs = &sja1110_regs, 834 .qinq_tpid = ETH_P_8021AD, 835 .tag_proto = DSA_TAG_PROTO_SJA1110, 836 .can_limit_mcast_flood = true, 837 .multiple_cascade_ports = true, 838 .ptp_ts_bits = 32, 839 .ptpegr_ts_bytes = 8, 840 .max_frame_mem = SJA1110_MAX_FRAME_MEMORY, 841 .num_ports = SJA1110_NUM_PORTS, 842 .num_cbs_shapers = SJA1110_MAX_CBS_COUNT, 843 .setup_rgmii_delay = sja1110_setup_rgmii_delay, 844 .reset_cmd = sja1110_reset_cmd, 845 .fdb_add_cmd = sja1105pqrs_fdb_add, 846 .fdb_del_cmd = sja1105pqrs_fdb_del, 847 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing, 848 .rxtstamp = sja1110_rxtstamp, 849 .txtstamp = sja1110_txtstamp, 850 .clocking_setup = sja1110_clocking_setup, 851 .pcs_mdio_read = sja1110_pcs_mdio_read, 852 .pcs_mdio_write = sja1110_pcs_mdio_write, 853 .port_speed = { 854 [SJA1105_SPEED_AUTO] = 0, 855 [SJA1105_SPEED_10MBPS] = 4, 856 [SJA1105_SPEED_100MBPS] = 3, 857 [SJA1105_SPEED_1000MBPS] = 2, 858 [SJA1105_SPEED_2500MBPS] = 1, 859 }, 860 .supports_mii = {true, true, true, true, false, 861 true, true, true, true, true, false}, 862 .supports_rmii = {false, false, true, true, false, 863 false, false, false, false, false, false}, 864 .supports_rgmii = {false, false, true, true, false, 865 false, false, false, false, false, false}, 866 .supports_sgmii = {false, false, false, true, true, 867 false, false, false, false, false, false}, 868 .supports_2500basex = {false, false, false, true, true, 869 false, false, false, false, false, false}, 870 .internal_phy = {SJA1105_NO_PHY, SJA1105_PHY_BASE_TX, 871 SJA1105_NO_PHY, SJA1105_NO_PHY, 872 SJA1105_NO_PHY, SJA1105_PHY_BASE_T1, 873 SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1, 874 SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1, 875 SJA1105_NO_PHY}, 876 .name = "SJA1110B", 877 }; 878 879 const struct sja1105_info sja1110c_info = { 880 .device_id = SJA1110_DEVICE_ID, 881 .part_no = SJA1110C_PART_NO, 882 .static_ops = sja1110_table_ops, 883 .dyn_ops = sja1110_dyn_ops, 884 .regs = &sja1110_regs, 885 .qinq_tpid = ETH_P_8021AD, 886 .tag_proto = DSA_TAG_PROTO_SJA1110, 887 .can_limit_mcast_flood = true, 888 .multiple_cascade_ports = true, 889 .ptp_ts_bits = 32, 890 .ptpegr_ts_bytes = 8, 891 .max_frame_mem = SJA1110_MAX_FRAME_MEMORY, 892 .num_ports = SJA1110_NUM_PORTS, 893 .num_cbs_shapers = SJA1110_MAX_CBS_COUNT, 894 .setup_rgmii_delay = sja1110_setup_rgmii_delay, 895 .reset_cmd = sja1110_reset_cmd, 896 .fdb_add_cmd = sja1105pqrs_fdb_add, 897 .fdb_del_cmd = sja1105pqrs_fdb_del, 898 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing, 899 .rxtstamp = sja1110_rxtstamp, 900 .txtstamp = sja1110_txtstamp, 901 .clocking_setup = sja1110_clocking_setup, 902 .pcs_mdio_read = sja1110_pcs_mdio_read, 903 .pcs_mdio_write = sja1110_pcs_mdio_write, 904 .port_speed = { 905 [SJA1105_SPEED_AUTO] = 0, 906 [SJA1105_SPEED_10MBPS] = 4, 907 [SJA1105_SPEED_100MBPS] = 3, 908 [SJA1105_SPEED_1000MBPS] = 2, 909 [SJA1105_SPEED_2500MBPS] = 1, 910 }, 911 .supports_mii = {true, true, true, true, false, 912 true, true, true, false, false, false}, 913 .supports_rmii = {false, false, true, true, false, 914 false, false, false, false, false, false}, 915 .supports_rgmii = {false, false, true, true, false, 916 false, false, false, false, false, false}, 917 .supports_sgmii = {false, false, false, false, true, 918 false, false, false, false, false, false}, 919 .supports_2500basex = {false, false, false, false, true, 920 false, false, false, false, false, false}, 921 .internal_phy = {SJA1105_NO_PHY, SJA1105_PHY_BASE_TX, 922 SJA1105_NO_PHY, SJA1105_NO_PHY, 923 SJA1105_NO_PHY, SJA1105_PHY_BASE_T1, 924 SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1, 925 SJA1105_NO_PHY, SJA1105_NO_PHY, 926 SJA1105_NO_PHY}, 927 .name = "SJA1110C", 928 }; 929 930 const struct sja1105_info sja1110d_info = { 931 .device_id = SJA1110_DEVICE_ID, 932 .part_no = SJA1110D_PART_NO, 933 .static_ops = sja1110_table_ops, 934 .dyn_ops = sja1110_dyn_ops, 935 .regs = &sja1110_regs, 936 .qinq_tpid = ETH_P_8021AD, 937 .tag_proto = DSA_TAG_PROTO_SJA1110, 938 .can_limit_mcast_flood = true, 939 .multiple_cascade_ports = true, 940 .ptp_ts_bits = 32, 941 .ptpegr_ts_bytes = 8, 942 .max_frame_mem = SJA1110_MAX_FRAME_MEMORY, 943 .num_ports = SJA1110_NUM_PORTS, 944 .num_cbs_shapers = SJA1110_MAX_CBS_COUNT, 945 .setup_rgmii_delay = sja1110_setup_rgmii_delay, 946 .reset_cmd = sja1110_reset_cmd, 947 .fdb_add_cmd = sja1105pqrs_fdb_add, 948 .fdb_del_cmd = sja1105pqrs_fdb_del, 949 .ptp_cmd_packing = sja1105pqrs_ptp_cmd_packing, 950 .rxtstamp = sja1110_rxtstamp, 951 .txtstamp = sja1110_txtstamp, 952 .clocking_setup = sja1110_clocking_setup, 953 .pcs_mdio_read = sja1110_pcs_mdio_read, 954 .pcs_mdio_write = sja1110_pcs_mdio_write, 955 .port_speed = { 956 [SJA1105_SPEED_AUTO] = 0, 957 [SJA1105_SPEED_10MBPS] = 4, 958 [SJA1105_SPEED_100MBPS] = 3, 959 [SJA1105_SPEED_1000MBPS] = 2, 960 [SJA1105_SPEED_2500MBPS] = 1, 961 }, 962 .supports_mii = {true, false, true, false, false, 963 true, true, true, false, false, false}, 964 .supports_rmii = {false, false, true, false, false, 965 false, false, false, false, false, false}, 966 .supports_rgmii = {false, false, true, false, false, 967 false, false, false, false, false, false}, 968 .supports_sgmii = {false, true, true, true, true, 969 false, false, false, false, false, false}, 970 .supports_2500basex = {false, false, false, true, true, 971 false, false, false, false, false, false}, 972 .internal_phy = {SJA1105_NO_PHY, SJA1105_NO_PHY, 973 SJA1105_NO_PHY, SJA1105_NO_PHY, 974 SJA1105_NO_PHY, SJA1105_PHY_BASE_T1, 975 SJA1105_PHY_BASE_T1, SJA1105_PHY_BASE_T1, 976 SJA1105_NO_PHY, SJA1105_NO_PHY, 977 SJA1105_NO_PHY}, 978 .name = "SJA1110D", 979 }; 980