1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright (c) 2016-2018, NXP Semiconductors 3 * Copyright (c) 2018, Sensor-Technik Wiedemann GmbH 4 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 5 */ 6 #include <linux/spi/spi.h> 7 #include <linux/packing.h> 8 #include "sja1105.h" 9 10 #define SJA1105_SIZE_PORT_CTRL 4 11 #define SJA1105_SIZE_RESET_CMD 4 12 #define SJA1105_SIZE_SPI_MSG_HEADER 4 13 #define SJA1105_SIZE_SPI_MSG_MAXLEN (64 * 4) 14 #define SJA1105_SIZE_SPI_TRANSFER_MAX \ 15 (SJA1105_SIZE_SPI_MSG_HEADER + SJA1105_SIZE_SPI_MSG_MAXLEN) 16 17 static int sja1105_spi_transfer(const struct sja1105_private *priv, 18 const void *tx, void *rx, int size) 19 { 20 struct spi_device *spi = priv->spidev; 21 struct spi_transfer transfer = { 22 .tx_buf = tx, 23 .rx_buf = rx, 24 .len = size, 25 }; 26 struct spi_message msg; 27 int rc; 28 29 if (size > SJA1105_SIZE_SPI_TRANSFER_MAX) { 30 dev_err(&spi->dev, "SPI message (%d) longer than max of %d\n", 31 size, SJA1105_SIZE_SPI_TRANSFER_MAX); 32 return -EMSGSIZE; 33 } 34 35 spi_message_init(&msg); 36 spi_message_add_tail(&transfer, &msg); 37 38 rc = spi_sync(spi, &msg); 39 if (rc < 0) { 40 dev_err(&spi->dev, "SPI transfer failed: %d\n", rc); 41 return rc; 42 } 43 44 return rc; 45 } 46 47 static void 48 sja1105_spi_message_pack(void *buf, const struct sja1105_spi_message *msg) 49 { 50 const int size = SJA1105_SIZE_SPI_MSG_HEADER; 51 52 memset(buf, 0, size); 53 54 sja1105_pack(buf, &msg->access, 31, 31, size); 55 sja1105_pack(buf, &msg->read_count, 30, 25, size); 56 sja1105_pack(buf, &msg->address, 24, 4, size); 57 } 58 59 /* If @rw is: 60 * - SPI_WRITE: creates and sends an SPI write message at absolute 61 * address reg_addr, taking size_bytes from *packed_buf 62 * - SPI_READ: creates and sends an SPI read message from absolute 63 * address reg_addr, writing size_bytes into *packed_buf 64 * 65 * This function should only be called if it is priorly known that 66 * @size_bytes is smaller than SIZE_SPI_MSG_MAXLEN. Larger packed buffers 67 * are chunked in smaller pieces by sja1105_spi_send_long_packed_buf below. 68 */ 69 int sja1105_spi_send_packed_buf(const struct sja1105_private *priv, 70 sja1105_spi_rw_mode_t rw, u64 reg_addr, 71 void *packed_buf, size_t size_bytes) 72 { 73 u8 tx_buf[SJA1105_SIZE_SPI_TRANSFER_MAX] = {0}; 74 u8 rx_buf[SJA1105_SIZE_SPI_TRANSFER_MAX] = {0}; 75 const int msg_len = size_bytes + SJA1105_SIZE_SPI_MSG_HEADER; 76 struct sja1105_spi_message msg = {0}; 77 int rc; 78 79 if (msg_len > SJA1105_SIZE_SPI_TRANSFER_MAX) 80 return -ERANGE; 81 82 msg.access = rw; 83 msg.address = reg_addr; 84 if (rw == SPI_READ) 85 msg.read_count = size_bytes / 4; 86 87 sja1105_spi_message_pack(tx_buf, &msg); 88 89 if (rw == SPI_WRITE) 90 memcpy(tx_buf + SJA1105_SIZE_SPI_MSG_HEADER, 91 packed_buf, size_bytes); 92 93 rc = sja1105_spi_transfer(priv, tx_buf, rx_buf, msg_len); 94 if (rc < 0) 95 return rc; 96 97 if (rw == SPI_READ) 98 memcpy(packed_buf, rx_buf + SJA1105_SIZE_SPI_MSG_HEADER, 99 size_bytes); 100 101 return 0; 102 } 103 104 /* If @rw is: 105 * - SPI_WRITE: creates and sends an SPI write message at absolute 106 * address reg_addr, taking size_bytes from *packed_buf 107 * - SPI_READ: creates and sends an SPI read message from absolute 108 * address reg_addr, writing size_bytes into *packed_buf 109 * 110 * The u64 *value is unpacked, meaning that it's stored in the native 111 * CPU endianness and directly usable by software running on the core. 112 * 113 * This is a wrapper around sja1105_spi_send_packed_buf(). 114 */ 115 int sja1105_spi_send_int(const struct sja1105_private *priv, 116 sja1105_spi_rw_mode_t rw, u64 reg_addr, 117 u64 *value, u64 size_bytes) 118 { 119 u8 packed_buf[SJA1105_SIZE_SPI_MSG_MAXLEN]; 120 int rc; 121 122 if (size_bytes > SJA1105_SIZE_SPI_MSG_MAXLEN) 123 return -ERANGE; 124 125 if (rw == SPI_WRITE) 126 sja1105_pack(packed_buf, value, 8 * size_bytes - 1, 0, 127 size_bytes); 128 129 rc = sja1105_spi_send_packed_buf(priv, rw, reg_addr, packed_buf, 130 size_bytes); 131 132 if (rw == SPI_READ) 133 sja1105_unpack(packed_buf, value, 8 * size_bytes - 1, 0, 134 size_bytes); 135 136 return rc; 137 } 138 139 /* Should be used if a @packed_buf larger than SJA1105_SIZE_SPI_MSG_MAXLEN 140 * must be sent/received. Splitting the buffer into chunks and assembling 141 * those into SPI messages is done automatically by this function. 142 */ 143 int sja1105_spi_send_long_packed_buf(const struct sja1105_private *priv, 144 sja1105_spi_rw_mode_t rw, u64 base_addr, 145 void *packed_buf, u64 buf_len) 146 { 147 struct chunk { 148 void *buf_ptr; 149 int len; 150 u64 spi_address; 151 } chunk; 152 int distance_to_end; 153 int rc; 154 155 /* Initialize chunk */ 156 chunk.buf_ptr = packed_buf; 157 chunk.spi_address = base_addr; 158 chunk.len = min_t(int, buf_len, SJA1105_SIZE_SPI_MSG_MAXLEN); 159 160 while (chunk.len) { 161 rc = sja1105_spi_send_packed_buf(priv, rw, chunk.spi_address, 162 chunk.buf_ptr, chunk.len); 163 if (rc < 0) 164 return rc; 165 166 chunk.buf_ptr += chunk.len; 167 chunk.spi_address += chunk.len / 4; 168 distance_to_end = (uintptr_t)(packed_buf + buf_len - 169 chunk.buf_ptr); 170 chunk.len = min(distance_to_end, SJA1105_SIZE_SPI_MSG_MAXLEN); 171 } 172 173 return 0; 174 } 175 176 /* Back-ported structure from UM11040 Table 112. 177 * Reset control register (addr. 100440h) 178 * In the SJA1105 E/T, only warm_rst and cold_rst are 179 * supported (exposed in UM10944 as rst_ctrl), but the bit 180 * offsets of warm_rst and cold_rst are actually reversed. 181 */ 182 struct sja1105_reset_cmd { 183 u64 switch_rst; 184 u64 cfg_rst; 185 u64 car_rst; 186 u64 otp_rst; 187 u64 warm_rst; 188 u64 cold_rst; 189 u64 por_rst; 190 }; 191 192 static void 193 sja1105et_reset_cmd_pack(void *buf, const struct sja1105_reset_cmd *reset) 194 { 195 const int size = SJA1105_SIZE_RESET_CMD; 196 197 memset(buf, 0, size); 198 199 sja1105_pack(buf, &reset->cold_rst, 3, 3, size); 200 sja1105_pack(buf, &reset->warm_rst, 2, 2, size); 201 } 202 203 static void 204 sja1105pqrs_reset_cmd_pack(void *buf, const struct sja1105_reset_cmd *reset) 205 { 206 const int size = SJA1105_SIZE_RESET_CMD; 207 208 memset(buf, 0, size); 209 210 sja1105_pack(buf, &reset->switch_rst, 8, 8, size); 211 sja1105_pack(buf, &reset->cfg_rst, 7, 7, size); 212 sja1105_pack(buf, &reset->car_rst, 5, 5, size); 213 sja1105_pack(buf, &reset->otp_rst, 4, 4, size); 214 sja1105_pack(buf, &reset->warm_rst, 3, 3, size); 215 sja1105_pack(buf, &reset->cold_rst, 2, 2, size); 216 sja1105_pack(buf, &reset->por_rst, 1, 1, size); 217 } 218 219 static int sja1105et_reset_cmd(const void *ctx, const void *data) 220 { 221 const struct sja1105_private *priv = ctx; 222 const struct sja1105_reset_cmd *reset = data; 223 const struct sja1105_regs *regs = priv->info->regs; 224 struct device *dev = priv->ds->dev; 225 u8 packed_buf[SJA1105_SIZE_RESET_CMD]; 226 227 if (reset->switch_rst || 228 reset->cfg_rst || 229 reset->car_rst || 230 reset->otp_rst || 231 reset->por_rst) { 232 dev_err(dev, "Only warm and cold reset is supported " 233 "for SJA1105 E/T!\n"); 234 return -EINVAL; 235 } 236 237 if (reset->warm_rst) 238 dev_dbg(dev, "Warm reset requested\n"); 239 if (reset->cold_rst) 240 dev_dbg(dev, "Cold reset requested\n"); 241 242 sja1105et_reset_cmd_pack(packed_buf, reset); 243 244 return sja1105_spi_send_packed_buf(priv, SPI_WRITE, regs->rgu, 245 packed_buf, SJA1105_SIZE_RESET_CMD); 246 } 247 248 static int sja1105pqrs_reset_cmd(const void *ctx, const void *data) 249 { 250 const struct sja1105_private *priv = ctx; 251 const struct sja1105_reset_cmd *reset = data; 252 const struct sja1105_regs *regs = priv->info->regs; 253 struct device *dev = priv->ds->dev; 254 u8 packed_buf[SJA1105_SIZE_RESET_CMD]; 255 256 if (reset->switch_rst) 257 dev_dbg(dev, "Main reset for all functional modules requested\n"); 258 if (reset->cfg_rst) 259 dev_dbg(dev, "Chip configuration reset requested\n"); 260 if (reset->car_rst) 261 dev_dbg(dev, "Clock and reset control logic reset requested\n"); 262 if (reset->otp_rst) 263 dev_dbg(dev, "OTP read cycle for reading product " 264 "config settings requested\n"); 265 if (reset->warm_rst) 266 dev_dbg(dev, "Warm reset requested\n"); 267 if (reset->cold_rst) 268 dev_dbg(dev, "Cold reset requested\n"); 269 if (reset->por_rst) 270 dev_dbg(dev, "Power-on reset requested\n"); 271 272 sja1105pqrs_reset_cmd_pack(packed_buf, reset); 273 274 return sja1105_spi_send_packed_buf(priv, SPI_WRITE, regs->rgu, 275 packed_buf, SJA1105_SIZE_RESET_CMD); 276 } 277 278 static int sja1105_cold_reset(const struct sja1105_private *priv) 279 { 280 struct sja1105_reset_cmd reset = {0}; 281 282 reset.cold_rst = 1; 283 return priv->info->reset_cmd(priv, &reset); 284 } 285 286 static int sja1105_inhibit_tx(const struct sja1105_private *priv, 287 const unsigned long *port_bitmap) 288 { 289 const struct sja1105_regs *regs = priv->info->regs; 290 u64 inhibit_cmd; 291 int port, rc; 292 293 rc = sja1105_spi_send_int(priv, SPI_READ, regs->port_control, 294 &inhibit_cmd, SJA1105_SIZE_PORT_CTRL); 295 if (rc < 0) 296 return rc; 297 298 for_each_set_bit(port, port_bitmap, SJA1105_NUM_PORTS) 299 inhibit_cmd |= BIT(port); 300 301 return sja1105_spi_send_int(priv, SPI_WRITE, regs->port_control, 302 &inhibit_cmd, SJA1105_SIZE_PORT_CTRL); 303 } 304 305 struct sja1105_status { 306 u64 configs; 307 u64 crcchkl; 308 u64 ids; 309 u64 crcchkg; 310 }; 311 312 /* This is not reading the entire General Status area, which is also 313 * divergent between E/T and P/Q/R/S, but only the relevant bits for 314 * ensuring that the static config upload procedure was successful. 315 */ 316 static void sja1105_status_unpack(void *buf, struct sja1105_status *status) 317 { 318 /* So that addition translates to 4 bytes */ 319 u32 *p = buf; 320 321 /* device_id is missing from the buffer, but we don't 322 * want to diverge from the manual definition of the 323 * register addresses, so we'll back off one step with 324 * the register pointer, and never access p[0]. 325 */ 326 p--; 327 sja1105_unpack(p + 0x1, &status->configs, 31, 31, 4); 328 sja1105_unpack(p + 0x1, &status->crcchkl, 30, 30, 4); 329 sja1105_unpack(p + 0x1, &status->ids, 29, 29, 4); 330 sja1105_unpack(p + 0x1, &status->crcchkg, 28, 28, 4); 331 } 332 333 static int sja1105_status_get(struct sja1105_private *priv, 334 struct sja1105_status *status) 335 { 336 const struct sja1105_regs *regs = priv->info->regs; 337 u8 packed_buf[4]; 338 int rc; 339 340 rc = sja1105_spi_send_packed_buf(priv, SPI_READ, 341 regs->status, 342 packed_buf, 4); 343 if (rc < 0) 344 return rc; 345 346 sja1105_status_unpack(packed_buf, status); 347 348 return 0; 349 } 350 351 /* Not const because unpacking priv->static_config into buffers and preparing 352 * for upload requires the recalculation of table CRCs and updating the 353 * structures with these. 354 */ 355 static int 356 static_config_buf_prepare_for_upload(struct sja1105_private *priv, 357 void *config_buf, int buf_len) 358 { 359 struct sja1105_static_config *config = &priv->static_config; 360 struct sja1105_table_header final_header; 361 sja1105_config_valid_t valid; 362 char *final_header_ptr; 363 int crc_len; 364 365 valid = sja1105_static_config_check_valid(config); 366 if (valid != SJA1105_CONFIG_OK) { 367 dev_err(&priv->spidev->dev, 368 sja1105_static_config_error_msg[valid]); 369 return -EINVAL; 370 } 371 372 /* Write Device ID and config tables to config_buf */ 373 sja1105_static_config_pack(config_buf, config); 374 /* Recalculate CRC of the last header (right now 0xDEADBEEF). 375 * Don't include the CRC field itself. 376 */ 377 crc_len = buf_len - 4; 378 /* Read the whole table header */ 379 final_header_ptr = config_buf + buf_len - SJA1105_SIZE_TABLE_HEADER; 380 sja1105_table_header_packing(final_header_ptr, &final_header, UNPACK); 381 /* Modify */ 382 final_header.crc = sja1105_crc32(config_buf, crc_len); 383 /* Rewrite */ 384 sja1105_table_header_packing(final_header_ptr, &final_header, PACK); 385 386 return 0; 387 } 388 389 #define RETRIES 10 390 391 int sja1105_static_config_upload(struct sja1105_private *priv) 392 { 393 unsigned long port_bitmap = GENMASK_ULL(SJA1105_NUM_PORTS - 1, 0); 394 struct sja1105_static_config *config = &priv->static_config; 395 const struct sja1105_regs *regs = priv->info->regs; 396 struct device *dev = &priv->spidev->dev; 397 struct sja1105_status status; 398 int rc, retries = RETRIES; 399 u8 *config_buf; 400 int buf_len; 401 402 buf_len = sja1105_static_config_get_length(config); 403 config_buf = kcalloc(buf_len, sizeof(char), GFP_KERNEL); 404 if (!config_buf) 405 return -ENOMEM; 406 407 rc = static_config_buf_prepare_for_upload(priv, config_buf, buf_len); 408 if (rc < 0) { 409 dev_err(dev, "Invalid config, cannot upload\n"); 410 return -EINVAL; 411 } 412 /* Prevent PHY jabbering during switch reset by inhibiting 413 * Tx on all ports and waiting for current packet to drain. 414 * Otherwise, the PHY will see an unterminated Ethernet packet. 415 */ 416 rc = sja1105_inhibit_tx(priv, &port_bitmap); 417 if (rc < 0) { 418 dev_err(dev, "Failed to inhibit Tx on ports\n"); 419 return -ENXIO; 420 } 421 /* Wait for an eventual egress packet to finish transmission 422 * (reach IFG). It is guaranteed that a second one will not 423 * follow, and that switch cold reset is thus safe 424 */ 425 usleep_range(500, 1000); 426 do { 427 /* Put the SJA1105 in programming mode */ 428 rc = sja1105_cold_reset(priv); 429 if (rc < 0) { 430 dev_err(dev, "Failed to reset switch, retrying...\n"); 431 continue; 432 } 433 /* Wait for the switch to come out of reset */ 434 usleep_range(1000, 5000); 435 /* Upload the static config to the device */ 436 rc = sja1105_spi_send_long_packed_buf(priv, SPI_WRITE, 437 regs->config, 438 config_buf, buf_len); 439 if (rc < 0) { 440 dev_err(dev, "Failed to upload config, retrying...\n"); 441 continue; 442 } 443 /* Check that SJA1105 responded well to the config upload */ 444 rc = sja1105_status_get(priv, &status); 445 if (rc < 0) 446 continue; 447 448 if (status.ids == 1) { 449 dev_err(dev, "Mismatch between hardware and static config " 450 "device id. Wrote 0x%llx, wants 0x%llx\n", 451 config->device_id, priv->info->device_id); 452 continue; 453 } 454 if (status.crcchkl == 1) { 455 dev_err(dev, "Switch reported invalid local CRC on " 456 "the uploaded config, retrying...\n"); 457 continue; 458 } 459 if (status.crcchkg == 1) { 460 dev_err(dev, "Switch reported invalid global CRC on " 461 "the uploaded config, retrying...\n"); 462 continue; 463 } 464 if (status.configs == 0) { 465 dev_err(dev, "Switch reported that configuration is " 466 "invalid, retrying...\n"); 467 continue; 468 } 469 /* Success! */ 470 break; 471 } while (--retries); 472 473 if (!retries) { 474 rc = -EIO; 475 dev_err(dev, "Failed to upload config to device, giving up\n"); 476 goto out; 477 } else if (retries != RETRIES) { 478 dev_info(dev, "Succeeded after %d tried\n", RETRIES - retries); 479 } 480 481 dev_info(dev, "Reset switch and programmed static config\n"); 482 out: 483 kfree(config_buf); 484 return rc; 485 } 486 487 static struct sja1105_regs sja1105et_regs = { 488 .device_id = 0x0, 489 .prod_id = 0x100BC3, 490 .status = 0x1, 491 .port_control = 0x11, 492 .config = 0x020000, 493 .rgu = 0x100440, 494 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808}, 495 .rmii_pll1 = 0x10000A, 496 .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F}, 497 /* UM10944.pdf, Table 86, ACU Register overview */ 498 .rgmii_pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808}, 499 .mac = {0x200, 0x202, 0x204, 0x206, 0x208}, 500 .mac_hl1 = {0x400, 0x410, 0x420, 0x430, 0x440}, 501 .mac_hl2 = {0x600, 0x610, 0x620, 0x630, 0x640}, 502 /* UM10944.pdf, Table 78, CGU Register overview */ 503 .mii_tx_clk = {0x100013, 0x10001A, 0x100021, 0x100028, 0x10002F}, 504 .mii_rx_clk = {0x100014, 0x10001B, 0x100022, 0x100029, 0x100030}, 505 .mii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034}, 506 .mii_ext_rx_clk = {0x100019, 0x100020, 0x100027, 0x10002E, 0x100035}, 507 .rgmii_tx_clk = {0x100016, 0x10001D, 0x100024, 0x10002B, 0x100032}, 508 .rmii_ref_clk = {0x100015, 0x10001C, 0x100023, 0x10002A, 0x100031}, 509 .rmii_ext_tx_clk = {0x100018, 0x10001F, 0x100026, 0x10002D, 0x100034}, 510 }; 511 512 static struct sja1105_regs sja1105pqrs_regs = { 513 .device_id = 0x0, 514 .prod_id = 0x100BC3, 515 .status = 0x1, 516 .port_control = 0x12, 517 .config = 0x020000, 518 .rgu = 0x100440, 519 .pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808}, 520 .rmii_pll1 = 0x10000A, 521 .cgu_idiv = {0x10000B, 0x10000C, 0x10000D, 0x10000E, 0x10000F}, 522 /* UM10944.pdf, Table 86, ACU Register overview */ 523 .rgmii_pad_mii_tx = {0x100800, 0x100802, 0x100804, 0x100806, 0x100808}, 524 .mac = {0x200, 0x202, 0x204, 0x206, 0x208}, 525 .mac_hl1 = {0x400, 0x410, 0x420, 0x430, 0x440}, 526 .mac_hl2 = {0x600, 0x610, 0x620, 0x630, 0x640}, 527 /* UM11040.pdf, Table 114 */ 528 .mii_tx_clk = {0x100013, 0x100019, 0x10001F, 0x100025, 0x10002B}, 529 .mii_rx_clk = {0x100014, 0x10001A, 0x100020, 0x100026, 0x10002C}, 530 .mii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F}, 531 .mii_ext_rx_clk = {0x100018, 0x10001E, 0x100024, 0x10002A, 0x100030}, 532 .rgmii_tx_clk = {0x100016, 0x10001C, 0x100022, 0x100028, 0x10002E}, 533 .rmii_ref_clk = {0x100015, 0x10001B, 0x100021, 0x100027, 0x10002D}, 534 .rmii_ext_tx_clk = {0x100017, 0x10001D, 0x100023, 0x100029, 0x10002F}, 535 .qlevel = {0x604, 0x614, 0x624, 0x634, 0x644}, 536 }; 537 538 struct sja1105_info sja1105e_info = { 539 .device_id = SJA1105E_DEVICE_ID, 540 .part_no = SJA1105ET_PART_NO, 541 .static_ops = sja1105e_table_ops, 542 .dyn_ops = sja1105et_dyn_ops, 543 .reset_cmd = sja1105et_reset_cmd, 544 .regs = &sja1105et_regs, 545 .name = "SJA1105E", 546 }; 547 struct sja1105_info sja1105t_info = { 548 .device_id = SJA1105T_DEVICE_ID, 549 .part_no = SJA1105ET_PART_NO, 550 .static_ops = sja1105t_table_ops, 551 .dyn_ops = sja1105et_dyn_ops, 552 .reset_cmd = sja1105et_reset_cmd, 553 .regs = &sja1105et_regs, 554 .name = "SJA1105T", 555 }; 556 struct sja1105_info sja1105p_info = { 557 .device_id = SJA1105PR_DEVICE_ID, 558 .part_no = SJA1105P_PART_NO, 559 .static_ops = sja1105p_table_ops, 560 .dyn_ops = sja1105pqrs_dyn_ops, 561 .reset_cmd = sja1105pqrs_reset_cmd, 562 .regs = &sja1105pqrs_regs, 563 .name = "SJA1105P", 564 }; 565 struct sja1105_info sja1105q_info = { 566 .device_id = SJA1105QS_DEVICE_ID, 567 .part_no = SJA1105Q_PART_NO, 568 .static_ops = sja1105q_table_ops, 569 .dyn_ops = sja1105pqrs_dyn_ops, 570 .reset_cmd = sja1105pqrs_reset_cmd, 571 .regs = &sja1105pqrs_regs, 572 .name = "SJA1105Q", 573 }; 574 struct sja1105_info sja1105r_info = { 575 .device_id = SJA1105PR_DEVICE_ID, 576 .part_no = SJA1105R_PART_NO, 577 .static_ops = sja1105r_table_ops, 578 .dyn_ops = sja1105pqrs_dyn_ops, 579 .reset_cmd = sja1105pqrs_reset_cmd, 580 .regs = &sja1105pqrs_regs, 581 .name = "SJA1105R", 582 }; 583 struct sja1105_info sja1105s_info = { 584 .device_id = SJA1105QS_DEVICE_ID, 585 .part_no = SJA1105S_PART_NO, 586 .static_ops = sja1105s_table_ops, 587 .dyn_ops = sja1105pqrs_dyn_ops, 588 .regs = &sja1105pqrs_regs, 589 .reset_cmd = sja1105pqrs_reset_cmd, 590 .name = "SJA1105S", 591 }; 592