1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
3  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
4  */
5 
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7 
8 #include <linux/delay.h>
9 #include <linux/module.h>
10 #include <linux/printk.h>
11 #include <linux/spi/spi.h>
12 #include <linux/errno.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/phylink.h>
15 #include <linux/of.h>
16 #include <linux/of_net.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_device.h>
19 #include <linux/pcs/pcs-xpcs.h>
20 #include <linux/netdev_features.h>
21 #include <linux/netdevice.h>
22 #include <linux/if_bridge.h>
23 #include <linux/if_ether.h>
24 #include <linux/dsa/8021q.h>
25 #include "sja1105.h"
26 #include "sja1105_tas.h"
27 
28 #define SJA1105_UNKNOWN_MULTICAST	0x010000000000ull
29 
30 /* Configure the optional reset pin and bring up switch */
31 static int sja1105_hw_reset(struct device *dev, unsigned int pulse_len,
32 			    unsigned int startup_delay)
33 {
34 	struct gpio_desc *gpio;
35 
36 	gpio = gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
37 	if (IS_ERR(gpio))
38 		return PTR_ERR(gpio);
39 
40 	if (!gpio)
41 		return 0;
42 
43 	gpiod_set_value_cansleep(gpio, 1);
44 	/* Wait for minimum reset pulse length */
45 	msleep(pulse_len);
46 	gpiod_set_value_cansleep(gpio, 0);
47 	/* Wait until chip is ready after reset */
48 	msleep(startup_delay);
49 
50 	gpiod_put(gpio);
51 
52 	return 0;
53 }
54 
55 static void
56 sja1105_port_allow_traffic(struct sja1105_l2_forwarding_entry *l2_fwd,
57 			   int from, int to, bool allow)
58 {
59 	if (allow)
60 		l2_fwd[from].reach_port |= BIT(to);
61 	else
62 		l2_fwd[from].reach_port &= ~BIT(to);
63 }
64 
65 static bool sja1105_can_forward(struct sja1105_l2_forwarding_entry *l2_fwd,
66 				int from, int to)
67 {
68 	return !!(l2_fwd[from].reach_port & BIT(to));
69 }
70 
71 static int sja1105_is_vlan_configured(struct sja1105_private *priv, u16 vid)
72 {
73 	struct sja1105_vlan_lookup_entry *vlan;
74 	int count, i;
75 
76 	vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
77 	count = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entry_count;
78 
79 	for (i = 0; i < count; i++)
80 		if (vlan[i].vlanid == vid)
81 			return i;
82 
83 	/* Return an invalid entry index if not found */
84 	return -1;
85 }
86 
87 static int sja1105_drop_untagged(struct dsa_switch *ds, int port, bool drop)
88 {
89 	struct sja1105_private *priv = ds->priv;
90 	struct sja1105_mac_config_entry *mac;
91 
92 	mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
93 
94 	if (mac[port].drpuntag == drop)
95 		return 0;
96 
97 	mac[port].drpuntag = drop;
98 
99 	return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
100 					    &mac[port], true);
101 }
102 
103 static int sja1105_pvid_apply(struct sja1105_private *priv, int port, u16 pvid)
104 {
105 	struct sja1105_mac_config_entry *mac;
106 
107 	mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
108 
109 	if (mac[port].vlanid == pvid)
110 		return 0;
111 
112 	mac[port].vlanid = pvid;
113 
114 	return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
115 					    &mac[port], true);
116 }
117 
118 static int sja1105_commit_pvid(struct dsa_switch *ds, int port)
119 {
120 	struct dsa_port *dp = dsa_to_port(ds, port);
121 	struct net_device *br = dsa_port_bridge_dev_get(dp);
122 	struct sja1105_private *priv = ds->priv;
123 	struct sja1105_vlan_lookup_entry *vlan;
124 	bool drop_untagged = false;
125 	int match, rc;
126 	u16 pvid;
127 
128 	if (br && br_vlan_enabled(br))
129 		pvid = priv->bridge_pvid[port];
130 	else
131 		pvid = priv->tag_8021q_pvid[port];
132 
133 	rc = sja1105_pvid_apply(priv, port, pvid);
134 	if (rc)
135 		return rc;
136 
137 	/* Only force dropping of untagged packets when the port is under a
138 	 * VLAN-aware bridge. When the tag_8021q pvid is used, we are
139 	 * deliberately removing the RX VLAN from the port's VMEMB_PORT list,
140 	 * to prevent DSA tag spoofing from the link partner. Untagged packets
141 	 * are the only ones that should be received with tag_8021q, so
142 	 * definitely don't drop them.
143 	 */
144 	if (pvid == priv->bridge_pvid[port]) {
145 		vlan = priv->static_config.tables[BLK_IDX_VLAN_LOOKUP].entries;
146 
147 		match = sja1105_is_vlan_configured(priv, pvid);
148 
149 		if (match < 0 || !(vlan[match].vmemb_port & BIT(port)))
150 			drop_untagged = true;
151 	}
152 
153 	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
154 		drop_untagged = true;
155 
156 	return sja1105_drop_untagged(ds, port, drop_untagged);
157 }
158 
159 static int sja1105_init_mac_settings(struct sja1105_private *priv)
160 {
161 	struct sja1105_mac_config_entry default_mac = {
162 		/* Enable all 8 priority queues on egress.
163 		 * Every queue i holds top[i] - base[i] frames.
164 		 * Sum of top[i] - base[i] is 511 (max hardware limit).
165 		 */
166 		.top  = {0x3F, 0x7F, 0xBF, 0xFF, 0x13F, 0x17F, 0x1BF, 0x1FF},
167 		.base = {0x0, 0x40, 0x80, 0xC0, 0x100, 0x140, 0x180, 0x1C0},
168 		.enabled = {true, true, true, true, true, true, true, true},
169 		/* Keep standard IFG of 12 bytes on egress. */
170 		.ifg = 0,
171 		/* Always put the MAC speed in automatic mode, where it can be
172 		 * adjusted at runtime by PHYLINK.
173 		 */
174 		.speed = priv->info->port_speed[SJA1105_SPEED_AUTO],
175 		/* No static correction for 1-step 1588 events */
176 		.tp_delin = 0,
177 		.tp_delout = 0,
178 		/* Disable aging for critical TTEthernet traffic */
179 		.maxage = 0xFF,
180 		/* Internal VLAN (pvid) to apply to untagged ingress */
181 		.vlanprio = 0,
182 		.vlanid = 1,
183 		.ing_mirr = false,
184 		.egr_mirr = false,
185 		/* Don't drop traffic with other EtherType than ETH_P_IP */
186 		.drpnona664 = false,
187 		/* Don't drop double-tagged traffic */
188 		.drpdtag = false,
189 		/* Don't drop untagged traffic */
190 		.drpuntag = false,
191 		/* Don't retag 802.1p (VID 0) traffic with the pvid */
192 		.retag = false,
193 		/* Disable learning and I/O on user ports by default -
194 		 * STP will enable it.
195 		 */
196 		.dyn_learn = false,
197 		.egress = false,
198 		.ingress = false,
199 	};
200 	struct sja1105_mac_config_entry *mac;
201 	struct dsa_switch *ds = priv->ds;
202 	struct sja1105_table *table;
203 	struct dsa_port *dp;
204 
205 	table = &priv->static_config.tables[BLK_IDX_MAC_CONFIG];
206 
207 	/* Discard previous MAC Configuration Table */
208 	if (table->entry_count) {
209 		kfree(table->entries);
210 		table->entry_count = 0;
211 	}
212 
213 	table->entries = kcalloc(table->ops->max_entry_count,
214 				 table->ops->unpacked_entry_size, GFP_KERNEL);
215 	if (!table->entries)
216 		return -ENOMEM;
217 
218 	table->entry_count = table->ops->max_entry_count;
219 
220 	mac = table->entries;
221 
222 	list_for_each_entry(dp, &ds->dst->ports, list) {
223 		if (dp->ds != ds)
224 			continue;
225 
226 		mac[dp->index] = default_mac;
227 
228 		/* Let sja1105_bridge_stp_state_set() keep address learning
229 		 * enabled for the DSA ports. CPU ports use software-assisted
230 		 * learning to ensure that only FDB entries belonging to the
231 		 * bridge are learned, and that they are learned towards all
232 		 * CPU ports in a cross-chip topology if multiple CPU ports
233 		 * exist.
234 		 */
235 		if (dsa_port_is_dsa(dp))
236 			dp->learning = true;
237 
238 		/* Disallow untagged packets from being received on the
239 		 * CPU and DSA ports.
240 		 */
241 		if (dsa_port_is_cpu(dp) || dsa_port_is_dsa(dp))
242 			mac[dp->index].drpuntag = true;
243 	}
244 
245 	return 0;
246 }
247 
248 static int sja1105_init_mii_settings(struct sja1105_private *priv)
249 {
250 	struct device *dev = &priv->spidev->dev;
251 	struct sja1105_xmii_params_entry *mii;
252 	struct dsa_switch *ds = priv->ds;
253 	struct sja1105_table *table;
254 	int i;
255 
256 	table = &priv->static_config.tables[BLK_IDX_XMII_PARAMS];
257 
258 	/* Discard previous xMII Mode Parameters Table */
259 	if (table->entry_count) {
260 		kfree(table->entries);
261 		table->entry_count = 0;
262 	}
263 
264 	table->entries = kcalloc(table->ops->max_entry_count,
265 				 table->ops->unpacked_entry_size, GFP_KERNEL);
266 	if (!table->entries)
267 		return -ENOMEM;
268 
269 	/* Override table based on PHYLINK DT bindings */
270 	table->entry_count = table->ops->max_entry_count;
271 
272 	mii = table->entries;
273 
274 	for (i = 0; i < ds->num_ports; i++) {
275 		sja1105_mii_role_t role = XMII_MAC;
276 
277 		if (dsa_is_unused_port(priv->ds, i))
278 			continue;
279 
280 		switch (priv->phy_mode[i]) {
281 		case PHY_INTERFACE_MODE_INTERNAL:
282 			if (priv->info->internal_phy[i] == SJA1105_NO_PHY)
283 				goto unsupported;
284 
285 			mii->xmii_mode[i] = XMII_MODE_MII;
286 			if (priv->info->internal_phy[i] == SJA1105_PHY_BASE_TX)
287 				mii->special[i] = true;
288 
289 			break;
290 		case PHY_INTERFACE_MODE_REVMII:
291 			role = XMII_PHY;
292 			fallthrough;
293 		case PHY_INTERFACE_MODE_MII:
294 			if (!priv->info->supports_mii[i])
295 				goto unsupported;
296 
297 			mii->xmii_mode[i] = XMII_MODE_MII;
298 			break;
299 		case PHY_INTERFACE_MODE_REVRMII:
300 			role = XMII_PHY;
301 			fallthrough;
302 		case PHY_INTERFACE_MODE_RMII:
303 			if (!priv->info->supports_rmii[i])
304 				goto unsupported;
305 
306 			mii->xmii_mode[i] = XMII_MODE_RMII;
307 			break;
308 		case PHY_INTERFACE_MODE_RGMII:
309 		case PHY_INTERFACE_MODE_RGMII_ID:
310 		case PHY_INTERFACE_MODE_RGMII_RXID:
311 		case PHY_INTERFACE_MODE_RGMII_TXID:
312 			if (!priv->info->supports_rgmii[i])
313 				goto unsupported;
314 
315 			mii->xmii_mode[i] = XMII_MODE_RGMII;
316 			break;
317 		case PHY_INTERFACE_MODE_SGMII:
318 			if (!priv->info->supports_sgmii[i])
319 				goto unsupported;
320 
321 			mii->xmii_mode[i] = XMII_MODE_SGMII;
322 			mii->special[i] = true;
323 			break;
324 		case PHY_INTERFACE_MODE_2500BASEX:
325 			if (!priv->info->supports_2500basex[i])
326 				goto unsupported;
327 
328 			mii->xmii_mode[i] = XMII_MODE_SGMII;
329 			mii->special[i] = true;
330 			break;
331 unsupported:
332 		default:
333 			dev_err(dev, "Unsupported PHY mode %s on port %d!\n",
334 				phy_modes(priv->phy_mode[i]), i);
335 			return -EINVAL;
336 		}
337 
338 		mii->phy_mac[i] = role;
339 	}
340 	return 0;
341 }
342 
343 static int sja1105_init_static_fdb(struct sja1105_private *priv)
344 {
345 	struct sja1105_l2_lookup_entry *l2_lookup;
346 	struct sja1105_table *table;
347 	int port;
348 
349 	table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
350 
351 	/* We only populate the FDB table through dynamic L2 Address Lookup
352 	 * entries, except for a special entry at the end which is a catch-all
353 	 * for unknown multicast and will be used to control flooding domain.
354 	 */
355 	if (table->entry_count) {
356 		kfree(table->entries);
357 		table->entry_count = 0;
358 	}
359 
360 	if (!priv->info->can_limit_mcast_flood)
361 		return 0;
362 
363 	table->entries = kcalloc(1, table->ops->unpacked_entry_size,
364 				 GFP_KERNEL);
365 	if (!table->entries)
366 		return -ENOMEM;
367 
368 	table->entry_count = 1;
369 	l2_lookup = table->entries;
370 
371 	/* All L2 multicast addresses have an odd first octet */
372 	l2_lookup[0].macaddr = SJA1105_UNKNOWN_MULTICAST;
373 	l2_lookup[0].mask_macaddr = SJA1105_UNKNOWN_MULTICAST;
374 	l2_lookup[0].lockeds = true;
375 	l2_lookup[0].index = SJA1105_MAX_L2_LOOKUP_COUNT - 1;
376 
377 	/* Flood multicast to every port by default */
378 	for (port = 0; port < priv->ds->num_ports; port++)
379 		if (!dsa_is_unused_port(priv->ds, port))
380 			l2_lookup[0].destports |= BIT(port);
381 
382 	return 0;
383 }
384 
385 static int sja1105_init_l2_lookup_params(struct sja1105_private *priv)
386 {
387 	struct sja1105_l2_lookup_params_entry default_l2_lookup_params = {
388 		/* Learned FDB entries are forgotten after 300 seconds */
389 		.maxage = SJA1105_AGEING_TIME_MS(300000),
390 		/* All entries within a FDB bin are available for learning */
391 		.dyn_tbsz = SJA1105ET_FDB_BIN_SIZE,
392 		/* And the P/Q/R/S equivalent setting: */
393 		.start_dynspc = 0,
394 		/* 2^8 + 2^5 + 2^3 + 2^2 + 2^1 + 1 in Koopman notation */
395 		.poly = 0x97,
396 		/* Always use Independent VLAN Learning (IVL) */
397 		.shared_learn = false,
398 		/* Don't discard management traffic based on ENFPORT -
399 		 * we don't perform SMAC port enforcement anyway, so
400 		 * what we are setting here doesn't matter.
401 		 */
402 		.no_enf_hostprt = false,
403 		/* Don't learn SMAC for mac_fltres1 and mac_fltres0.
404 		 * Maybe correlate with no_linklocal_learn from bridge driver?
405 		 */
406 		.no_mgmt_learn = true,
407 		/* P/Q/R/S only */
408 		.use_static = true,
409 		/* Dynamically learned FDB entries can overwrite other (older)
410 		 * dynamic FDB entries
411 		 */
412 		.owr_dyn = true,
413 		.drpnolearn = true,
414 	};
415 	struct dsa_switch *ds = priv->ds;
416 	int port, num_used_ports = 0;
417 	struct sja1105_table *table;
418 	u64 max_fdb_entries;
419 
420 	for (port = 0; port < ds->num_ports; port++)
421 		if (!dsa_is_unused_port(ds, port))
422 			num_used_ports++;
423 
424 	max_fdb_entries = SJA1105_MAX_L2_LOOKUP_COUNT / num_used_ports;
425 
426 	for (port = 0; port < ds->num_ports; port++) {
427 		if (dsa_is_unused_port(ds, port))
428 			continue;
429 
430 		default_l2_lookup_params.maxaddrp[port] = max_fdb_entries;
431 	}
432 
433 	table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
434 
435 	if (table->entry_count) {
436 		kfree(table->entries);
437 		table->entry_count = 0;
438 	}
439 
440 	table->entries = kcalloc(table->ops->max_entry_count,
441 				 table->ops->unpacked_entry_size, GFP_KERNEL);
442 	if (!table->entries)
443 		return -ENOMEM;
444 
445 	table->entry_count = table->ops->max_entry_count;
446 
447 	/* This table only has a single entry */
448 	((struct sja1105_l2_lookup_params_entry *)table->entries)[0] =
449 				default_l2_lookup_params;
450 
451 	return 0;
452 }
453 
454 /* Set up a default VLAN for untagged traffic injected from the CPU
455  * using management routes (e.g. STP, PTP) as opposed to tag_8021q.
456  * All DT-defined ports are members of this VLAN, and there are no
457  * restrictions on forwarding (since the CPU selects the destination).
458  * Frames from this VLAN will always be transmitted as untagged, and
459  * neither the bridge nor the 8021q module cannot create this VLAN ID.
460  */
461 static int sja1105_init_static_vlan(struct sja1105_private *priv)
462 {
463 	struct sja1105_table *table;
464 	struct sja1105_vlan_lookup_entry pvid = {
465 		.type_entry = SJA1110_VLAN_D_TAG,
466 		.ving_mirr = 0,
467 		.vegr_mirr = 0,
468 		.vmemb_port = 0,
469 		.vlan_bc = 0,
470 		.tag_port = 0,
471 		.vlanid = SJA1105_DEFAULT_VLAN,
472 	};
473 	struct dsa_switch *ds = priv->ds;
474 	int port;
475 
476 	table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
477 
478 	if (table->entry_count) {
479 		kfree(table->entries);
480 		table->entry_count = 0;
481 	}
482 
483 	table->entries = kzalloc(table->ops->unpacked_entry_size,
484 				 GFP_KERNEL);
485 	if (!table->entries)
486 		return -ENOMEM;
487 
488 	table->entry_count = 1;
489 
490 	for (port = 0; port < ds->num_ports; port++) {
491 		if (dsa_is_unused_port(ds, port))
492 			continue;
493 
494 		pvid.vmemb_port |= BIT(port);
495 		pvid.vlan_bc |= BIT(port);
496 		pvid.tag_port &= ~BIT(port);
497 
498 		if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
499 			priv->tag_8021q_pvid[port] = SJA1105_DEFAULT_VLAN;
500 			priv->bridge_pvid[port] = SJA1105_DEFAULT_VLAN;
501 		}
502 	}
503 
504 	((struct sja1105_vlan_lookup_entry *)table->entries)[0] = pvid;
505 	return 0;
506 }
507 
508 static int sja1105_init_l2_forwarding(struct sja1105_private *priv)
509 {
510 	struct sja1105_l2_forwarding_entry *l2fwd;
511 	struct dsa_switch *ds = priv->ds;
512 	struct dsa_switch_tree *dst;
513 	struct sja1105_table *table;
514 	struct dsa_link *dl;
515 	int port, tc;
516 	int from, to;
517 
518 	table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING];
519 
520 	if (table->entry_count) {
521 		kfree(table->entries);
522 		table->entry_count = 0;
523 	}
524 
525 	table->entries = kcalloc(table->ops->max_entry_count,
526 				 table->ops->unpacked_entry_size, GFP_KERNEL);
527 	if (!table->entries)
528 		return -ENOMEM;
529 
530 	table->entry_count = table->ops->max_entry_count;
531 
532 	l2fwd = table->entries;
533 
534 	/* First 5 entries in the L2 Forwarding Table define the forwarding
535 	 * rules and the VLAN PCP to ingress queue mapping.
536 	 * Set up the ingress queue mapping first.
537 	 */
538 	for (port = 0; port < ds->num_ports; port++) {
539 		if (dsa_is_unused_port(ds, port))
540 			continue;
541 
542 		for (tc = 0; tc < SJA1105_NUM_TC; tc++)
543 			l2fwd[port].vlan_pmap[tc] = tc;
544 	}
545 
546 	/* Then manage the forwarding domain for user ports. These can forward
547 	 * only to the always-on domain (CPU port and DSA links)
548 	 */
549 	for (from = 0; from < ds->num_ports; from++) {
550 		if (!dsa_is_user_port(ds, from))
551 			continue;
552 
553 		for (to = 0; to < ds->num_ports; to++) {
554 			if (!dsa_is_cpu_port(ds, to) &&
555 			    !dsa_is_dsa_port(ds, to))
556 				continue;
557 
558 			l2fwd[from].bc_domain |= BIT(to);
559 			l2fwd[from].fl_domain |= BIT(to);
560 
561 			sja1105_port_allow_traffic(l2fwd, from, to, true);
562 		}
563 	}
564 
565 	/* Then manage the forwarding domain for DSA links and CPU ports (the
566 	 * always-on domain). These can send packets to any enabled port except
567 	 * themselves.
568 	 */
569 	for (from = 0; from < ds->num_ports; from++) {
570 		if (!dsa_is_cpu_port(ds, from) && !dsa_is_dsa_port(ds, from))
571 			continue;
572 
573 		for (to = 0; to < ds->num_ports; to++) {
574 			if (dsa_is_unused_port(ds, to))
575 				continue;
576 
577 			if (from == to)
578 				continue;
579 
580 			l2fwd[from].bc_domain |= BIT(to);
581 			l2fwd[from].fl_domain |= BIT(to);
582 
583 			sja1105_port_allow_traffic(l2fwd, from, to, true);
584 		}
585 	}
586 
587 	/* In odd topologies ("H" connections where there is a DSA link to
588 	 * another switch which also has its own CPU port), TX packets can loop
589 	 * back into the system (they are flooded from CPU port 1 to the DSA
590 	 * link, and from there to CPU port 2). Prevent this from happening by
591 	 * cutting RX from DSA links towards our CPU port, if the remote switch
592 	 * has its own CPU port and therefore doesn't need ours for network
593 	 * stack termination.
594 	 */
595 	dst = ds->dst;
596 
597 	list_for_each_entry(dl, &dst->rtable, list) {
598 		if (dl->dp->ds != ds || dl->link_dp->cpu_dp == dl->dp->cpu_dp)
599 			continue;
600 
601 		from = dl->dp->index;
602 		to = dsa_upstream_port(ds, from);
603 
604 		dev_warn(ds->dev,
605 			 "H topology detected, cutting RX from DSA link %d to CPU port %d to prevent TX packet loops\n",
606 			 from, to);
607 
608 		sja1105_port_allow_traffic(l2fwd, from, to, false);
609 
610 		l2fwd[from].bc_domain &= ~BIT(to);
611 		l2fwd[from].fl_domain &= ~BIT(to);
612 	}
613 
614 	/* Finally, manage the egress flooding domain. All ports start up with
615 	 * flooding enabled, including the CPU port and DSA links.
616 	 */
617 	for (port = 0; port < ds->num_ports; port++) {
618 		if (dsa_is_unused_port(ds, port))
619 			continue;
620 
621 		priv->ucast_egress_floods |= BIT(port);
622 		priv->bcast_egress_floods |= BIT(port);
623 	}
624 
625 	/* Next 8 entries define VLAN PCP mapping from ingress to egress.
626 	 * Create a one-to-one mapping.
627 	 */
628 	for (tc = 0; tc < SJA1105_NUM_TC; tc++) {
629 		for (port = 0; port < ds->num_ports; port++) {
630 			if (dsa_is_unused_port(ds, port))
631 				continue;
632 
633 			l2fwd[ds->num_ports + tc].vlan_pmap[port] = tc;
634 		}
635 
636 		l2fwd[ds->num_ports + tc].type_egrpcp2outputq = true;
637 	}
638 
639 	return 0;
640 }
641 
642 static int sja1110_init_pcp_remapping(struct sja1105_private *priv)
643 {
644 	struct sja1110_pcp_remapping_entry *pcp_remap;
645 	struct dsa_switch *ds = priv->ds;
646 	struct sja1105_table *table;
647 	int port, tc;
648 
649 	table = &priv->static_config.tables[BLK_IDX_PCP_REMAPPING];
650 
651 	/* Nothing to do for SJA1105 */
652 	if (!table->ops->max_entry_count)
653 		return 0;
654 
655 	if (table->entry_count) {
656 		kfree(table->entries);
657 		table->entry_count = 0;
658 	}
659 
660 	table->entries = kcalloc(table->ops->max_entry_count,
661 				 table->ops->unpacked_entry_size, GFP_KERNEL);
662 	if (!table->entries)
663 		return -ENOMEM;
664 
665 	table->entry_count = table->ops->max_entry_count;
666 
667 	pcp_remap = table->entries;
668 
669 	/* Repeat the configuration done for vlan_pmap */
670 	for (port = 0; port < ds->num_ports; port++) {
671 		if (dsa_is_unused_port(ds, port))
672 			continue;
673 
674 		for (tc = 0; tc < SJA1105_NUM_TC; tc++)
675 			pcp_remap[port].egrpcp[tc] = tc;
676 	}
677 
678 	return 0;
679 }
680 
681 static int sja1105_init_l2_forwarding_params(struct sja1105_private *priv)
682 {
683 	struct sja1105_l2_forwarding_params_entry *l2fwd_params;
684 	struct sja1105_table *table;
685 
686 	table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
687 
688 	if (table->entry_count) {
689 		kfree(table->entries);
690 		table->entry_count = 0;
691 	}
692 
693 	table->entries = kcalloc(table->ops->max_entry_count,
694 				 table->ops->unpacked_entry_size, GFP_KERNEL);
695 	if (!table->entries)
696 		return -ENOMEM;
697 
698 	table->entry_count = table->ops->max_entry_count;
699 
700 	/* This table only has a single entry */
701 	l2fwd_params = table->entries;
702 
703 	/* Disallow dynamic reconfiguration of vlan_pmap */
704 	l2fwd_params->max_dynp = 0;
705 	/* Use a single memory partition for all ingress queues */
706 	l2fwd_params->part_spc[0] = priv->info->max_frame_mem;
707 
708 	return 0;
709 }
710 
711 void sja1105_frame_memory_partitioning(struct sja1105_private *priv)
712 {
713 	struct sja1105_l2_forwarding_params_entry *l2_fwd_params;
714 	struct sja1105_vl_forwarding_params_entry *vl_fwd_params;
715 	struct sja1105_table *table;
716 
717 	table = &priv->static_config.tables[BLK_IDX_L2_FORWARDING_PARAMS];
718 	l2_fwd_params = table->entries;
719 	l2_fwd_params->part_spc[0] = SJA1105_MAX_FRAME_MEMORY;
720 
721 	/* If we have any critical-traffic virtual links, we need to reserve
722 	 * some frame buffer memory for them. At the moment, hardcode the value
723 	 * at 100 blocks of 128 bytes of memory each. This leaves 829 blocks
724 	 * remaining for best-effort traffic. TODO: figure out a more flexible
725 	 * way to perform the frame buffer partitioning.
726 	 */
727 	if (!priv->static_config.tables[BLK_IDX_VL_FORWARDING].entry_count)
728 		return;
729 
730 	table = &priv->static_config.tables[BLK_IDX_VL_FORWARDING_PARAMS];
731 	vl_fwd_params = table->entries;
732 
733 	l2_fwd_params->part_spc[0] -= SJA1105_VL_FRAME_MEMORY;
734 	vl_fwd_params->partspc[0] = SJA1105_VL_FRAME_MEMORY;
735 }
736 
737 /* SJA1110 TDMACONFIGIDX values:
738  *
739  *      | 100 Mbps ports |  1Gbps ports  | 2.5Gbps ports | Disabled ports
740  * -----+----------------+---------------+---------------+---------------
741  *   0  |   0, [5:10]    |     [1:2]     |     [3:4]     |     retag
742  *   1  |0, [5:10], retag|     [1:2]     |     [3:4]     |       -
743  *   2  |   0, [5:10]    |  [1:3], retag |       4       |       -
744  *   3  |   0, [5:10]    |[1:2], 4, retag|       3       |       -
745  *   4  |  0, 2, [5:10]  |    1, retag   |     [3:4]     |       -
746  *   5  |  0, 1, [5:10]  |    2, retag   |     [3:4]     |       -
747  *  14  |   0, [5:10]    | [1:4], retag  |       -       |       -
748  *  15  |     [5:10]     | [0:4], retag  |       -       |       -
749  */
750 static void sja1110_select_tdmaconfigidx(struct sja1105_private *priv)
751 {
752 	struct sja1105_general_params_entry *general_params;
753 	struct sja1105_table *table;
754 	bool port_1_is_base_tx;
755 	bool port_3_is_2500;
756 	bool port_4_is_2500;
757 	u64 tdmaconfigidx;
758 
759 	if (priv->info->device_id != SJA1110_DEVICE_ID)
760 		return;
761 
762 	table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
763 	general_params = table->entries;
764 
765 	/* All the settings below are "as opposed to SGMII", which is the
766 	 * other pinmuxing option.
767 	 */
768 	port_1_is_base_tx = priv->phy_mode[1] == PHY_INTERFACE_MODE_INTERNAL;
769 	port_3_is_2500 = priv->phy_mode[3] == PHY_INTERFACE_MODE_2500BASEX;
770 	port_4_is_2500 = priv->phy_mode[4] == PHY_INTERFACE_MODE_2500BASEX;
771 
772 	if (port_1_is_base_tx)
773 		/* Retagging port will operate at 1 Gbps */
774 		tdmaconfigidx = 5;
775 	else if (port_3_is_2500 && port_4_is_2500)
776 		/* Retagging port will operate at 100 Mbps */
777 		tdmaconfigidx = 1;
778 	else if (port_3_is_2500)
779 		/* Retagging port will operate at 1 Gbps */
780 		tdmaconfigidx = 3;
781 	else if (port_4_is_2500)
782 		/* Retagging port will operate at 1 Gbps */
783 		tdmaconfigidx = 2;
784 	else
785 		/* Retagging port will operate at 1 Gbps */
786 		tdmaconfigidx = 14;
787 
788 	general_params->tdmaconfigidx = tdmaconfigidx;
789 }
790 
791 static int sja1105_init_topology(struct sja1105_private *priv,
792 				 struct sja1105_general_params_entry *general_params)
793 {
794 	struct dsa_switch *ds = priv->ds;
795 	int port;
796 
797 	/* The host port is the destination for traffic matching mac_fltres1
798 	 * and mac_fltres0 on all ports except itself. Default to an invalid
799 	 * value.
800 	 */
801 	general_params->host_port = ds->num_ports;
802 
803 	/* Link-local traffic received on casc_port will be forwarded
804 	 * to host_port without embedding the source port and device ID
805 	 * info in the destination MAC address, and no RX timestamps will be
806 	 * taken either (presumably because it is a cascaded port and a
807 	 * downstream SJA switch already did that).
808 	 * To disable the feature, we need to do different things depending on
809 	 * switch generation. On SJA1105 we need to set an invalid port, while
810 	 * on SJA1110 which support multiple cascaded ports, this field is a
811 	 * bitmask so it must be left zero.
812 	 */
813 	if (!priv->info->multiple_cascade_ports)
814 		general_params->casc_port = ds->num_ports;
815 
816 	for (port = 0; port < ds->num_ports; port++) {
817 		bool is_upstream = dsa_is_upstream_port(ds, port);
818 		bool is_dsa_link = dsa_is_dsa_port(ds, port);
819 
820 		/* Upstream ports can be dedicated CPU ports or
821 		 * upstream-facing DSA links
822 		 */
823 		if (is_upstream) {
824 			if (general_params->host_port == ds->num_ports) {
825 				general_params->host_port = port;
826 			} else {
827 				dev_err(ds->dev,
828 					"Port %llu is already a host port, configuring %d as one too is not supported\n",
829 					general_params->host_port, port);
830 				return -EINVAL;
831 			}
832 		}
833 
834 		/* Cascade ports are downstream-facing DSA links */
835 		if (is_dsa_link && !is_upstream) {
836 			if (priv->info->multiple_cascade_ports) {
837 				general_params->casc_port |= BIT(port);
838 			} else if (general_params->casc_port == ds->num_ports) {
839 				general_params->casc_port = port;
840 			} else {
841 				dev_err(ds->dev,
842 					"Port %llu is already a cascade port, configuring %d as one too is not supported\n",
843 					general_params->casc_port, port);
844 				return -EINVAL;
845 			}
846 		}
847 	}
848 
849 	if (general_params->host_port == ds->num_ports) {
850 		dev_err(ds->dev, "No host port configured\n");
851 		return -EINVAL;
852 	}
853 
854 	return 0;
855 }
856 
857 static int sja1105_init_general_params(struct sja1105_private *priv)
858 {
859 	struct sja1105_general_params_entry default_general_params = {
860 		/* Allow dynamic changing of the mirror port */
861 		.mirr_ptacu = true,
862 		.switchid = priv->ds->index,
863 		/* Priority queue for link-local management frames
864 		 * (both ingress to and egress from CPU - PTP, STP etc)
865 		 */
866 		.hostprio = 7,
867 		.mac_fltres1 = SJA1105_LINKLOCAL_FILTER_A,
868 		.mac_flt1    = SJA1105_LINKLOCAL_FILTER_A_MASK,
869 		.incl_srcpt1 = true,
870 		.send_meta1  = true,
871 		.mac_fltres0 = SJA1105_LINKLOCAL_FILTER_B,
872 		.mac_flt0    = SJA1105_LINKLOCAL_FILTER_B_MASK,
873 		.incl_srcpt0 = true,
874 		.send_meta0  = true,
875 		/* Default to an invalid value */
876 		.mirr_port = priv->ds->num_ports,
877 		/* No TTEthernet */
878 		.vllupformat = SJA1105_VL_FORMAT_PSFP,
879 		.vlmarker = 0,
880 		.vlmask = 0,
881 		/* Only update correctionField for 1-step PTP (L2 transport) */
882 		.ignore2stf = 0,
883 		/* Forcefully disable VLAN filtering by telling
884 		 * the switch that VLAN has a different EtherType.
885 		 */
886 		.tpid = ETH_P_SJA1105,
887 		.tpid2 = ETH_P_SJA1105,
888 		/* Enable the TTEthernet engine on SJA1110 */
889 		.tte_en = true,
890 		/* Set up the EtherType for control packets on SJA1110 */
891 		.header_type = ETH_P_SJA1110,
892 	};
893 	struct sja1105_general_params_entry *general_params;
894 	struct sja1105_table *table;
895 	int rc;
896 
897 	rc = sja1105_init_topology(priv, &default_general_params);
898 	if (rc)
899 		return rc;
900 
901 	table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
902 
903 	if (table->entry_count) {
904 		kfree(table->entries);
905 		table->entry_count = 0;
906 	}
907 
908 	table->entries = kcalloc(table->ops->max_entry_count,
909 				 table->ops->unpacked_entry_size, GFP_KERNEL);
910 	if (!table->entries)
911 		return -ENOMEM;
912 
913 	table->entry_count = table->ops->max_entry_count;
914 
915 	general_params = table->entries;
916 
917 	/* This table only has a single entry */
918 	general_params[0] = default_general_params;
919 
920 	sja1110_select_tdmaconfigidx(priv);
921 
922 	return 0;
923 }
924 
925 static int sja1105_init_avb_params(struct sja1105_private *priv)
926 {
927 	struct sja1105_avb_params_entry *avb;
928 	struct sja1105_table *table;
929 
930 	table = &priv->static_config.tables[BLK_IDX_AVB_PARAMS];
931 
932 	/* Discard previous AVB Parameters Table */
933 	if (table->entry_count) {
934 		kfree(table->entries);
935 		table->entry_count = 0;
936 	}
937 
938 	table->entries = kcalloc(table->ops->max_entry_count,
939 				 table->ops->unpacked_entry_size, GFP_KERNEL);
940 	if (!table->entries)
941 		return -ENOMEM;
942 
943 	table->entry_count = table->ops->max_entry_count;
944 
945 	avb = table->entries;
946 
947 	/* Configure the MAC addresses for meta frames */
948 	avb->destmeta = SJA1105_META_DMAC;
949 	avb->srcmeta  = SJA1105_META_SMAC;
950 	/* On P/Q/R/S, configure the direction of the PTP_CLK pin as input by
951 	 * default. This is because there might be boards with a hardware
952 	 * layout where enabling the pin as output might cause an electrical
953 	 * clash. On E/T the pin is always an output, which the board designers
954 	 * probably already knew, so even if there are going to be electrical
955 	 * issues, there's nothing we can do.
956 	 */
957 	avb->cas_master = false;
958 
959 	return 0;
960 }
961 
962 /* The L2 policing table is 2-stage. The table is looked up for each frame
963  * according to the ingress port, whether it was broadcast or not, and the
964  * classified traffic class (given by VLAN PCP). This portion of the lookup is
965  * fixed, and gives access to the SHARINDX, an indirection register pointing
966  * within the policing table itself, which is used to resolve the policer that
967  * will be used for this frame.
968  *
969  *  Stage 1                              Stage 2
970  * +------------+--------+              +---------------------------------+
971  * |Port 0 TC 0 |SHARINDX|              | Policer 0: Rate, Burst, MTU     |
972  * +------------+--------+              +---------------------------------+
973  * |Port 0 TC 1 |SHARINDX|              | Policer 1: Rate, Burst, MTU     |
974  * +------------+--------+              +---------------------------------+
975  *    ...                               | Policer 2: Rate, Burst, MTU     |
976  * +------------+--------+              +---------------------------------+
977  * |Port 0 TC 7 |SHARINDX|              | Policer 3: Rate, Burst, MTU     |
978  * +------------+--------+              +---------------------------------+
979  * |Port 1 TC 0 |SHARINDX|              | Policer 4: Rate, Burst, MTU     |
980  * +------------+--------+              +---------------------------------+
981  *    ...                               | Policer 5: Rate, Burst, MTU     |
982  * +------------+--------+              +---------------------------------+
983  * |Port 1 TC 7 |SHARINDX|              | Policer 6: Rate, Burst, MTU     |
984  * +------------+--------+              +---------------------------------+
985  *    ...                               | Policer 7: Rate, Burst, MTU     |
986  * +------------+--------+              +---------------------------------+
987  * |Port 4 TC 7 |SHARINDX|                 ...
988  * +------------+--------+
989  * |Port 0 BCAST|SHARINDX|                 ...
990  * +------------+--------+
991  * |Port 1 BCAST|SHARINDX|                 ...
992  * +------------+--------+
993  *    ...                                  ...
994  * +------------+--------+              +---------------------------------+
995  * |Port 4 BCAST|SHARINDX|              | Policer 44: Rate, Burst, MTU    |
996  * +------------+--------+              +---------------------------------+
997  *
998  * In this driver, we shall use policers 0-4 as statically alocated port
999  * (matchall) policers. So we need to make the SHARINDX for all lookups
1000  * corresponding to this ingress port (8 VLAN PCP lookups and 1 broadcast
1001  * lookup) equal.
1002  * The remaining policers (40) shall be dynamically allocated for flower
1003  * policers, where the key is either vlan_prio or dst_mac ff:ff:ff:ff:ff:ff.
1004  */
1005 #define SJA1105_RATE_MBPS(speed) (((speed) * 64000) / 1000)
1006 
1007 static int sja1105_init_l2_policing(struct sja1105_private *priv)
1008 {
1009 	struct sja1105_l2_policing_entry *policing;
1010 	struct dsa_switch *ds = priv->ds;
1011 	struct sja1105_table *table;
1012 	int port, tc;
1013 
1014 	table = &priv->static_config.tables[BLK_IDX_L2_POLICING];
1015 
1016 	/* Discard previous L2 Policing Table */
1017 	if (table->entry_count) {
1018 		kfree(table->entries);
1019 		table->entry_count = 0;
1020 	}
1021 
1022 	table->entries = kcalloc(table->ops->max_entry_count,
1023 				 table->ops->unpacked_entry_size, GFP_KERNEL);
1024 	if (!table->entries)
1025 		return -ENOMEM;
1026 
1027 	table->entry_count = table->ops->max_entry_count;
1028 
1029 	policing = table->entries;
1030 
1031 	/* Setup shared indices for the matchall policers */
1032 	for (port = 0; port < ds->num_ports; port++) {
1033 		int mcast = (ds->num_ports * (SJA1105_NUM_TC + 1)) + port;
1034 		int bcast = (ds->num_ports * SJA1105_NUM_TC) + port;
1035 
1036 		for (tc = 0; tc < SJA1105_NUM_TC; tc++)
1037 			policing[port * SJA1105_NUM_TC + tc].sharindx = port;
1038 
1039 		policing[bcast].sharindx = port;
1040 		/* Only SJA1110 has multicast policers */
1041 		if (mcast < table->ops->max_entry_count)
1042 			policing[mcast].sharindx = port;
1043 	}
1044 
1045 	/* Setup the matchall policer parameters */
1046 	for (port = 0; port < ds->num_ports; port++) {
1047 		int mtu = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1048 
1049 		if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1050 			mtu += VLAN_HLEN;
1051 
1052 		policing[port].smax = 65535; /* Burst size in bytes */
1053 		policing[port].rate = SJA1105_RATE_MBPS(1000);
1054 		policing[port].maxlen = mtu;
1055 		policing[port].partition = 0;
1056 	}
1057 
1058 	return 0;
1059 }
1060 
1061 static int sja1105_static_config_load(struct sja1105_private *priv)
1062 {
1063 	int rc;
1064 
1065 	sja1105_static_config_free(&priv->static_config);
1066 	rc = sja1105_static_config_init(&priv->static_config,
1067 					priv->info->static_ops,
1068 					priv->info->device_id);
1069 	if (rc)
1070 		return rc;
1071 
1072 	/* Build static configuration */
1073 	rc = sja1105_init_mac_settings(priv);
1074 	if (rc < 0)
1075 		return rc;
1076 	rc = sja1105_init_mii_settings(priv);
1077 	if (rc < 0)
1078 		return rc;
1079 	rc = sja1105_init_static_fdb(priv);
1080 	if (rc < 0)
1081 		return rc;
1082 	rc = sja1105_init_static_vlan(priv);
1083 	if (rc < 0)
1084 		return rc;
1085 	rc = sja1105_init_l2_lookup_params(priv);
1086 	if (rc < 0)
1087 		return rc;
1088 	rc = sja1105_init_l2_forwarding(priv);
1089 	if (rc < 0)
1090 		return rc;
1091 	rc = sja1105_init_l2_forwarding_params(priv);
1092 	if (rc < 0)
1093 		return rc;
1094 	rc = sja1105_init_l2_policing(priv);
1095 	if (rc < 0)
1096 		return rc;
1097 	rc = sja1105_init_general_params(priv);
1098 	if (rc < 0)
1099 		return rc;
1100 	rc = sja1105_init_avb_params(priv);
1101 	if (rc < 0)
1102 		return rc;
1103 	rc = sja1110_init_pcp_remapping(priv);
1104 	if (rc < 0)
1105 		return rc;
1106 
1107 	/* Send initial configuration to hardware via SPI */
1108 	return sja1105_static_config_upload(priv);
1109 }
1110 
1111 /* This is the "new way" for a MAC driver to configure its RGMII delay lines,
1112  * based on the explicit "rx-internal-delay-ps" and "tx-internal-delay-ps"
1113  * properties. It has the advantage of working with fixed links and with PHYs
1114  * that apply RGMII delays too, and the MAC driver needs not perform any
1115  * special checks.
1116  *
1117  * Previously we were acting upon the "phy-mode" property when we were
1118  * operating in fixed-link, basically acting as a PHY, but with a reversed
1119  * interpretation: PHY_INTERFACE_MODE_RGMII_TXID means that the MAC should
1120  * behave as if it is connected to a PHY which has applied RGMII delays in the
1121  * TX direction. So if anything, RX delays should have been added by the MAC,
1122  * but we were adding TX delays.
1123  *
1124  * If the "{rx,tx}-internal-delay-ps" properties are not specified, we fall
1125  * back to the legacy behavior and apply delays on fixed-link ports based on
1126  * the reverse interpretation of the phy-mode. This is a deviation from the
1127  * expected default behavior which is to simply apply no delays. To achieve
1128  * that behavior with the new bindings, it is mandatory to specify
1129  * "{rx,tx}-internal-delay-ps" with a value of 0.
1130  */
1131 static int sja1105_parse_rgmii_delays(struct sja1105_private *priv, int port,
1132 				      struct device_node *port_dn)
1133 {
1134 	phy_interface_t phy_mode = priv->phy_mode[port];
1135 	struct device *dev = &priv->spidev->dev;
1136 	int rx_delay = -1, tx_delay = -1;
1137 
1138 	if (!phy_interface_mode_is_rgmii(phy_mode))
1139 		return 0;
1140 
1141 	of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
1142 	of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
1143 
1144 	if (rx_delay == -1 && tx_delay == -1 && priv->fixed_link[port]) {
1145 		dev_warn(dev,
1146 			 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
1147 			 "please update device tree to specify \"rx-internal-delay-ps\" and "
1148 			 "\"tx-internal-delay-ps\"",
1149 			 port);
1150 
1151 		if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
1152 		    phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1153 			rx_delay = 2000;
1154 
1155 		if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
1156 		    phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
1157 			tx_delay = 2000;
1158 	}
1159 
1160 	if (rx_delay < 0)
1161 		rx_delay = 0;
1162 	if (tx_delay < 0)
1163 		tx_delay = 0;
1164 
1165 	if ((rx_delay || tx_delay) && !priv->info->setup_rgmii_delay) {
1166 		dev_err(dev, "Chip cannot apply RGMII delays\n");
1167 		return -EINVAL;
1168 	}
1169 
1170 	if ((rx_delay && rx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1171 	    (tx_delay && tx_delay < SJA1105_RGMII_DELAY_MIN_PS) ||
1172 	    (rx_delay > SJA1105_RGMII_DELAY_MAX_PS) ||
1173 	    (tx_delay > SJA1105_RGMII_DELAY_MAX_PS)) {
1174 		dev_err(dev,
1175 			"port %d RGMII delay values out of range, must be between %d and %d ps\n",
1176 			port, SJA1105_RGMII_DELAY_MIN_PS, SJA1105_RGMII_DELAY_MAX_PS);
1177 		return -ERANGE;
1178 	}
1179 
1180 	priv->rgmii_rx_delay_ps[port] = rx_delay;
1181 	priv->rgmii_tx_delay_ps[port] = tx_delay;
1182 
1183 	return 0;
1184 }
1185 
1186 static int sja1105_parse_ports_node(struct sja1105_private *priv,
1187 				    struct device_node *ports_node)
1188 {
1189 	struct device *dev = &priv->spidev->dev;
1190 	struct device_node *child;
1191 
1192 	for_each_available_child_of_node(ports_node, child) {
1193 		struct device_node *phy_node;
1194 		phy_interface_t phy_mode;
1195 		u32 index;
1196 		int err;
1197 
1198 		/* Get switch port number from DT */
1199 		if (of_property_read_u32(child, "reg", &index) < 0) {
1200 			dev_err(dev, "Port number not defined in device tree "
1201 				"(property \"reg\")\n");
1202 			of_node_put(child);
1203 			return -ENODEV;
1204 		}
1205 
1206 		/* Get PHY mode from DT */
1207 		err = of_get_phy_mode(child, &phy_mode);
1208 		if (err) {
1209 			dev_err(dev, "Failed to read phy-mode or "
1210 				"phy-interface-type property for port %d\n",
1211 				index);
1212 			of_node_put(child);
1213 			return -ENODEV;
1214 		}
1215 
1216 		phy_node = of_parse_phandle(child, "phy-handle", 0);
1217 		if (!phy_node) {
1218 			if (!of_phy_is_fixed_link(child)) {
1219 				dev_err(dev, "phy-handle or fixed-link "
1220 					"properties missing!\n");
1221 				of_node_put(child);
1222 				return -ENODEV;
1223 			}
1224 			/* phy-handle is missing, but fixed-link isn't.
1225 			 * So it's a fixed link. Default to PHY role.
1226 			 */
1227 			priv->fixed_link[index] = true;
1228 		} else {
1229 			of_node_put(phy_node);
1230 		}
1231 
1232 		priv->phy_mode[index] = phy_mode;
1233 
1234 		err = sja1105_parse_rgmii_delays(priv, index, child);
1235 		if (err) {
1236 			of_node_put(child);
1237 			return err;
1238 		}
1239 	}
1240 
1241 	return 0;
1242 }
1243 
1244 static int sja1105_parse_dt(struct sja1105_private *priv)
1245 {
1246 	struct device *dev = &priv->spidev->dev;
1247 	struct device_node *switch_node = dev->of_node;
1248 	struct device_node *ports_node;
1249 	int rc;
1250 
1251 	ports_node = of_get_child_by_name(switch_node, "ports");
1252 	if (!ports_node)
1253 		ports_node = of_get_child_by_name(switch_node, "ethernet-ports");
1254 	if (!ports_node) {
1255 		dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
1256 		return -ENODEV;
1257 	}
1258 
1259 	rc = sja1105_parse_ports_node(priv, ports_node);
1260 	of_node_put(ports_node);
1261 
1262 	return rc;
1263 }
1264 
1265 /* Convert link speed from SJA1105 to ethtool encoding */
1266 static int sja1105_port_speed_to_ethtool(struct sja1105_private *priv,
1267 					 u64 speed)
1268 {
1269 	if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS])
1270 		return SPEED_10;
1271 	if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS])
1272 		return SPEED_100;
1273 	if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS])
1274 		return SPEED_1000;
1275 	if (speed == priv->info->port_speed[SJA1105_SPEED_2500MBPS])
1276 		return SPEED_2500;
1277 	return SPEED_UNKNOWN;
1278 }
1279 
1280 /* Set link speed in the MAC configuration for a specific port. */
1281 static int sja1105_adjust_port_config(struct sja1105_private *priv, int port,
1282 				      int speed_mbps)
1283 {
1284 	struct sja1105_mac_config_entry *mac;
1285 	struct device *dev = priv->ds->dev;
1286 	u64 speed;
1287 	int rc;
1288 
1289 	/* On P/Q/R/S, one can read from the device via the MAC reconfiguration
1290 	 * tables. On E/T, MAC reconfig tables are not readable, only writable.
1291 	 * We have to *know* what the MAC looks like.  For the sake of keeping
1292 	 * the code common, we'll use the static configuration tables as a
1293 	 * reasonable approximation for both E/T and P/Q/R/S.
1294 	 */
1295 	mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
1296 
1297 	switch (speed_mbps) {
1298 	case SPEED_UNKNOWN:
1299 		/* PHYLINK called sja1105_mac_config() to inform us about
1300 		 * the state->interface, but AN has not completed and the
1301 		 * speed is not yet valid. UM10944.pdf says that setting
1302 		 * SJA1105_SPEED_AUTO at runtime disables the port, so that is
1303 		 * ok for power consumption in case AN will never complete -
1304 		 * otherwise PHYLINK should come back with a new update.
1305 		 */
1306 		speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
1307 		break;
1308 	case SPEED_10:
1309 		speed = priv->info->port_speed[SJA1105_SPEED_10MBPS];
1310 		break;
1311 	case SPEED_100:
1312 		speed = priv->info->port_speed[SJA1105_SPEED_100MBPS];
1313 		break;
1314 	case SPEED_1000:
1315 		speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1316 		break;
1317 	case SPEED_2500:
1318 		speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1319 		break;
1320 	default:
1321 		dev_err(dev, "Invalid speed %iMbps\n", speed_mbps);
1322 		return -EINVAL;
1323 	}
1324 
1325 	/* Overwrite SJA1105_SPEED_AUTO from the static MAC configuration
1326 	 * table, since this will be used for the clocking setup, and we no
1327 	 * longer need to store it in the static config (already told hardware
1328 	 * we want auto during upload phase).
1329 	 * Actually for the SGMII port, the MAC is fixed at 1 Gbps and
1330 	 * we need to configure the PCS only (if even that).
1331 	 */
1332 	if (priv->phy_mode[port] == PHY_INTERFACE_MODE_SGMII)
1333 		mac[port].speed = priv->info->port_speed[SJA1105_SPEED_1000MBPS];
1334 	else if (priv->phy_mode[port] == PHY_INTERFACE_MODE_2500BASEX)
1335 		mac[port].speed = priv->info->port_speed[SJA1105_SPEED_2500MBPS];
1336 	else
1337 		mac[port].speed = speed;
1338 
1339 	/* Write to the dynamic reconfiguration tables */
1340 	rc = sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
1341 					  &mac[port], true);
1342 	if (rc < 0) {
1343 		dev_err(dev, "Failed to write MAC config: %d\n", rc);
1344 		return rc;
1345 	}
1346 
1347 	/* Reconfigure the PLLs for the RGMII interfaces (required 125 MHz at
1348 	 * gigabit, 25 MHz at 100 Mbps and 2.5 MHz at 10 Mbps). For MII and
1349 	 * RMII no change of the clock setup is required. Actually, changing
1350 	 * the clock setup does interrupt the clock signal for a certain time
1351 	 * which causes trouble for all PHYs relying on this signal.
1352 	 */
1353 	if (!phy_interface_mode_is_rgmii(priv->phy_mode[port]))
1354 		return 0;
1355 
1356 	return sja1105_clocking_setup_port(priv, port);
1357 }
1358 
1359 static struct phylink_pcs *
1360 sja1105_mac_select_pcs(struct dsa_switch *ds, int port, phy_interface_t iface)
1361 {
1362 	struct sja1105_private *priv = ds->priv;
1363 	struct dw_xpcs *xpcs = priv->xpcs[port];
1364 
1365 	if (xpcs)
1366 		return &xpcs->pcs;
1367 
1368 	return NULL;
1369 }
1370 
1371 static void sja1105_mac_link_down(struct dsa_switch *ds, int port,
1372 				  unsigned int mode,
1373 				  phy_interface_t interface)
1374 {
1375 	sja1105_inhibit_tx(ds->priv, BIT(port), true);
1376 }
1377 
1378 static void sja1105_mac_link_up(struct dsa_switch *ds, int port,
1379 				unsigned int mode,
1380 				phy_interface_t interface,
1381 				struct phy_device *phydev,
1382 				int speed, int duplex,
1383 				bool tx_pause, bool rx_pause)
1384 {
1385 	struct sja1105_private *priv = ds->priv;
1386 
1387 	sja1105_adjust_port_config(priv, port, speed);
1388 
1389 	sja1105_inhibit_tx(priv, BIT(port), false);
1390 }
1391 
1392 static void sja1105_phylink_get_caps(struct dsa_switch *ds, int port,
1393 				     struct phylink_config *config)
1394 {
1395 	struct sja1105_private *priv = ds->priv;
1396 	struct sja1105_xmii_params_entry *mii;
1397 	phy_interface_t phy_mode;
1398 
1399 	/* This driver does not make use of the speed, duplex, pause or the
1400 	 * advertisement in its mac_config, so it is safe to mark this driver
1401 	 * as non-legacy.
1402 	 */
1403 	config->legacy_pre_march2020 = false;
1404 
1405 	phy_mode = priv->phy_mode[port];
1406 	if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
1407 	    phy_mode == PHY_INTERFACE_MODE_2500BASEX) {
1408 		/* Changing the PHY mode on SERDES ports is possible and makes
1409 		 * sense, because that is done through the XPCS. We allow
1410 		 * changes between SGMII and 2500base-X.
1411 		 */
1412 		if (priv->info->supports_sgmii[port])
1413 			__set_bit(PHY_INTERFACE_MODE_SGMII,
1414 				  config->supported_interfaces);
1415 
1416 		if (priv->info->supports_2500basex[port])
1417 			__set_bit(PHY_INTERFACE_MODE_2500BASEX,
1418 				  config->supported_interfaces);
1419 	} else {
1420 		/* The SJA1105 MAC programming model is through the static
1421 		 * config (the xMII Mode table cannot be dynamically
1422 		 * reconfigured), and we have to program that early.
1423 		 */
1424 		__set_bit(phy_mode, config->supported_interfaces);
1425 	}
1426 
1427 	/* The MAC does not support pause frames, and also doesn't
1428 	 * support half-duplex traffic modes.
1429 	 */
1430 	config->mac_capabilities = MAC_10FD | MAC_100FD;
1431 
1432 	mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries;
1433 	if (mii->xmii_mode[port] == XMII_MODE_RGMII ||
1434 	    mii->xmii_mode[port] == XMII_MODE_SGMII)
1435 		config->mac_capabilities |= MAC_1000FD;
1436 
1437 	if (priv->info->supports_2500basex[port])
1438 		config->mac_capabilities |= MAC_2500FD;
1439 }
1440 
1441 static int
1442 sja1105_find_static_fdb_entry(struct sja1105_private *priv, int port,
1443 			      const struct sja1105_l2_lookup_entry *requested)
1444 {
1445 	struct sja1105_l2_lookup_entry *l2_lookup;
1446 	struct sja1105_table *table;
1447 	int i;
1448 
1449 	table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1450 	l2_lookup = table->entries;
1451 
1452 	for (i = 0; i < table->entry_count; i++)
1453 		if (l2_lookup[i].macaddr == requested->macaddr &&
1454 		    l2_lookup[i].vlanid == requested->vlanid &&
1455 		    l2_lookup[i].destports & BIT(port))
1456 			return i;
1457 
1458 	return -1;
1459 }
1460 
1461 /* We want FDB entries added statically through the bridge command to persist
1462  * across switch resets, which are a common thing during normal SJA1105
1463  * operation. So we have to back them up in the static configuration tables
1464  * and hence apply them on next static config upload... yay!
1465  */
1466 static int
1467 sja1105_static_fdb_change(struct sja1105_private *priv, int port,
1468 			  const struct sja1105_l2_lookup_entry *requested,
1469 			  bool keep)
1470 {
1471 	struct sja1105_l2_lookup_entry *l2_lookup;
1472 	struct sja1105_table *table;
1473 	int rc, match;
1474 
1475 	table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
1476 
1477 	match = sja1105_find_static_fdb_entry(priv, port, requested);
1478 	if (match < 0) {
1479 		/* Can't delete a missing entry. */
1480 		if (!keep)
1481 			return 0;
1482 
1483 		/* No match => new entry */
1484 		rc = sja1105_table_resize(table, table->entry_count + 1);
1485 		if (rc)
1486 			return rc;
1487 
1488 		match = table->entry_count - 1;
1489 	}
1490 
1491 	/* Assign pointer after the resize (it may be new memory) */
1492 	l2_lookup = table->entries;
1493 
1494 	/* We have a match.
1495 	 * If the job was to add this FDB entry, it's already done (mostly
1496 	 * anyway, since the port forwarding mask may have changed, case in
1497 	 * which we update it).
1498 	 * Otherwise we have to delete it.
1499 	 */
1500 	if (keep) {
1501 		l2_lookup[match] = *requested;
1502 		return 0;
1503 	}
1504 
1505 	/* To remove, the strategy is to overwrite the element with
1506 	 * the last one, and then reduce the array size by 1
1507 	 */
1508 	l2_lookup[match] = l2_lookup[table->entry_count - 1];
1509 	return sja1105_table_resize(table, table->entry_count - 1);
1510 }
1511 
1512 /* First-generation switches have a 4-way set associative TCAM that
1513  * holds the FDB entries. An FDB index spans from 0 to 1023 and is comprised of
1514  * a "bin" (grouping of 4 entries) and a "way" (an entry within a bin).
1515  * For the placement of a newly learnt FDB entry, the switch selects the bin
1516  * based on a hash function, and the way within that bin incrementally.
1517  */
1518 static int sja1105et_fdb_index(int bin, int way)
1519 {
1520 	return bin * SJA1105ET_FDB_BIN_SIZE + way;
1521 }
1522 
1523 static int sja1105et_is_fdb_entry_in_bin(struct sja1105_private *priv, int bin,
1524 					 const u8 *addr, u16 vid,
1525 					 struct sja1105_l2_lookup_entry *match,
1526 					 int *last_unused)
1527 {
1528 	int way;
1529 
1530 	for (way = 0; way < SJA1105ET_FDB_BIN_SIZE; way++) {
1531 		struct sja1105_l2_lookup_entry l2_lookup = {0};
1532 		int index = sja1105et_fdb_index(bin, way);
1533 
1534 		/* Skip unused entries, optionally marking them
1535 		 * into the return value
1536 		 */
1537 		if (sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1538 						index, &l2_lookup)) {
1539 			if (last_unused)
1540 				*last_unused = way;
1541 			continue;
1542 		}
1543 
1544 		if (l2_lookup.macaddr == ether_addr_to_u64(addr) &&
1545 		    l2_lookup.vlanid == vid) {
1546 			if (match)
1547 				*match = l2_lookup;
1548 			return way;
1549 		}
1550 	}
1551 	/* Return an invalid entry index if not found */
1552 	return -1;
1553 }
1554 
1555 int sja1105et_fdb_add(struct dsa_switch *ds, int port,
1556 		      const unsigned char *addr, u16 vid)
1557 {
1558 	struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1559 	struct sja1105_private *priv = ds->priv;
1560 	struct device *dev = ds->dev;
1561 	int last_unused = -1;
1562 	int start, end, i;
1563 	int bin, way, rc;
1564 
1565 	bin = sja1105et_fdb_hash(priv, addr, vid);
1566 
1567 	way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1568 					    &l2_lookup, &last_unused);
1569 	if (way >= 0) {
1570 		/* We have an FDB entry. Is our port in the destination
1571 		 * mask? If yes, we need to do nothing. If not, we need
1572 		 * to rewrite the entry by adding this port to it.
1573 		 */
1574 		if ((l2_lookup.destports & BIT(port)) && l2_lookup.lockeds)
1575 			return 0;
1576 		l2_lookup.destports |= BIT(port);
1577 	} else {
1578 		int index = sja1105et_fdb_index(bin, way);
1579 
1580 		/* We don't have an FDB entry. We construct a new one and
1581 		 * try to find a place for it within the FDB table.
1582 		 */
1583 		l2_lookup.macaddr = ether_addr_to_u64(addr);
1584 		l2_lookup.destports = BIT(port);
1585 		l2_lookup.vlanid = vid;
1586 
1587 		if (last_unused >= 0) {
1588 			way = last_unused;
1589 		} else {
1590 			/* Bin is full, need to evict somebody.
1591 			 * Choose victim at random. If you get these messages
1592 			 * often, you may need to consider changing the
1593 			 * distribution function:
1594 			 * static_config[BLK_IDX_L2_LOOKUP_PARAMS].entries->poly
1595 			 */
1596 			get_random_bytes(&way, sizeof(u8));
1597 			way %= SJA1105ET_FDB_BIN_SIZE;
1598 			dev_warn(dev, "Warning, FDB bin %d full while adding entry for %pM. Evicting entry %u.\n",
1599 				 bin, addr, way);
1600 			/* Evict entry */
1601 			sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1602 						     index, NULL, false);
1603 		}
1604 	}
1605 	l2_lookup.lockeds = true;
1606 	l2_lookup.index = sja1105et_fdb_index(bin, way);
1607 
1608 	rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1609 					  l2_lookup.index, &l2_lookup,
1610 					  true);
1611 	if (rc < 0)
1612 		return rc;
1613 
1614 	/* Invalidate a dynamically learned entry if that exists */
1615 	start = sja1105et_fdb_index(bin, 0);
1616 	end = sja1105et_fdb_index(bin, way);
1617 
1618 	for (i = start; i < end; i++) {
1619 		rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1620 						 i, &tmp);
1621 		if (rc == -ENOENT)
1622 			continue;
1623 		if (rc)
1624 			return rc;
1625 
1626 		if (tmp.macaddr != ether_addr_to_u64(addr) || tmp.vlanid != vid)
1627 			continue;
1628 
1629 		rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1630 						  i, NULL, false);
1631 		if (rc)
1632 			return rc;
1633 
1634 		break;
1635 	}
1636 
1637 	return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1638 }
1639 
1640 int sja1105et_fdb_del(struct dsa_switch *ds, int port,
1641 		      const unsigned char *addr, u16 vid)
1642 {
1643 	struct sja1105_l2_lookup_entry l2_lookup = {0};
1644 	struct sja1105_private *priv = ds->priv;
1645 	int index, bin, way, rc;
1646 	bool keep;
1647 
1648 	bin = sja1105et_fdb_hash(priv, addr, vid);
1649 	way = sja1105et_is_fdb_entry_in_bin(priv, bin, addr, vid,
1650 					    &l2_lookup, NULL);
1651 	if (way < 0)
1652 		return 0;
1653 	index = sja1105et_fdb_index(bin, way);
1654 
1655 	/* We have an FDB entry. Is our port in the destination mask? If yes,
1656 	 * we need to remove it. If the resulting port mask becomes empty, we
1657 	 * need to completely evict the FDB entry.
1658 	 * Otherwise we just write it back.
1659 	 */
1660 	l2_lookup.destports &= ~BIT(port);
1661 
1662 	if (l2_lookup.destports)
1663 		keep = true;
1664 	else
1665 		keep = false;
1666 
1667 	rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1668 					  index, &l2_lookup, keep);
1669 	if (rc < 0)
1670 		return rc;
1671 
1672 	return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1673 }
1674 
1675 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
1676 			const unsigned char *addr, u16 vid)
1677 {
1678 	struct sja1105_l2_lookup_entry l2_lookup = {0}, tmp;
1679 	struct sja1105_private *priv = ds->priv;
1680 	int rc, i;
1681 
1682 	/* Search for an existing entry in the FDB table */
1683 	l2_lookup.macaddr = ether_addr_to_u64(addr);
1684 	l2_lookup.vlanid = vid;
1685 	l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1686 	l2_lookup.mask_vlanid = VLAN_VID_MASK;
1687 	l2_lookup.destports = BIT(port);
1688 
1689 	tmp = l2_lookup;
1690 
1691 	rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1692 					 SJA1105_SEARCH, &tmp);
1693 	if (rc == 0 && tmp.index != SJA1105_MAX_L2_LOOKUP_COUNT - 1) {
1694 		/* Found a static entry and this port is already in the entry's
1695 		 * port mask => job done
1696 		 */
1697 		if ((tmp.destports & BIT(port)) && tmp.lockeds)
1698 			return 0;
1699 
1700 		l2_lookup = tmp;
1701 
1702 		/* l2_lookup.index is populated by the switch in case it
1703 		 * found something.
1704 		 */
1705 		l2_lookup.destports |= BIT(port);
1706 		goto skip_finding_an_index;
1707 	}
1708 
1709 	/* Not found, so try to find an unused spot in the FDB.
1710 	 * This is slightly inefficient because the strategy is knock-knock at
1711 	 * every possible position from 0 to 1023.
1712 	 */
1713 	for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1714 		rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1715 						 i, NULL);
1716 		if (rc < 0)
1717 			break;
1718 	}
1719 	if (i == SJA1105_MAX_L2_LOOKUP_COUNT) {
1720 		dev_err(ds->dev, "FDB is full, cannot add entry.\n");
1721 		return -EINVAL;
1722 	}
1723 	l2_lookup.index = i;
1724 
1725 skip_finding_an_index:
1726 	l2_lookup.lockeds = true;
1727 
1728 	rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1729 					  l2_lookup.index, &l2_lookup,
1730 					  true);
1731 	if (rc < 0)
1732 		return rc;
1733 
1734 	/* The switch learns dynamic entries and looks up the FDB left to
1735 	 * right. It is possible that our addition was concurrent with the
1736 	 * dynamic learning of the same address, so now that the static entry
1737 	 * has been installed, we are certain that address learning for this
1738 	 * particular address has been turned off, so the dynamic entry either
1739 	 * is in the FDB at an index smaller than the static one, or isn't (it
1740 	 * can also be at a larger index, but in that case it is inactive
1741 	 * because the static FDB entry will match first, and the dynamic one
1742 	 * will eventually age out). Search for a dynamically learned address
1743 	 * prior to our static one and invalidate it.
1744 	 */
1745 	tmp = l2_lookup;
1746 
1747 	rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1748 					 SJA1105_SEARCH, &tmp);
1749 	if (rc < 0) {
1750 		dev_err(ds->dev,
1751 			"port %d failed to read back entry for %pM vid %d: %pe\n",
1752 			port, addr, vid, ERR_PTR(rc));
1753 		return rc;
1754 	}
1755 
1756 	if (tmp.index < l2_lookup.index) {
1757 		rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1758 						  tmp.index, NULL, false);
1759 		if (rc < 0)
1760 			return rc;
1761 	}
1762 
1763 	return sja1105_static_fdb_change(priv, port, &l2_lookup, true);
1764 }
1765 
1766 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
1767 			const unsigned char *addr, u16 vid)
1768 {
1769 	struct sja1105_l2_lookup_entry l2_lookup = {0};
1770 	struct sja1105_private *priv = ds->priv;
1771 	bool keep;
1772 	int rc;
1773 
1774 	l2_lookup.macaddr = ether_addr_to_u64(addr);
1775 	l2_lookup.vlanid = vid;
1776 	l2_lookup.mask_macaddr = GENMASK_ULL(ETH_ALEN * 8 - 1, 0);
1777 	l2_lookup.mask_vlanid = VLAN_VID_MASK;
1778 	l2_lookup.destports = BIT(port);
1779 
1780 	rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1781 					 SJA1105_SEARCH, &l2_lookup);
1782 	if (rc < 0)
1783 		return 0;
1784 
1785 	l2_lookup.destports &= ~BIT(port);
1786 
1787 	/* Decide whether we remove just this port from the FDB entry,
1788 	 * or if we remove it completely.
1789 	 */
1790 	if (l2_lookup.destports)
1791 		keep = true;
1792 	else
1793 		keep = false;
1794 
1795 	rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
1796 					  l2_lookup.index, &l2_lookup, keep);
1797 	if (rc < 0)
1798 		return rc;
1799 
1800 	return sja1105_static_fdb_change(priv, port, &l2_lookup, keep);
1801 }
1802 
1803 static int sja1105_fdb_add(struct dsa_switch *ds, int port,
1804 			   const unsigned char *addr, u16 vid,
1805 			   struct dsa_db db)
1806 {
1807 	struct sja1105_private *priv = ds->priv;
1808 
1809 	if (!vid) {
1810 		switch (db.type) {
1811 		case DSA_DB_PORT:
1812 			vid = dsa_tag_8021q_standalone_vid(db.dp);
1813 			break;
1814 		case DSA_DB_BRIDGE:
1815 			vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
1816 			break;
1817 		default:
1818 			return -EOPNOTSUPP;
1819 		}
1820 	}
1821 
1822 	return priv->info->fdb_add_cmd(ds, port, addr, vid);
1823 }
1824 
1825 static int sja1105_fdb_del(struct dsa_switch *ds, int port,
1826 			   const unsigned char *addr, u16 vid,
1827 			   struct dsa_db db)
1828 {
1829 	struct sja1105_private *priv = ds->priv;
1830 
1831 	if (!vid) {
1832 		switch (db.type) {
1833 		case DSA_DB_PORT:
1834 			vid = dsa_tag_8021q_standalone_vid(db.dp);
1835 			break;
1836 		case DSA_DB_BRIDGE:
1837 			vid = dsa_tag_8021q_bridge_vid(db.bridge.num);
1838 			break;
1839 		default:
1840 			return -EOPNOTSUPP;
1841 		}
1842 	}
1843 
1844 	return priv->info->fdb_del_cmd(ds, port, addr, vid);
1845 }
1846 
1847 static int sja1105_fdb_dump(struct dsa_switch *ds, int port,
1848 			    dsa_fdb_dump_cb_t *cb, void *data)
1849 {
1850 	struct sja1105_private *priv = ds->priv;
1851 	struct device *dev = ds->dev;
1852 	int i;
1853 
1854 	for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1855 		struct sja1105_l2_lookup_entry l2_lookup = {0};
1856 		u8 macaddr[ETH_ALEN];
1857 		int rc;
1858 
1859 		rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1860 						 i, &l2_lookup);
1861 		/* No fdb entry at i, not an issue */
1862 		if (rc == -ENOENT)
1863 			continue;
1864 		if (rc) {
1865 			dev_err(dev, "Failed to dump FDB: %d\n", rc);
1866 			return rc;
1867 		}
1868 
1869 		/* FDB dump callback is per port. This means we have to
1870 		 * disregard a valid entry if it's not for this port, even if
1871 		 * only to revisit it later. This is inefficient because the
1872 		 * 1024-sized FDB table needs to be traversed 4 times through
1873 		 * SPI during a 'bridge fdb show' command.
1874 		 */
1875 		if (!(l2_lookup.destports & BIT(port)))
1876 			continue;
1877 
1878 		/* We need to hide the FDB entry for unknown multicast */
1879 		if (l2_lookup.macaddr == SJA1105_UNKNOWN_MULTICAST &&
1880 		    l2_lookup.mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
1881 			continue;
1882 
1883 		u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1884 
1885 		/* We need to hide the dsa_8021q VLANs from the user. */
1886 		if (vid_is_dsa_8021q(l2_lookup.vlanid))
1887 			l2_lookup.vlanid = 0;
1888 		rc = cb(macaddr, l2_lookup.vlanid, l2_lookup.lockeds, data);
1889 		if (rc)
1890 			return rc;
1891 	}
1892 	return 0;
1893 }
1894 
1895 static void sja1105_fast_age(struct dsa_switch *ds, int port)
1896 {
1897 	struct dsa_port *dp = dsa_to_port(ds, port);
1898 	struct sja1105_private *priv = ds->priv;
1899 	struct dsa_db db = {
1900 		.type = DSA_DB_BRIDGE,
1901 		.bridge = {
1902 			.dev = dsa_port_bridge_dev_get(dp),
1903 			.num = dsa_port_bridge_num_get(dp),
1904 		},
1905 	};
1906 	int i;
1907 
1908 	for (i = 0; i < SJA1105_MAX_L2_LOOKUP_COUNT; i++) {
1909 		struct sja1105_l2_lookup_entry l2_lookup = {0};
1910 		u8 macaddr[ETH_ALEN];
1911 		int rc;
1912 
1913 		rc = sja1105_dynamic_config_read(priv, BLK_IDX_L2_LOOKUP,
1914 						 i, &l2_lookup);
1915 		/* No fdb entry at i, not an issue */
1916 		if (rc == -ENOENT)
1917 			continue;
1918 		if (rc) {
1919 			dev_err(ds->dev, "Failed to read FDB: %pe\n",
1920 				ERR_PTR(rc));
1921 			return;
1922 		}
1923 
1924 		if (!(l2_lookup.destports & BIT(port)))
1925 			continue;
1926 
1927 		/* Don't delete static FDB entries */
1928 		if (l2_lookup.lockeds)
1929 			continue;
1930 
1931 		u64_to_ether_addr(l2_lookup.macaddr, macaddr);
1932 
1933 		rc = sja1105_fdb_del(ds, port, macaddr, l2_lookup.vlanid, db);
1934 		if (rc) {
1935 			dev_err(ds->dev,
1936 				"Failed to delete FDB entry %pM vid %lld: %pe\n",
1937 				macaddr, l2_lookup.vlanid, ERR_PTR(rc));
1938 			return;
1939 		}
1940 	}
1941 }
1942 
1943 static int sja1105_mdb_add(struct dsa_switch *ds, int port,
1944 			   const struct switchdev_obj_port_mdb *mdb,
1945 			   struct dsa_db db)
1946 {
1947 	return sja1105_fdb_add(ds, port, mdb->addr, mdb->vid, db);
1948 }
1949 
1950 static int sja1105_mdb_del(struct dsa_switch *ds, int port,
1951 			   const struct switchdev_obj_port_mdb *mdb,
1952 			   struct dsa_db db)
1953 {
1954 	return sja1105_fdb_del(ds, port, mdb->addr, mdb->vid, db);
1955 }
1956 
1957 /* Common function for unicast and broadcast flood configuration.
1958  * Flooding is configured between each {ingress, egress} port pair, and since
1959  * the bridge's semantics are those of "egress flooding", it means we must
1960  * enable flooding towards this port from all ingress ports that are in the
1961  * same forwarding domain.
1962  */
1963 static int sja1105_manage_flood_domains(struct sja1105_private *priv)
1964 {
1965 	struct sja1105_l2_forwarding_entry *l2_fwd;
1966 	struct dsa_switch *ds = priv->ds;
1967 	int from, to, rc;
1968 
1969 	l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
1970 
1971 	for (from = 0; from < ds->num_ports; from++) {
1972 		u64 fl_domain = 0, bc_domain = 0;
1973 
1974 		for (to = 0; to < priv->ds->num_ports; to++) {
1975 			if (!sja1105_can_forward(l2_fwd, from, to))
1976 				continue;
1977 
1978 			if (priv->ucast_egress_floods & BIT(to))
1979 				fl_domain |= BIT(to);
1980 			if (priv->bcast_egress_floods & BIT(to))
1981 				bc_domain |= BIT(to);
1982 		}
1983 
1984 		/* Nothing changed, nothing to do */
1985 		if (l2_fwd[from].fl_domain == fl_domain &&
1986 		    l2_fwd[from].bc_domain == bc_domain)
1987 			continue;
1988 
1989 		l2_fwd[from].fl_domain = fl_domain;
1990 		l2_fwd[from].bc_domain = bc_domain;
1991 
1992 		rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
1993 						  from, &l2_fwd[from], true);
1994 		if (rc < 0)
1995 			return rc;
1996 	}
1997 
1998 	return 0;
1999 }
2000 
2001 static int sja1105_bridge_member(struct dsa_switch *ds, int port,
2002 				 struct dsa_bridge bridge, bool member)
2003 {
2004 	struct sja1105_l2_forwarding_entry *l2_fwd;
2005 	struct sja1105_private *priv = ds->priv;
2006 	int i, rc;
2007 
2008 	l2_fwd = priv->static_config.tables[BLK_IDX_L2_FORWARDING].entries;
2009 
2010 	for (i = 0; i < ds->num_ports; i++) {
2011 		/* Add this port to the forwarding matrix of the
2012 		 * other ports in the same bridge, and viceversa.
2013 		 */
2014 		if (!dsa_is_user_port(ds, i))
2015 			continue;
2016 		/* For the ports already under the bridge, only one thing needs
2017 		 * to be done, and that is to add this port to their
2018 		 * reachability domain. So we can perform the SPI write for
2019 		 * them immediately. However, for this port itself (the one
2020 		 * that is new to the bridge), we need to add all other ports
2021 		 * to its reachability domain. So we do that incrementally in
2022 		 * this loop, and perform the SPI write only at the end, once
2023 		 * the domain contains all other bridge ports.
2024 		 */
2025 		if (i == port)
2026 			continue;
2027 		if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
2028 			continue;
2029 		sja1105_port_allow_traffic(l2_fwd, i, port, member);
2030 		sja1105_port_allow_traffic(l2_fwd, port, i, member);
2031 
2032 		rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2033 						  i, &l2_fwd[i], true);
2034 		if (rc < 0)
2035 			return rc;
2036 	}
2037 
2038 	rc = sja1105_dynamic_config_write(priv, BLK_IDX_L2_FORWARDING,
2039 					  port, &l2_fwd[port], true);
2040 	if (rc)
2041 		return rc;
2042 
2043 	rc = sja1105_commit_pvid(ds, port);
2044 	if (rc)
2045 		return rc;
2046 
2047 	return sja1105_manage_flood_domains(priv);
2048 }
2049 
2050 static void sja1105_bridge_stp_state_set(struct dsa_switch *ds, int port,
2051 					 u8 state)
2052 {
2053 	struct dsa_port *dp = dsa_to_port(ds, port);
2054 	struct sja1105_private *priv = ds->priv;
2055 	struct sja1105_mac_config_entry *mac;
2056 
2057 	mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2058 
2059 	switch (state) {
2060 	case BR_STATE_DISABLED:
2061 	case BR_STATE_BLOCKING:
2062 		/* From UM10944 description of DRPDTAG (why put this there?):
2063 		 * "Management traffic flows to the port regardless of the state
2064 		 * of the INGRESS flag". So BPDUs are still be allowed to pass.
2065 		 * At the moment no difference between DISABLED and BLOCKING.
2066 		 */
2067 		mac[port].ingress   = false;
2068 		mac[port].egress    = false;
2069 		mac[port].dyn_learn = false;
2070 		break;
2071 	case BR_STATE_LISTENING:
2072 		mac[port].ingress   = true;
2073 		mac[port].egress    = false;
2074 		mac[port].dyn_learn = false;
2075 		break;
2076 	case BR_STATE_LEARNING:
2077 		mac[port].ingress   = true;
2078 		mac[port].egress    = false;
2079 		mac[port].dyn_learn = dp->learning;
2080 		break;
2081 	case BR_STATE_FORWARDING:
2082 		mac[port].ingress   = true;
2083 		mac[port].egress    = true;
2084 		mac[port].dyn_learn = dp->learning;
2085 		break;
2086 	default:
2087 		dev_err(ds->dev, "invalid STP state: %d\n", state);
2088 		return;
2089 	}
2090 
2091 	sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2092 				     &mac[port], true);
2093 }
2094 
2095 static int sja1105_bridge_join(struct dsa_switch *ds, int port,
2096 			       struct dsa_bridge bridge,
2097 			       bool *tx_fwd_offload,
2098 			       struct netlink_ext_ack *extack)
2099 {
2100 	int rc;
2101 
2102 	rc = sja1105_bridge_member(ds, port, bridge, true);
2103 	if (rc)
2104 		return rc;
2105 
2106 	rc = dsa_tag_8021q_bridge_join(ds, port, bridge);
2107 	if (rc) {
2108 		sja1105_bridge_member(ds, port, bridge, false);
2109 		return rc;
2110 	}
2111 
2112 	*tx_fwd_offload = true;
2113 
2114 	return 0;
2115 }
2116 
2117 static void sja1105_bridge_leave(struct dsa_switch *ds, int port,
2118 				 struct dsa_bridge bridge)
2119 {
2120 	dsa_tag_8021q_bridge_leave(ds, port, bridge);
2121 	sja1105_bridge_member(ds, port, bridge, false);
2122 }
2123 
2124 #define BYTES_PER_KBIT (1000LL / 8)
2125 
2126 static int sja1105_find_unused_cbs_shaper(struct sja1105_private *priv)
2127 {
2128 	int i;
2129 
2130 	for (i = 0; i < priv->info->num_cbs_shapers; i++)
2131 		if (!priv->cbs[i].idle_slope && !priv->cbs[i].send_slope)
2132 			return i;
2133 
2134 	return -1;
2135 }
2136 
2137 static int sja1105_delete_cbs_shaper(struct sja1105_private *priv, int port,
2138 				     int prio)
2139 {
2140 	int i;
2141 
2142 	for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2143 		struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2144 
2145 		if (cbs->port == port && cbs->prio == prio) {
2146 			memset(cbs, 0, sizeof(*cbs));
2147 			return sja1105_dynamic_config_write(priv, BLK_IDX_CBS,
2148 							    i, cbs, true);
2149 		}
2150 	}
2151 
2152 	return 0;
2153 }
2154 
2155 static int sja1105_setup_tc_cbs(struct dsa_switch *ds, int port,
2156 				struct tc_cbs_qopt_offload *offload)
2157 {
2158 	struct sja1105_private *priv = ds->priv;
2159 	struct sja1105_cbs_entry *cbs;
2160 	int index;
2161 
2162 	if (!offload->enable)
2163 		return sja1105_delete_cbs_shaper(priv, port, offload->queue);
2164 
2165 	index = sja1105_find_unused_cbs_shaper(priv);
2166 	if (index < 0)
2167 		return -ENOSPC;
2168 
2169 	cbs = &priv->cbs[index];
2170 	cbs->port = port;
2171 	cbs->prio = offload->queue;
2172 	/* locredit and sendslope are negative by definition. In hardware,
2173 	 * positive values must be provided, and the negative sign is implicit.
2174 	 */
2175 	cbs->credit_hi = offload->hicredit;
2176 	cbs->credit_lo = abs(offload->locredit);
2177 	/* User space is in kbits/sec, hardware in bytes/sec */
2178 	cbs->idle_slope = offload->idleslope * BYTES_PER_KBIT;
2179 	cbs->send_slope = abs(offload->sendslope * BYTES_PER_KBIT);
2180 	/* Convert the negative values from 64-bit 2's complement
2181 	 * to 32-bit 2's complement (for the case of 0x80000000 whose
2182 	 * negative is still negative).
2183 	 */
2184 	cbs->credit_lo &= GENMASK_ULL(31, 0);
2185 	cbs->send_slope &= GENMASK_ULL(31, 0);
2186 
2187 	return sja1105_dynamic_config_write(priv, BLK_IDX_CBS, index, cbs,
2188 					    true);
2189 }
2190 
2191 static int sja1105_reload_cbs(struct sja1105_private *priv)
2192 {
2193 	int rc = 0, i;
2194 
2195 	/* The credit based shapers are only allocated if
2196 	 * CONFIG_NET_SCH_CBS is enabled.
2197 	 */
2198 	if (!priv->cbs)
2199 		return 0;
2200 
2201 	for (i = 0; i < priv->info->num_cbs_shapers; i++) {
2202 		struct sja1105_cbs_entry *cbs = &priv->cbs[i];
2203 
2204 		if (!cbs->idle_slope && !cbs->send_slope)
2205 			continue;
2206 
2207 		rc = sja1105_dynamic_config_write(priv, BLK_IDX_CBS, i, cbs,
2208 						  true);
2209 		if (rc)
2210 			break;
2211 	}
2212 
2213 	return rc;
2214 }
2215 
2216 static const char * const sja1105_reset_reasons[] = {
2217 	[SJA1105_VLAN_FILTERING] = "VLAN filtering",
2218 	[SJA1105_AGEING_TIME] = "Ageing time",
2219 	[SJA1105_SCHEDULING] = "Time-aware scheduling",
2220 	[SJA1105_BEST_EFFORT_POLICING] = "Best-effort policing",
2221 	[SJA1105_VIRTUAL_LINKS] = "Virtual links",
2222 };
2223 
2224 /* For situations where we need to change a setting at runtime that is only
2225  * available through the static configuration, resetting the switch in order
2226  * to upload the new static config is unavoidable. Back up the settings we
2227  * modify at runtime (currently only MAC) and restore them after uploading,
2228  * such that this operation is relatively seamless.
2229  */
2230 int sja1105_static_config_reload(struct sja1105_private *priv,
2231 				 enum sja1105_reset_reason reason)
2232 {
2233 	struct ptp_system_timestamp ptp_sts_before;
2234 	struct ptp_system_timestamp ptp_sts_after;
2235 	int speed_mbps[SJA1105_MAX_NUM_PORTS];
2236 	u16 bmcr[SJA1105_MAX_NUM_PORTS] = {0};
2237 	struct sja1105_mac_config_entry *mac;
2238 	struct dsa_switch *ds = priv->ds;
2239 	s64 t1, t2, t3, t4;
2240 	s64 t12, t34;
2241 	int rc, i;
2242 	s64 now;
2243 
2244 	mutex_lock(&priv->mgmt_lock);
2245 
2246 	mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2247 
2248 	/* Back up the dynamic link speed changed by sja1105_adjust_port_config
2249 	 * in order to temporarily restore it to SJA1105_SPEED_AUTO - which the
2250 	 * switch wants to see in the static config in order to allow us to
2251 	 * change it through the dynamic interface later.
2252 	 */
2253 	for (i = 0; i < ds->num_ports; i++) {
2254 		speed_mbps[i] = sja1105_port_speed_to_ethtool(priv,
2255 							      mac[i].speed);
2256 		mac[i].speed = priv->info->port_speed[SJA1105_SPEED_AUTO];
2257 
2258 		if (priv->xpcs[i])
2259 			bmcr[i] = mdiobus_c45_read(priv->mdio_pcs, i,
2260 						   MDIO_MMD_VEND2, MDIO_CTRL1);
2261 	}
2262 
2263 	/* No PTP operations can run right now */
2264 	mutex_lock(&priv->ptp_data.lock);
2265 
2266 	rc = __sja1105_ptp_gettimex(ds, &now, &ptp_sts_before);
2267 	if (rc < 0) {
2268 		mutex_unlock(&priv->ptp_data.lock);
2269 		goto out;
2270 	}
2271 
2272 	/* Reset switch and send updated static configuration */
2273 	rc = sja1105_static_config_upload(priv);
2274 	if (rc < 0) {
2275 		mutex_unlock(&priv->ptp_data.lock);
2276 		goto out;
2277 	}
2278 
2279 	rc = __sja1105_ptp_settime(ds, 0, &ptp_sts_after);
2280 	if (rc < 0) {
2281 		mutex_unlock(&priv->ptp_data.lock);
2282 		goto out;
2283 	}
2284 
2285 	t1 = timespec64_to_ns(&ptp_sts_before.pre_ts);
2286 	t2 = timespec64_to_ns(&ptp_sts_before.post_ts);
2287 	t3 = timespec64_to_ns(&ptp_sts_after.pre_ts);
2288 	t4 = timespec64_to_ns(&ptp_sts_after.post_ts);
2289 	/* Mid point, corresponds to pre-reset PTPCLKVAL */
2290 	t12 = t1 + (t2 - t1) / 2;
2291 	/* Mid point, corresponds to post-reset PTPCLKVAL, aka 0 */
2292 	t34 = t3 + (t4 - t3) / 2;
2293 	/* Advance PTPCLKVAL by the time it took since its readout */
2294 	now += (t34 - t12);
2295 
2296 	__sja1105_ptp_adjtime(ds, now);
2297 
2298 	mutex_unlock(&priv->ptp_data.lock);
2299 
2300 	dev_info(priv->ds->dev,
2301 		 "Reset switch and programmed static config. Reason: %s\n",
2302 		 sja1105_reset_reasons[reason]);
2303 
2304 	/* Configure the CGU (PLLs) for MII and RMII PHYs.
2305 	 * For these interfaces there is no dynamic configuration
2306 	 * needed, since PLLs have same settings at all speeds.
2307 	 */
2308 	if (priv->info->clocking_setup) {
2309 		rc = priv->info->clocking_setup(priv);
2310 		if (rc < 0)
2311 			goto out;
2312 	}
2313 
2314 	for (i = 0; i < ds->num_ports; i++) {
2315 		struct dw_xpcs *xpcs = priv->xpcs[i];
2316 		unsigned int neg_mode;
2317 
2318 		rc = sja1105_adjust_port_config(priv, i, speed_mbps[i]);
2319 		if (rc < 0)
2320 			goto out;
2321 
2322 		if (!xpcs)
2323 			continue;
2324 
2325 		if (bmcr[i] & BMCR_ANENABLE)
2326 			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
2327 		else
2328 			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
2329 
2330 		rc = xpcs_do_config(xpcs, priv->phy_mode[i], NULL, neg_mode);
2331 		if (rc < 0)
2332 			goto out;
2333 
2334 		if (neg_mode == PHYLINK_PCS_NEG_OUTBAND) {
2335 			int speed = SPEED_UNKNOWN;
2336 
2337 			if (priv->phy_mode[i] == PHY_INTERFACE_MODE_2500BASEX)
2338 				speed = SPEED_2500;
2339 			else if (bmcr[i] & BMCR_SPEED1000)
2340 				speed = SPEED_1000;
2341 			else if (bmcr[i] & BMCR_SPEED100)
2342 				speed = SPEED_100;
2343 			else
2344 				speed = SPEED_10;
2345 
2346 			xpcs_link_up(&xpcs->pcs, neg_mode, priv->phy_mode[i],
2347 				     speed, DUPLEX_FULL);
2348 		}
2349 	}
2350 
2351 	rc = sja1105_reload_cbs(priv);
2352 	if (rc < 0)
2353 		goto out;
2354 out:
2355 	mutex_unlock(&priv->mgmt_lock);
2356 
2357 	return rc;
2358 }
2359 
2360 static enum dsa_tag_protocol
2361 sja1105_get_tag_protocol(struct dsa_switch *ds, int port,
2362 			 enum dsa_tag_protocol mp)
2363 {
2364 	struct sja1105_private *priv = ds->priv;
2365 
2366 	return priv->info->tag_proto;
2367 }
2368 
2369 /* The TPID setting belongs to the General Parameters table,
2370  * which can only be partially reconfigured at runtime (and not the TPID).
2371  * So a switch reset is required.
2372  */
2373 int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
2374 			   struct netlink_ext_ack *extack)
2375 {
2376 	struct sja1105_general_params_entry *general_params;
2377 	struct sja1105_private *priv = ds->priv;
2378 	struct sja1105_table *table;
2379 	struct sja1105_rule *rule;
2380 	u16 tpid, tpid2;
2381 	int rc;
2382 
2383 	list_for_each_entry(rule, &priv->flow_block.rules, list) {
2384 		if (rule->type == SJA1105_RULE_VL) {
2385 			NL_SET_ERR_MSG_MOD(extack,
2386 					   "Cannot change VLAN filtering with active VL rules");
2387 			return -EBUSY;
2388 		}
2389 	}
2390 
2391 	if (enabled) {
2392 		/* Enable VLAN filtering. */
2393 		tpid  = ETH_P_8021Q;
2394 		tpid2 = ETH_P_8021AD;
2395 	} else {
2396 		/* Disable VLAN filtering. */
2397 		tpid  = ETH_P_SJA1105;
2398 		tpid2 = ETH_P_SJA1105;
2399 	}
2400 
2401 	table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2402 	general_params = table->entries;
2403 	/* EtherType used to identify inner tagged (C-tag) VLAN traffic */
2404 	general_params->tpid = tpid;
2405 	/* EtherType used to identify outer tagged (S-tag) VLAN traffic */
2406 	general_params->tpid2 = tpid2;
2407 
2408 	for (port = 0; port < ds->num_ports; port++) {
2409 		if (dsa_is_unused_port(ds, port))
2410 			continue;
2411 
2412 		rc = sja1105_commit_pvid(ds, port);
2413 		if (rc)
2414 			return rc;
2415 	}
2416 
2417 	rc = sja1105_static_config_reload(priv, SJA1105_VLAN_FILTERING);
2418 	if (rc)
2419 		NL_SET_ERR_MSG_MOD(extack, "Failed to change VLAN Ethertype");
2420 
2421 	return rc;
2422 }
2423 
2424 static int sja1105_vlan_add(struct sja1105_private *priv, int port, u16 vid,
2425 			    u16 flags, bool allowed_ingress)
2426 {
2427 	struct sja1105_vlan_lookup_entry *vlan;
2428 	struct sja1105_table *table;
2429 	int match, rc;
2430 
2431 	table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2432 
2433 	match = sja1105_is_vlan_configured(priv, vid);
2434 	if (match < 0) {
2435 		rc = sja1105_table_resize(table, table->entry_count + 1);
2436 		if (rc)
2437 			return rc;
2438 		match = table->entry_count - 1;
2439 	}
2440 
2441 	/* Assign pointer after the resize (it's new memory) */
2442 	vlan = table->entries;
2443 
2444 	vlan[match].type_entry = SJA1110_VLAN_D_TAG;
2445 	vlan[match].vlanid = vid;
2446 	vlan[match].vlan_bc |= BIT(port);
2447 
2448 	if (allowed_ingress)
2449 		vlan[match].vmemb_port |= BIT(port);
2450 	else
2451 		vlan[match].vmemb_port &= ~BIT(port);
2452 
2453 	if (flags & BRIDGE_VLAN_INFO_UNTAGGED)
2454 		vlan[match].tag_port &= ~BIT(port);
2455 	else
2456 		vlan[match].tag_port |= BIT(port);
2457 
2458 	return sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2459 					    &vlan[match], true);
2460 }
2461 
2462 static int sja1105_vlan_del(struct sja1105_private *priv, int port, u16 vid)
2463 {
2464 	struct sja1105_vlan_lookup_entry *vlan;
2465 	struct sja1105_table *table;
2466 	bool keep = true;
2467 	int match, rc;
2468 
2469 	table = &priv->static_config.tables[BLK_IDX_VLAN_LOOKUP];
2470 
2471 	match = sja1105_is_vlan_configured(priv, vid);
2472 	/* Can't delete a missing entry. */
2473 	if (match < 0)
2474 		return 0;
2475 
2476 	/* Assign pointer after the resize (it's new memory) */
2477 	vlan = table->entries;
2478 
2479 	vlan[match].vlanid = vid;
2480 	vlan[match].vlan_bc &= ~BIT(port);
2481 	vlan[match].vmemb_port &= ~BIT(port);
2482 	/* Also unset tag_port, just so we don't have a confusing bitmap
2483 	 * (no practical purpose).
2484 	 */
2485 	vlan[match].tag_port &= ~BIT(port);
2486 
2487 	/* If there's no port left as member of this VLAN,
2488 	 * it's time for it to go.
2489 	 */
2490 	if (!vlan[match].vmemb_port)
2491 		keep = false;
2492 
2493 	rc = sja1105_dynamic_config_write(priv, BLK_IDX_VLAN_LOOKUP, vid,
2494 					  &vlan[match], keep);
2495 	if (rc < 0)
2496 		return rc;
2497 
2498 	if (!keep)
2499 		return sja1105_table_delete_entry(table, match);
2500 
2501 	return 0;
2502 }
2503 
2504 static int sja1105_bridge_vlan_add(struct dsa_switch *ds, int port,
2505 				   const struct switchdev_obj_port_vlan *vlan,
2506 				   struct netlink_ext_ack *extack)
2507 {
2508 	struct sja1105_private *priv = ds->priv;
2509 	u16 flags = vlan->flags;
2510 	int rc;
2511 
2512 	/* Be sure to deny alterations to the configuration done by tag_8021q.
2513 	 */
2514 	if (vid_is_dsa_8021q(vlan->vid)) {
2515 		NL_SET_ERR_MSG_MOD(extack,
2516 				   "Range 3072-4095 reserved for dsa_8021q operation");
2517 		return -EBUSY;
2518 	}
2519 
2520 	/* Always install bridge VLANs as egress-tagged on CPU and DSA ports */
2521 	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2522 		flags = 0;
2523 
2524 	rc = sja1105_vlan_add(priv, port, vlan->vid, flags, true);
2525 	if (rc)
2526 		return rc;
2527 
2528 	if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
2529 		priv->bridge_pvid[port] = vlan->vid;
2530 
2531 	return sja1105_commit_pvid(ds, port);
2532 }
2533 
2534 static int sja1105_bridge_vlan_del(struct dsa_switch *ds, int port,
2535 				   const struct switchdev_obj_port_vlan *vlan)
2536 {
2537 	struct sja1105_private *priv = ds->priv;
2538 	int rc;
2539 
2540 	rc = sja1105_vlan_del(priv, port, vlan->vid);
2541 	if (rc)
2542 		return rc;
2543 
2544 	/* In case the pvid was deleted, make sure that untagged packets will
2545 	 * be dropped.
2546 	 */
2547 	return sja1105_commit_pvid(ds, port);
2548 }
2549 
2550 static int sja1105_dsa_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid,
2551 				      u16 flags)
2552 {
2553 	struct sja1105_private *priv = ds->priv;
2554 	bool allowed_ingress = true;
2555 	int rc;
2556 
2557 	/* Prevent attackers from trying to inject a DSA tag from
2558 	 * the outside world.
2559 	 */
2560 	if (dsa_is_user_port(ds, port))
2561 		allowed_ingress = false;
2562 
2563 	rc = sja1105_vlan_add(priv, port, vid, flags, allowed_ingress);
2564 	if (rc)
2565 		return rc;
2566 
2567 	if (flags & BRIDGE_VLAN_INFO_PVID)
2568 		priv->tag_8021q_pvid[port] = vid;
2569 
2570 	return sja1105_commit_pvid(ds, port);
2571 }
2572 
2573 static int sja1105_dsa_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid)
2574 {
2575 	struct sja1105_private *priv = ds->priv;
2576 
2577 	return sja1105_vlan_del(priv, port, vid);
2578 }
2579 
2580 static int sja1105_prechangeupper(struct dsa_switch *ds, int port,
2581 				  struct netdev_notifier_changeupper_info *info)
2582 {
2583 	struct netlink_ext_ack *extack = info->info.extack;
2584 	struct net_device *upper = info->upper_dev;
2585 	struct dsa_switch_tree *dst = ds->dst;
2586 	struct dsa_port *dp;
2587 
2588 	if (is_vlan_dev(upper)) {
2589 		NL_SET_ERR_MSG_MOD(extack, "8021q uppers are not supported");
2590 		return -EBUSY;
2591 	}
2592 
2593 	if (netif_is_bridge_master(upper)) {
2594 		list_for_each_entry(dp, &dst->ports, list) {
2595 			struct net_device *br = dsa_port_bridge_dev_get(dp);
2596 
2597 			if (br && br != upper && br_vlan_enabled(br)) {
2598 				NL_SET_ERR_MSG_MOD(extack,
2599 						   "Only one VLAN-aware bridge is supported");
2600 				return -EBUSY;
2601 			}
2602 		}
2603 	}
2604 
2605 	return 0;
2606 }
2607 
2608 static int sja1105_mgmt_xmit(struct dsa_switch *ds, int port, int slot,
2609 			     struct sk_buff *skb, bool takets)
2610 {
2611 	struct sja1105_mgmt_entry mgmt_route = {0};
2612 	struct sja1105_private *priv = ds->priv;
2613 	struct ethhdr *hdr;
2614 	int timeout = 10;
2615 	int rc;
2616 
2617 	hdr = eth_hdr(skb);
2618 
2619 	mgmt_route.macaddr = ether_addr_to_u64(hdr->h_dest);
2620 	mgmt_route.destports = BIT(port);
2621 	mgmt_route.enfport = 1;
2622 	mgmt_route.tsreg = 0;
2623 	mgmt_route.takets = takets;
2624 
2625 	rc = sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2626 					  slot, &mgmt_route, true);
2627 	if (rc < 0) {
2628 		kfree_skb(skb);
2629 		return rc;
2630 	}
2631 
2632 	/* Transfer skb to the host port. */
2633 	dsa_enqueue_skb(skb, dsa_to_port(ds, port)->slave);
2634 
2635 	/* Wait until the switch has processed the frame */
2636 	do {
2637 		rc = sja1105_dynamic_config_read(priv, BLK_IDX_MGMT_ROUTE,
2638 						 slot, &mgmt_route);
2639 		if (rc < 0) {
2640 			dev_err_ratelimited(priv->ds->dev,
2641 					    "failed to poll for mgmt route\n");
2642 			continue;
2643 		}
2644 
2645 		/* UM10944: The ENFPORT flag of the respective entry is
2646 		 * cleared when a match is found. The host can use this
2647 		 * flag as an acknowledgment.
2648 		 */
2649 		cpu_relax();
2650 	} while (mgmt_route.enfport && --timeout);
2651 
2652 	if (!timeout) {
2653 		/* Clean up the management route so that a follow-up
2654 		 * frame may not match on it by mistake.
2655 		 * This is only hardware supported on P/Q/R/S - on E/T it is
2656 		 * a no-op and we are silently discarding the -EOPNOTSUPP.
2657 		 */
2658 		sja1105_dynamic_config_write(priv, BLK_IDX_MGMT_ROUTE,
2659 					     slot, &mgmt_route, false);
2660 		dev_err_ratelimited(priv->ds->dev, "xmit timed out\n");
2661 	}
2662 
2663 	return NETDEV_TX_OK;
2664 }
2665 
2666 #define work_to_xmit_work(w) \
2667 		container_of((w), struct sja1105_deferred_xmit_work, work)
2668 
2669 /* Deferred work is unfortunately necessary because setting up the management
2670  * route cannot be done from atomit context (SPI transfer takes a sleepable
2671  * lock on the bus)
2672  */
2673 static void sja1105_port_deferred_xmit(struct kthread_work *work)
2674 {
2675 	struct sja1105_deferred_xmit_work *xmit_work = work_to_xmit_work(work);
2676 	struct sk_buff *clone, *skb = xmit_work->skb;
2677 	struct dsa_switch *ds = xmit_work->dp->ds;
2678 	struct sja1105_private *priv = ds->priv;
2679 	int port = xmit_work->dp->index;
2680 
2681 	clone = SJA1105_SKB_CB(skb)->clone;
2682 
2683 	mutex_lock(&priv->mgmt_lock);
2684 
2685 	sja1105_mgmt_xmit(ds, port, 0, skb, !!clone);
2686 
2687 	/* The clone, if there, was made by dsa_skb_tx_timestamp */
2688 	if (clone)
2689 		sja1105_ptp_txtstamp_skb(ds, port, clone);
2690 
2691 	mutex_unlock(&priv->mgmt_lock);
2692 
2693 	kfree(xmit_work);
2694 }
2695 
2696 static int sja1105_connect_tag_protocol(struct dsa_switch *ds,
2697 					enum dsa_tag_protocol proto)
2698 {
2699 	struct sja1105_private *priv = ds->priv;
2700 	struct sja1105_tagger_data *tagger_data;
2701 
2702 	if (proto != priv->info->tag_proto)
2703 		return -EPROTONOSUPPORT;
2704 
2705 	tagger_data = sja1105_tagger_data(ds);
2706 	tagger_data->xmit_work_fn = sja1105_port_deferred_xmit;
2707 	tagger_data->meta_tstamp_handler = sja1110_process_meta_tstamp;
2708 
2709 	return 0;
2710 }
2711 
2712 /* The MAXAGE setting belongs to the L2 Forwarding Parameters table,
2713  * which cannot be reconfigured at runtime. So a switch reset is required.
2714  */
2715 static int sja1105_set_ageing_time(struct dsa_switch *ds,
2716 				   unsigned int ageing_time)
2717 {
2718 	struct sja1105_l2_lookup_params_entry *l2_lookup_params;
2719 	struct sja1105_private *priv = ds->priv;
2720 	struct sja1105_table *table;
2721 	unsigned int maxage;
2722 
2723 	table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP_PARAMS];
2724 	l2_lookup_params = table->entries;
2725 
2726 	maxage = SJA1105_AGEING_TIME_MS(ageing_time);
2727 
2728 	if (l2_lookup_params->maxage == maxage)
2729 		return 0;
2730 
2731 	l2_lookup_params->maxage = maxage;
2732 
2733 	return sja1105_static_config_reload(priv, SJA1105_AGEING_TIME);
2734 }
2735 
2736 static int sja1105_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
2737 {
2738 	struct sja1105_l2_policing_entry *policing;
2739 	struct sja1105_private *priv = ds->priv;
2740 
2741 	new_mtu += VLAN_ETH_HLEN + ETH_FCS_LEN;
2742 
2743 	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2744 		new_mtu += VLAN_HLEN;
2745 
2746 	policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2747 
2748 	if (policing[port].maxlen == new_mtu)
2749 		return 0;
2750 
2751 	policing[port].maxlen = new_mtu;
2752 
2753 	return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2754 }
2755 
2756 static int sja1105_get_max_mtu(struct dsa_switch *ds, int port)
2757 {
2758 	return 2043 - VLAN_ETH_HLEN - ETH_FCS_LEN;
2759 }
2760 
2761 static int sja1105_port_setup_tc(struct dsa_switch *ds, int port,
2762 				 enum tc_setup_type type,
2763 				 void *type_data)
2764 {
2765 	switch (type) {
2766 	case TC_SETUP_QDISC_TAPRIO:
2767 		return sja1105_setup_tc_taprio(ds, port, type_data);
2768 	case TC_SETUP_QDISC_CBS:
2769 		return sja1105_setup_tc_cbs(ds, port, type_data);
2770 	default:
2771 		return -EOPNOTSUPP;
2772 	}
2773 }
2774 
2775 /* We have a single mirror (@to) port, but can configure ingress and egress
2776  * mirroring on all other (@from) ports.
2777  * We need to allow mirroring rules only as long as the @to port is always the
2778  * same, and we need to unset the @to port from mirr_port only when there is no
2779  * mirroring rule that references it.
2780  */
2781 static int sja1105_mirror_apply(struct sja1105_private *priv, int from, int to,
2782 				bool ingress, bool enabled)
2783 {
2784 	struct sja1105_general_params_entry *general_params;
2785 	struct sja1105_mac_config_entry *mac;
2786 	struct dsa_switch *ds = priv->ds;
2787 	struct sja1105_table *table;
2788 	bool already_enabled;
2789 	u64 new_mirr_port;
2790 	int rc;
2791 
2792 	table = &priv->static_config.tables[BLK_IDX_GENERAL_PARAMS];
2793 	general_params = table->entries;
2794 
2795 	mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2796 
2797 	already_enabled = (general_params->mirr_port != ds->num_ports);
2798 	if (already_enabled && enabled && general_params->mirr_port != to) {
2799 		dev_err(priv->ds->dev,
2800 			"Delete mirroring rules towards port %llu first\n",
2801 			general_params->mirr_port);
2802 		return -EBUSY;
2803 	}
2804 
2805 	new_mirr_port = to;
2806 	if (!enabled) {
2807 		bool keep = false;
2808 		int port;
2809 
2810 		/* Anybody still referencing mirr_port? */
2811 		for (port = 0; port < ds->num_ports; port++) {
2812 			if (mac[port].ing_mirr || mac[port].egr_mirr) {
2813 				keep = true;
2814 				break;
2815 			}
2816 		}
2817 		/* Unset already_enabled for next time */
2818 		if (!keep)
2819 			new_mirr_port = ds->num_ports;
2820 	}
2821 	if (new_mirr_port != general_params->mirr_port) {
2822 		general_params->mirr_port = new_mirr_port;
2823 
2824 		rc = sja1105_dynamic_config_write(priv, BLK_IDX_GENERAL_PARAMS,
2825 						  0, general_params, true);
2826 		if (rc < 0)
2827 			return rc;
2828 	}
2829 
2830 	if (ingress)
2831 		mac[from].ing_mirr = enabled;
2832 	else
2833 		mac[from].egr_mirr = enabled;
2834 
2835 	return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, from,
2836 					    &mac[from], true);
2837 }
2838 
2839 static int sja1105_mirror_add(struct dsa_switch *ds, int port,
2840 			      struct dsa_mall_mirror_tc_entry *mirror,
2841 			      bool ingress, struct netlink_ext_ack *extack)
2842 {
2843 	return sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2844 				    ingress, true);
2845 }
2846 
2847 static void sja1105_mirror_del(struct dsa_switch *ds, int port,
2848 			       struct dsa_mall_mirror_tc_entry *mirror)
2849 {
2850 	sja1105_mirror_apply(ds->priv, port, mirror->to_local_port,
2851 			     mirror->ingress, false);
2852 }
2853 
2854 static int sja1105_port_policer_add(struct dsa_switch *ds, int port,
2855 				    struct dsa_mall_policer_tc_entry *policer)
2856 {
2857 	struct sja1105_l2_policing_entry *policing;
2858 	struct sja1105_private *priv = ds->priv;
2859 
2860 	policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2861 
2862 	/* In hardware, every 8 microseconds the credit level is incremented by
2863 	 * the value of RATE bytes divided by 64, up to a maximum of SMAX
2864 	 * bytes.
2865 	 */
2866 	policing[port].rate = div_u64(512 * policer->rate_bytes_per_sec,
2867 				      1000000);
2868 	policing[port].smax = policer->burst;
2869 
2870 	return sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2871 }
2872 
2873 static void sja1105_port_policer_del(struct dsa_switch *ds, int port)
2874 {
2875 	struct sja1105_l2_policing_entry *policing;
2876 	struct sja1105_private *priv = ds->priv;
2877 
2878 	policing = priv->static_config.tables[BLK_IDX_L2_POLICING].entries;
2879 
2880 	policing[port].rate = SJA1105_RATE_MBPS(1000);
2881 	policing[port].smax = 65535;
2882 
2883 	sja1105_static_config_reload(priv, SJA1105_BEST_EFFORT_POLICING);
2884 }
2885 
2886 static int sja1105_port_set_learning(struct sja1105_private *priv, int port,
2887 				     bool enabled)
2888 {
2889 	struct sja1105_mac_config_entry *mac;
2890 
2891 	mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries;
2892 
2893 	mac[port].dyn_learn = enabled;
2894 
2895 	return sja1105_dynamic_config_write(priv, BLK_IDX_MAC_CONFIG, port,
2896 					    &mac[port], true);
2897 }
2898 
2899 static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to,
2900 					  struct switchdev_brport_flags flags)
2901 {
2902 	if (flags.mask & BR_FLOOD) {
2903 		if (flags.val & BR_FLOOD)
2904 			priv->ucast_egress_floods |= BIT(to);
2905 		else
2906 			priv->ucast_egress_floods &= ~BIT(to);
2907 	}
2908 
2909 	if (flags.mask & BR_BCAST_FLOOD) {
2910 		if (flags.val & BR_BCAST_FLOOD)
2911 			priv->bcast_egress_floods |= BIT(to);
2912 		else
2913 			priv->bcast_egress_floods &= ~BIT(to);
2914 	}
2915 
2916 	return sja1105_manage_flood_domains(priv);
2917 }
2918 
2919 static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to,
2920 				    struct switchdev_brport_flags flags,
2921 				    struct netlink_ext_ack *extack)
2922 {
2923 	struct sja1105_l2_lookup_entry *l2_lookup;
2924 	struct sja1105_table *table;
2925 	int match;
2926 
2927 	table = &priv->static_config.tables[BLK_IDX_L2_LOOKUP];
2928 	l2_lookup = table->entries;
2929 
2930 	for (match = 0; match < table->entry_count; match++)
2931 		if (l2_lookup[match].macaddr == SJA1105_UNKNOWN_MULTICAST &&
2932 		    l2_lookup[match].mask_macaddr == SJA1105_UNKNOWN_MULTICAST)
2933 			break;
2934 
2935 	if (match == table->entry_count) {
2936 		NL_SET_ERR_MSG_MOD(extack,
2937 				   "Could not find FDB entry for unknown multicast");
2938 		return -ENOSPC;
2939 	}
2940 
2941 	if (flags.val & BR_MCAST_FLOOD)
2942 		l2_lookup[match].destports |= BIT(to);
2943 	else
2944 		l2_lookup[match].destports &= ~BIT(to);
2945 
2946 	return sja1105_dynamic_config_write(priv, BLK_IDX_L2_LOOKUP,
2947 					    l2_lookup[match].index,
2948 					    &l2_lookup[match],
2949 					    true);
2950 }
2951 
2952 static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2953 					 struct switchdev_brport_flags flags,
2954 					 struct netlink_ext_ack *extack)
2955 {
2956 	struct sja1105_private *priv = ds->priv;
2957 
2958 	if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
2959 			   BR_BCAST_FLOOD))
2960 		return -EINVAL;
2961 
2962 	if (flags.mask & (BR_FLOOD | BR_MCAST_FLOOD) &&
2963 	    !priv->info->can_limit_mcast_flood) {
2964 		bool multicast = !!(flags.val & BR_MCAST_FLOOD);
2965 		bool unicast = !!(flags.val & BR_FLOOD);
2966 
2967 		if (unicast != multicast) {
2968 			NL_SET_ERR_MSG_MOD(extack,
2969 					   "This chip cannot configure multicast flooding independently of unicast");
2970 			return -EINVAL;
2971 		}
2972 	}
2973 
2974 	return 0;
2975 }
2976 
2977 static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port,
2978 				     struct switchdev_brport_flags flags,
2979 				     struct netlink_ext_ack *extack)
2980 {
2981 	struct sja1105_private *priv = ds->priv;
2982 	int rc;
2983 
2984 	if (flags.mask & BR_LEARNING) {
2985 		bool learn_ena = !!(flags.val & BR_LEARNING);
2986 
2987 		rc = sja1105_port_set_learning(priv, port, learn_ena);
2988 		if (rc)
2989 			return rc;
2990 	}
2991 
2992 	if (flags.mask & (BR_FLOOD | BR_BCAST_FLOOD)) {
2993 		rc = sja1105_port_ucast_bcast_flood(priv, port, flags);
2994 		if (rc)
2995 			return rc;
2996 	}
2997 
2998 	/* For chips that can't offload BR_MCAST_FLOOD independently, there
2999 	 * is nothing to do here, we ensured the configuration is in sync by
3000 	 * offloading BR_FLOOD.
3001 	 */
3002 	if (flags.mask & BR_MCAST_FLOOD && priv->info->can_limit_mcast_flood) {
3003 		rc = sja1105_port_mcast_flood(priv, port, flags,
3004 					      extack);
3005 		if (rc)
3006 			return rc;
3007 	}
3008 
3009 	return 0;
3010 }
3011 
3012 /* The programming model for the SJA1105 switch is "all-at-once" via static
3013  * configuration tables. Some of these can be dynamically modified at runtime,
3014  * but not the xMII mode parameters table.
3015  * Furthermode, some PHYs may not have crystals for generating their clocks
3016  * (e.g. RMII). Instead, their 50MHz clock is supplied via the SJA1105 port's
3017  * ref_clk pin. So port clocking needs to be initialized early, before
3018  * connecting to PHYs is attempted, otherwise they won't respond through MDIO.
3019  * Setting correct PHY link speed does not matter now.
3020  * But dsa_slave_phy_setup is called later than sja1105_setup, so the PHY
3021  * bindings are not yet parsed by DSA core. We need to parse early so that we
3022  * can populate the xMII mode parameters table.
3023  */
3024 static int sja1105_setup(struct dsa_switch *ds)
3025 {
3026 	struct sja1105_private *priv = ds->priv;
3027 	int rc;
3028 
3029 	if (priv->info->disable_microcontroller) {
3030 		rc = priv->info->disable_microcontroller(priv);
3031 		if (rc < 0) {
3032 			dev_err(ds->dev,
3033 				"Failed to disable microcontroller: %pe\n",
3034 				ERR_PTR(rc));
3035 			return rc;
3036 		}
3037 	}
3038 
3039 	/* Create and send configuration down to device */
3040 	rc = sja1105_static_config_load(priv);
3041 	if (rc < 0) {
3042 		dev_err(ds->dev, "Failed to load static config: %d\n", rc);
3043 		return rc;
3044 	}
3045 
3046 	/* Configure the CGU (PHY link modes and speeds) */
3047 	if (priv->info->clocking_setup) {
3048 		rc = priv->info->clocking_setup(priv);
3049 		if (rc < 0) {
3050 			dev_err(ds->dev,
3051 				"Failed to configure MII clocking: %pe\n",
3052 				ERR_PTR(rc));
3053 			goto out_static_config_free;
3054 		}
3055 	}
3056 
3057 	sja1105_tas_setup(ds);
3058 	sja1105_flower_setup(ds);
3059 
3060 	rc = sja1105_ptp_clock_register(ds);
3061 	if (rc < 0) {
3062 		dev_err(ds->dev, "Failed to register PTP clock: %d\n", rc);
3063 		goto out_flower_teardown;
3064 	}
3065 
3066 	rc = sja1105_mdiobus_register(ds);
3067 	if (rc < 0) {
3068 		dev_err(ds->dev, "Failed to register MDIO bus: %pe\n",
3069 			ERR_PTR(rc));
3070 		goto out_ptp_clock_unregister;
3071 	}
3072 
3073 	rc = sja1105_devlink_setup(ds);
3074 	if (rc < 0)
3075 		goto out_mdiobus_unregister;
3076 
3077 	rtnl_lock();
3078 	rc = dsa_tag_8021q_register(ds, htons(ETH_P_8021Q));
3079 	rtnl_unlock();
3080 	if (rc)
3081 		goto out_devlink_teardown;
3082 
3083 	/* On SJA1105, VLAN filtering per se is always enabled in hardware.
3084 	 * The only thing we can do to disable it is lie about what the 802.1Q
3085 	 * EtherType is.
3086 	 * So it will still try to apply VLAN filtering, but all ingress
3087 	 * traffic (except frames received with EtherType of ETH_P_SJA1105)
3088 	 * will be internally tagged with a distorted VLAN header where the
3089 	 * TPID is ETH_P_SJA1105, and the VLAN ID is the port pvid.
3090 	 */
3091 	ds->vlan_filtering_is_global = true;
3092 	ds->untag_bridge_pvid = true;
3093 	ds->fdb_isolation = true;
3094 	/* tag_8021q has 3 bits for the VBID, and the value 0 is reserved */
3095 	ds->max_num_bridges = 7;
3096 
3097 	/* Advertise the 8 egress queues */
3098 	ds->num_tx_queues = SJA1105_NUM_TC;
3099 
3100 	ds->mtu_enforcement_ingress = true;
3101 	ds->assisted_learning_on_cpu_port = true;
3102 
3103 	return 0;
3104 
3105 out_devlink_teardown:
3106 	sja1105_devlink_teardown(ds);
3107 out_mdiobus_unregister:
3108 	sja1105_mdiobus_unregister(ds);
3109 out_ptp_clock_unregister:
3110 	sja1105_ptp_clock_unregister(ds);
3111 out_flower_teardown:
3112 	sja1105_flower_teardown(ds);
3113 	sja1105_tas_teardown(ds);
3114 out_static_config_free:
3115 	sja1105_static_config_free(&priv->static_config);
3116 
3117 	return rc;
3118 }
3119 
3120 static void sja1105_teardown(struct dsa_switch *ds)
3121 {
3122 	struct sja1105_private *priv = ds->priv;
3123 
3124 	rtnl_lock();
3125 	dsa_tag_8021q_unregister(ds);
3126 	rtnl_unlock();
3127 
3128 	sja1105_devlink_teardown(ds);
3129 	sja1105_mdiobus_unregister(ds);
3130 	sja1105_ptp_clock_unregister(ds);
3131 	sja1105_flower_teardown(ds);
3132 	sja1105_tas_teardown(ds);
3133 	sja1105_static_config_free(&priv->static_config);
3134 }
3135 
3136 static const struct dsa_switch_ops sja1105_switch_ops = {
3137 	.get_tag_protocol	= sja1105_get_tag_protocol,
3138 	.connect_tag_protocol	= sja1105_connect_tag_protocol,
3139 	.setup			= sja1105_setup,
3140 	.teardown		= sja1105_teardown,
3141 	.set_ageing_time	= sja1105_set_ageing_time,
3142 	.port_change_mtu	= sja1105_change_mtu,
3143 	.port_max_mtu		= sja1105_get_max_mtu,
3144 	.phylink_get_caps	= sja1105_phylink_get_caps,
3145 	.phylink_mac_select_pcs	= sja1105_mac_select_pcs,
3146 	.phylink_mac_link_up	= sja1105_mac_link_up,
3147 	.phylink_mac_link_down	= sja1105_mac_link_down,
3148 	.get_strings		= sja1105_get_strings,
3149 	.get_ethtool_stats	= sja1105_get_ethtool_stats,
3150 	.get_sset_count		= sja1105_get_sset_count,
3151 	.get_ts_info		= sja1105_get_ts_info,
3152 	.port_fdb_dump		= sja1105_fdb_dump,
3153 	.port_fdb_add		= sja1105_fdb_add,
3154 	.port_fdb_del		= sja1105_fdb_del,
3155 	.port_fast_age		= sja1105_fast_age,
3156 	.port_bridge_join	= sja1105_bridge_join,
3157 	.port_bridge_leave	= sja1105_bridge_leave,
3158 	.port_pre_bridge_flags	= sja1105_port_pre_bridge_flags,
3159 	.port_bridge_flags	= sja1105_port_bridge_flags,
3160 	.port_stp_state_set	= sja1105_bridge_stp_state_set,
3161 	.port_vlan_filtering	= sja1105_vlan_filtering,
3162 	.port_vlan_add		= sja1105_bridge_vlan_add,
3163 	.port_vlan_del		= sja1105_bridge_vlan_del,
3164 	.port_mdb_add		= sja1105_mdb_add,
3165 	.port_mdb_del		= sja1105_mdb_del,
3166 	.port_hwtstamp_get	= sja1105_hwtstamp_get,
3167 	.port_hwtstamp_set	= sja1105_hwtstamp_set,
3168 	.port_rxtstamp		= sja1105_port_rxtstamp,
3169 	.port_txtstamp		= sja1105_port_txtstamp,
3170 	.port_setup_tc		= sja1105_port_setup_tc,
3171 	.port_mirror_add	= sja1105_mirror_add,
3172 	.port_mirror_del	= sja1105_mirror_del,
3173 	.port_policer_add	= sja1105_port_policer_add,
3174 	.port_policer_del	= sja1105_port_policer_del,
3175 	.cls_flower_add		= sja1105_cls_flower_add,
3176 	.cls_flower_del		= sja1105_cls_flower_del,
3177 	.cls_flower_stats	= sja1105_cls_flower_stats,
3178 	.devlink_info_get	= sja1105_devlink_info_get,
3179 	.tag_8021q_vlan_add	= sja1105_dsa_8021q_vlan_add,
3180 	.tag_8021q_vlan_del	= sja1105_dsa_8021q_vlan_del,
3181 	.port_prechangeupper	= sja1105_prechangeupper,
3182 };
3183 
3184 static const struct of_device_id sja1105_dt_ids[];
3185 
3186 static int sja1105_check_device_id(struct sja1105_private *priv)
3187 {
3188 	const struct sja1105_regs *regs = priv->info->regs;
3189 	u8 prod_id[SJA1105_SIZE_DEVICE_ID] = {0};
3190 	struct device *dev = &priv->spidev->dev;
3191 	const struct of_device_id *match;
3192 	u32 device_id;
3193 	u64 part_no;
3194 	int rc;
3195 
3196 	rc = sja1105_xfer_u32(priv, SPI_READ, regs->device_id, &device_id,
3197 			      NULL);
3198 	if (rc < 0)
3199 		return rc;
3200 
3201 	rc = sja1105_xfer_buf(priv, SPI_READ, regs->prod_id, prod_id,
3202 			      SJA1105_SIZE_DEVICE_ID);
3203 	if (rc < 0)
3204 		return rc;
3205 
3206 	sja1105_unpack(prod_id, &part_no, 19, 4, SJA1105_SIZE_DEVICE_ID);
3207 
3208 	for (match = sja1105_dt_ids; match->compatible[0]; match++) {
3209 		const struct sja1105_info *info = match->data;
3210 
3211 		/* Is what's been probed in our match table at all? */
3212 		if (info->device_id != device_id || info->part_no != part_no)
3213 			continue;
3214 
3215 		/* But is it what's in the device tree? */
3216 		if (priv->info->device_id != device_id ||
3217 		    priv->info->part_no != part_no) {
3218 			dev_warn(dev, "Device tree specifies chip %s but found %s, please fix it!\n",
3219 				 priv->info->name, info->name);
3220 			/* It isn't. No problem, pick that up. */
3221 			priv->info = info;
3222 		}
3223 
3224 		return 0;
3225 	}
3226 
3227 	dev_err(dev, "Unexpected {device ID, part number}: 0x%x 0x%llx\n",
3228 		device_id, part_no);
3229 
3230 	return -ENODEV;
3231 }
3232 
3233 static int sja1105_probe(struct spi_device *spi)
3234 {
3235 	struct device *dev = &spi->dev;
3236 	struct sja1105_private *priv;
3237 	size_t max_xfer, max_msg;
3238 	struct dsa_switch *ds;
3239 	int rc;
3240 
3241 	if (!dev->of_node) {
3242 		dev_err(dev, "No DTS bindings for SJA1105 driver\n");
3243 		return -EINVAL;
3244 	}
3245 
3246 	rc = sja1105_hw_reset(dev, 1, 1);
3247 	if (rc)
3248 		return rc;
3249 
3250 	priv = devm_kzalloc(dev, sizeof(struct sja1105_private), GFP_KERNEL);
3251 	if (!priv)
3252 		return -ENOMEM;
3253 
3254 	/* Populate our driver private structure (priv) based on
3255 	 * the device tree node that was probed (spi)
3256 	 */
3257 	priv->spidev = spi;
3258 	spi_set_drvdata(spi, priv);
3259 
3260 	/* Configure the SPI bus */
3261 	spi->bits_per_word = 8;
3262 	rc = spi_setup(spi);
3263 	if (rc < 0) {
3264 		dev_err(dev, "Could not init SPI\n");
3265 		return rc;
3266 	}
3267 
3268 	/* In sja1105_xfer, we send spi_messages composed of two spi_transfers:
3269 	 * a small one for the message header and another one for the current
3270 	 * chunk of the packed buffer.
3271 	 * Check that the restrictions imposed by the SPI controller are
3272 	 * respected: the chunk buffer is smaller than the max transfer size,
3273 	 * and the total length of the chunk plus its message header is smaller
3274 	 * than the max message size.
3275 	 * We do that during probe time since the maximum transfer size is a
3276 	 * runtime invariant.
3277 	 */
3278 	max_xfer = spi_max_transfer_size(spi);
3279 	max_msg = spi_max_message_size(spi);
3280 
3281 	/* We need to send at least one 64-bit word of SPI payload per message
3282 	 * in order to be able to make useful progress.
3283 	 */
3284 	if (max_msg < SJA1105_SIZE_SPI_MSG_HEADER + 8) {
3285 		dev_err(dev, "SPI master cannot send large enough buffers, aborting\n");
3286 		return -EINVAL;
3287 	}
3288 
3289 	priv->max_xfer_len = SJA1105_SIZE_SPI_MSG_MAXLEN;
3290 	if (priv->max_xfer_len > max_xfer)
3291 		priv->max_xfer_len = max_xfer;
3292 	if (priv->max_xfer_len > max_msg - SJA1105_SIZE_SPI_MSG_HEADER)
3293 		priv->max_xfer_len = max_msg - SJA1105_SIZE_SPI_MSG_HEADER;
3294 
3295 	priv->info = of_device_get_match_data(dev);
3296 
3297 	/* Detect hardware device */
3298 	rc = sja1105_check_device_id(priv);
3299 	if (rc < 0) {
3300 		dev_err(dev, "Device ID check failed: %d\n", rc);
3301 		return rc;
3302 	}
3303 
3304 	dev_info(dev, "Probed switch chip: %s\n", priv->info->name);
3305 
3306 	ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3307 	if (!ds)
3308 		return -ENOMEM;
3309 
3310 	ds->dev = dev;
3311 	ds->num_ports = priv->info->num_ports;
3312 	ds->ops = &sja1105_switch_ops;
3313 	ds->priv = priv;
3314 	priv->ds = ds;
3315 
3316 	mutex_init(&priv->ptp_data.lock);
3317 	mutex_init(&priv->dynamic_config_lock);
3318 	mutex_init(&priv->mgmt_lock);
3319 	spin_lock_init(&priv->ts_id_lock);
3320 
3321 	rc = sja1105_parse_dt(priv);
3322 	if (rc < 0) {
3323 		dev_err(ds->dev, "Failed to parse DT: %d\n", rc);
3324 		return rc;
3325 	}
3326 
3327 	if (IS_ENABLED(CONFIG_NET_SCH_CBS)) {
3328 		priv->cbs = devm_kcalloc(dev, priv->info->num_cbs_shapers,
3329 					 sizeof(struct sja1105_cbs_entry),
3330 					 GFP_KERNEL);
3331 		if (!priv->cbs)
3332 			return -ENOMEM;
3333 	}
3334 
3335 	return dsa_register_switch(priv->ds);
3336 }
3337 
3338 static void sja1105_remove(struct spi_device *spi)
3339 {
3340 	struct sja1105_private *priv = spi_get_drvdata(spi);
3341 
3342 	if (!priv)
3343 		return;
3344 
3345 	dsa_unregister_switch(priv->ds);
3346 }
3347 
3348 static void sja1105_shutdown(struct spi_device *spi)
3349 {
3350 	struct sja1105_private *priv = spi_get_drvdata(spi);
3351 
3352 	if (!priv)
3353 		return;
3354 
3355 	dsa_switch_shutdown(priv->ds);
3356 
3357 	spi_set_drvdata(spi, NULL);
3358 }
3359 
3360 static const struct of_device_id sja1105_dt_ids[] = {
3361 	{ .compatible = "nxp,sja1105e", .data = &sja1105e_info },
3362 	{ .compatible = "nxp,sja1105t", .data = &sja1105t_info },
3363 	{ .compatible = "nxp,sja1105p", .data = &sja1105p_info },
3364 	{ .compatible = "nxp,sja1105q", .data = &sja1105q_info },
3365 	{ .compatible = "nxp,sja1105r", .data = &sja1105r_info },
3366 	{ .compatible = "nxp,sja1105s", .data = &sja1105s_info },
3367 	{ .compatible = "nxp,sja1110a", .data = &sja1110a_info },
3368 	{ .compatible = "nxp,sja1110b", .data = &sja1110b_info },
3369 	{ .compatible = "nxp,sja1110c", .data = &sja1110c_info },
3370 	{ .compatible = "nxp,sja1110d", .data = &sja1110d_info },
3371 	{ /* sentinel */ },
3372 };
3373 MODULE_DEVICE_TABLE(of, sja1105_dt_ids);
3374 
3375 static const struct spi_device_id sja1105_spi_ids[] = {
3376 	{ "sja1105e" },
3377 	{ "sja1105t" },
3378 	{ "sja1105p" },
3379 	{ "sja1105q" },
3380 	{ "sja1105r" },
3381 	{ "sja1105s" },
3382 	{ "sja1110a" },
3383 	{ "sja1110b" },
3384 	{ "sja1110c" },
3385 	{ "sja1110d" },
3386 	{ },
3387 };
3388 MODULE_DEVICE_TABLE(spi, sja1105_spi_ids);
3389 
3390 static struct spi_driver sja1105_driver = {
3391 	.driver = {
3392 		.name  = "sja1105",
3393 		.owner = THIS_MODULE,
3394 		.of_match_table = of_match_ptr(sja1105_dt_ids),
3395 	},
3396 	.id_table = sja1105_spi_ids,
3397 	.probe  = sja1105_probe,
3398 	.remove = sja1105_remove,
3399 	.shutdown = sja1105_shutdown,
3400 };
3401 
3402 module_spi_driver(sja1105_driver);
3403 
3404 MODULE_AUTHOR("Vladimir Oltean <olteanv@gmail.com>");
3405 MODULE_AUTHOR("Georg Waibel <georg.waibel@sensor-technik.de>");
3406 MODULE_DESCRIPTION("SJA1105 Driver");
3407 MODULE_LICENSE("GPL v2");
3408