1 // SPDX-License-Identifier: BSD-3-Clause 2 /* Copyright (c) 2016-2018, NXP Semiconductors 3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 4 */ 5 #include <linux/packing.h> 6 #include "sja1105.h" 7 8 #define SJA1105_SIZE_CGU_CMD 4 9 10 /* Common structure for CFG_PAD_MIIx_RX and CFG_PAD_MIIx_TX */ 11 struct sja1105_cfg_pad_mii { 12 u64 d32_os; 13 u64 d32_ih; 14 u64 d32_ipud; 15 u64 d10_ih; 16 u64 d10_os; 17 u64 d10_ipud; 18 u64 ctrl_os; 19 u64 ctrl_ih; 20 u64 ctrl_ipud; 21 u64 clk_os; 22 u64 clk_ih; 23 u64 clk_ipud; 24 }; 25 26 struct sja1105_cfg_pad_mii_id { 27 u64 rxc_stable_ovr; 28 u64 rxc_delay; 29 u64 rxc_bypass; 30 u64 rxc_pd; 31 u64 txc_stable_ovr; 32 u64 txc_delay; 33 u64 txc_bypass; 34 u64 txc_pd; 35 }; 36 37 /* UM10944 Table 82. 38 * IDIV_0_C to IDIV_4_C control registers 39 * (addr. 10000Bh to 10000Fh) 40 */ 41 struct sja1105_cgu_idiv { 42 u64 clksrc; 43 u64 autoblock; 44 u64 idiv; 45 u64 pd; 46 }; 47 48 /* PLL_1_C control register 49 * 50 * SJA1105 E/T: UM10944 Table 81 (address 10000Ah) 51 * SJA1105 P/Q/R/S: UM11040 Table 116 (address 10000Ah) 52 */ 53 struct sja1105_cgu_pll_ctrl { 54 u64 pllclksrc; 55 u64 msel; 56 u64 autoblock; 57 u64 psel; 58 u64 direct; 59 u64 fbsel; 60 u64 bypass; 61 u64 pd; 62 }; 63 64 enum { 65 CLKSRC_MII0_TX_CLK = 0x00, 66 CLKSRC_MII0_RX_CLK = 0x01, 67 CLKSRC_MII1_TX_CLK = 0x02, 68 CLKSRC_MII1_RX_CLK = 0x03, 69 CLKSRC_MII2_TX_CLK = 0x04, 70 CLKSRC_MII2_RX_CLK = 0x05, 71 CLKSRC_MII3_TX_CLK = 0x06, 72 CLKSRC_MII3_RX_CLK = 0x07, 73 CLKSRC_MII4_TX_CLK = 0x08, 74 CLKSRC_MII4_RX_CLK = 0x09, 75 CLKSRC_PLL0 = 0x0B, 76 CLKSRC_PLL1 = 0x0E, 77 CLKSRC_IDIV0 = 0x11, 78 CLKSRC_IDIV1 = 0x12, 79 CLKSRC_IDIV2 = 0x13, 80 CLKSRC_IDIV3 = 0x14, 81 CLKSRC_IDIV4 = 0x15, 82 }; 83 84 /* UM10944 Table 83. 85 * MIIx clock control registers 1 to 30 86 * (addresses 100013h to 100035h) 87 */ 88 struct sja1105_cgu_mii_ctrl { 89 u64 clksrc; 90 u64 autoblock; 91 u64 pd; 92 }; 93 94 static void sja1105_cgu_idiv_packing(void *buf, struct sja1105_cgu_idiv *idiv, 95 enum packing_op op) 96 { 97 const int size = 4; 98 99 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); 100 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); 101 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); 102 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); 103 } 104 105 static int sja1105_cgu_idiv_config(struct sja1105_private *priv, int port, 106 bool enabled, int factor) 107 { 108 const struct sja1105_regs *regs = priv->info->regs; 109 struct device *dev = priv->ds->dev; 110 struct sja1105_cgu_idiv idiv; 111 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 112 113 if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR) 114 return 0; 115 116 if (enabled && factor != 1 && factor != 10) { 117 dev_err(dev, "idiv factor must be 1 or 10\n"); 118 return -ERANGE; 119 } 120 121 /* Payload for packed_buf */ 122 idiv.clksrc = 0x0A; /* 25MHz */ 123 idiv.autoblock = 1; /* Block clk automatically */ 124 idiv.idiv = factor - 1; /* Divide by 1 or 10 */ 125 idiv.pd = enabled ? 0 : 1; /* Power down? */ 126 sja1105_cgu_idiv_packing(packed_buf, &idiv, PACK); 127 128 return sja1105_xfer_buf(priv, SPI_WRITE, regs->cgu_idiv[port], 129 packed_buf, SJA1105_SIZE_CGU_CMD); 130 } 131 132 static void 133 sja1105_cgu_mii_control_packing(void *buf, struct sja1105_cgu_mii_ctrl *cmd, 134 enum packing_op op) 135 { 136 const int size = 4; 137 138 sja1105_packing(buf, &cmd->clksrc, 28, 24, size, op); 139 sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op); 140 sja1105_packing(buf, &cmd->pd, 0, 0, size, op); 141 } 142 143 static int sja1105_cgu_mii_tx_clk_config(struct sja1105_private *priv, 144 int port, sja1105_mii_role_t role) 145 { 146 const struct sja1105_regs *regs = priv->info->regs; 147 struct sja1105_cgu_mii_ctrl mii_tx_clk; 148 const int mac_clk_sources[] = { 149 CLKSRC_MII0_TX_CLK, 150 CLKSRC_MII1_TX_CLK, 151 CLKSRC_MII2_TX_CLK, 152 CLKSRC_MII3_TX_CLK, 153 CLKSRC_MII4_TX_CLK, 154 }; 155 const int phy_clk_sources[] = { 156 CLKSRC_IDIV0, 157 CLKSRC_IDIV1, 158 CLKSRC_IDIV2, 159 CLKSRC_IDIV3, 160 CLKSRC_IDIV4, 161 }; 162 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 163 int clksrc; 164 165 if (regs->mii_tx_clk[port] == SJA1105_RSV_ADDR) 166 return 0; 167 168 if (role == XMII_MAC) 169 clksrc = mac_clk_sources[port]; 170 else 171 clksrc = phy_clk_sources[port]; 172 173 /* Payload for packed_buf */ 174 mii_tx_clk.clksrc = clksrc; 175 mii_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 176 mii_tx_clk.pd = 0; /* Power Down off => enabled */ 177 sja1105_cgu_mii_control_packing(packed_buf, &mii_tx_clk, PACK); 178 179 return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_tx_clk[port], 180 packed_buf, SJA1105_SIZE_CGU_CMD); 181 } 182 183 static int 184 sja1105_cgu_mii_rx_clk_config(struct sja1105_private *priv, int port) 185 { 186 const struct sja1105_regs *regs = priv->info->regs; 187 struct sja1105_cgu_mii_ctrl mii_rx_clk; 188 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 189 const int clk_sources[] = { 190 CLKSRC_MII0_RX_CLK, 191 CLKSRC_MII1_RX_CLK, 192 CLKSRC_MII2_RX_CLK, 193 CLKSRC_MII3_RX_CLK, 194 CLKSRC_MII4_RX_CLK, 195 }; 196 197 if (regs->mii_rx_clk[port] == SJA1105_RSV_ADDR) 198 return 0; 199 200 /* Payload for packed_buf */ 201 mii_rx_clk.clksrc = clk_sources[port]; 202 mii_rx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 203 mii_rx_clk.pd = 0; /* Power Down off => enabled */ 204 sja1105_cgu_mii_control_packing(packed_buf, &mii_rx_clk, PACK); 205 206 return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_rx_clk[port], 207 packed_buf, SJA1105_SIZE_CGU_CMD); 208 } 209 210 static int 211 sja1105_cgu_mii_ext_tx_clk_config(struct sja1105_private *priv, int port) 212 { 213 const struct sja1105_regs *regs = priv->info->regs; 214 struct sja1105_cgu_mii_ctrl mii_ext_tx_clk; 215 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 216 const int clk_sources[] = { 217 CLKSRC_IDIV0, 218 CLKSRC_IDIV1, 219 CLKSRC_IDIV2, 220 CLKSRC_IDIV3, 221 CLKSRC_IDIV4, 222 }; 223 224 if (regs->mii_ext_tx_clk[port] == SJA1105_RSV_ADDR) 225 return 0; 226 227 /* Payload for packed_buf */ 228 mii_ext_tx_clk.clksrc = clk_sources[port]; 229 mii_ext_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 230 mii_ext_tx_clk.pd = 0; /* Power Down off => enabled */ 231 sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_tx_clk, PACK); 232 233 return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_tx_clk[port], 234 packed_buf, SJA1105_SIZE_CGU_CMD); 235 } 236 237 static int 238 sja1105_cgu_mii_ext_rx_clk_config(struct sja1105_private *priv, int port) 239 { 240 const struct sja1105_regs *regs = priv->info->regs; 241 struct sja1105_cgu_mii_ctrl mii_ext_rx_clk; 242 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 243 const int clk_sources[] = { 244 CLKSRC_IDIV0, 245 CLKSRC_IDIV1, 246 CLKSRC_IDIV2, 247 CLKSRC_IDIV3, 248 CLKSRC_IDIV4, 249 }; 250 251 if (regs->mii_ext_rx_clk[port] == SJA1105_RSV_ADDR) 252 return 0; 253 254 /* Payload for packed_buf */ 255 mii_ext_rx_clk.clksrc = clk_sources[port]; 256 mii_ext_rx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 257 mii_ext_rx_clk.pd = 0; /* Power Down off => enabled */ 258 sja1105_cgu_mii_control_packing(packed_buf, &mii_ext_rx_clk, PACK); 259 260 return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_rx_clk[port], 261 packed_buf, SJA1105_SIZE_CGU_CMD); 262 } 263 264 static int sja1105_mii_clocking_setup(struct sja1105_private *priv, int port, 265 sja1105_mii_role_t role) 266 { 267 struct device *dev = priv->ds->dev; 268 int rc; 269 270 dev_dbg(dev, "Configuring MII-%s clocking\n", 271 (role == XMII_MAC) ? "MAC" : "PHY"); 272 /* If role is MAC, disable IDIV 273 * If role is PHY, enable IDIV and configure for 1/1 divider 274 */ 275 rc = sja1105_cgu_idiv_config(priv, port, (role == XMII_PHY), 1); 276 if (rc < 0) 277 return rc; 278 279 /* Configure CLKSRC of MII_TX_CLK_n 280 * * If role is MAC, select TX_CLK_n 281 * * If role is PHY, select IDIV_n 282 */ 283 rc = sja1105_cgu_mii_tx_clk_config(priv, port, role); 284 if (rc < 0) 285 return rc; 286 287 /* Configure CLKSRC of MII_RX_CLK_n 288 * Select RX_CLK_n 289 */ 290 rc = sja1105_cgu_mii_rx_clk_config(priv, port); 291 if (rc < 0) 292 return rc; 293 294 if (role == XMII_PHY) { 295 /* Per MII spec, the PHY (which is us) drives the TX_CLK pin */ 296 297 /* Configure CLKSRC of EXT_TX_CLK_n 298 * Select IDIV_n 299 */ 300 rc = sja1105_cgu_mii_ext_tx_clk_config(priv, port); 301 if (rc < 0) 302 return rc; 303 304 /* Configure CLKSRC of EXT_RX_CLK_n 305 * Select IDIV_n 306 */ 307 rc = sja1105_cgu_mii_ext_rx_clk_config(priv, port); 308 if (rc < 0) 309 return rc; 310 } 311 return 0; 312 } 313 314 static void 315 sja1105_cgu_pll_control_packing(void *buf, struct sja1105_cgu_pll_ctrl *cmd, 316 enum packing_op op) 317 { 318 const int size = 4; 319 320 sja1105_packing(buf, &cmd->pllclksrc, 28, 24, size, op); 321 sja1105_packing(buf, &cmd->msel, 23, 16, size, op); 322 sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op); 323 sja1105_packing(buf, &cmd->psel, 9, 8, size, op); 324 sja1105_packing(buf, &cmd->direct, 7, 7, size, op); 325 sja1105_packing(buf, &cmd->fbsel, 6, 6, size, op); 326 sja1105_packing(buf, &cmd->bypass, 1, 1, size, op); 327 sja1105_packing(buf, &cmd->pd, 0, 0, size, op); 328 } 329 330 static int sja1105_cgu_rgmii_tx_clk_config(struct sja1105_private *priv, 331 int port, u64 speed) 332 { 333 const struct sja1105_regs *regs = priv->info->regs; 334 struct sja1105_cgu_mii_ctrl txc; 335 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 336 int clksrc; 337 338 if (regs->rgmii_tx_clk[port] == SJA1105_RSV_ADDR) 339 return 0; 340 341 if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) { 342 clksrc = CLKSRC_PLL0; 343 } else { 344 int clk_sources[] = {CLKSRC_IDIV0, CLKSRC_IDIV1, CLKSRC_IDIV2, 345 CLKSRC_IDIV3, CLKSRC_IDIV4}; 346 clksrc = clk_sources[port]; 347 } 348 349 /* RGMII: 125MHz for 1000, 25MHz for 100, 2.5MHz for 10 */ 350 txc.clksrc = clksrc; 351 /* Autoblock clk while changing clksrc */ 352 txc.autoblock = 1; 353 /* Power Down off => enabled */ 354 txc.pd = 0; 355 sja1105_cgu_mii_control_packing(packed_buf, &txc, PACK); 356 357 return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgmii_tx_clk[port], 358 packed_buf, SJA1105_SIZE_CGU_CMD); 359 } 360 361 /* AGU */ 362 static void 363 sja1105_cfg_pad_mii_packing(void *buf, struct sja1105_cfg_pad_mii *cmd, 364 enum packing_op op) 365 { 366 const int size = 4; 367 368 sja1105_packing(buf, &cmd->d32_os, 28, 27, size, op); 369 sja1105_packing(buf, &cmd->d32_ih, 26, 26, size, op); 370 sja1105_packing(buf, &cmd->d32_ipud, 25, 24, size, op); 371 sja1105_packing(buf, &cmd->d10_os, 20, 19, size, op); 372 sja1105_packing(buf, &cmd->d10_ih, 18, 18, size, op); 373 sja1105_packing(buf, &cmd->d10_ipud, 17, 16, size, op); 374 sja1105_packing(buf, &cmd->ctrl_os, 12, 11, size, op); 375 sja1105_packing(buf, &cmd->ctrl_ih, 10, 10, size, op); 376 sja1105_packing(buf, &cmd->ctrl_ipud, 9, 8, size, op); 377 sja1105_packing(buf, &cmd->clk_os, 4, 3, size, op); 378 sja1105_packing(buf, &cmd->clk_ih, 2, 2, size, op); 379 sja1105_packing(buf, &cmd->clk_ipud, 1, 0, size, op); 380 } 381 382 static int sja1105_rgmii_cfg_pad_tx_config(struct sja1105_private *priv, 383 int port) 384 { 385 const struct sja1105_regs *regs = priv->info->regs; 386 struct sja1105_cfg_pad_mii pad_mii_tx = {0}; 387 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 388 389 if (regs->pad_mii_tx[port] == SJA1105_RSV_ADDR) 390 return 0; 391 392 /* Payload */ 393 pad_mii_tx.d32_os = 3; /* TXD[3:2] output stage: */ 394 /* high noise/high speed */ 395 pad_mii_tx.d10_os = 3; /* TXD[1:0] output stage: */ 396 /* high noise/high speed */ 397 pad_mii_tx.d32_ipud = 2; /* TXD[3:2] input stage: */ 398 /* plain input (default) */ 399 pad_mii_tx.d10_ipud = 2; /* TXD[1:0] input stage: */ 400 /* plain input (default) */ 401 pad_mii_tx.ctrl_os = 3; /* TX_CTL / TX_ER output stage */ 402 pad_mii_tx.ctrl_ipud = 2; /* TX_CTL / TX_ER input stage (default) */ 403 pad_mii_tx.clk_os = 3; /* TX_CLK output stage */ 404 pad_mii_tx.clk_ih = 0; /* TX_CLK input hysteresis (default) */ 405 pad_mii_tx.clk_ipud = 2; /* TX_CLK input stage (default) */ 406 sja1105_cfg_pad_mii_packing(packed_buf, &pad_mii_tx, PACK); 407 408 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_tx[port], 409 packed_buf, SJA1105_SIZE_CGU_CMD); 410 } 411 412 static int sja1105_cfg_pad_rx_config(struct sja1105_private *priv, int port) 413 { 414 const struct sja1105_regs *regs = priv->info->regs; 415 struct sja1105_cfg_pad_mii pad_mii_rx = {0}; 416 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 417 418 if (regs->pad_mii_rx[port] == SJA1105_RSV_ADDR) 419 return 0; 420 421 /* Payload */ 422 pad_mii_rx.d32_ih = 0; /* RXD[3:2] input stage hysteresis: */ 423 /* non-Schmitt (default) */ 424 pad_mii_rx.d32_ipud = 2; /* RXD[3:2] input weak pull-up/down */ 425 /* plain input (default) */ 426 pad_mii_rx.d10_ih = 0; /* RXD[1:0] input stage hysteresis: */ 427 /* non-Schmitt (default) */ 428 pad_mii_rx.d10_ipud = 2; /* RXD[1:0] input weak pull-up/down */ 429 /* plain input (default) */ 430 pad_mii_rx.ctrl_ih = 0; /* RX_DV/CRS_DV/RX_CTL and RX_ER */ 431 /* input stage hysteresis: */ 432 /* non-Schmitt (default) */ 433 pad_mii_rx.ctrl_ipud = 3; /* RX_DV/CRS_DV/RX_CTL and RX_ER */ 434 /* input stage weak pull-up/down: */ 435 /* pull-down */ 436 pad_mii_rx.clk_os = 2; /* RX_CLK/RXC output stage: */ 437 /* medium noise/fast speed (default) */ 438 pad_mii_rx.clk_ih = 0; /* RX_CLK/RXC input hysteresis: */ 439 /* non-Schmitt (default) */ 440 pad_mii_rx.clk_ipud = 2; /* RX_CLK/RXC input pull-up/down: */ 441 /* plain input (default) */ 442 sja1105_cfg_pad_mii_packing(packed_buf, &pad_mii_rx, PACK); 443 444 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_rx[port], 445 packed_buf, SJA1105_SIZE_CGU_CMD); 446 } 447 448 static void 449 sja1105_cfg_pad_mii_id_packing(void *buf, struct sja1105_cfg_pad_mii_id *cmd, 450 enum packing_op op) 451 { 452 const int size = SJA1105_SIZE_CGU_CMD; 453 454 sja1105_packing(buf, &cmd->rxc_stable_ovr, 15, 15, size, op); 455 sja1105_packing(buf, &cmd->rxc_delay, 14, 10, size, op); 456 sja1105_packing(buf, &cmd->rxc_bypass, 9, 9, size, op); 457 sja1105_packing(buf, &cmd->rxc_pd, 8, 8, size, op); 458 sja1105_packing(buf, &cmd->txc_stable_ovr, 7, 7, size, op); 459 sja1105_packing(buf, &cmd->txc_delay, 6, 2, size, op); 460 sja1105_packing(buf, &cmd->txc_bypass, 1, 1, size, op); 461 sja1105_packing(buf, &cmd->txc_pd, 0, 0, size, op); 462 } 463 464 /* Valid range in degrees is an integer between 73.8 and 101.7 */ 465 static u64 sja1105_rgmii_delay(u64 phase) 466 { 467 /* UM11040.pdf: The delay in degree phase is 73.8 + delay_tune * 0.9. 468 * To avoid floating point operations we'll multiply by 10 469 * and get 1 decimal point precision. 470 */ 471 phase *= 10; 472 return (phase - 738) / 9; 473 } 474 475 /* The RGMII delay setup procedure is 2-step and gets called upon each 476 * .phylink_mac_config. Both are strategic. 477 * The reason is that the RX Tunable Delay Line of the SJA1105 MAC has issues 478 * with recovering from a frequency change of the link partner's RGMII clock. 479 * The easiest way to recover from this is to temporarily power down the TDL, 480 * as it will re-lock at the new frequency afterwards. 481 */ 482 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port) 483 { 484 const struct sja1105_private *priv = ctx; 485 const struct sja1105_regs *regs = priv->info->regs; 486 struct sja1105_cfg_pad_mii_id pad_mii_id = {0}; 487 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 488 int rc; 489 490 if (priv->rgmii_rx_delay[port]) 491 pad_mii_id.rxc_delay = sja1105_rgmii_delay(90); 492 if (priv->rgmii_tx_delay[port]) 493 pad_mii_id.txc_delay = sja1105_rgmii_delay(90); 494 495 /* Stage 1: Turn the RGMII delay lines off. */ 496 pad_mii_id.rxc_bypass = 1; 497 pad_mii_id.rxc_pd = 1; 498 pad_mii_id.txc_bypass = 1; 499 pad_mii_id.txc_pd = 1; 500 sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK); 501 502 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port], 503 packed_buf, SJA1105_SIZE_CGU_CMD); 504 if (rc < 0) 505 return rc; 506 507 /* Stage 2: Turn the RGMII delay lines on. */ 508 if (priv->rgmii_rx_delay[port]) { 509 pad_mii_id.rxc_bypass = 0; 510 pad_mii_id.rxc_pd = 0; 511 } 512 if (priv->rgmii_tx_delay[port]) { 513 pad_mii_id.txc_bypass = 0; 514 pad_mii_id.txc_pd = 0; 515 } 516 sja1105_cfg_pad_mii_id_packing(packed_buf, &pad_mii_id, PACK); 517 518 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port], 519 packed_buf, SJA1105_SIZE_CGU_CMD); 520 } 521 522 static int sja1105_rgmii_clocking_setup(struct sja1105_private *priv, int port, 523 sja1105_mii_role_t role) 524 { 525 struct device *dev = priv->ds->dev; 526 struct sja1105_mac_config_entry *mac; 527 u64 speed; 528 int rc; 529 530 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; 531 speed = mac[port].speed; 532 533 dev_dbg(dev, "Configuring port %d RGMII at speed %lldMbps\n", 534 port, speed); 535 536 if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) { 537 /* 1000Mbps, IDIV disabled (125 MHz) */ 538 rc = sja1105_cgu_idiv_config(priv, port, false, 1); 539 } else if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS]) { 540 /* 100Mbps, IDIV enabled, divide by 1 (25 MHz) */ 541 rc = sja1105_cgu_idiv_config(priv, port, true, 1); 542 } else if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS]) { 543 /* 10Mbps, IDIV enabled, divide by 10 (2.5 MHz) */ 544 rc = sja1105_cgu_idiv_config(priv, port, true, 10); 545 } else if (speed == priv->info->port_speed[SJA1105_SPEED_AUTO]) { 546 /* Skip CGU configuration if there is no speed available 547 * (e.g. link is not established yet) 548 */ 549 dev_dbg(dev, "Speed not available, skipping CGU config\n"); 550 return 0; 551 } else { 552 rc = -EINVAL; 553 } 554 555 if (rc < 0) { 556 dev_err(dev, "Failed to configure idiv\n"); 557 return rc; 558 } 559 rc = sja1105_cgu_rgmii_tx_clk_config(priv, port, speed); 560 if (rc < 0) { 561 dev_err(dev, "Failed to configure RGMII Tx clock\n"); 562 return rc; 563 } 564 rc = sja1105_rgmii_cfg_pad_tx_config(priv, port); 565 if (rc < 0) { 566 dev_err(dev, "Failed to configure Tx pad registers\n"); 567 return rc; 568 } 569 570 if (!priv->info->setup_rgmii_delay) 571 return 0; 572 573 return priv->info->setup_rgmii_delay(priv, port); 574 } 575 576 static int sja1105_cgu_rmii_ref_clk_config(struct sja1105_private *priv, 577 int port) 578 { 579 const struct sja1105_regs *regs = priv->info->regs; 580 struct sja1105_cgu_mii_ctrl ref_clk; 581 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 582 const int clk_sources[] = { 583 CLKSRC_MII0_TX_CLK, 584 CLKSRC_MII1_TX_CLK, 585 CLKSRC_MII2_TX_CLK, 586 CLKSRC_MII3_TX_CLK, 587 CLKSRC_MII4_TX_CLK, 588 }; 589 590 if (regs->rmii_ref_clk[port] == SJA1105_RSV_ADDR) 591 return 0; 592 593 /* Payload for packed_buf */ 594 ref_clk.clksrc = clk_sources[port]; 595 ref_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 596 ref_clk.pd = 0; /* Power Down off => enabled */ 597 sja1105_cgu_mii_control_packing(packed_buf, &ref_clk, PACK); 598 599 return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ref_clk[port], 600 packed_buf, SJA1105_SIZE_CGU_CMD); 601 } 602 603 static int 604 sja1105_cgu_rmii_ext_tx_clk_config(struct sja1105_private *priv, int port) 605 { 606 const struct sja1105_regs *regs = priv->info->regs; 607 struct sja1105_cgu_mii_ctrl ext_tx_clk; 608 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 609 610 if (regs->rmii_ext_tx_clk[port] == SJA1105_RSV_ADDR) 611 return 0; 612 613 /* Payload for packed_buf */ 614 ext_tx_clk.clksrc = CLKSRC_PLL1; 615 ext_tx_clk.autoblock = 1; /* Autoblock clk while changing clksrc */ 616 ext_tx_clk.pd = 0; /* Power Down off => enabled */ 617 sja1105_cgu_mii_control_packing(packed_buf, &ext_tx_clk, PACK); 618 619 return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ext_tx_clk[port], 620 packed_buf, SJA1105_SIZE_CGU_CMD); 621 } 622 623 static int sja1105_cgu_rmii_pll_config(struct sja1105_private *priv) 624 { 625 const struct sja1105_regs *regs = priv->info->regs; 626 u8 packed_buf[SJA1105_SIZE_CGU_CMD] = {0}; 627 struct sja1105_cgu_pll_ctrl pll = {0}; 628 struct device *dev = priv->ds->dev; 629 int rc; 630 631 if (regs->rmii_pll1 == SJA1105_RSV_ADDR) 632 return 0; 633 634 /* PLL1 must be enabled and output 50 Mhz. 635 * This is done by writing first 0x0A010941 to 636 * the PLL_1_C register and then deasserting 637 * power down (PD) 0x0A010940. 638 */ 639 640 /* Step 1: PLL1 setup for 50Mhz */ 641 pll.pllclksrc = 0xA; 642 pll.msel = 0x1; 643 pll.autoblock = 0x1; 644 pll.psel = 0x1; 645 pll.direct = 0x0; 646 pll.fbsel = 0x1; 647 pll.bypass = 0x0; 648 pll.pd = 0x1; 649 650 sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK); 651 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf, 652 SJA1105_SIZE_CGU_CMD); 653 if (rc < 0) { 654 dev_err(dev, "failed to configure PLL1 for 50MHz\n"); 655 return rc; 656 } 657 658 /* Step 2: Enable PLL1 */ 659 pll.pd = 0x0; 660 661 sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK); 662 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf, 663 SJA1105_SIZE_CGU_CMD); 664 if (rc < 0) { 665 dev_err(dev, "failed to enable PLL1\n"); 666 return rc; 667 } 668 return rc; 669 } 670 671 static int sja1105_rmii_clocking_setup(struct sja1105_private *priv, int port, 672 sja1105_mii_role_t role) 673 { 674 struct device *dev = priv->ds->dev; 675 int rc; 676 677 dev_dbg(dev, "Configuring RMII-%s clocking\n", 678 (role == XMII_MAC) ? "MAC" : "PHY"); 679 /* AH1601.pdf chapter 2.5.1. Sources */ 680 if (role == XMII_MAC) { 681 /* Configure and enable PLL1 for 50Mhz output */ 682 rc = sja1105_cgu_rmii_pll_config(priv); 683 if (rc < 0) 684 return rc; 685 } 686 /* Disable IDIV for this port */ 687 rc = sja1105_cgu_idiv_config(priv, port, false, 1); 688 if (rc < 0) 689 return rc; 690 /* Source to sink mappings */ 691 rc = sja1105_cgu_rmii_ref_clk_config(priv, port); 692 if (rc < 0) 693 return rc; 694 if (role == XMII_MAC) { 695 rc = sja1105_cgu_rmii_ext_tx_clk_config(priv, port); 696 if (rc < 0) 697 return rc; 698 } 699 return 0; 700 } 701 702 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port) 703 { 704 struct sja1105_xmii_params_entry *mii; 705 struct device *dev = priv->ds->dev; 706 sja1105_phy_interface_t phy_mode; 707 sja1105_mii_role_t role; 708 int rc; 709 710 mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries; 711 712 /* RGMII etc */ 713 phy_mode = mii->xmii_mode[port]; 714 /* MAC or PHY, for applicable types (not RGMII) */ 715 role = mii->phy_mac[port]; 716 717 switch (phy_mode) { 718 case XMII_MODE_MII: 719 rc = sja1105_mii_clocking_setup(priv, port, role); 720 break; 721 case XMII_MODE_RMII: 722 rc = sja1105_rmii_clocking_setup(priv, port, role); 723 break; 724 case XMII_MODE_RGMII: 725 rc = sja1105_rgmii_clocking_setup(priv, port, role); 726 break; 727 case XMII_MODE_SGMII: 728 /* Nothing to do in the CGU for SGMII */ 729 rc = 0; 730 break; 731 default: 732 dev_err(dev, "Invalid interface mode specified: %d\n", 733 phy_mode); 734 return -EINVAL; 735 } 736 if (rc) { 737 dev_err(dev, "Clocking setup for port %d failed: %d\n", 738 port, rc); 739 return rc; 740 } 741 742 /* Internally pull down the RX_DV/CRS_DV/RX_CTL and RX_ER inputs */ 743 return sja1105_cfg_pad_rx_config(priv, port); 744 } 745 746 int sja1105_clocking_setup(struct sja1105_private *priv) 747 { 748 struct dsa_switch *ds = priv->ds; 749 int port, rc; 750 751 for (port = 0; port < ds->num_ports; port++) { 752 rc = sja1105_clocking_setup_port(priv, port); 753 if (rc < 0) 754 return rc; 755 } 756 return 0; 757 } 758