1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH 3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 4 */ 5 #ifndef _SJA1105_H 6 #define _SJA1105_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/timecounter.h> 10 #include <linux/dsa/sja1105.h> 11 #include <linux/dsa/8021q.h> 12 #include <net/dsa.h> 13 #include <linux/mutex.h> 14 #include "sja1105_static_config.h" 15 16 #define SJA1105_NUM_PORTS 5 17 #define SJA1105_NUM_TC 8 18 #define SJA1105ET_FDB_BIN_SIZE 4 19 /* The hardware value is in multiples of 10 ms. 20 * The passed parameter is in multiples of 1 ms. 21 */ 22 #define SJA1105_AGEING_TIME_MS(ms) ((ms) / 10) 23 #define SJA1105_NUM_L2_POLICERS 45 24 25 typedef enum { 26 SPI_READ = 0, 27 SPI_WRITE = 1, 28 } sja1105_spi_rw_mode_t; 29 30 #include "sja1105_tas.h" 31 #include "sja1105_ptp.h" 32 33 /* Keeps the different addresses between E/T and P/Q/R/S */ 34 struct sja1105_regs { 35 u64 device_id; 36 u64 prod_id; 37 u64 status; 38 u64 port_control; 39 u64 rgu; 40 u64 vl_status; 41 u64 config; 42 u64 sgmii; 43 u64 rmii_pll1; 44 u64 ptppinst; 45 u64 ptppindur; 46 u64 ptp_control; 47 u64 ptpclkval; 48 u64 ptpclkrate; 49 u64 ptpclkcorp; 50 u64 ptpsyncts; 51 u64 ptpschtm; 52 u64 ptpegr_ts[SJA1105_NUM_PORTS]; 53 u64 pad_mii_tx[SJA1105_NUM_PORTS]; 54 u64 pad_mii_rx[SJA1105_NUM_PORTS]; 55 u64 pad_mii_id[SJA1105_NUM_PORTS]; 56 u64 cgu_idiv[SJA1105_NUM_PORTS]; 57 u64 mii_tx_clk[SJA1105_NUM_PORTS]; 58 u64 mii_rx_clk[SJA1105_NUM_PORTS]; 59 u64 mii_ext_tx_clk[SJA1105_NUM_PORTS]; 60 u64 mii_ext_rx_clk[SJA1105_NUM_PORTS]; 61 u64 rgmii_tx_clk[SJA1105_NUM_PORTS]; 62 u64 rmii_ref_clk[SJA1105_NUM_PORTS]; 63 u64 rmii_ext_tx_clk[SJA1105_NUM_PORTS]; 64 u64 mac[SJA1105_NUM_PORTS]; 65 u64 mac_hl1[SJA1105_NUM_PORTS]; 66 u64 mac_hl2[SJA1105_NUM_PORTS]; 67 u64 ether_stats[SJA1105_NUM_PORTS]; 68 u64 qlevel[SJA1105_NUM_PORTS]; 69 }; 70 71 struct sja1105_info { 72 u64 device_id; 73 /* Needed for distinction between P and R, and between Q and S 74 * (since the parts with/without SGMII share the same 75 * switch core and device_id) 76 */ 77 u64 part_no; 78 /* E/T and P/Q/R/S have partial timestamps of different sizes. 79 * They must be reconstructed on both families anyway to get the full 80 * 64-bit values back. 81 */ 82 int ptp_ts_bits; 83 /* Also SPI commands are of different sizes to retrieve 84 * the egress timestamps. 85 */ 86 int ptpegr_ts_bytes; 87 const struct sja1105_dynamic_table_ops *dyn_ops; 88 const struct sja1105_table_ops *static_ops; 89 const struct sja1105_regs *regs; 90 int (*reset_cmd)(struct dsa_switch *ds); 91 int (*setup_rgmii_delay)(const void *ctx, int port); 92 /* Prototypes from include/net/dsa.h */ 93 int (*fdb_add_cmd)(struct dsa_switch *ds, int port, 94 const unsigned char *addr, u16 vid); 95 int (*fdb_del_cmd)(struct dsa_switch *ds, int port, 96 const unsigned char *addr, u16 vid); 97 void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd, 98 enum packing_op op); 99 const char *name; 100 }; 101 102 enum sja1105_key_type { 103 SJA1105_KEY_BCAST, 104 SJA1105_KEY_TC, 105 SJA1105_KEY_VLAN_UNAWARE_VL, 106 SJA1105_KEY_VLAN_AWARE_VL, 107 }; 108 109 struct sja1105_key { 110 enum sja1105_key_type type; 111 112 union { 113 /* SJA1105_KEY_TC */ 114 struct { 115 int pcp; 116 } tc; 117 118 /* SJA1105_KEY_VLAN_UNAWARE_VL */ 119 /* SJA1105_KEY_VLAN_AWARE_VL */ 120 struct { 121 u64 dmac; 122 u16 vid; 123 u16 pcp; 124 } vl; 125 }; 126 }; 127 128 enum sja1105_rule_type { 129 SJA1105_RULE_BCAST_POLICER, 130 SJA1105_RULE_TC_POLICER, 131 SJA1105_RULE_VL, 132 }; 133 134 enum sja1105_vl_type { 135 SJA1105_VL_NONCRITICAL, 136 SJA1105_VL_RATE_CONSTRAINED, 137 SJA1105_VL_TIME_TRIGGERED, 138 }; 139 140 struct sja1105_rule { 141 struct list_head list; 142 unsigned long cookie; 143 unsigned long port_mask; 144 struct sja1105_key key; 145 enum sja1105_rule_type type; 146 147 /* Action */ 148 union { 149 /* SJA1105_RULE_BCAST_POLICER */ 150 struct { 151 int sharindx; 152 } bcast_pol; 153 154 /* SJA1105_RULE_TC_POLICER */ 155 struct { 156 int sharindx; 157 } tc_pol; 158 159 /* SJA1105_RULE_VL */ 160 struct { 161 enum sja1105_vl_type type; 162 unsigned long destports; 163 int sharindx; 164 int maxlen; 165 int ipv; 166 u64 base_time; 167 u64 cycle_time; 168 int num_entries; 169 struct action_gate_entry *entries; 170 struct flow_stats stats; 171 } vl; 172 }; 173 }; 174 175 struct sja1105_flow_block { 176 struct list_head rules; 177 bool l2_policer_used[SJA1105_NUM_L2_POLICERS]; 178 int num_virtual_links; 179 }; 180 181 struct sja1105_private { 182 struct sja1105_static_config static_config; 183 bool rgmii_rx_delay[SJA1105_NUM_PORTS]; 184 bool rgmii_tx_delay[SJA1105_NUM_PORTS]; 185 const struct sja1105_info *info; 186 struct gpio_desc *reset_gpio; 187 struct spi_device *spidev; 188 struct dsa_switch *ds; 189 struct list_head crosschip_links; 190 struct sja1105_flow_block flow_block; 191 struct sja1105_port ports[SJA1105_NUM_PORTS]; 192 /* Serializes transmission of management frames so that 193 * the switch doesn't confuse them with one another. 194 */ 195 struct mutex mgmt_lock; 196 struct sja1105_tagger_data tagger_data; 197 struct sja1105_ptp_data ptp_data; 198 struct sja1105_tas_data tas_data; 199 }; 200 201 #include "sja1105_dynamic_config.h" 202 203 struct sja1105_spi_message { 204 u64 access; 205 u64 read_count; 206 u64 address; 207 }; 208 209 /* From sja1105_main.c */ 210 enum sja1105_reset_reason { 211 SJA1105_VLAN_FILTERING = 0, 212 SJA1105_RX_HWTSTAMPING, 213 SJA1105_AGEING_TIME, 214 SJA1105_SCHEDULING, 215 SJA1105_BEST_EFFORT_POLICING, 216 SJA1105_VIRTUAL_LINKS, 217 }; 218 219 int sja1105_static_config_reload(struct sja1105_private *priv, 220 enum sja1105_reset_reason reason); 221 222 /* From sja1105_spi.c */ 223 int sja1105_xfer_buf(const struct sja1105_private *priv, 224 sja1105_spi_rw_mode_t rw, u64 reg_addr, 225 u8 *buf, size_t len); 226 int sja1105_xfer_u32(const struct sja1105_private *priv, 227 sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value, 228 struct ptp_system_timestamp *ptp_sts); 229 int sja1105_xfer_u64(const struct sja1105_private *priv, 230 sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value, 231 struct ptp_system_timestamp *ptp_sts); 232 int sja1105_static_config_upload(struct sja1105_private *priv); 233 int sja1105_inhibit_tx(const struct sja1105_private *priv, 234 unsigned long port_bitmap, bool tx_inhibited); 235 236 extern struct sja1105_info sja1105e_info; 237 extern struct sja1105_info sja1105t_info; 238 extern struct sja1105_info sja1105p_info; 239 extern struct sja1105_info sja1105q_info; 240 extern struct sja1105_info sja1105r_info; 241 extern struct sja1105_info sja1105s_info; 242 243 /* From sja1105_clocking.c */ 244 245 typedef enum { 246 XMII_MAC = 0, 247 XMII_PHY = 1, 248 } sja1105_mii_role_t; 249 250 typedef enum { 251 XMII_MODE_MII = 0, 252 XMII_MODE_RMII = 1, 253 XMII_MODE_RGMII = 2, 254 XMII_MODE_SGMII = 3, 255 } sja1105_phy_interface_t; 256 257 typedef enum { 258 SJA1105_SPEED_10MBPS = 3, 259 SJA1105_SPEED_100MBPS = 2, 260 SJA1105_SPEED_1000MBPS = 1, 261 SJA1105_SPEED_AUTO = 0, 262 } sja1105_speed_t; 263 264 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port); 265 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port); 266 int sja1105_clocking_setup(struct sja1105_private *priv); 267 268 /* From sja1105_ethtool.c */ 269 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data); 270 void sja1105_get_strings(struct dsa_switch *ds, int port, 271 u32 stringset, u8 *data); 272 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset); 273 274 /* From sja1105_dynamic_config.c */ 275 int sja1105_dynamic_config_read(struct sja1105_private *priv, 276 enum sja1105_blk_idx blk_idx, 277 int index, void *entry); 278 int sja1105_dynamic_config_write(struct sja1105_private *priv, 279 enum sja1105_blk_idx blk_idx, 280 int index, void *entry, bool keep); 281 282 enum sja1105_iotag { 283 SJA1105_C_TAG = 0, /* Inner VLAN header */ 284 SJA1105_S_TAG = 1, /* Outer VLAN header */ 285 }; 286 287 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid); 288 int sja1105et_fdb_add(struct dsa_switch *ds, int port, 289 const unsigned char *addr, u16 vid); 290 int sja1105et_fdb_del(struct dsa_switch *ds, int port, 291 const unsigned char *addr, u16 vid); 292 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, 293 const unsigned char *addr, u16 vid); 294 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, 295 const unsigned char *addr, u16 vid); 296 297 /* Common implementations for the static and dynamic configs */ 298 size_t sja1105_l2_forwarding_entry_packing(void *buf, void *entry_ptr, 299 enum packing_op op); 300 size_t sja1105pqrs_l2_lookup_entry_packing(void *buf, void *entry_ptr, 301 enum packing_op op); 302 size_t sja1105et_l2_lookup_entry_packing(void *buf, void *entry_ptr, 303 enum packing_op op); 304 size_t sja1105_vlan_lookup_entry_packing(void *buf, void *entry_ptr, 305 enum packing_op op); 306 size_t sja1105pqrs_mac_config_entry_packing(void *buf, void *entry_ptr, 307 enum packing_op op); 308 size_t sja1105pqrs_avb_params_entry_packing(void *buf, void *entry_ptr, 309 enum packing_op op); 310 size_t sja1105_vl_lookup_entry_packing(void *buf, void *entry_ptr, 311 enum packing_op op); 312 313 /* From sja1105_flower.c */ 314 int sja1105_cls_flower_del(struct dsa_switch *ds, int port, 315 struct flow_cls_offload *cls, bool ingress); 316 int sja1105_cls_flower_add(struct dsa_switch *ds, int port, 317 struct flow_cls_offload *cls, bool ingress); 318 int sja1105_cls_flower_stats(struct dsa_switch *ds, int port, 319 struct flow_cls_offload *cls, bool ingress); 320 void sja1105_flower_setup(struct dsa_switch *ds); 321 void sja1105_flower_teardown(struct dsa_switch *ds); 322 struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv, 323 unsigned long cookie); 324 325 #endif 326