1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH 3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com> 4 */ 5 #ifndef _SJA1105_H 6 #define _SJA1105_H 7 8 #include <linux/ptp_clock_kernel.h> 9 #include <linux/timecounter.h> 10 #include <linux/dsa/sja1105.h> 11 #include <net/dsa.h> 12 #include <linux/mutex.h> 13 #include "sja1105_static_config.h" 14 15 #define SJA1105_NUM_PORTS 5 16 #define SJA1105_NUM_TC 8 17 #define SJA1105ET_FDB_BIN_SIZE 4 18 /* The hardware value is in multiples of 10 ms. 19 * The passed parameter is in multiples of 1 ms. 20 */ 21 #define SJA1105_AGEING_TIME_MS(ms) ((ms) / 10) 22 23 typedef enum { 24 SPI_READ = 0, 25 SPI_WRITE = 1, 26 } sja1105_spi_rw_mode_t; 27 28 #include "sja1105_tas.h" 29 #include "sja1105_ptp.h" 30 31 /* Keeps the different addresses between E/T and P/Q/R/S */ 32 struct sja1105_regs { 33 u64 device_id; 34 u64 prod_id; 35 u64 status; 36 u64 port_control; 37 u64 rgu; 38 u64 config; 39 u64 sgmii; 40 u64 rmii_pll1; 41 u64 ptppinst; 42 u64 ptppindur; 43 u64 ptp_control; 44 u64 ptpclkval; 45 u64 ptpclkrate; 46 u64 ptpclkcorp; 47 u64 ptpsyncts; 48 u64 ptpschtm; 49 u64 ptpegr_ts[SJA1105_NUM_PORTS]; 50 u64 pad_mii_tx[SJA1105_NUM_PORTS]; 51 u64 pad_mii_id[SJA1105_NUM_PORTS]; 52 u64 cgu_idiv[SJA1105_NUM_PORTS]; 53 u64 mii_tx_clk[SJA1105_NUM_PORTS]; 54 u64 mii_rx_clk[SJA1105_NUM_PORTS]; 55 u64 mii_ext_tx_clk[SJA1105_NUM_PORTS]; 56 u64 mii_ext_rx_clk[SJA1105_NUM_PORTS]; 57 u64 rgmii_tx_clk[SJA1105_NUM_PORTS]; 58 u64 rmii_ref_clk[SJA1105_NUM_PORTS]; 59 u64 rmii_ext_tx_clk[SJA1105_NUM_PORTS]; 60 u64 mac[SJA1105_NUM_PORTS]; 61 u64 mac_hl1[SJA1105_NUM_PORTS]; 62 u64 mac_hl2[SJA1105_NUM_PORTS]; 63 u64 qlevel[SJA1105_NUM_PORTS]; 64 }; 65 66 struct sja1105_info { 67 u64 device_id; 68 /* Needed for distinction between P and R, and between Q and S 69 * (since the parts with/without SGMII share the same 70 * switch core and device_id) 71 */ 72 u64 part_no; 73 /* E/T and P/Q/R/S have partial timestamps of different sizes. 74 * They must be reconstructed on both families anyway to get the full 75 * 64-bit values back. 76 */ 77 int ptp_ts_bits; 78 /* Also SPI commands are of different sizes to retrieve 79 * the egress timestamps. 80 */ 81 int ptpegr_ts_bytes; 82 const struct sja1105_dynamic_table_ops *dyn_ops; 83 const struct sja1105_table_ops *static_ops; 84 const struct sja1105_regs *regs; 85 int (*reset_cmd)(struct dsa_switch *ds); 86 int (*setup_rgmii_delay)(const void *ctx, int port); 87 /* Prototypes from include/net/dsa.h */ 88 int (*fdb_add_cmd)(struct dsa_switch *ds, int port, 89 const unsigned char *addr, u16 vid); 90 int (*fdb_del_cmd)(struct dsa_switch *ds, int port, 91 const unsigned char *addr, u16 vid); 92 void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd, 93 enum packing_op op); 94 const char *name; 95 }; 96 97 struct sja1105_private { 98 struct sja1105_static_config static_config; 99 bool rgmii_rx_delay[SJA1105_NUM_PORTS]; 100 bool rgmii_tx_delay[SJA1105_NUM_PORTS]; 101 const struct sja1105_info *info; 102 struct gpio_desc *reset_gpio; 103 struct spi_device *spidev; 104 struct dsa_switch *ds; 105 struct sja1105_port ports[SJA1105_NUM_PORTS]; 106 /* Serializes transmission of management frames so that 107 * the switch doesn't confuse them with one another. 108 */ 109 struct mutex mgmt_lock; 110 struct sja1105_tagger_data tagger_data; 111 struct sja1105_ptp_data ptp_data; 112 struct sja1105_tas_data tas_data; 113 }; 114 115 #include "sja1105_dynamic_config.h" 116 117 struct sja1105_spi_message { 118 u64 access; 119 u64 read_count; 120 u64 address; 121 }; 122 123 /* From sja1105_main.c */ 124 enum sja1105_reset_reason { 125 SJA1105_VLAN_FILTERING = 0, 126 SJA1105_RX_HWTSTAMPING, 127 SJA1105_AGEING_TIME, 128 SJA1105_SCHEDULING, 129 }; 130 131 int sja1105_static_config_reload(struct sja1105_private *priv, 132 enum sja1105_reset_reason reason); 133 134 /* From sja1105_spi.c */ 135 int sja1105_xfer_buf(const struct sja1105_private *priv, 136 sja1105_spi_rw_mode_t rw, u64 reg_addr, 137 u8 *buf, size_t len); 138 int sja1105_xfer_u32(const struct sja1105_private *priv, 139 sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value, 140 struct ptp_system_timestamp *ptp_sts); 141 int sja1105_xfer_u64(const struct sja1105_private *priv, 142 sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value, 143 struct ptp_system_timestamp *ptp_sts); 144 int sja1105_static_config_upload(struct sja1105_private *priv); 145 int sja1105_inhibit_tx(const struct sja1105_private *priv, 146 unsigned long port_bitmap, bool tx_inhibited); 147 148 extern struct sja1105_info sja1105e_info; 149 extern struct sja1105_info sja1105t_info; 150 extern struct sja1105_info sja1105p_info; 151 extern struct sja1105_info sja1105q_info; 152 extern struct sja1105_info sja1105r_info; 153 extern struct sja1105_info sja1105s_info; 154 155 /* From sja1105_clocking.c */ 156 157 typedef enum { 158 XMII_MAC = 0, 159 XMII_PHY = 1, 160 } sja1105_mii_role_t; 161 162 typedef enum { 163 XMII_MODE_MII = 0, 164 XMII_MODE_RMII = 1, 165 XMII_MODE_RGMII = 2, 166 XMII_MODE_SGMII = 3, 167 } sja1105_phy_interface_t; 168 169 typedef enum { 170 SJA1105_SPEED_10MBPS = 3, 171 SJA1105_SPEED_100MBPS = 2, 172 SJA1105_SPEED_1000MBPS = 1, 173 SJA1105_SPEED_AUTO = 0, 174 } sja1105_speed_t; 175 176 int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port); 177 int sja1105_clocking_setup_port(struct sja1105_private *priv, int port); 178 int sja1105_clocking_setup(struct sja1105_private *priv); 179 180 /* From sja1105_ethtool.c */ 181 void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data); 182 void sja1105_get_strings(struct dsa_switch *ds, int port, 183 u32 stringset, u8 *data); 184 int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset); 185 186 /* From sja1105_dynamic_config.c */ 187 int sja1105_dynamic_config_read(struct sja1105_private *priv, 188 enum sja1105_blk_idx blk_idx, 189 int index, void *entry); 190 int sja1105_dynamic_config_write(struct sja1105_private *priv, 191 enum sja1105_blk_idx blk_idx, 192 int index, void *entry, bool keep); 193 194 enum sja1105_iotag { 195 SJA1105_C_TAG = 0, /* Inner VLAN header */ 196 SJA1105_S_TAG = 1, /* Outer VLAN header */ 197 }; 198 199 u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid); 200 int sja1105et_fdb_add(struct dsa_switch *ds, int port, 201 const unsigned char *addr, u16 vid); 202 int sja1105et_fdb_del(struct dsa_switch *ds, int port, 203 const unsigned char *addr, u16 vid); 204 int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port, 205 const unsigned char *addr, u16 vid); 206 int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port, 207 const unsigned char *addr, u16 vid); 208 209 /* Common implementations for the static and dynamic configs */ 210 size_t sja1105_l2_forwarding_entry_packing(void *buf, void *entry_ptr, 211 enum packing_op op); 212 size_t sja1105pqrs_l2_lookup_entry_packing(void *buf, void *entry_ptr, 213 enum packing_op op); 214 size_t sja1105et_l2_lookup_entry_packing(void *buf, void *entry_ptr, 215 enum packing_op op); 216 size_t sja1105_vlan_lookup_entry_packing(void *buf, void *entry_ptr, 217 enum packing_op op); 218 size_t sja1105pqrs_mac_config_entry_packing(void *buf, void *entry_ptr, 219 enum packing_op op); 220 size_t sja1105pqrs_avb_params_entry_packing(void *buf, void *entry_ptr, 221 enum packing_op op); 222 223 #endif 224