1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
3  *
4  * This is a sparsely documented chip, the only viable documentation seems
5  * to be a patched up code drop from the vendor that appear in various
6  * GPL source trees.
7  *
8  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
9  * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
10  * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
11  * Copyright (C) 2010 Roman Yeryomin <roman@advem.lv>
12  * Copyright (C) 2011 Colin Leitner <colin.leitner@googlemail.com>
13  */
14 
15 #include <linux/bitops.h>
16 #include <linux/etherdevice.h>
17 #include <linux/if_bridge.h>
18 #include <linux/interrupt.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/of_irq.h>
22 #include <linux/regmap.h>
23 
24 #include "realtek.h"
25 
26 #define RTL8366RB_PORT_NUM_CPU		5
27 #define RTL8366RB_NUM_PORTS		6
28 #define RTL8366RB_PHY_NO_MAX		4
29 #define RTL8366RB_PHY_ADDR_MAX		31
30 
31 /* Switch Global Configuration register */
32 #define RTL8366RB_SGCR				0x0000
33 #define RTL8366RB_SGCR_EN_BC_STORM_CTRL		BIT(0)
34 #define RTL8366RB_SGCR_MAX_LENGTH(a)		((a) << 4)
35 #define RTL8366RB_SGCR_MAX_LENGTH_MASK		RTL8366RB_SGCR_MAX_LENGTH(0x3)
36 #define RTL8366RB_SGCR_MAX_LENGTH_1522		RTL8366RB_SGCR_MAX_LENGTH(0x0)
37 #define RTL8366RB_SGCR_MAX_LENGTH_1536		RTL8366RB_SGCR_MAX_LENGTH(0x1)
38 #define RTL8366RB_SGCR_MAX_LENGTH_1552		RTL8366RB_SGCR_MAX_LENGTH(0x2)
39 #define RTL8366RB_SGCR_MAX_LENGTH_16000		RTL8366RB_SGCR_MAX_LENGTH(0x3)
40 #define RTL8366RB_SGCR_EN_VLAN			BIT(13)
41 #define RTL8366RB_SGCR_EN_VLAN_4KTB		BIT(14)
42 
43 /* Port Enable Control register */
44 #define RTL8366RB_PECR				0x0001
45 
46 /* Switch per-port learning disablement register */
47 #define RTL8366RB_PORT_LEARNDIS_CTRL		0x0002
48 
49 /* Security control, actually aging register */
50 #define RTL8366RB_SECURITY_CTRL			0x0003
51 
52 #define RTL8366RB_SSCR2				0x0004
53 #define RTL8366RB_SSCR2_DROP_UNKNOWN_DA		BIT(0)
54 
55 /* Port Mode Control registers */
56 #define RTL8366RB_PMC0				0x0005
57 #define RTL8366RB_PMC0_SPI			BIT(0)
58 #define RTL8366RB_PMC0_EN_AUTOLOAD		BIT(1)
59 #define RTL8366RB_PMC0_PROBE			BIT(2)
60 #define RTL8366RB_PMC0_DIS_BISR			BIT(3)
61 #define RTL8366RB_PMC0_ADCTEST			BIT(4)
62 #define RTL8366RB_PMC0_SRAM_DIAG		BIT(5)
63 #define RTL8366RB_PMC0_EN_SCAN			BIT(6)
64 #define RTL8366RB_PMC0_P4_IOMODE_SHIFT		7
65 #define RTL8366RB_PMC0_P4_IOMODE_MASK		GENMASK(9, 7)
66 #define RTL8366RB_PMC0_P5_IOMODE_SHIFT		10
67 #define RTL8366RB_PMC0_P5_IOMODE_MASK		GENMASK(12, 10)
68 #define RTL8366RB_PMC0_SDSMODE_SHIFT		13
69 #define RTL8366RB_PMC0_SDSMODE_MASK		GENMASK(15, 13)
70 #define RTL8366RB_PMC1				0x0006
71 
72 /* Port Mirror Control Register */
73 #define RTL8366RB_PMCR				0x0007
74 #define RTL8366RB_PMCR_SOURCE_PORT(a)		(a)
75 #define RTL8366RB_PMCR_SOURCE_PORT_MASK		0x000f
76 #define RTL8366RB_PMCR_MONITOR_PORT(a)		((a) << 4)
77 #define RTL8366RB_PMCR_MONITOR_PORT_MASK	0x00f0
78 #define RTL8366RB_PMCR_MIRROR_RX		BIT(8)
79 #define RTL8366RB_PMCR_MIRROR_TX		BIT(9)
80 #define RTL8366RB_PMCR_MIRROR_SPC		BIT(10)
81 #define RTL8366RB_PMCR_MIRROR_ISO		BIT(11)
82 
83 /* bits 0..7 = port 0, bits 8..15 = port 1 */
84 #define RTL8366RB_PAACR0		0x0010
85 /* bits 0..7 = port 2, bits 8..15 = port 3 */
86 #define RTL8366RB_PAACR1		0x0011
87 /* bits 0..7 = port 4, bits 8..15 = port 5 */
88 #define RTL8366RB_PAACR2		0x0012
89 #define RTL8366RB_PAACR_SPEED_10M	0
90 #define RTL8366RB_PAACR_SPEED_100M	1
91 #define RTL8366RB_PAACR_SPEED_1000M	2
92 #define RTL8366RB_PAACR_FULL_DUPLEX	BIT(2)
93 #define RTL8366RB_PAACR_LINK_UP		BIT(4)
94 #define RTL8366RB_PAACR_TX_PAUSE	BIT(5)
95 #define RTL8366RB_PAACR_RX_PAUSE	BIT(6)
96 #define RTL8366RB_PAACR_AN		BIT(7)
97 
98 #define RTL8366RB_PAACR_CPU_PORT	(RTL8366RB_PAACR_SPEED_1000M | \
99 					 RTL8366RB_PAACR_FULL_DUPLEX | \
100 					 RTL8366RB_PAACR_LINK_UP | \
101 					 RTL8366RB_PAACR_TX_PAUSE | \
102 					 RTL8366RB_PAACR_RX_PAUSE)
103 
104 /* bits 0..7 = port 0, bits 8..15 = port 1 */
105 #define RTL8366RB_PSTAT0		0x0014
106 /* bits 0..7 = port 2, bits 8..15 = port 3 */
107 #define RTL8366RB_PSTAT1		0x0015
108 /* bits 0..7 = port 4, bits 8..15 = port 5 */
109 #define RTL8366RB_PSTAT2		0x0016
110 
111 #define RTL8366RB_POWER_SAVING_REG	0x0021
112 
113 /* Spanning tree status (STP) control, two bits per port per FID */
114 #define RTL8366RB_STP_STATE_BASE	0x0050 /* 0x0050..0x0057 */
115 #define RTL8366RB_STP_STATE_DISABLED	0x0
116 #define RTL8366RB_STP_STATE_BLOCKING	0x1
117 #define RTL8366RB_STP_STATE_LEARNING	0x2
118 #define RTL8366RB_STP_STATE_FORWARDING	0x3
119 #define RTL8366RB_STP_MASK		GENMASK(1, 0)
120 #define RTL8366RB_STP_STATE(port, state) \
121 	((state) << ((port) * 2))
122 #define RTL8366RB_STP_STATE_MASK(port) \
123 	RTL8366RB_STP_STATE((port), RTL8366RB_STP_MASK)
124 
125 /* CPU port control reg */
126 #define RTL8368RB_CPU_CTRL_REG		0x0061
127 #define RTL8368RB_CPU_PORTS_MSK		0x00FF
128 /* Disables inserting custom tag length/type 0x8899 */
129 #define RTL8368RB_CPU_NO_TAG		BIT(15)
130 
131 #define RTL8366RB_SMAR0			0x0070 /* bits 0..15 */
132 #define RTL8366RB_SMAR1			0x0071 /* bits 16..31 */
133 #define RTL8366RB_SMAR2			0x0072 /* bits 32..47 */
134 
135 #define RTL8366RB_RESET_CTRL_REG		0x0100
136 #define RTL8366RB_CHIP_CTRL_RESET_HW		BIT(0)
137 #define RTL8366RB_CHIP_CTRL_RESET_SW		BIT(1)
138 
139 #define RTL8366RB_CHIP_ID_REG			0x0509
140 #define RTL8366RB_CHIP_ID_8366			0x5937
141 #define RTL8366RB_CHIP_VERSION_CTRL_REG		0x050A
142 #define RTL8366RB_CHIP_VERSION_MASK		0xf
143 
144 /* PHY registers control */
145 #define RTL8366RB_PHY_ACCESS_CTRL_REG		0x8000
146 #define RTL8366RB_PHY_CTRL_READ			BIT(0)
147 #define RTL8366RB_PHY_CTRL_WRITE		0
148 #define RTL8366RB_PHY_ACCESS_BUSY_REG		0x8001
149 #define RTL8366RB_PHY_INT_BUSY			BIT(0)
150 #define RTL8366RB_PHY_EXT_BUSY			BIT(4)
151 #define RTL8366RB_PHY_ACCESS_DATA_REG		0x8002
152 #define RTL8366RB_PHY_EXT_CTRL_REG		0x8010
153 #define RTL8366RB_PHY_EXT_WRDATA_REG		0x8011
154 #define RTL8366RB_PHY_EXT_RDDATA_REG		0x8012
155 
156 #define RTL8366RB_PHY_REG_MASK			0x1f
157 #define RTL8366RB_PHY_PAGE_OFFSET		5
158 #define RTL8366RB_PHY_PAGE_MASK			(0xf << 5)
159 #define RTL8366RB_PHY_NO_OFFSET			9
160 #define RTL8366RB_PHY_NO_MASK			(0x1f << 9)
161 
162 /* VLAN Ingress Control Register 1, one bit per port.
163  * bit 0 .. 5 will make the switch drop ingress frames without
164  * VID such as untagged or priority-tagged frames for respective
165  * port.
166  * bit 6 .. 11 will make the switch drop ingress frames carrying
167  * a C-tag with VID != 0 for respective port.
168  */
169 #define RTL8366RB_VLAN_INGRESS_CTRL1_REG	0x037E
170 #define RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port)	(BIT((port)) | BIT((port) + 6))
171 
172 /* VLAN Ingress Control Register 2, one bit per port.
173  * bit0 .. bit5 will make the switch drop all ingress frames with
174  * a VLAN classification that does not include the port is in its
175  * member set.
176  */
177 #define RTL8366RB_VLAN_INGRESS_CTRL2_REG	0x037f
178 
179 /* LED control registers */
180 #define RTL8366RB_LED_BLINKRATE_REG		0x0430
181 #define RTL8366RB_LED_BLINKRATE_MASK		0x0007
182 #define RTL8366RB_LED_BLINKRATE_28MS		0x0000
183 #define RTL8366RB_LED_BLINKRATE_56MS		0x0001
184 #define RTL8366RB_LED_BLINKRATE_84MS		0x0002
185 #define RTL8366RB_LED_BLINKRATE_111MS		0x0003
186 #define RTL8366RB_LED_BLINKRATE_222MS		0x0004
187 #define RTL8366RB_LED_BLINKRATE_446MS		0x0005
188 
189 #define RTL8366RB_LED_CTRL_REG			0x0431
190 #define RTL8366RB_LED_OFF			0x0
191 #define RTL8366RB_LED_DUP_COL			0x1
192 #define RTL8366RB_LED_LINK_ACT			0x2
193 #define RTL8366RB_LED_SPD1000			0x3
194 #define RTL8366RB_LED_SPD100			0x4
195 #define RTL8366RB_LED_SPD10			0x5
196 #define RTL8366RB_LED_SPD1000_ACT		0x6
197 #define RTL8366RB_LED_SPD100_ACT		0x7
198 #define RTL8366RB_LED_SPD10_ACT			0x8
199 #define RTL8366RB_LED_SPD100_10_ACT		0x9
200 #define RTL8366RB_LED_FIBER			0xa
201 #define RTL8366RB_LED_AN_FAULT			0xb
202 #define RTL8366RB_LED_LINK_RX			0xc
203 #define RTL8366RB_LED_LINK_TX			0xd
204 #define RTL8366RB_LED_MASTER			0xe
205 #define RTL8366RB_LED_FORCE			0xf
206 #define RTL8366RB_LED_0_1_CTRL_REG		0x0432
207 #define RTL8366RB_LED_1_OFFSET			6
208 #define RTL8366RB_LED_2_3_CTRL_REG		0x0433
209 #define RTL8366RB_LED_3_OFFSET			6
210 
211 #define RTL8366RB_MIB_COUNT			33
212 #define RTL8366RB_GLOBAL_MIB_COUNT		1
213 #define RTL8366RB_MIB_COUNTER_PORT_OFFSET	0x0050
214 #define RTL8366RB_MIB_COUNTER_BASE		0x1000
215 #define RTL8366RB_MIB_CTRL_REG			0x13F0
216 #define RTL8366RB_MIB_CTRL_USER_MASK		0x0FFC
217 #define RTL8366RB_MIB_CTRL_BUSY_MASK		BIT(0)
218 #define RTL8366RB_MIB_CTRL_RESET_MASK		BIT(1)
219 #define RTL8366RB_MIB_CTRL_PORT_RESET(_p)	BIT(2 + (_p))
220 #define RTL8366RB_MIB_CTRL_GLOBAL_RESET		BIT(11)
221 
222 #define RTL8366RB_PORT_VLAN_CTRL_BASE		0x0063
223 #define RTL8366RB_PORT_VLAN_CTRL_REG(_p)  \
224 		(RTL8366RB_PORT_VLAN_CTRL_BASE + (_p) / 4)
225 #define RTL8366RB_PORT_VLAN_CTRL_MASK		0xf
226 #define RTL8366RB_PORT_VLAN_CTRL_SHIFT(_p)	(4 * ((_p) % 4))
227 
228 #define RTL8366RB_VLAN_TABLE_READ_BASE		0x018C
229 #define RTL8366RB_VLAN_TABLE_WRITE_BASE		0x0185
230 
231 #define RTL8366RB_TABLE_ACCESS_CTRL_REG		0x0180
232 #define RTL8366RB_TABLE_VLAN_READ_CTRL		0x0E01
233 #define RTL8366RB_TABLE_VLAN_WRITE_CTRL		0x0F01
234 
235 #define RTL8366RB_VLAN_MC_BASE(_x)		(0x0020 + (_x) * 3)
236 
237 #define RTL8366RB_PORT_LINK_STATUS_BASE		0x0014
238 #define RTL8366RB_PORT_STATUS_SPEED_MASK	0x0003
239 #define RTL8366RB_PORT_STATUS_DUPLEX_MASK	0x0004
240 #define RTL8366RB_PORT_STATUS_LINK_MASK		0x0010
241 #define RTL8366RB_PORT_STATUS_TXPAUSE_MASK	0x0020
242 #define RTL8366RB_PORT_STATUS_RXPAUSE_MASK	0x0040
243 #define RTL8366RB_PORT_STATUS_AN_MASK		0x0080
244 
245 #define RTL8366RB_NUM_VLANS		16
246 #define RTL8366RB_NUM_LEDGROUPS		4
247 #define RTL8366RB_NUM_VIDS		4096
248 #define RTL8366RB_PRIORITYMAX		7
249 #define RTL8366RB_NUM_FIDS		8
250 #define RTL8366RB_FIDMAX		7
251 
252 #define RTL8366RB_PORT_1		BIT(0) /* In userspace port 0 */
253 #define RTL8366RB_PORT_2		BIT(1) /* In userspace port 1 */
254 #define RTL8366RB_PORT_3		BIT(2) /* In userspace port 2 */
255 #define RTL8366RB_PORT_4		BIT(3) /* In userspace port 3 */
256 #define RTL8366RB_PORT_5		BIT(4) /* In userspace port 4 */
257 
258 #define RTL8366RB_PORT_CPU		BIT(5) /* CPU port */
259 
260 #define RTL8366RB_PORT_ALL		(RTL8366RB_PORT_1 |	\
261 					 RTL8366RB_PORT_2 |	\
262 					 RTL8366RB_PORT_3 |	\
263 					 RTL8366RB_PORT_4 |	\
264 					 RTL8366RB_PORT_5 |	\
265 					 RTL8366RB_PORT_CPU)
266 
267 #define RTL8366RB_PORT_ALL_BUT_CPU	(RTL8366RB_PORT_1 |	\
268 					 RTL8366RB_PORT_2 |	\
269 					 RTL8366RB_PORT_3 |	\
270 					 RTL8366RB_PORT_4 |	\
271 					 RTL8366RB_PORT_5)
272 
273 #define RTL8366RB_PORT_ALL_EXTERNAL	(RTL8366RB_PORT_1 |	\
274 					 RTL8366RB_PORT_2 |	\
275 					 RTL8366RB_PORT_3 |	\
276 					 RTL8366RB_PORT_4)
277 
278 #define RTL8366RB_PORT_ALL_INTERNAL	 RTL8366RB_PORT_CPU
279 
280 /* First configuration word per member config, VID and prio */
281 #define RTL8366RB_VLAN_VID_MASK		0xfff
282 #define RTL8366RB_VLAN_PRIORITY_SHIFT	12
283 #define RTL8366RB_VLAN_PRIORITY_MASK	0x7
284 /* Second configuration word per member config, member and untagged */
285 #define RTL8366RB_VLAN_UNTAG_SHIFT	8
286 #define RTL8366RB_VLAN_UNTAG_MASK	0xff
287 #define RTL8366RB_VLAN_MEMBER_MASK	0xff
288 /* Third config word per member config, STAG currently unused */
289 #define RTL8366RB_VLAN_STAG_MBR_MASK	0xff
290 #define RTL8366RB_VLAN_STAG_MBR_SHIFT	8
291 #define RTL8366RB_VLAN_STAG_IDX_MASK	0x7
292 #define RTL8366RB_VLAN_STAG_IDX_SHIFT	5
293 #define RTL8366RB_VLAN_FID_MASK		0x7
294 
295 /* Port ingress bandwidth control */
296 #define RTL8366RB_IB_BASE		0x0200
297 #define RTL8366RB_IB_REG(pnum)		(RTL8366RB_IB_BASE + (pnum))
298 #define RTL8366RB_IB_BDTH_MASK		0x3fff
299 #define RTL8366RB_IB_PREIFG		BIT(14)
300 
301 /* Port egress bandwidth control */
302 #define RTL8366RB_EB_BASE		0x02d1
303 #define RTL8366RB_EB_REG(pnum)		(RTL8366RB_EB_BASE + (pnum))
304 #define RTL8366RB_EB_BDTH_MASK		0x3fff
305 #define RTL8366RB_EB_PREIFG_REG		0x02f8
306 #define RTL8366RB_EB_PREIFG		BIT(9)
307 
308 #define RTL8366RB_BDTH_SW_MAX		1048512 /* 1048576? */
309 #define RTL8366RB_BDTH_UNIT		64
310 #define RTL8366RB_BDTH_REG_DEFAULT	16383
311 
312 /* QOS */
313 #define RTL8366RB_QOS			BIT(15)
314 /* Include/Exclude Preamble and IFG (20 bytes). 0:Exclude, 1:Include. */
315 #define RTL8366RB_QOS_DEFAULT_PREIFG	1
316 
317 /* Interrupt handling */
318 #define RTL8366RB_INTERRUPT_CONTROL_REG	0x0440
319 #define RTL8366RB_INTERRUPT_POLARITY	BIT(0)
320 #define RTL8366RB_P4_RGMII_LED		BIT(2)
321 #define RTL8366RB_INTERRUPT_MASK_REG	0x0441
322 #define RTL8366RB_INTERRUPT_LINK_CHGALL	GENMASK(11, 0)
323 #define RTL8366RB_INTERRUPT_ACLEXCEED	BIT(8)
324 #define RTL8366RB_INTERRUPT_STORMEXCEED	BIT(9)
325 #define RTL8366RB_INTERRUPT_P4_FIBER	BIT(12)
326 #define RTL8366RB_INTERRUPT_P4_UTP	BIT(13)
327 #define RTL8366RB_INTERRUPT_VALID	(RTL8366RB_INTERRUPT_LINK_CHGALL | \
328 					 RTL8366RB_INTERRUPT_ACLEXCEED | \
329 					 RTL8366RB_INTERRUPT_STORMEXCEED | \
330 					 RTL8366RB_INTERRUPT_P4_FIBER | \
331 					 RTL8366RB_INTERRUPT_P4_UTP)
332 #define RTL8366RB_INTERRUPT_STATUS_REG	0x0442
333 #define RTL8366RB_NUM_INTERRUPT		14 /* 0..13 */
334 
335 /* Port isolation registers */
336 #define RTL8366RB_PORT_ISO_BASE		0x0F08
337 #define RTL8366RB_PORT_ISO(pnum)	(RTL8366RB_PORT_ISO_BASE + (pnum))
338 #define RTL8366RB_PORT_ISO_EN		BIT(0)
339 #define RTL8366RB_PORT_ISO_PORTS_MASK	GENMASK(7, 1)
340 #define RTL8366RB_PORT_ISO_PORTS(pmask)	((pmask) << 1)
341 
342 /* bits 0..5 enable force when cleared */
343 #define RTL8366RB_MAC_FORCE_CTRL_REG	0x0F11
344 
345 #define RTL8366RB_OAM_PARSER_REG	0x0F14
346 #define RTL8366RB_OAM_MULTIPLEXER_REG	0x0F15
347 
348 #define RTL8366RB_GREEN_FEATURE_REG	0x0F51
349 #define RTL8366RB_GREEN_FEATURE_MSK	0x0007
350 #define RTL8366RB_GREEN_FEATURE_TX	BIT(0)
351 #define RTL8366RB_GREEN_FEATURE_RX	BIT(2)
352 
353 /**
354  * struct rtl8366rb - RTL8366RB-specific data
355  * @max_mtu: per-port max MTU setting
356  * @pvid_enabled: if PVID is set for respective port
357  */
358 struct rtl8366rb {
359 	unsigned int max_mtu[RTL8366RB_NUM_PORTS];
360 	bool pvid_enabled[RTL8366RB_NUM_PORTS];
361 };
362 
363 static struct rtl8366_mib_counter rtl8366rb_mib_counters[] = {
364 	{ 0,  0, 4, "IfInOctets"				},
365 	{ 0,  4, 4, "EtherStatsOctets"				},
366 	{ 0,  8, 2, "EtherStatsUnderSizePkts"			},
367 	{ 0, 10, 2, "EtherFragments"				},
368 	{ 0, 12, 2, "EtherStatsPkts64Octets"			},
369 	{ 0, 14, 2, "EtherStatsPkts65to127Octets"		},
370 	{ 0, 16, 2, "EtherStatsPkts128to255Octets"		},
371 	{ 0, 18, 2, "EtherStatsPkts256to511Octets"		},
372 	{ 0, 20, 2, "EtherStatsPkts512to1023Octets"		},
373 	{ 0, 22, 2, "EtherStatsPkts1024to1518Octets"		},
374 	{ 0, 24, 2, "EtherOversizeStats"			},
375 	{ 0, 26, 2, "EtherStatsJabbers"				},
376 	{ 0, 28, 2, "IfInUcastPkts"				},
377 	{ 0, 30, 2, "EtherStatsMulticastPkts"			},
378 	{ 0, 32, 2, "EtherStatsBroadcastPkts"			},
379 	{ 0, 34, 2, "EtherStatsDropEvents"			},
380 	{ 0, 36, 2, "Dot3StatsFCSErrors"			},
381 	{ 0, 38, 2, "Dot3StatsSymbolErrors"			},
382 	{ 0, 40, 2, "Dot3InPauseFrames"				},
383 	{ 0, 42, 2, "Dot3ControlInUnknownOpcodes"		},
384 	{ 0, 44, 4, "IfOutOctets"				},
385 	{ 0, 48, 2, "Dot3StatsSingleCollisionFrames"		},
386 	{ 0, 50, 2, "Dot3StatMultipleCollisionFrames"		},
387 	{ 0, 52, 2, "Dot3sDeferredTransmissions"		},
388 	{ 0, 54, 2, "Dot3StatsLateCollisions"			},
389 	{ 0, 56, 2, "EtherStatsCollisions"			},
390 	{ 0, 58, 2, "Dot3StatsExcessiveCollisions"		},
391 	{ 0, 60, 2, "Dot3OutPauseFrames"			},
392 	{ 0, 62, 2, "Dot1dBasePortDelayExceededDiscards"	},
393 	{ 0, 64, 2, "Dot1dTpPortInDiscards"			},
394 	{ 0, 66, 2, "IfOutUcastPkts"				},
395 	{ 0, 68, 2, "IfOutMulticastPkts"			},
396 	{ 0, 70, 2, "IfOutBroadcastPkts"			},
397 };
398 
399 static int rtl8366rb_get_mib_counter(struct realtek_priv *priv,
400 				     int port,
401 				     struct rtl8366_mib_counter *mib,
402 				     u64 *mibvalue)
403 {
404 	u32 addr, val;
405 	int ret;
406 	int i;
407 
408 	addr = RTL8366RB_MIB_COUNTER_BASE +
409 		RTL8366RB_MIB_COUNTER_PORT_OFFSET * (port) +
410 		mib->offset;
411 
412 	/* Writing access counter address first
413 	 * then ASIC will prepare 64bits counter wait for being retrived
414 	 */
415 	ret = regmap_write(priv->map, addr, 0); /* Write whatever */
416 	if (ret)
417 		return ret;
418 
419 	/* Read MIB control register */
420 	ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val);
421 	if (ret)
422 		return -EIO;
423 
424 	if (val & RTL8366RB_MIB_CTRL_BUSY_MASK)
425 		return -EBUSY;
426 
427 	if (val & RTL8366RB_MIB_CTRL_RESET_MASK)
428 		return -EIO;
429 
430 	/* Read each individual MIB 16 bits at the time */
431 	*mibvalue = 0;
432 	for (i = mib->length; i > 0; i--) {
433 		ret = regmap_read(priv->map, addr + (i - 1), &val);
434 		if (ret)
435 			return ret;
436 		*mibvalue = (*mibvalue << 16) | (val & 0xFFFF);
437 	}
438 	return 0;
439 }
440 
441 static u32 rtl8366rb_get_irqmask(struct irq_data *d)
442 {
443 	int line = irqd_to_hwirq(d);
444 	u32 val;
445 
446 	/* For line interrupts we combine link down in bits
447 	 * 6..11 with link up in bits 0..5 into one interrupt.
448 	 */
449 	if (line < 12)
450 		val = BIT(line) | BIT(line + 6);
451 	else
452 		val = BIT(line);
453 	return val;
454 }
455 
456 static void rtl8366rb_mask_irq(struct irq_data *d)
457 {
458 	struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
459 	int ret;
460 
461 	ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
462 				 rtl8366rb_get_irqmask(d), 0);
463 	if (ret)
464 		dev_err(priv->dev, "could not mask IRQ\n");
465 }
466 
467 static void rtl8366rb_unmask_irq(struct irq_data *d)
468 {
469 	struct realtek_priv *priv = irq_data_get_irq_chip_data(d);
470 	int ret;
471 
472 	ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG,
473 				 rtl8366rb_get_irqmask(d),
474 				 rtl8366rb_get_irqmask(d));
475 	if (ret)
476 		dev_err(priv->dev, "could not unmask IRQ\n");
477 }
478 
479 static irqreturn_t rtl8366rb_irq(int irq, void *data)
480 {
481 	struct realtek_priv *priv = data;
482 	u32 stat;
483 	int ret;
484 
485 	/* This clears the IRQ status register */
486 	ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
487 			  &stat);
488 	if (ret) {
489 		dev_err(priv->dev, "can't read interrupt status\n");
490 		return IRQ_NONE;
491 	}
492 	stat &= RTL8366RB_INTERRUPT_VALID;
493 	if (!stat)
494 		return IRQ_NONE;
495 	while (stat) {
496 		int line = __ffs(stat);
497 		int child_irq;
498 
499 		stat &= ~BIT(line);
500 		/* For line interrupts we combine link down in bits
501 		 * 6..11 with link up in bits 0..5 into one interrupt.
502 		 */
503 		if (line < 12 && line > 5)
504 			line -= 5;
505 		child_irq = irq_find_mapping(priv->irqdomain, line);
506 		handle_nested_irq(child_irq);
507 	}
508 	return IRQ_HANDLED;
509 }
510 
511 static struct irq_chip rtl8366rb_irq_chip = {
512 	.name = "RTL8366RB",
513 	.irq_mask = rtl8366rb_mask_irq,
514 	.irq_unmask = rtl8366rb_unmask_irq,
515 };
516 
517 static int rtl8366rb_irq_map(struct irq_domain *domain, unsigned int irq,
518 			     irq_hw_number_t hwirq)
519 {
520 	irq_set_chip_data(irq, domain->host_data);
521 	irq_set_chip_and_handler(irq, &rtl8366rb_irq_chip, handle_simple_irq);
522 	irq_set_nested_thread(irq, 1);
523 	irq_set_noprobe(irq);
524 
525 	return 0;
526 }
527 
528 static void rtl8366rb_irq_unmap(struct irq_domain *d, unsigned int irq)
529 {
530 	irq_set_nested_thread(irq, 0);
531 	irq_set_chip_and_handler(irq, NULL, NULL);
532 	irq_set_chip_data(irq, NULL);
533 }
534 
535 static const struct irq_domain_ops rtl8366rb_irqdomain_ops = {
536 	.map = rtl8366rb_irq_map,
537 	.unmap = rtl8366rb_irq_unmap,
538 	.xlate  = irq_domain_xlate_onecell,
539 };
540 
541 static int rtl8366rb_setup_cascaded_irq(struct realtek_priv *priv)
542 {
543 	struct device_node *intc;
544 	unsigned long irq_trig;
545 	int irq;
546 	int ret;
547 	u32 val;
548 	int i;
549 
550 	intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");
551 	if (!intc) {
552 		dev_err(priv->dev, "missing child interrupt-controller node\n");
553 		return -EINVAL;
554 	}
555 	/* RB8366RB IRQs cascade off this one */
556 	irq = of_irq_get(intc, 0);
557 	if (irq <= 0) {
558 		dev_err(priv->dev, "failed to get parent IRQ\n");
559 		ret = irq ? irq : -EINVAL;
560 		goto out_put_node;
561 	}
562 
563 	/* This clears the IRQ status register */
564 	ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG,
565 			  &val);
566 	if (ret) {
567 		dev_err(priv->dev, "can't read interrupt status\n");
568 		goto out_put_node;
569 	}
570 
571 	/* Fetch IRQ edge information from the descriptor */
572 	irq_trig = irqd_get_trigger_type(irq_get_irq_data(irq));
573 	switch (irq_trig) {
574 	case IRQF_TRIGGER_RISING:
575 	case IRQF_TRIGGER_HIGH:
576 		dev_info(priv->dev, "active high/rising IRQ\n");
577 		val = 0;
578 		break;
579 	case IRQF_TRIGGER_FALLING:
580 	case IRQF_TRIGGER_LOW:
581 		dev_info(priv->dev, "active low/falling IRQ\n");
582 		val = RTL8366RB_INTERRUPT_POLARITY;
583 		break;
584 	}
585 	ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG,
586 				 RTL8366RB_INTERRUPT_POLARITY,
587 				 val);
588 	if (ret) {
589 		dev_err(priv->dev, "could not configure IRQ polarity\n");
590 		goto out_put_node;
591 	}
592 
593 	ret = devm_request_threaded_irq(priv->dev, irq, NULL,
594 					rtl8366rb_irq, IRQF_ONESHOT,
595 					"RTL8366RB", priv);
596 	if (ret) {
597 		dev_err(priv->dev, "unable to request irq: %d\n", ret);
598 		goto out_put_node;
599 	}
600 	priv->irqdomain = irq_domain_add_linear(intc,
601 						RTL8366RB_NUM_INTERRUPT,
602 						&rtl8366rb_irqdomain_ops,
603 						priv);
604 	if (!priv->irqdomain) {
605 		dev_err(priv->dev, "failed to create IRQ domain\n");
606 		ret = -EINVAL;
607 		goto out_put_node;
608 	}
609 	for (i = 0; i < priv->num_ports; i++)
610 		irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq);
611 
612 out_put_node:
613 	of_node_put(intc);
614 	return ret;
615 }
616 
617 static int rtl8366rb_set_addr(struct realtek_priv *priv)
618 {
619 	u8 addr[ETH_ALEN];
620 	u16 val;
621 	int ret;
622 
623 	eth_random_addr(addr);
624 
625 	dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n",
626 		 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
627 	val = addr[0] << 8 | addr[1];
628 	ret = regmap_write(priv->map, RTL8366RB_SMAR0, val);
629 	if (ret)
630 		return ret;
631 	val = addr[2] << 8 | addr[3];
632 	ret = regmap_write(priv->map, RTL8366RB_SMAR1, val);
633 	if (ret)
634 		return ret;
635 	val = addr[4] << 8 | addr[5];
636 	ret = regmap_write(priv->map, RTL8366RB_SMAR2, val);
637 	if (ret)
638 		return ret;
639 
640 	return 0;
641 }
642 
643 /* Found in a vendor driver */
644 
645 /* Struct for handling the jam tables' entries */
646 struct rtl8366rb_jam_tbl_entry {
647 	u16 reg;
648 	u16 val;
649 };
650 
651 /* For the "version 0" early silicon, appear in most source releases */
652 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_0[] = {
653 	{0x000B, 0x0001}, {0x03A6, 0x0100}, {0x03A7, 0x0001}, {0x02D1, 0x3FFF},
654 	{0x02D2, 0x3FFF}, {0x02D3, 0x3FFF}, {0x02D4, 0x3FFF}, {0x02D5, 0x3FFF},
655 	{0x02D6, 0x3FFF}, {0x02D7, 0x3FFF}, {0x02D8, 0x3FFF}, {0x022B, 0x0688},
656 	{0x022C, 0x0FAC}, {0x03D0, 0x4688}, {0x03D1, 0x01F5}, {0x0000, 0x0830},
657 	{0x02F9, 0x0200}, {0x02F7, 0x7FFF}, {0x02F8, 0x03FF}, {0x0080, 0x03E8},
658 	{0x0081, 0x00CE}, {0x0082, 0x00DA}, {0x0083, 0x0230}, {0xBE0F, 0x2000},
659 	{0x0231, 0x422A}, {0x0232, 0x422A}, {0x0233, 0x422A}, {0x0234, 0x422A},
660 	{0x0235, 0x422A}, {0x0236, 0x422A}, {0x0237, 0x422A}, {0x0238, 0x422A},
661 	{0x0239, 0x422A}, {0x023A, 0x422A}, {0x023B, 0x422A}, {0x023C, 0x422A},
662 	{0x023D, 0x422A}, {0x023E, 0x422A}, {0x023F, 0x422A}, {0x0240, 0x422A},
663 	{0x0241, 0x422A}, {0x0242, 0x422A}, {0x0243, 0x422A}, {0x0244, 0x422A},
664 	{0x0245, 0x422A}, {0x0246, 0x422A}, {0x0247, 0x422A}, {0x0248, 0x422A},
665 	{0x0249, 0x0146}, {0x024A, 0x0146}, {0x024B, 0x0146}, {0xBE03, 0xC961},
666 	{0x024D, 0x0146}, {0x024E, 0x0146}, {0x024F, 0x0146}, {0x0250, 0x0146},
667 	{0xBE64, 0x0226}, {0x0252, 0x0146}, {0x0253, 0x0146}, {0x024C, 0x0146},
668 	{0x0251, 0x0146}, {0x0254, 0x0146}, {0xBE62, 0x3FD0}, {0x0084, 0x0320},
669 	{0x0255, 0x0146}, {0x0256, 0x0146}, {0x0257, 0x0146}, {0x0258, 0x0146},
670 	{0x0259, 0x0146}, {0x025A, 0x0146}, {0x025B, 0x0146}, {0x025C, 0x0146},
671 	{0x025D, 0x0146}, {0x025E, 0x0146}, {0x025F, 0x0146}, {0x0260, 0x0146},
672 	{0x0261, 0xA23F}, {0x0262, 0x0294}, {0x0263, 0xA23F}, {0x0264, 0x0294},
673 	{0x0265, 0xA23F}, {0x0266, 0x0294}, {0x0267, 0xA23F}, {0x0268, 0x0294},
674 	{0x0269, 0xA23F}, {0x026A, 0x0294}, {0x026B, 0xA23F}, {0x026C, 0x0294},
675 	{0x026D, 0xA23F}, {0x026E, 0x0294}, {0x026F, 0xA23F}, {0x0270, 0x0294},
676 	{0x02F5, 0x0048}, {0xBE09, 0x0E00}, {0xBE1E, 0x0FA0}, {0xBE14, 0x8448},
677 	{0xBE15, 0x1007}, {0xBE4A, 0xA284}, {0xC454, 0x3F0B}, {0xC474, 0x3F0B},
678 	{0xBE48, 0x3672}, {0xBE4B, 0x17A7}, {0xBE4C, 0x0B15}, {0xBE52, 0x0EDD},
679 	{0xBE49, 0x8C00}, {0xBE5B, 0x785C}, {0xBE5C, 0x785C}, {0xBE5D, 0x785C},
680 	{0xBE61, 0x368A}, {0xBE63, 0x9B84}, {0xC456, 0xCC13}, {0xC476, 0xCC13},
681 	{0xBE65, 0x307D}, {0xBE6D, 0x0005}, {0xBE6E, 0xE120}, {0xBE2E, 0x7BAF},
682 };
683 
684 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */
685 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_1[] = {
686 	{0x0000, 0x0830}, {0x0001, 0x8000}, {0x0400, 0x8130}, {0xBE78, 0x3C3C},
687 	{0x0431, 0x5432}, {0xBE37, 0x0CE4}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
688 	{0xC44C, 0x1585}, {0xC44C, 0x1185}, {0xC44C, 0x1585}, {0xC46C, 0x1585},
689 	{0xC46C, 0x1185}, {0xC46C, 0x1585}, {0xC451, 0x2135}, {0xC471, 0x2135},
690 	{0xBE10, 0x8140}, {0xBE15, 0x0007}, {0xBE6E, 0xE120}, {0xBE69, 0xD20F},
691 	{0xBE6B, 0x0320}, {0xBE24, 0xB000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF20},
692 	{0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800}, {0xBE24, 0x0000},
693 	{0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60}, {0xBE21, 0x0140},
694 	{0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000}, {0xBE2E, 0x7B7A},
695 	{0xBE36, 0x0CE4}, {0x02F5, 0x0048}, {0xBE77, 0x2940}, {0x000A, 0x83E0},
696 	{0xBE79, 0x3C3C}, {0xBE00, 0x1340},
697 };
698 
699 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */
700 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_2[] = {
701 	{0x0450, 0x0000}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
702 	{0xC44F, 0x6250}, {0xC46F, 0x6250}, {0xC456, 0x0C14}, {0xC476, 0x0C14},
703 	{0xC44C, 0x1C85}, {0xC44C, 0x1885}, {0xC44C, 0x1C85}, {0xC46C, 0x1C85},
704 	{0xC46C, 0x1885}, {0xC46C, 0x1C85}, {0xC44C, 0x0885}, {0xC44C, 0x0881},
705 	{0xC44C, 0x0885}, {0xC46C, 0x0885}, {0xC46C, 0x0881}, {0xC46C, 0x0885},
706 	{0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
707 	{0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6E, 0x0320},
708 	{0xBE77, 0x2940}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
709 	{0x8000, 0x0001}, {0xBE15, 0x1007}, {0x8000, 0x0000}, {0xBE15, 0x1007},
710 	{0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160}, {0xBE10, 0x8140},
711 	{0xBE00, 0x1340}, {0x0F51, 0x0010},
712 };
713 
714 /* Appears in a DDWRT code dump */
715 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_ver_3[] = {
716 	{0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0431, 0x5432},
717 	{0x0F51, 0x0017}, {0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0},
718 	{0xC456, 0x0C14}, {0xC476, 0x0C14}, {0xC454, 0x3F8B}, {0xC474, 0x3F8B},
719 	{0xC450, 0x2071}, {0xC470, 0x2071}, {0xC451, 0x226B}, {0xC471, 0x226B},
720 	{0xC452, 0xA293}, {0xC472, 0xA293}, {0xC44C, 0x1585}, {0xC44C, 0x1185},
721 	{0xC44C, 0x1585}, {0xC46C, 0x1585}, {0xC46C, 0x1185}, {0xC46C, 0x1585},
722 	{0xC44C, 0x0185}, {0xC44C, 0x0181}, {0xC44C, 0x0185}, {0xC46C, 0x0185},
723 	{0xC46C, 0x0181}, {0xC46C, 0x0185}, {0xBE24, 0xB000}, {0xBE23, 0xFF51},
724 	{0xBE22, 0xDF20}, {0xBE21, 0x0140}, {0xBE20, 0x00BB}, {0xBE24, 0xB800},
725 	{0xBE24, 0x0000}, {0xBE24, 0x7000}, {0xBE23, 0xFF51}, {0xBE22, 0xDF60},
726 	{0xBE21, 0x0140}, {0xBE20, 0x0077}, {0xBE24, 0x7800}, {0xBE24, 0x0000},
727 	{0xBE2E, 0x7BA7}, {0xBE36, 0x1000}, {0xBE37, 0x1000}, {0x8000, 0x0001},
728 	{0xBE69, 0xD50F}, {0x8000, 0x0000}, {0xBE69, 0xD50F}, {0xBE6B, 0x0320},
729 	{0xBE77, 0x2800}, {0xBE78, 0x3C3C}, {0xBE79, 0x3C3C}, {0xBE6E, 0xE120},
730 	{0x8000, 0x0001}, {0xBE10, 0x8140}, {0x8000, 0x0000}, {0xBE10, 0x8140},
731 	{0xBE15, 0x1007}, {0xBE14, 0x0448}, {0xBE1E, 0x00A0}, {0xBE10, 0x8160},
732 	{0xBE10, 0x8140}, {0xBE00, 0x1340}, {0x0450, 0x0000}, {0x0401, 0x0000},
733 };
734 
735 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
736 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_f5d8235[] = {
737 	{0x0242, 0x02BF}, {0x0245, 0x02BF}, {0x0248, 0x02BF}, {0x024B, 0x02BF},
738 	{0x024E, 0x02BF}, {0x0251, 0x02BF}, {0x0254, 0x0A3F}, {0x0256, 0x0A3F},
739 	{0x0258, 0x0A3F}, {0x025A, 0x0A3F}, {0x025C, 0x0A3F}, {0x025E, 0x0A3F},
740 	{0x0263, 0x007C}, {0x0100, 0x0004}, {0xBE5B, 0x3500}, {0x800E, 0x200F},
741 	{0xBE1D, 0x0F00}, {0x8001, 0x5011}, {0x800A, 0xA2F4}, {0x800B, 0x17A3},
742 	{0xBE4B, 0x17A3}, {0xBE41, 0x5011}, {0xBE17, 0x2100}, {0x8000, 0x8304},
743 	{0xBE40, 0x8304}, {0xBE4A, 0xA2F4}, {0x800C, 0xA8D5}, {0x8014, 0x5500},
744 	{0x8015, 0x0004}, {0xBE4C, 0xA8D5}, {0xBE59, 0x0008}, {0xBE09, 0x0E00},
745 	{0xBE36, 0x1036}, {0xBE37, 0x1036}, {0x800D, 0x00FF}, {0xBE4D, 0x00FF},
746 };
747 
748 /* DGN3500, "netgear,dgn3500", "netgear,dgn3500b" */
749 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_init_jam_dgn3500[] = {
750 	{0x0000, 0x0830}, {0x0400, 0x8130}, {0x000A, 0x83ED}, {0x0F51, 0x0017},
751 	{0x02F5, 0x0048}, {0x02FA, 0xFFDF}, {0x02FB, 0xFFE0}, {0x0450, 0x0000},
752 	{0x0401, 0x0000}, {0x0431, 0x0960},
753 };
754 
755 /* This jam table activates "green ethernet", which means low power mode
756  * and is claimed to detect the cable length and not use more power than
757  * necessary, and the ports should enter power saving mode 10 seconds after
758  * a cable is disconnected. Seems to always be the same.
759  */
760 static const struct rtl8366rb_jam_tbl_entry rtl8366rb_green_jam[] = {
761 	{0xBE78, 0x323C}, {0xBE77, 0x5000}, {0xBE2E, 0x7BA7},
762 	{0xBE59, 0x3459}, {0xBE5A, 0x745A}, {0xBE5B, 0x785C},
763 	{0xBE5C, 0x785C}, {0xBE6E, 0xE120}, {0xBE79, 0x323C},
764 };
765 
766 /* Function that jams the tables in the proper registers */
767 static int rtl8366rb_jam_table(const struct rtl8366rb_jam_tbl_entry *jam_table,
768 			       int jam_size, struct realtek_priv *priv,
769 			       bool write_dbg)
770 {
771 	u32 val;
772 	int ret;
773 	int i;
774 
775 	for (i = 0; i < jam_size; i++) {
776 		if ((jam_table[i].reg & 0xBE00) == 0xBE00) {
777 			ret = regmap_read(priv->map,
778 					  RTL8366RB_PHY_ACCESS_BUSY_REG,
779 					  &val);
780 			if (ret)
781 				return ret;
782 			if (!(val & RTL8366RB_PHY_INT_BUSY)) {
783 				ret = regmap_write(priv->map,
784 						   RTL8366RB_PHY_ACCESS_CTRL_REG,
785 						   RTL8366RB_PHY_CTRL_WRITE);
786 				if (ret)
787 					return ret;
788 			}
789 		}
790 		if (write_dbg)
791 			dev_dbg(priv->dev, "jam %04x into register %04x\n",
792 				jam_table[i].val,
793 				jam_table[i].reg);
794 		ret = regmap_write(priv->map,
795 				   jam_table[i].reg,
796 				   jam_table[i].val);
797 		if (ret)
798 			return ret;
799 	}
800 	return 0;
801 }
802 
803 static int rtl8366rb_setup(struct dsa_switch *ds)
804 {
805 	struct realtek_priv *priv = ds->priv;
806 	const struct rtl8366rb_jam_tbl_entry *jam_table;
807 	struct rtl8366rb *rb;
808 	u32 chip_ver = 0;
809 	u32 chip_id = 0;
810 	int jam_size;
811 	u32 val;
812 	int ret;
813 	int i;
814 
815 	rb = priv->chip_data;
816 
817 	ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id);
818 	if (ret) {
819 		dev_err(priv->dev, "unable to read chip id\n");
820 		return ret;
821 	}
822 
823 	switch (chip_id) {
824 	case RTL8366RB_CHIP_ID_8366:
825 		break;
826 	default:
827 		dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id);
828 		return -ENODEV;
829 	}
830 
831 	ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG,
832 			  &chip_ver);
833 	if (ret) {
834 		dev_err(priv->dev, "unable to read chip version\n");
835 		return ret;
836 	}
837 
838 	dev_info(priv->dev, "RTL%04x ver %u chip found\n",
839 		 chip_id, chip_ver & RTL8366RB_CHIP_VERSION_MASK);
840 
841 	/* Do the init dance using the right jam table */
842 	switch (chip_ver) {
843 	case 0:
844 		jam_table = rtl8366rb_init_jam_ver_0;
845 		jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_0);
846 		break;
847 	case 1:
848 		jam_table = rtl8366rb_init_jam_ver_1;
849 		jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_1);
850 		break;
851 	case 2:
852 		jam_table = rtl8366rb_init_jam_ver_2;
853 		jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_2);
854 		break;
855 	default:
856 		jam_table = rtl8366rb_init_jam_ver_3;
857 		jam_size = ARRAY_SIZE(rtl8366rb_init_jam_ver_3);
858 		break;
859 	}
860 
861 	/* Special jam tables for special routers
862 	 * TODO: are these necessary? Maintainers, please test
863 	 * without them, using just the off-the-shelf tables.
864 	 */
865 	if (of_machine_is_compatible("belkin,f5d8235-v1")) {
866 		jam_table = rtl8366rb_init_jam_f5d8235;
867 		jam_size = ARRAY_SIZE(rtl8366rb_init_jam_f5d8235);
868 	}
869 	if (of_machine_is_compatible("netgear,dgn3500") ||
870 	    of_machine_is_compatible("netgear,dgn3500b")) {
871 		jam_table = rtl8366rb_init_jam_dgn3500;
872 		jam_size = ARRAY_SIZE(rtl8366rb_init_jam_dgn3500);
873 	}
874 
875 	ret = rtl8366rb_jam_table(jam_table, jam_size, priv, true);
876 	if (ret)
877 		return ret;
878 
879 	/* Isolate all user ports so they can only send packets to itself and the CPU port */
880 	for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
881 		ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i),
882 				   RTL8366RB_PORT_ISO_PORTS(BIT(RTL8366RB_PORT_NUM_CPU)) |
883 				   RTL8366RB_PORT_ISO_EN);
884 		if (ret)
885 			return ret;
886 	}
887 	/* CPU port can send packets to all ports */
888 	ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU),
889 			   RTL8366RB_PORT_ISO_PORTS(dsa_user_ports(ds)) |
890 			   RTL8366RB_PORT_ISO_EN);
891 	if (ret)
892 		return ret;
893 
894 	/* Set up the "green ethernet" feature */
895 	ret = rtl8366rb_jam_table(rtl8366rb_green_jam,
896 				  ARRAY_SIZE(rtl8366rb_green_jam), priv, false);
897 	if (ret)
898 		return ret;
899 
900 	ret = regmap_write(priv->map,
901 			   RTL8366RB_GREEN_FEATURE_REG,
902 			   (chip_ver == 1) ? 0x0007 : 0x0003);
903 	if (ret)
904 		return ret;
905 
906 	/* Vendor driver sets 0x240 in registers 0xc and 0xd (undocumented) */
907 	ret = regmap_write(priv->map, 0x0c, 0x240);
908 	if (ret)
909 		return ret;
910 	ret = regmap_write(priv->map, 0x0d, 0x240);
911 	if (ret)
912 		return ret;
913 
914 	/* Set some random MAC address */
915 	ret = rtl8366rb_set_addr(priv);
916 	if (ret)
917 		return ret;
918 
919 	/* Enable CPU port with custom DSA tag 8899.
920 	 *
921 	 * If you set RTL8368RB_CPU_NO_TAG (bit 15) in this registers
922 	 * the custom tag is turned off.
923 	 */
924 	ret = regmap_update_bits(priv->map, RTL8368RB_CPU_CTRL_REG,
925 				 0xFFFF,
926 				 BIT(priv->cpu_port));
927 	if (ret)
928 		return ret;
929 
930 	/* Make sure we default-enable the fixed CPU port */
931 	ret = regmap_update_bits(priv->map, RTL8366RB_PECR,
932 				 BIT(priv->cpu_port),
933 				 0);
934 	if (ret)
935 		return ret;
936 
937 	/* Set maximum packet length to 1536 bytes */
938 	ret = regmap_update_bits(priv->map, RTL8366RB_SGCR,
939 				 RTL8366RB_SGCR_MAX_LENGTH_MASK,
940 				 RTL8366RB_SGCR_MAX_LENGTH_1536);
941 	if (ret)
942 		return ret;
943 	for (i = 0; i < RTL8366RB_NUM_PORTS; i++)
944 		/* layer 2 size, see rtl8366rb_change_mtu() */
945 		rb->max_mtu[i] = 1532;
946 
947 	/* Disable learning for all ports */
948 	ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
949 			   RTL8366RB_PORT_ALL);
950 	if (ret)
951 		return ret;
952 
953 	/* Enable auto ageing for all ports */
954 	ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0);
955 	if (ret)
956 		return ret;
957 
958 	/* Port 4 setup: this enables Port 4, usually the WAN port,
959 	 * common PHY IO mode is apparently mode 0, and this is not what
960 	 * the port is initialized to. There is no explanation of the
961 	 * IO modes in the Realtek source code, if your WAN port is
962 	 * connected to something exotic such as fiber, then this might
963 	 * be worth experimenting with.
964 	 */
965 	ret = regmap_update_bits(priv->map, RTL8366RB_PMC0,
966 				 RTL8366RB_PMC0_P4_IOMODE_MASK,
967 				 0 << RTL8366RB_PMC0_P4_IOMODE_SHIFT);
968 	if (ret)
969 		return ret;
970 
971 	/* Accept all packets by default, we enable filtering on-demand */
972 	ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
973 			   0);
974 	if (ret)
975 		return ret;
976 	ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
977 			   0);
978 	if (ret)
979 		return ret;
980 
981 	/* Don't drop packets whose DA has not been learned */
982 	ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2,
983 				 RTL8366RB_SSCR2_DROP_UNKNOWN_DA, 0);
984 	if (ret)
985 		return ret;
986 
987 	/* Set blinking, TODO: make this configurable */
988 	ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG,
989 				 RTL8366RB_LED_BLINKRATE_MASK,
990 				 RTL8366RB_LED_BLINKRATE_56MS);
991 	if (ret)
992 		return ret;
993 
994 	/* Set up LED activity:
995 	 * Each port has 4 LEDs, we configure all ports to the same
996 	 * behaviour (no individual config) but we can set up each
997 	 * LED separately.
998 	 */
999 	if (priv->leds_disabled) {
1000 		/* Turn everything off */
1001 		regmap_update_bits(priv->map,
1002 				   RTL8366RB_LED_0_1_CTRL_REG,
1003 				   0x0FFF, 0);
1004 		regmap_update_bits(priv->map,
1005 				   RTL8366RB_LED_2_3_CTRL_REG,
1006 				   0x0FFF, 0);
1007 		regmap_update_bits(priv->map,
1008 				   RTL8366RB_INTERRUPT_CONTROL_REG,
1009 				   RTL8366RB_P4_RGMII_LED,
1010 				   0);
1011 		val = RTL8366RB_LED_OFF;
1012 	} else {
1013 		/* TODO: make this configurable per LED */
1014 		val = RTL8366RB_LED_FORCE;
1015 	}
1016 	for (i = 0; i < 4; i++) {
1017 		ret = regmap_update_bits(priv->map,
1018 					 RTL8366RB_LED_CTRL_REG,
1019 					 0xf << (i * 4),
1020 					 val << (i * 4));
1021 		if (ret)
1022 			return ret;
1023 	}
1024 
1025 	ret = rtl8366_reset_vlan(priv);
1026 	if (ret)
1027 		return ret;
1028 
1029 	ret = rtl8366rb_setup_cascaded_irq(priv);
1030 	if (ret)
1031 		dev_info(priv->dev, "no interrupt support\n");
1032 
1033 	if (priv->setup_interface) {
1034 		ret = priv->setup_interface(ds);
1035 		if (ret) {
1036 			dev_err(priv->dev, "could not set up MDIO bus\n");
1037 			return -ENODEV;
1038 		}
1039 	}
1040 
1041 	return 0;
1042 }
1043 
1044 static enum dsa_tag_protocol rtl8366_get_tag_protocol(struct dsa_switch *ds,
1045 						      int port,
1046 						      enum dsa_tag_protocol mp)
1047 {
1048 	/* This switch uses the 4 byte protocol A Realtek DSA tag */
1049 	return DSA_TAG_PROTO_RTL4_A;
1050 }
1051 
1052 static void
1053 rtl8366rb_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode,
1054 		      phy_interface_t interface, struct phy_device *phydev,
1055 		      int speed, int duplex, bool tx_pause, bool rx_pause)
1056 {
1057 	struct realtek_priv *priv = ds->priv;
1058 	int ret;
1059 
1060 	if (port != priv->cpu_port)
1061 		return;
1062 
1063 	dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port);
1064 
1065 	/* Force the fixed CPU port into 1Gbit mode, no autonegotiation */
1066 	ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG,
1067 				 BIT(port), BIT(port));
1068 	if (ret) {
1069 		dev_err(priv->dev, "failed to force 1Gbit on CPU port\n");
1070 		return;
1071 	}
1072 
1073 	ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2,
1074 				 0xFF00U,
1075 				 RTL8366RB_PAACR_CPU_PORT << 8);
1076 	if (ret) {
1077 		dev_err(priv->dev, "failed to set PAACR on CPU port\n");
1078 		return;
1079 	}
1080 
1081 	/* Enable the CPU port */
1082 	ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1083 				 0);
1084 	if (ret) {
1085 		dev_err(priv->dev, "failed to enable the CPU port\n");
1086 		return;
1087 	}
1088 }
1089 
1090 static void
1091 rtl8366rb_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode,
1092 			phy_interface_t interface)
1093 {
1094 	struct realtek_priv *priv = ds->priv;
1095 	int ret;
1096 
1097 	if (port != priv->cpu_port)
1098 		return;
1099 
1100 	dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port);
1101 
1102 	/* Disable the CPU port */
1103 	ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1104 				 BIT(port));
1105 	if (ret) {
1106 		dev_err(priv->dev, "failed to disable the CPU port\n");
1107 		return;
1108 	}
1109 }
1110 
1111 static void rb8366rb_set_port_led(struct realtek_priv *priv,
1112 				  int port, bool enable)
1113 {
1114 	u16 val = enable ? 0x3f : 0;
1115 	int ret;
1116 
1117 	if (priv->leds_disabled)
1118 		return;
1119 
1120 	switch (port) {
1121 	case 0:
1122 		ret = regmap_update_bits(priv->map,
1123 					 RTL8366RB_LED_0_1_CTRL_REG,
1124 					 0x3F, val);
1125 		break;
1126 	case 1:
1127 		ret = regmap_update_bits(priv->map,
1128 					 RTL8366RB_LED_0_1_CTRL_REG,
1129 					 0x3F << RTL8366RB_LED_1_OFFSET,
1130 					 val << RTL8366RB_LED_1_OFFSET);
1131 		break;
1132 	case 2:
1133 		ret = regmap_update_bits(priv->map,
1134 					 RTL8366RB_LED_2_3_CTRL_REG,
1135 					 0x3F, val);
1136 		break;
1137 	case 3:
1138 		ret = regmap_update_bits(priv->map,
1139 					 RTL8366RB_LED_2_3_CTRL_REG,
1140 					 0x3F << RTL8366RB_LED_3_OFFSET,
1141 					 val << RTL8366RB_LED_3_OFFSET);
1142 		break;
1143 	case 4:
1144 		ret = regmap_update_bits(priv->map,
1145 					 RTL8366RB_INTERRUPT_CONTROL_REG,
1146 					 RTL8366RB_P4_RGMII_LED,
1147 					 enable ? RTL8366RB_P4_RGMII_LED : 0);
1148 		break;
1149 	default:
1150 		dev_err(priv->dev, "no LED for port %d\n", port);
1151 		return;
1152 	}
1153 	if (ret)
1154 		dev_err(priv->dev, "error updating LED on port %d\n", port);
1155 }
1156 
1157 static int
1158 rtl8366rb_port_enable(struct dsa_switch *ds, int port,
1159 		      struct phy_device *phy)
1160 {
1161 	struct realtek_priv *priv = ds->priv;
1162 	int ret;
1163 
1164 	dev_dbg(priv->dev, "enable port %d\n", port);
1165 	ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1166 				 0);
1167 	if (ret)
1168 		return ret;
1169 
1170 	rb8366rb_set_port_led(priv, port, true);
1171 	return 0;
1172 }
1173 
1174 static void
1175 rtl8366rb_port_disable(struct dsa_switch *ds, int port)
1176 {
1177 	struct realtek_priv *priv = ds->priv;
1178 	int ret;
1179 
1180 	dev_dbg(priv->dev, "disable port %d\n", port);
1181 	ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port),
1182 				 BIT(port));
1183 	if (ret)
1184 		return;
1185 
1186 	rb8366rb_set_port_led(priv, port, false);
1187 }
1188 
1189 static int
1190 rtl8366rb_port_bridge_join(struct dsa_switch *ds, int port,
1191 			   struct dsa_bridge bridge,
1192 			   bool *tx_fwd_offload,
1193 			   struct netlink_ext_ack *extack)
1194 {
1195 	struct realtek_priv *priv = ds->priv;
1196 	unsigned int port_bitmap = 0;
1197 	int ret, i;
1198 
1199 	/* Loop over all other ports than the current one */
1200 	for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1201 		/* Current port handled last */
1202 		if (i == port)
1203 			continue;
1204 		/* Not on this bridge */
1205 		if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1206 			continue;
1207 		/* Join this port to each other port on the bridge */
1208 		ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1209 					 RTL8366RB_PORT_ISO_PORTS(BIT(port)),
1210 					 RTL8366RB_PORT_ISO_PORTS(BIT(port)));
1211 		if (ret)
1212 			dev_err(priv->dev, "failed to join port %d\n", port);
1213 
1214 		port_bitmap |= BIT(i);
1215 	}
1216 
1217 	/* Set the bits for the ports we can access */
1218 	return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1219 				  RTL8366RB_PORT_ISO_PORTS(port_bitmap),
1220 				  RTL8366RB_PORT_ISO_PORTS(port_bitmap));
1221 }
1222 
1223 static void
1224 rtl8366rb_port_bridge_leave(struct dsa_switch *ds, int port,
1225 			    struct dsa_bridge bridge)
1226 {
1227 	struct realtek_priv *priv = ds->priv;
1228 	unsigned int port_bitmap = 0;
1229 	int ret, i;
1230 
1231 	/* Loop over all other ports than this one */
1232 	for (i = 0; i < RTL8366RB_PORT_NUM_CPU; i++) {
1233 		/* Current port handled last */
1234 		if (i == port)
1235 			continue;
1236 		/* Not on this bridge */
1237 		if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1238 			continue;
1239 		/* Remove this port from any other port on the bridge */
1240 		ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i),
1241 					 RTL8366RB_PORT_ISO_PORTS(BIT(port)), 0);
1242 		if (ret)
1243 			dev_err(priv->dev, "failed to leave port %d\n", port);
1244 
1245 		port_bitmap |= BIT(i);
1246 	}
1247 
1248 	/* Clear the bits for the ports we can not access, leave ourselves */
1249 	regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port),
1250 			   RTL8366RB_PORT_ISO_PORTS(port_bitmap), 0);
1251 }
1252 
1253 /**
1254  * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames
1255  * @priv: SMI state container
1256  * @port: the port to drop untagged and C-tagged frames on
1257  * @drop: whether to drop or pass untagged and C-tagged frames
1258  *
1259  * Return: zero for success, a negative number on error.
1260  */
1261 static int rtl8366rb_drop_untagged(struct realtek_priv *priv, int port, bool drop)
1262 {
1263 	return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG,
1264 				  RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port),
1265 				  drop ? RTL8366RB_VLAN_INGRESS_CTRL1_DROP(port) : 0);
1266 }
1267 
1268 static int rtl8366rb_vlan_filtering(struct dsa_switch *ds, int port,
1269 				    bool vlan_filtering,
1270 				    struct netlink_ext_ack *extack)
1271 {
1272 	struct realtek_priv *priv = ds->priv;
1273 	struct rtl8366rb *rb;
1274 	int ret;
1275 
1276 	rb = priv->chip_data;
1277 
1278 	dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port,
1279 		vlan_filtering ? "enable" : "disable");
1280 
1281 	/* If the port is not in the member set, the frame will be dropped */
1282 	ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG,
1283 				 BIT(port), vlan_filtering ? BIT(port) : 0);
1284 	if (ret)
1285 		return ret;
1286 
1287 	/* If VLAN filtering is enabled and PVID is also enabled, we must
1288 	 * not drop any untagged or C-tagged frames. If we turn off VLAN
1289 	 * filtering on a port, we need to accept any frames.
1290 	 */
1291 	if (vlan_filtering)
1292 		ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]);
1293 	else
1294 		ret = rtl8366rb_drop_untagged(priv, port, false);
1295 
1296 	return ret;
1297 }
1298 
1299 static int
1300 rtl8366rb_port_pre_bridge_flags(struct dsa_switch *ds, int port,
1301 				struct switchdev_brport_flags flags,
1302 				struct netlink_ext_ack *extack)
1303 {
1304 	/* We support enabling/disabling learning */
1305 	if (flags.mask & ~(BR_LEARNING))
1306 		return -EINVAL;
1307 
1308 	return 0;
1309 }
1310 
1311 static int
1312 rtl8366rb_port_bridge_flags(struct dsa_switch *ds, int port,
1313 			    struct switchdev_brport_flags flags,
1314 			    struct netlink_ext_ack *extack)
1315 {
1316 	struct realtek_priv *priv = ds->priv;
1317 	int ret;
1318 
1319 	if (flags.mask & BR_LEARNING) {
1320 		ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL,
1321 					 BIT(port),
1322 					 (flags.val & BR_LEARNING) ? 0 : BIT(port));
1323 		if (ret)
1324 			return ret;
1325 	}
1326 
1327 	return 0;
1328 }
1329 
1330 static void
1331 rtl8366rb_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1332 {
1333 	struct realtek_priv *priv = ds->priv;
1334 	u32 val;
1335 	int i;
1336 
1337 	switch (state) {
1338 	case BR_STATE_DISABLED:
1339 		val = RTL8366RB_STP_STATE_DISABLED;
1340 		break;
1341 	case BR_STATE_BLOCKING:
1342 	case BR_STATE_LISTENING:
1343 		val = RTL8366RB_STP_STATE_BLOCKING;
1344 		break;
1345 	case BR_STATE_LEARNING:
1346 		val = RTL8366RB_STP_STATE_LEARNING;
1347 		break;
1348 	case BR_STATE_FORWARDING:
1349 		val = RTL8366RB_STP_STATE_FORWARDING;
1350 		break;
1351 	default:
1352 		dev_err(priv->dev, "unknown bridge state requested\n");
1353 		return;
1354 	}
1355 
1356 	/* Set the same status for the port on all the FIDs */
1357 	for (i = 0; i < RTL8366RB_NUM_FIDS; i++) {
1358 		regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i,
1359 				   RTL8366RB_STP_STATE_MASK(port),
1360 				   RTL8366RB_STP_STATE(port, val));
1361 	}
1362 }
1363 
1364 static void
1365 rtl8366rb_port_fast_age(struct dsa_switch *ds, int port)
1366 {
1367 	struct realtek_priv *priv = ds->priv;
1368 
1369 	/* This will age out any learned L2 entries */
1370 	regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1371 			   BIT(port), BIT(port));
1372 	/* Restore the normal state of things */
1373 	regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL,
1374 			   BIT(port), 0);
1375 }
1376 
1377 static int rtl8366rb_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1378 {
1379 	struct realtek_priv *priv = ds->priv;
1380 	struct rtl8366rb *rb;
1381 	unsigned int max_mtu;
1382 	u32 len;
1383 	int i;
1384 
1385 	/* Cache the per-port MTU setting */
1386 	rb = priv->chip_data;
1387 	rb->max_mtu[port] = new_mtu;
1388 
1389 	/* Roof out the MTU for the entire switch to the greatest
1390 	 * common denominator: the biggest set for any one port will
1391 	 * be the biggest MTU for the switch.
1392 	 *
1393 	 * The first setting, 1522 bytes, is max IP packet 1500 bytes,
1394 	 * plus ethernet header, 1518 bytes, plus CPU tag, 4 bytes.
1395 	 * This function should consider the parameter an SDU, so the
1396 	 * MTU passed for this setting is 1518 bytes. The same logic
1397 	 * of subtracting the DSA tag of 4 bytes apply to the other
1398 	 * settings.
1399 	 */
1400 	max_mtu = 1518;
1401 	for (i = 0; i < RTL8366RB_NUM_PORTS; i++) {
1402 		if (rb->max_mtu[i] > max_mtu)
1403 			max_mtu = rb->max_mtu[i];
1404 	}
1405 	if (max_mtu <= 1518)
1406 		len = RTL8366RB_SGCR_MAX_LENGTH_1522;
1407 	else if (max_mtu > 1518 && max_mtu <= 1532)
1408 		len = RTL8366RB_SGCR_MAX_LENGTH_1536;
1409 	else if (max_mtu > 1532 && max_mtu <= 1548)
1410 		len = RTL8366RB_SGCR_MAX_LENGTH_1552;
1411 	else
1412 		len = RTL8366RB_SGCR_MAX_LENGTH_16000;
1413 
1414 	return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1415 				  RTL8366RB_SGCR_MAX_LENGTH_MASK,
1416 				  len);
1417 }
1418 
1419 static int rtl8366rb_max_mtu(struct dsa_switch *ds, int port)
1420 {
1421 	/* The max MTU is 16000 bytes, so we subtract the CPU tag
1422 	 * and the max presented to the system is 15996 bytes.
1423 	 */
1424 	return 15996;
1425 }
1426 
1427 static int rtl8366rb_get_vlan_4k(struct realtek_priv *priv, u32 vid,
1428 				 struct rtl8366_vlan_4k *vlan4k)
1429 {
1430 	u32 data[3];
1431 	int ret;
1432 	int i;
1433 
1434 	memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
1435 
1436 	if (vid >= RTL8366RB_NUM_VIDS)
1437 		return -EINVAL;
1438 
1439 	/* write VID */
1440 	ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE,
1441 			   vid & RTL8366RB_VLAN_VID_MASK);
1442 	if (ret)
1443 		return ret;
1444 
1445 	/* write table access control word */
1446 	ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1447 			   RTL8366RB_TABLE_VLAN_READ_CTRL);
1448 	if (ret)
1449 		return ret;
1450 
1451 	for (i = 0; i < 3; i++) {
1452 		ret = regmap_read(priv->map,
1453 				  RTL8366RB_VLAN_TABLE_READ_BASE + i,
1454 				  &data[i]);
1455 		if (ret)
1456 			return ret;
1457 	}
1458 
1459 	vlan4k->vid = vid;
1460 	vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1461 			RTL8366RB_VLAN_UNTAG_MASK;
1462 	vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1463 	vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1464 
1465 	return 0;
1466 }
1467 
1468 static int rtl8366rb_set_vlan_4k(struct realtek_priv *priv,
1469 				 const struct rtl8366_vlan_4k *vlan4k)
1470 {
1471 	u32 data[3];
1472 	int ret;
1473 	int i;
1474 
1475 	if (vlan4k->vid >= RTL8366RB_NUM_VIDS ||
1476 	    vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK ||
1477 	    vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1478 	    vlan4k->fid > RTL8366RB_FIDMAX)
1479 		return -EINVAL;
1480 
1481 	data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK;
1482 	data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) |
1483 		  ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1484 			RTL8366RB_VLAN_UNTAG_SHIFT);
1485 	data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK;
1486 
1487 	for (i = 0; i < 3; i++) {
1488 		ret = regmap_write(priv->map,
1489 				   RTL8366RB_VLAN_TABLE_WRITE_BASE + i,
1490 				   data[i]);
1491 		if (ret)
1492 			return ret;
1493 	}
1494 
1495 	/* write table access control word */
1496 	ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG,
1497 			   RTL8366RB_TABLE_VLAN_WRITE_CTRL);
1498 
1499 	return ret;
1500 }
1501 
1502 static int rtl8366rb_get_vlan_mc(struct realtek_priv *priv, u32 index,
1503 				 struct rtl8366_vlan_mc *vlanmc)
1504 {
1505 	u32 data[3];
1506 	int ret;
1507 	int i;
1508 
1509 	memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
1510 
1511 	if (index >= RTL8366RB_NUM_VLANS)
1512 		return -EINVAL;
1513 
1514 	for (i = 0; i < 3; i++) {
1515 		ret = regmap_read(priv->map,
1516 				  RTL8366RB_VLAN_MC_BASE(index) + i,
1517 				  &data[i]);
1518 		if (ret)
1519 			return ret;
1520 	}
1521 
1522 	vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK;
1523 	vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) &
1524 		RTL8366RB_VLAN_PRIORITY_MASK;
1525 	vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) &
1526 		RTL8366RB_VLAN_UNTAG_MASK;
1527 	vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK;
1528 	vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK;
1529 
1530 	return 0;
1531 }
1532 
1533 static int rtl8366rb_set_vlan_mc(struct realtek_priv *priv, u32 index,
1534 				 const struct rtl8366_vlan_mc *vlanmc)
1535 {
1536 	u32 data[3];
1537 	int ret;
1538 	int i;
1539 
1540 	if (index >= RTL8366RB_NUM_VLANS ||
1541 	    vlanmc->vid >= RTL8366RB_NUM_VIDS ||
1542 	    vlanmc->priority > RTL8366RB_PRIORITYMAX ||
1543 	    vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK ||
1544 	    vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK ||
1545 	    vlanmc->fid > RTL8366RB_FIDMAX)
1546 		return -EINVAL;
1547 
1548 	data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) |
1549 		  ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) <<
1550 			RTL8366RB_VLAN_PRIORITY_SHIFT);
1551 	data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) |
1552 		  ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) <<
1553 			RTL8366RB_VLAN_UNTAG_SHIFT);
1554 	data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK;
1555 
1556 	for (i = 0; i < 3; i++) {
1557 		ret = regmap_write(priv->map,
1558 				   RTL8366RB_VLAN_MC_BASE(index) + i,
1559 				   data[i]);
1560 		if (ret)
1561 			return ret;
1562 	}
1563 
1564 	return 0;
1565 }
1566 
1567 static int rtl8366rb_get_mc_index(struct realtek_priv *priv, int port, int *val)
1568 {
1569 	u32 data;
1570 	int ret;
1571 
1572 	if (port >= priv->num_ports)
1573 		return -EINVAL;
1574 
1575 	ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1576 			  &data);
1577 	if (ret)
1578 		return ret;
1579 
1580 	*val = (data >> RTL8366RB_PORT_VLAN_CTRL_SHIFT(port)) &
1581 		RTL8366RB_PORT_VLAN_CTRL_MASK;
1582 
1583 	return 0;
1584 }
1585 
1586 static int rtl8366rb_set_mc_index(struct realtek_priv *priv, int port, int index)
1587 {
1588 	struct rtl8366rb *rb;
1589 	bool pvid_enabled;
1590 	int ret;
1591 
1592 	rb = priv->chip_data;
1593 	pvid_enabled = !!index;
1594 
1595 	if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS)
1596 		return -EINVAL;
1597 
1598 	ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port),
1599 				 RTL8366RB_PORT_VLAN_CTRL_MASK <<
1600 					RTL8366RB_PORT_VLAN_CTRL_SHIFT(port),
1601 				 (index & RTL8366RB_PORT_VLAN_CTRL_MASK) <<
1602 					RTL8366RB_PORT_VLAN_CTRL_SHIFT(port));
1603 	if (ret)
1604 		return ret;
1605 
1606 	rb->pvid_enabled[port] = pvid_enabled;
1607 
1608 	/* If VLAN filtering is enabled and PVID is also enabled, we must
1609 	 * not drop any untagged or C-tagged frames. Make sure to update the
1610 	 * filtering setting.
1611 	 */
1612 	if (dsa_port_is_vlan_filtering(dsa_to_port(priv->ds, port)))
1613 		ret = rtl8366rb_drop_untagged(priv, port, !pvid_enabled);
1614 
1615 	return ret;
1616 }
1617 
1618 static bool rtl8366rb_is_vlan_valid(struct realtek_priv *priv, unsigned int vlan)
1619 {
1620 	unsigned int max = RTL8366RB_NUM_VLANS - 1;
1621 
1622 	if (priv->vlan4k_enabled)
1623 		max = RTL8366RB_NUM_VIDS - 1;
1624 
1625 	if (vlan > max)
1626 		return false;
1627 
1628 	return true;
1629 }
1630 
1631 static int rtl8366rb_enable_vlan(struct realtek_priv *priv, bool enable)
1632 {
1633 	dev_dbg(priv->dev, "%s VLAN\n", enable ? "enable" : "disable");
1634 	return regmap_update_bits(priv->map,
1635 				  RTL8366RB_SGCR, RTL8366RB_SGCR_EN_VLAN,
1636 				  enable ? RTL8366RB_SGCR_EN_VLAN : 0);
1637 }
1638 
1639 static int rtl8366rb_enable_vlan4k(struct realtek_priv *priv, bool enable)
1640 {
1641 	dev_dbg(priv->dev, "%s VLAN 4k\n", enable ? "enable" : "disable");
1642 	return regmap_update_bits(priv->map, RTL8366RB_SGCR,
1643 				  RTL8366RB_SGCR_EN_VLAN_4KTB,
1644 				  enable ? RTL8366RB_SGCR_EN_VLAN_4KTB : 0);
1645 }
1646 
1647 static int rtl8366rb_phy_read(struct realtek_priv *priv, int phy, int regnum)
1648 {
1649 	u32 val;
1650 	u32 reg;
1651 	int ret;
1652 
1653 	if (phy > RTL8366RB_PHY_NO_MAX)
1654 		return -EINVAL;
1655 
1656 	ret = regmap_write(priv->map, RTL8366RB_PHY_ACCESS_CTRL_REG,
1657 			   RTL8366RB_PHY_CTRL_READ);
1658 	if (ret)
1659 		return ret;
1660 
1661 	reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1662 
1663 	ret = regmap_write(priv->map, reg, 0);
1664 	if (ret) {
1665 		dev_err(priv->dev,
1666 			"failed to write PHY%d reg %04x @ %04x, ret %d\n",
1667 			phy, regnum, reg, ret);
1668 		return ret;
1669 	}
1670 
1671 	ret = regmap_read(priv->map, RTL8366RB_PHY_ACCESS_DATA_REG, &val);
1672 	if (ret)
1673 		return ret;
1674 
1675 	dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n",
1676 		phy, regnum, reg, val);
1677 
1678 	return val;
1679 }
1680 
1681 static int rtl8366rb_phy_write(struct realtek_priv *priv, int phy, int regnum,
1682 			       u16 val)
1683 {
1684 	u32 reg;
1685 	int ret;
1686 
1687 	if (phy > RTL8366RB_PHY_NO_MAX)
1688 		return -EINVAL;
1689 
1690 	ret = regmap_write(priv->map, RTL8366RB_PHY_ACCESS_CTRL_REG,
1691 			   RTL8366RB_PHY_CTRL_WRITE);
1692 	if (ret)
1693 		return ret;
1694 
1695 	reg = 0x8000 | (1 << (phy + RTL8366RB_PHY_NO_OFFSET)) | regnum;
1696 
1697 	dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n",
1698 		phy, regnum, reg, val);
1699 
1700 	ret = regmap_write(priv->map, reg, val);
1701 	if (ret)
1702 		return ret;
1703 
1704 	return 0;
1705 }
1706 
1707 static int rtl8366rb_dsa_phy_read(struct dsa_switch *ds, int phy, int regnum)
1708 {
1709 	return rtl8366rb_phy_read(ds->priv, phy, regnum);
1710 }
1711 
1712 static int rtl8366rb_dsa_phy_write(struct dsa_switch *ds, int phy, int regnum,
1713 				   u16 val)
1714 {
1715 	return rtl8366rb_phy_write(ds->priv, phy, regnum, val);
1716 }
1717 
1718 static int rtl8366rb_reset_chip(struct realtek_priv *priv)
1719 {
1720 	int timeout = 10;
1721 	u32 val;
1722 	int ret;
1723 
1724 	priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG,
1725 			      RTL8366RB_CHIP_CTRL_RESET_HW);
1726 	do {
1727 		usleep_range(20000, 25000);
1728 		ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val);
1729 		if (ret)
1730 			return ret;
1731 
1732 		if (!(val & RTL8366RB_CHIP_CTRL_RESET_HW))
1733 			break;
1734 	} while (--timeout);
1735 
1736 	if (!timeout) {
1737 		dev_err(priv->dev, "timeout waiting for the switch to reset\n");
1738 		return -EIO;
1739 	}
1740 
1741 	return 0;
1742 }
1743 
1744 static int rtl8366rb_detect(struct realtek_priv *priv)
1745 {
1746 	struct device *dev = priv->dev;
1747 	int ret;
1748 	u32 val;
1749 
1750 	/* Detect device */
1751 	ret = regmap_read(priv->map, 0x5c, &val);
1752 	if (ret) {
1753 		dev_err(dev, "can't get chip ID (%d)\n", ret);
1754 		return ret;
1755 	}
1756 
1757 	switch (val) {
1758 	case 0x6027:
1759 		dev_info(dev, "found an RTL8366S switch\n");
1760 		dev_err(dev, "this switch is not yet supported, submit patches!\n");
1761 		return -ENODEV;
1762 	case 0x5937:
1763 		dev_info(dev, "found an RTL8366RB switch\n");
1764 		priv->cpu_port = RTL8366RB_PORT_NUM_CPU;
1765 		priv->num_ports = RTL8366RB_NUM_PORTS;
1766 		priv->num_vlan_mc = RTL8366RB_NUM_VLANS;
1767 		priv->mib_counters = rtl8366rb_mib_counters;
1768 		priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters);
1769 		break;
1770 	default:
1771 		dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n",
1772 			 val);
1773 		break;
1774 	}
1775 
1776 	ret = rtl8366rb_reset_chip(priv);
1777 	if (ret)
1778 		return ret;
1779 
1780 	return 0;
1781 }
1782 
1783 static const struct dsa_switch_ops rtl8366rb_switch_ops_smi = {
1784 	.get_tag_protocol = rtl8366_get_tag_protocol,
1785 	.setup = rtl8366rb_setup,
1786 	.phylink_mac_link_up = rtl8366rb_mac_link_up,
1787 	.phylink_mac_link_down = rtl8366rb_mac_link_down,
1788 	.get_strings = rtl8366_get_strings,
1789 	.get_ethtool_stats = rtl8366_get_ethtool_stats,
1790 	.get_sset_count = rtl8366_get_sset_count,
1791 	.port_bridge_join = rtl8366rb_port_bridge_join,
1792 	.port_bridge_leave = rtl8366rb_port_bridge_leave,
1793 	.port_vlan_filtering = rtl8366rb_vlan_filtering,
1794 	.port_vlan_add = rtl8366_vlan_add,
1795 	.port_vlan_del = rtl8366_vlan_del,
1796 	.port_enable = rtl8366rb_port_enable,
1797 	.port_disable = rtl8366rb_port_disable,
1798 	.port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
1799 	.port_bridge_flags = rtl8366rb_port_bridge_flags,
1800 	.port_stp_state_set = rtl8366rb_port_stp_state_set,
1801 	.port_fast_age = rtl8366rb_port_fast_age,
1802 	.port_change_mtu = rtl8366rb_change_mtu,
1803 	.port_max_mtu = rtl8366rb_max_mtu,
1804 };
1805 
1806 static const struct dsa_switch_ops rtl8366rb_switch_ops_mdio = {
1807 	.get_tag_protocol = rtl8366_get_tag_protocol,
1808 	.setup = rtl8366rb_setup,
1809 	.phy_read = rtl8366rb_dsa_phy_read,
1810 	.phy_write = rtl8366rb_dsa_phy_write,
1811 	.phylink_mac_link_up = rtl8366rb_mac_link_up,
1812 	.phylink_mac_link_down = rtl8366rb_mac_link_down,
1813 	.get_strings = rtl8366_get_strings,
1814 	.get_ethtool_stats = rtl8366_get_ethtool_stats,
1815 	.get_sset_count = rtl8366_get_sset_count,
1816 	.port_bridge_join = rtl8366rb_port_bridge_join,
1817 	.port_bridge_leave = rtl8366rb_port_bridge_leave,
1818 	.port_vlan_filtering = rtl8366rb_vlan_filtering,
1819 	.port_vlan_add = rtl8366_vlan_add,
1820 	.port_vlan_del = rtl8366_vlan_del,
1821 	.port_enable = rtl8366rb_port_enable,
1822 	.port_disable = rtl8366rb_port_disable,
1823 	.port_pre_bridge_flags = rtl8366rb_port_pre_bridge_flags,
1824 	.port_bridge_flags = rtl8366rb_port_bridge_flags,
1825 	.port_stp_state_set = rtl8366rb_port_stp_state_set,
1826 	.port_fast_age = rtl8366rb_port_fast_age,
1827 	.port_change_mtu = rtl8366rb_change_mtu,
1828 	.port_max_mtu = rtl8366rb_max_mtu,
1829 };
1830 
1831 static const struct realtek_ops rtl8366rb_ops = {
1832 	.detect		= rtl8366rb_detect,
1833 	.get_vlan_mc	= rtl8366rb_get_vlan_mc,
1834 	.set_vlan_mc	= rtl8366rb_set_vlan_mc,
1835 	.get_vlan_4k	= rtl8366rb_get_vlan_4k,
1836 	.set_vlan_4k	= rtl8366rb_set_vlan_4k,
1837 	.get_mc_index	= rtl8366rb_get_mc_index,
1838 	.set_mc_index	= rtl8366rb_set_mc_index,
1839 	.get_mib_counter = rtl8366rb_get_mib_counter,
1840 	.is_vlan_valid	= rtl8366rb_is_vlan_valid,
1841 	.enable_vlan	= rtl8366rb_enable_vlan,
1842 	.enable_vlan4k	= rtl8366rb_enable_vlan4k,
1843 	.phy_read	= rtl8366rb_phy_read,
1844 	.phy_write	= rtl8366rb_phy_write,
1845 };
1846 
1847 const struct realtek_variant rtl8366rb_variant = {
1848 	.ds_ops_smi = &rtl8366rb_switch_ops_smi,
1849 	.ds_ops_mdio = &rtl8366rb_switch_ops_mdio,
1850 	.ops = &rtl8366rb_ops,
1851 	.clk_delay = 10,
1852 	.cmd_read = 0xa9,
1853 	.cmd_write = 0xa8,
1854 	.chip_data_sz = sizeof(struct rtl8366rb),
1855 };
1856 EXPORT_SYMBOL_GPL(rtl8366rb_variant);
1857 
1858 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1859 MODULE_DESCRIPTION("Driver for RTL8366RB ethernet switch");
1860 MODULE_LICENSE("GPL");
1861