1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name> 4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> 5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2016 John Crispin <john@phrozen.org> 7 */ 8 9 #include <linux/netdevice.h> 10 #include <net/dsa.h> 11 #include <linux/if_bridge.h> 12 13 #include "qca8k.h" 14 15 #define MIB_DESC(_s, _o, _n) \ 16 { \ 17 .size = (_s), \ 18 .offset = (_o), \ 19 .name = (_n), \ 20 } 21 22 const struct qca8k_mib_desc ar8327_mib[] = { 23 MIB_DESC(1, 0x00, "RxBroad"), 24 MIB_DESC(1, 0x04, "RxPause"), 25 MIB_DESC(1, 0x08, "RxMulti"), 26 MIB_DESC(1, 0x0c, "RxFcsErr"), 27 MIB_DESC(1, 0x10, "RxAlignErr"), 28 MIB_DESC(1, 0x14, "RxRunt"), 29 MIB_DESC(1, 0x18, "RxFragment"), 30 MIB_DESC(1, 0x1c, "Rx64Byte"), 31 MIB_DESC(1, 0x20, "Rx128Byte"), 32 MIB_DESC(1, 0x24, "Rx256Byte"), 33 MIB_DESC(1, 0x28, "Rx512Byte"), 34 MIB_DESC(1, 0x2c, "Rx1024Byte"), 35 MIB_DESC(1, 0x30, "Rx1518Byte"), 36 MIB_DESC(1, 0x34, "RxMaxByte"), 37 MIB_DESC(1, 0x38, "RxTooLong"), 38 MIB_DESC(2, 0x3c, "RxGoodByte"), 39 MIB_DESC(2, 0x44, "RxBadByte"), 40 MIB_DESC(1, 0x4c, "RxOverFlow"), 41 MIB_DESC(1, 0x50, "Filtered"), 42 MIB_DESC(1, 0x54, "TxBroad"), 43 MIB_DESC(1, 0x58, "TxPause"), 44 MIB_DESC(1, 0x5c, "TxMulti"), 45 MIB_DESC(1, 0x60, "TxUnderRun"), 46 MIB_DESC(1, 0x64, "Tx64Byte"), 47 MIB_DESC(1, 0x68, "Tx128Byte"), 48 MIB_DESC(1, 0x6c, "Tx256Byte"), 49 MIB_DESC(1, 0x70, "Tx512Byte"), 50 MIB_DESC(1, 0x74, "Tx1024Byte"), 51 MIB_DESC(1, 0x78, "Tx1518Byte"), 52 MIB_DESC(1, 0x7c, "TxMaxByte"), 53 MIB_DESC(1, 0x80, "TxOverSize"), 54 MIB_DESC(2, 0x84, "TxByte"), 55 MIB_DESC(1, 0x8c, "TxCollision"), 56 MIB_DESC(1, 0x90, "TxAbortCol"), 57 MIB_DESC(1, 0x94, "TxMultiCol"), 58 MIB_DESC(1, 0x98, "TxSingleCol"), 59 MIB_DESC(1, 0x9c, "TxExcDefer"), 60 MIB_DESC(1, 0xa0, "TxDefer"), 61 MIB_DESC(1, 0xa4, "TxLateCol"), 62 MIB_DESC(1, 0xa8, "RXUnicast"), 63 MIB_DESC(1, 0xac, "TXUnicast"), 64 }; 65 66 int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val) 67 { 68 return regmap_read(priv->regmap, reg, val); 69 } 70 71 int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val) 72 { 73 return regmap_write(priv->regmap, reg, val); 74 } 75 76 int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val) 77 { 78 return regmap_update_bits(priv->regmap, reg, mask, write_val); 79 } 80 81 static const struct regmap_range qca8k_readable_ranges[] = { 82 regmap_reg_range(0x0000, 0x00e4), /* Global control */ 83 regmap_reg_range(0x0100, 0x0168), /* EEE control */ 84 regmap_reg_range(0x0200, 0x0270), /* Parser control */ 85 regmap_reg_range(0x0400, 0x0454), /* ACL */ 86 regmap_reg_range(0x0600, 0x0718), /* Lookup */ 87 regmap_reg_range(0x0800, 0x0b70), /* QM */ 88 regmap_reg_range(0x0c00, 0x0c80), /* PKT */ 89 regmap_reg_range(0x0e00, 0x0e98), /* L3 */ 90 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */ 91 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */ 92 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */ 93 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */ 94 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */ 95 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */ 96 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */ 97 }; 98 99 const struct regmap_access_table qca8k_readable_table = { 100 .yes_ranges = qca8k_readable_ranges, 101 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges), 102 }; 103 104 static int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask) 105 { 106 u32 val; 107 108 return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0, 109 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC); 110 } 111 112 static int qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb) 113 { 114 u32 reg[QCA8K_ATU_TABLE_SIZE]; 115 int ret; 116 117 /* load the ARL table into an array */ 118 ret = regmap_bulk_read(priv->regmap, QCA8K_REG_ATU_DATA0, reg, 119 QCA8K_ATU_TABLE_SIZE); 120 if (ret) 121 return ret; 122 123 /* vid - 83:72 */ 124 fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]); 125 /* aging - 67:64 */ 126 fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]); 127 /* portmask - 54:48 */ 128 fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]); 129 /* mac - 47:0 */ 130 fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]); 131 fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]); 132 fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]); 133 fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]); 134 fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]); 135 fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]); 136 137 return 0; 138 } 139 140 static void qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, 141 const u8 *mac, u8 aging) 142 { 143 u32 reg[QCA8K_ATU_TABLE_SIZE] = { 0 }; 144 145 /* vid - 83:72 */ 146 reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid); 147 /* aging - 67:64 */ 148 reg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging); 149 /* portmask - 54:48 */ 150 reg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask); 151 /* mac - 47:0 */ 152 reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]); 153 reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]); 154 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]); 155 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]); 156 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]); 157 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]); 158 159 /* load the array into the ARL table */ 160 regmap_bulk_write(priv->regmap, QCA8K_REG_ATU_DATA0, reg, 161 QCA8K_ATU_TABLE_SIZE); 162 } 163 164 static int qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, 165 int port) 166 { 167 u32 reg; 168 int ret; 169 170 /* Set the command and FDB index */ 171 reg = QCA8K_ATU_FUNC_BUSY; 172 reg |= cmd; 173 if (port >= 0) { 174 reg |= QCA8K_ATU_FUNC_PORT_EN; 175 reg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port); 176 } 177 178 /* Write the function register triggering the table access */ 179 ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg); 180 if (ret) 181 return ret; 182 183 /* wait for completion */ 184 ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY); 185 if (ret) 186 return ret; 187 188 /* Check for table full violation when adding an entry */ 189 if (cmd == QCA8K_FDB_LOAD) { 190 ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, ®); 191 if (ret < 0) 192 return ret; 193 if (reg & QCA8K_ATU_FUNC_FULL) 194 return -1; 195 } 196 197 return 0; 198 } 199 200 static int qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, 201 int port) 202 { 203 int ret; 204 205 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging); 206 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port); 207 if (ret < 0) 208 return ret; 209 210 return qca8k_fdb_read(priv, fdb); 211 } 212 213 static int qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, 214 u16 port_mask, u16 vid, u8 aging) 215 { 216 int ret; 217 218 mutex_lock(&priv->reg_mutex); 219 qca8k_fdb_write(priv, vid, port_mask, mac, aging); 220 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); 221 mutex_unlock(&priv->reg_mutex); 222 223 return ret; 224 } 225 226 static int qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, 227 u16 port_mask, u16 vid) 228 { 229 int ret; 230 231 mutex_lock(&priv->reg_mutex); 232 qca8k_fdb_write(priv, vid, port_mask, mac, 0); 233 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); 234 mutex_unlock(&priv->reg_mutex); 235 236 return ret; 237 } 238 239 void qca8k_fdb_flush(struct qca8k_priv *priv) 240 { 241 mutex_lock(&priv->reg_mutex); 242 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1); 243 mutex_unlock(&priv->reg_mutex); 244 } 245 246 static int qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask, 247 const u8 *mac, u16 vid, u8 aging) 248 { 249 struct qca8k_fdb fdb = { 0 }; 250 int ret; 251 252 mutex_lock(&priv->reg_mutex); 253 254 qca8k_fdb_write(priv, vid, 0, mac, 0); 255 ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); 256 if (ret < 0) 257 goto exit; 258 259 ret = qca8k_fdb_read(priv, &fdb); 260 if (ret < 0) 261 goto exit; 262 263 /* Rule exist. Delete first */ 264 if (fdb.aging) { 265 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); 266 if (ret) 267 goto exit; 268 } else { 269 fdb.aging = aging; 270 } 271 272 /* Add port to fdb portmask */ 273 fdb.port_mask |= port_mask; 274 275 qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging); 276 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); 277 278 exit: 279 mutex_unlock(&priv->reg_mutex); 280 return ret; 281 } 282 283 static int qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask, 284 const u8 *mac, u16 vid) 285 { 286 struct qca8k_fdb fdb = { 0 }; 287 int ret; 288 289 mutex_lock(&priv->reg_mutex); 290 291 qca8k_fdb_write(priv, vid, 0, mac, 0); 292 ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); 293 if (ret < 0) 294 goto exit; 295 296 ret = qca8k_fdb_read(priv, &fdb); 297 if (ret < 0) 298 goto exit; 299 300 /* Rule doesn't exist. Why delete? */ 301 if (!fdb.aging) { 302 ret = -EINVAL; 303 goto exit; 304 } 305 306 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); 307 if (ret) 308 goto exit; 309 310 /* Only port in the rule is this port. Don't re insert */ 311 if (fdb.port_mask == port_mask) 312 goto exit; 313 314 /* Remove port from port mask */ 315 fdb.port_mask &= ~port_mask; 316 317 qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging); 318 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); 319 320 exit: 321 mutex_unlock(&priv->reg_mutex); 322 return ret; 323 } 324 325 static int qca8k_vlan_access(struct qca8k_priv *priv, 326 enum qca8k_vlan_cmd cmd, u16 vid) 327 { 328 u32 reg; 329 int ret; 330 331 /* Set the command and VLAN index */ 332 reg = QCA8K_VTU_FUNC1_BUSY; 333 reg |= cmd; 334 reg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid); 335 336 /* Write the function register triggering the table access */ 337 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg); 338 if (ret) 339 return ret; 340 341 /* wait for completion */ 342 ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY); 343 if (ret) 344 return ret; 345 346 /* Check for table full violation when adding an entry */ 347 if (cmd == QCA8K_VLAN_LOAD) { 348 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, ®); 349 if (ret < 0) 350 return ret; 351 if (reg & QCA8K_VTU_FUNC1_FULL) 352 return -ENOMEM; 353 } 354 355 return 0; 356 } 357 358 static int qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, 359 bool untagged) 360 { 361 u32 reg; 362 int ret; 363 364 /* We do the right thing with VLAN 0 and treat it as untagged while 365 * preserving the tag on egress. 366 */ 367 if (vid == 0) 368 return 0; 369 370 mutex_lock(&priv->reg_mutex); 371 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid); 372 if (ret < 0) 373 goto out; 374 375 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); 376 if (ret < 0) 377 goto out; 378 reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN; 379 reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port); 380 if (untagged) 381 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port); 382 else 383 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port); 384 385 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); 386 if (ret) 387 goto out; 388 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); 389 390 out: 391 mutex_unlock(&priv->reg_mutex); 392 393 return ret; 394 } 395 396 static int qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid) 397 { 398 u32 reg, mask; 399 int ret, i; 400 bool del; 401 402 mutex_lock(&priv->reg_mutex); 403 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid); 404 if (ret < 0) 405 goto out; 406 407 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®); 408 if (ret < 0) 409 goto out; 410 reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port); 411 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port); 412 413 /* Check if we're the last member to be removed */ 414 del = true; 415 for (i = 0; i < QCA8K_NUM_PORTS; i++) { 416 mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i); 417 418 if ((reg & mask) != mask) { 419 del = false; 420 break; 421 } 422 } 423 424 if (del) { 425 ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid); 426 } else { 427 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg); 428 if (ret) 429 goto out; 430 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid); 431 } 432 433 out: 434 mutex_unlock(&priv->reg_mutex); 435 436 return ret; 437 } 438 439 int qca8k_mib_init(struct qca8k_priv *priv) 440 { 441 int ret; 442 443 mutex_lock(&priv->reg_mutex); 444 ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB, 445 QCA8K_MIB_FUNC | QCA8K_MIB_BUSY, 446 FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_FLUSH) | 447 QCA8K_MIB_BUSY); 448 if (ret) 449 goto exit; 450 451 ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY); 452 if (ret) 453 goto exit; 454 455 ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); 456 if (ret) 457 goto exit; 458 459 ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB); 460 461 exit: 462 mutex_unlock(&priv->reg_mutex); 463 return ret; 464 } 465 466 void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable) 467 { 468 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC; 469 470 /* Port 0 and 6 have no internal PHY */ 471 if (port > 0 && port < 6) 472 mask |= QCA8K_PORT_STATUS_LINK_AUTO; 473 474 if (enable) 475 regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); 476 else 477 regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); 478 } 479 480 void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, 481 uint8_t *data) 482 { 483 struct qca8k_priv *priv = ds->priv; 484 int i; 485 486 if (stringset != ETH_SS_STATS) 487 return; 488 489 for (i = 0; i < priv->info->mib_count; i++) 490 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name, 491 ETH_GSTRING_LEN); 492 } 493 494 void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port, 495 uint64_t *data) 496 { 497 struct qca8k_priv *priv = ds->priv; 498 const struct qca8k_mib_desc *mib; 499 u32 reg, i, val; 500 u32 hi = 0; 501 int ret; 502 503 if (priv->mgmt_master && priv->info->ops->autocast_mib && 504 priv->info->ops->autocast_mib(ds, port, data) > 0) 505 return; 506 507 for (i = 0; i < priv->info->mib_count; i++) { 508 mib = &ar8327_mib[i]; 509 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset; 510 511 ret = qca8k_read(priv, reg, &val); 512 if (ret < 0) 513 continue; 514 515 if (mib->size == 2) { 516 ret = qca8k_read(priv, reg + 4, &hi); 517 if (ret < 0) 518 continue; 519 } 520 521 data[i] = val; 522 if (mib->size == 2) 523 data[i] |= (u64)hi << 32; 524 } 525 } 526 527 int qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset) 528 { 529 struct qca8k_priv *priv = ds->priv; 530 531 if (sset != ETH_SS_STATS) 532 return 0; 533 534 return priv->info->mib_count; 535 } 536 537 int qca8k_set_mac_eee(struct dsa_switch *ds, int port, 538 struct ethtool_eee *eee) 539 { 540 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port); 541 struct qca8k_priv *priv = ds->priv; 542 u32 reg; 543 int ret; 544 545 mutex_lock(&priv->reg_mutex); 546 ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, ®); 547 if (ret < 0) 548 goto exit; 549 550 if (eee->eee_enabled) 551 reg |= lpi_en; 552 else 553 reg &= ~lpi_en; 554 ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg); 555 556 exit: 557 mutex_unlock(&priv->reg_mutex); 558 return ret; 559 } 560 561 int qca8k_get_mac_eee(struct dsa_switch *ds, int port, 562 struct ethtool_eee *e) 563 { 564 /* Nothing to do on the port's MAC */ 565 return 0; 566 } 567 568 void qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 569 { 570 struct qca8k_priv *priv = ds->priv; 571 u32 stp_state; 572 573 switch (state) { 574 case BR_STATE_DISABLED: 575 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED; 576 break; 577 case BR_STATE_BLOCKING: 578 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING; 579 break; 580 case BR_STATE_LISTENING: 581 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING; 582 break; 583 case BR_STATE_LEARNING: 584 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING; 585 break; 586 case BR_STATE_FORWARDING: 587 default: 588 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD; 589 break; 590 } 591 592 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), 593 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state); 594 } 595 596 int qca8k_port_bridge_join(struct dsa_switch *ds, int port, 597 struct dsa_bridge bridge, 598 bool *tx_fwd_offload, 599 struct netlink_ext_ack *extack) 600 { 601 struct qca8k_priv *priv = ds->priv; 602 int port_mask, cpu_port; 603 int i, ret; 604 605 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 606 port_mask = BIT(cpu_port); 607 608 for (i = 0; i < QCA8K_NUM_PORTS; i++) { 609 if (dsa_is_cpu_port(ds, i)) 610 continue; 611 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 612 continue; 613 /* Add this port to the portvlan mask of the other ports 614 * in the bridge 615 */ 616 ret = regmap_set_bits(priv->regmap, 617 QCA8K_PORT_LOOKUP_CTRL(i), 618 BIT(port)); 619 if (ret) 620 return ret; 621 if (i != port) 622 port_mask |= BIT(i); 623 } 624 625 /* Add all other ports to this ports portvlan mask */ 626 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), 627 QCA8K_PORT_LOOKUP_MEMBER, port_mask); 628 629 return ret; 630 } 631 632 void qca8k_port_bridge_leave(struct dsa_switch *ds, int port, 633 struct dsa_bridge bridge) 634 { 635 struct qca8k_priv *priv = ds->priv; 636 int cpu_port, i; 637 638 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; 639 640 for (i = 0; i < QCA8K_NUM_PORTS; i++) { 641 if (dsa_is_cpu_port(ds, i)) 642 continue; 643 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge)) 644 continue; 645 /* Remove this port to the portvlan mask of the other ports 646 * in the bridge 647 */ 648 regmap_clear_bits(priv->regmap, 649 QCA8K_PORT_LOOKUP_CTRL(i), 650 BIT(port)); 651 } 652 653 /* Set the cpu port to be the only one in the portvlan mask of 654 * this port 655 */ 656 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), 657 QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port)); 658 } 659 660 void qca8k_port_fast_age(struct dsa_switch *ds, int port) 661 { 662 struct qca8k_priv *priv = ds->priv; 663 664 mutex_lock(&priv->reg_mutex); 665 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port); 666 mutex_unlock(&priv->reg_mutex); 667 } 668 669 int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 670 { 671 struct qca8k_priv *priv = ds->priv; 672 unsigned int secs = msecs / 1000; 673 u32 val; 674 675 /* AGE_TIME reg is set in 7s step */ 676 val = secs / 7; 677 678 /* Handle case with 0 as val to NOT disable 679 * learning 680 */ 681 if (!val) 682 val = 1; 683 684 return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, 685 QCA8K_ATU_AGE_TIME_MASK, 686 QCA8K_ATU_AGE_TIME(val)); 687 } 688 689 int qca8k_port_enable(struct dsa_switch *ds, int port, 690 struct phy_device *phy) 691 { 692 struct qca8k_priv *priv = ds->priv; 693 694 qca8k_port_set_status(priv, port, 1); 695 priv->port_enabled_map |= BIT(port); 696 697 if (dsa_is_user_port(ds, port)) 698 phy_support_asym_pause(phy); 699 700 return 0; 701 } 702 703 void qca8k_port_disable(struct dsa_switch *ds, int port) 704 { 705 struct qca8k_priv *priv = ds->priv; 706 707 qca8k_port_set_status(priv, port, 0); 708 priv->port_enabled_map &= ~BIT(port); 709 } 710 711 int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 712 { 713 struct qca8k_priv *priv = ds->priv; 714 int ret; 715 716 /* We have only have a general MTU setting. 717 * DSA always set the CPU port's MTU to the largest MTU of the slave 718 * ports. 719 * Setting MTU just for the CPU port is sufficient to correctly set a 720 * value for every port. 721 */ 722 if (!dsa_is_cpu_port(ds, port)) 723 return 0; 724 725 /* To change the MAX_FRAME_SIZE the cpu ports must be off or 726 * the switch panics. 727 * Turn off both cpu ports before applying the new value to prevent 728 * this. 729 */ 730 if (priv->port_enabled_map & BIT(0)) 731 qca8k_port_set_status(priv, 0, 0); 732 733 if (priv->port_enabled_map & BIT(6)) 734 qca8k_port_set_status(priv, 6, 0); 735 736 /* Include L2 header / FCS length */ 737 ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu + 738 ETH_HLEN + ETH_FCS_LEN); 739 740 if (priv->port_enabled_map & BIT(0)) 741 qca8k_port_set_status(priv, 0, 1); 742 743 if (priv->port_enabled_map & BIT(6)) 744 qca8k_port_set_status(priv, 6, 1); 745 746 return ret; 747 } 748 749 int qca8k_port_max_mtu(struct dsa_switch *ds, int port) 750 { 751 return QCA8K_MAX_MTU; 752 } 753 754 int qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr, 755 u16 port_mask, u16 vid) 756 { 757 /* Set the vid to the port vlan id if no vid is set */ 758 if (!vid) 759 vid = QCA8K_PORT_VID_DEF; 760 761 return qca8k_fdb_add(priv, addr, port_mask, vid, 762 QCA8K_ATU_STATUS_STATIC); 763 } 764 765 int qca8k_port_fdb_add(struct dsa_switch *ds, int port, 766 const unsigned char *addr, u16 vid, 767 struct dsa_db db) 768 { 769 struct qca8k_priv *priv = ds->priv; 770 u16 port_mask = BIT(port); 771 772 return qca8k_port_fdb_insert(priv, addr, port_mask, vid); 773 } 774 775 int qca8k_port_fdb_del(struct dsa_switch *ds, int port, 776 const unsigned char *addr, u16 vid, 777 struct dsa_db db) 778 { 779 struct qca8k_priv *priv = ds->priv; 780 u16 port_mask = BIT(port); 781 782 if (!vid) 783 vid = QCA8K_PORT_VID_DEF; 784 785 return qca8k_fdb_del(priv, addr, port_mask, vid); 786 } 787 788 int qca8k_port_fdb_dump(struct dsa_switch *ds, int port, 789 dsa_fdb_dump_cb_t *cb, void *data) 790 { 791 struct qca8k_priv *priv = ds->priv; 792 struct qca8k_fdb _fdb = { 0 }; 793 int cnt = QCA8K_NUM_FDB_RECORDS; 794 bool is_static; 795 int ret = 0; 796 797 mutex_lock(&priv->reg_mutex); 798 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) { 799 if (!_fdb.aging) 800 break; 801 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC); 802 ret = cb(_fdb.mac, _fdb.vid, is_static, data); 803 if (ret) 804 break; 805 } 806 mutex_unlock(&priv->reg_mutex); 807 808 return 0; 809 } 810 811 int qca8k_port_mdb_add(struct dsa_switch *ds, int port, 812 const struct switchdev_obj_port_mdb *mdb, 813 struct dsa_db db) 814 { 815 struct qca8k_priv *priv = ds->priv; 816 const u8 *addr = mdb->addr; 817 u16 vid = mdb->vid; 818 819 if (!vid) 820 vid = QCA8K_PORT_VID_DEF; 821 822 return qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid, 823 QCA8K_ATU_STATUS_STATIC); 824 } 825 826 int qca8k_port_mdb_del(struct dsa_switch *ds, int port, 827 const struct switchdev_obj_port_mdb *mdb, 828 struct dsa_db db) 829 { 830 struct qca8k_priv *priv = ds->priv; 831 const u8 *addr = mdb->addr; 832 u16 vid = mdb->vid; 833 834 if (!vid) 835 vid = QCA8K_PORT_VID_DEF; 836 837 return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid); 838 } 839 840 int qca8k_port_mirror_add(struct dsa_switch *ds, int port, 841 struct dsa_mall_mirror_tc_entry *mirror, 842 bool ingress, struct netlink_ext_ack *extack) 843 { 844 struct qca8k_priv *priv = ds->priv; 845 int monitor_port, ret; 846 u32 reg, val; 847 848 /* Check for existent entry */ 849 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 850 return -EEXIST; 851 852 ret = regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val); 853 if (ret) 854 return ret; 855 856 /* QCA83xx can have only one port set to mirror mode. 857 * Check that the correct port is requested and return error otherwise. 858 * When no mirror port is set, the values is set to 0xF 859 */ 860 monitor_port = FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val); 861 if (monitor_port != 0xF && monitor_port != mirror->to_local_port) 862 return -EEXIST; 863 864 /* Set the monitor port */ 865 val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 866 mirror->to_local_port); 867 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, 868 QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val); 869 if (ret) 870 return ret; 871 872 if (ingress) { 873 reg = QCA8K_PORT_LOOKUP_CTRL(port); 874 val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN; 875 } else { 876 reg = QCA8K_REG_PORT_HOL_CTRL1(port); 877 val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN; 878 } 879 880 ret = regmap_update_bits(priv->regmap, reg, val, val); 881 if (ret) 882 return ret; 883 884 /* Track mirror port for tx and rx to decide when the 885 * mirror port has to be disabled. 886 */ 887 if (ingress) 888 priv->mirror_rx |= BIT(port); 889 else 890 priv->mirror_tx |= BIT(port); 891 892 return 0; 893 } 894 895 void qca8k_port_mirror_del(struct dsa_switch *ds, int port, 896 struct dsa_mall_mirror_tc_entry *mirror) 897 { 898 struct qca8k_priv *priv = ds->priv; 899 u32 reg, val; 900 int ret; 901 902 if (mirror->ingress) { 903 reg = QCA8K_PORT_LOOKUP_CTRL(port); 904 val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN; 905 } else { 906 reg = QCA8K_REG_PORT_HOL_CTRL1(port); 907 val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN; 908 } 909 910 ret = regmap_clear_bits(priv->regmap, reg, val); 911 if (ret) 912 goto err; 913 914 if (mirror->ingress) 915 priv->mirror_rx &= ~BIT(port); 916 else 917 priv->mirror_tx &= ~BIT(port); 918 919 /* No port set to send packet to mirror port. Disable mirror port */ 920 if (!priv->mirror_rx && !priv->mirror_tx) { 921 val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF); 922 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, 923 QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val); 924 if (ret) 925 goto err; 926 } 927 err: 928 dev_err(priv->dev, "Failed to del mirror port from %d", port); 929 } 930 931 int qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, 932 bool vlan_filtering, 933 struct netlink_ext_ack *extack) 934 { 935 struct qca8k_priv *priv = ds->priv; 936 int ret; 937 938 if (vlan_filtering) { 939 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), 940 QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, 941 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE); 942 } else { 943 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), 944 QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, 945 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE); 946 } 947 948 return ret; 949 } 950 951 int qca8k_port_vlan_add(struct dsa_switch *ds, int port, 952 const struct switchdev_obj_port_vlan *vlan, 953 struct netlink_ext_ack *extack) 954 { 955 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 956 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 957 struct qca8k_priv *priv = ds->priv; 958 int ret; 959 960 ret = qca8k_vlan_add(priv, port, vlan->vid, untagged); 961 if (ret) { 962 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret); 963 return ret; 964 } 965 966 if (pvid) { 967 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), 968 QCA8K_EGREES_VLAN_PORT_MASK(port), 969 QCA8K_EGREES_VLAN_PORT(port, vlan->vid)); 970 if (ret) 971 return ret; 972 973 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), 974 QCA8K_PORT_VLAN_CVID(vlan->vid) | 975 QCA8K_PORT_VLAN_SVID(vlan->vid)); 976 } 977 978 return ret; 979 } 980 981 int qca8k_port_vlan_del(struct dsa_switch *ds, int port, 982 const struct switchdev_obj_port_vlan *vlan) 983 { 984 struct qca8k_priv *priv = ds->priv; 985 int ret; 986 987 ret = qca8k_vlan_del(priv, port, vlan->vid); 988 if (ret) 989 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret); 990 991 return ret; 992 } 993 994 static bool qca8k_lag_can_offload(struct dsa_switch *ds, 995 struct dsa_lag lag, 996 struct netdev_lag_upper_info *info, 997 struct netlink_ext_ack *extack) 998 { 999 struct dsa_port *dp; 1000 int members = 0; 1001 1002 if (!lag.id) 1003 return false; 1004 1005 dsa_lag_foreach_port(dp, ds->dst, &lag) 1006 /* Includes the port joining the LAG */ 1007 members++; 1008 1009 if (members > QCA8K_NUM_PORTS_FOR_LAG) { 1010 NL_SET_ERR_MSG_MOD(extack, 1011 "Cannot offload more than 4 LAG ports"); 1012 return false; 1013 } 1014 1015 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1016 NL_SET_ERR_MSG_MOD(extack, 1017 "Can only offload LAG using hash TX type"); 1018 return false; 1019 } 1020 1021 if (info->hash_type != NETDEV_LAG_HASH_L2 && 1022 info->hash_type != NETDEV_LAG_HASH_L23) { 1023 NL_SET_ERR_MSG_MOD(extack, 1024 "Can only offload L2 or L2+L3 TX hash"); 1025 return false; 1026 } 1027 1028 return true; 1029 } 1030 1031 static int qca8k_lag_setup_hash(struct dsa_switch *ds, 1032 struct dsa_lag lag, 1033 struct netdev_lag_upper_info *info) 1034 { 1035 struct net_device *lag_dev = lag.dev; 1036 struct qca8k_priv *priv = ds->priv; 1037 bool unique_lag = true; 1038 unsigned int i; 1039 u32 hash = 0; 1040 1041 switch (info->hash_type) { 1042 case NETDEV_LAG_HASH_L23: 1043 hash |= QCA8K_TRUNK_HASH_SIP_EN; 1044 hash |= QCA8K_TRUNK_HASH_DIP_EN; 1045 fallthrough; 1046 case NETDEV_LAG_HASH_L2: 1047 hash |= QCA8K_TRUNK_HASH_SA_EN; 1048 hash |= QCA8K_TRUNK_HASH_DA_EN; 1049 break; 1050 default: /* We should NEVER reach this */ 1051 return -EOPNOTSUPP; 1052 } 1053 1054 /* Check if we are the unique configured LAG */ 1055 dsa_lags_foreach_id(i, ds->dst) 1056 if (i != lag.id && dsa_lag_by_id(ds->dst, i)) { 1057 unique_lag = false; 1058 break; 1059 } 1060 1061 /* Hash Mode is global. Make sure the same Hash Mode 1062 * is set to all the 4 possible lag. 1063 * If we are the unique LAG we can set whatever hash 1064 * mode we want. 1065 * To change hash mode it's needed to remove all LAG 1066 * and change the mode with the latest. 1067 */ 1068 if (unique_lag) { 1069 priv->lag_hash_mode = hash; 1070 } else if (priv->lag_hash_mode != hash) { 1071 netdev_err(lag_dev, "Error: Mismatched Hash Mode across different lag is not supported\n"); 1072 return -EOPNOTSUPP; 1073 } 1074 1075 return regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL, 1076 QCA8K_TRUNK_HASH_MASK, hash); 1077 } 1078 1079 static int qca8k_lag_refresh_portmap(struct dsa_switch *ds, int port, 1080 struct dsa_lag lag, bool delete) 1081 { 1082 struct qca8k_priv *priv = ds->priv; 1083 int ret, id, i; 1084 u32 val; 1085 1086 /* DSA LAG IDs are one-based, hardware is zero-based */ 1087 id = lag.id - 1; 1088 1089 /* Read current port member */ 1090 ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val); 1091 if (ret) 1092 return ret; 1093 1094 /* Shift val to the correct trunk */ 1095 val >>= QCA8K_REG_GOL_TRUNK_SHIFT(id); 1096 val &= QCA8K_REG_GOL_TRUNK_MEMBER_MASK; 1097 if (delete) 1098 val &= ~BIT(port); 1099 else 1100 val |= BIT(port); 1101 1102 /* Update port member. With empty portmap disable trunk */ 1103 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, 1104 QCA8K_REG_GOL_TRUNK_MEMBER(id) | 1105 QCA8K_REG_GOL_TRUNK_EN(id), 1106 !val << QCA8K_REG_GOL_TRUNK_SHIFT(id) | 1107 val << QCA8K_REG_GOL_TRUNK_SHIFT(id)); 1108 1109 /* Search empty member if adding or port on deleting */ 1110 for (i = 0; i < QCA8K_NUM_PORTS_FOR_LAG; i++) { 1111 ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val); 1112 if (ret) 1113 return ret; 1114 1115 val >>= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i); 1116 val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK; 1117 1118 if (delete) { 1119 /* If port flagged to be disabled assume this member is 1120 * empty 1121 */ 1122 if (val != QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK) 1123 continue; 1124 1125 val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK; 1126 if (val != port) 1127 continue; 1128 } else { 1129 /* If port flagged to be enabled assume this member is 1130 * already set 1131 */ 1132 if (val == QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK) 1133 continue; 1134 } 1135 1136 /* We have found the member to add/remove */ 1137 break; 1138 } 1139 1140 /* Set port in the correct port mask or disable port if in delete mode */ 1141 return regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), 1142 QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(id, i) | 1143 QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(id, i), 1144 !delete << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i) | 1145 port << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i)); 1146 } 1147 1148 int qca8k_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag lag, 1149 struct netdev_lag_upper_info *info, 1150 struct netlink_ext_ack *extack) 1151 { 1152 int ret; 1153 1154 if (!qca8k_lag_can_offload(ds, lag, info, extack)) 1155 return -EOPNOTSUPP; 1156 1157 ret = qca8k_lag_setup_hash(ds, lag, info); 1158 if (ret) 1159 return ret; 1160 1161 return qca8k_lag_refresh_portmap(ds, port, lag, false); 1162 } 1163 1164 int qca8k_port_lag_leave(struct dsa_switch *ds, int port, 1165 struct dsa_lag lag) 1166 { 1167 return qca8k_lag_refresh_portmap(ds, port, lag, true); 1168 } 1169 1170 int qca8k_read_switch_id(struct qca8k_priv *priv) 1171 { 1172 u32 val; 1173 u8 id; 1174 int ret; 1175 1176 if (!priv->info) 1177 return -ENODEV; 1178 1179 ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val); 1180 if (ret < 0) 1181 return -ENODEV; 1182 1183 id = QCA8K_MASK_CTRL_DEVICE_ID(val); 1184 if (id != priv->info->id) { 1185 dev_err(priv->dev, 1186 "Switch id detected %x but expected %x", 1187 id, priv->info->id); 1188 return -ENODEV; 1189 } 1190 1191 priv->switch_id = id; 1192 1193 /* Save revision to communicate to the internal PHY driver */ 1194 priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val); 1195 1196 return 0; 1197 } 1198