1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name> 4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> 5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2016 John Crispin <john@phrozen.org> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/phy.h> 11 #include <linux/netdevice.h> 12 #include <linux/bitfield.h> 13 #include <linux/regmap.h> 14 #include <net/dsa.h> 15 #include <linux/of_net.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_platform.h> 18 #include <linux/mdio.h> 19 #include <linux/phylink.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/etherdevice.h> 22 #include <linux/dsa/tag_qca.h> 23 24 #include "qca8k.h" 25 #include "qca8k_leds.h" 26 27 static void 28 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page) 29 { 30 regaddr >>= 1; 31 *r1 = regaddr & 0x1e; 32 33 regaddr >>= 5; 34 *r2 = regaddr & 0x7; 35 36 regaddr >>= 3; 37 *page = regaddr & 0x3ff; 38 } 39 40 static int 41 qca8k_mii_write_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 val) 42 { 43 int ret; 44 u16 lo; 45 46 lo = val & 0xffff; 47 ret = bus->write(bus, phy_id, regnum, lo); 48 if (ret < 0) 49 dev_err_ratelimited(&bus->dev, 50 "failed to write qca8k 32bit lo register\n"); 51 52 return ret; 53 } 54 55 static int 56 qca8k_mii_write_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 val) 57 { 58 int ret; 59 u16 hi; 60 61 hi = (u16)(val >> 16); 62 ret = bus->write(bus, phy_id, regnum, hi); 63 if (ret < 0) 64 dev_err_ratelimited(&bus->dev, 65 "failed to write qca8k 32bit hi register\n"); 66 67 return ret; 68 } 69 70 static int 71 qca8k_mii_read_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val) 72 { 73 int ret; 74 75 ret = bus->read(bus, phy_id, regnum); 76 if (ret < 0) 77 goto err; 78 79 *val = ret & 0xffff; 80 return 0; 81 82 err: 83 dev_err_ratelimited(&bus->dev, 84 "failed to read qca8k 32bit lo register\n"); 85 *val = 0; 86 87 return ret; 88 } 89 90 static int 91 qca8k_mii_read_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val) 92 { 93 int ret; 94 95 ret = bus->read(bus, phy_id, regnum); 96 if (ret < 0) 97 goto err; 98 99 *val = ret << 16; 100 return 0; 101 102 err: 103 dev_err_ratelimited(&bus->dev, 104 "failed to read qca8k 32bit hi register\n"); 105 *val = 0; 106 107 return ret; 108 } 109 110 static int 111 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val) 112 { 113 u32 hi, lo; 114 int ret; 115 116 *val = 0; 117 118 ret = qca8k_mii_read_lo(bus, phy_id, regnum, &lo); 119 if (ret < 0) 120 goto err; 121 122 ret = qca8k_mii_read_hi(bus, phy_id, regnum + 1, &hi); 123 if (ret < 0) 124 goto err; 125 126 *val = lo | hi; 127 128 err: 129 return ret; 130 } 131 132 static void 133 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val) 134 { 135 if (qca8k_mii_write_lo(bus, phy_id, regnum, val) < 0) 136 return; 137 138 qca8k_mii_write_hi(bus, phy_id, regnum + 1, val); 139 } 140 141 static int 142 qca8k_set_page(struct qca8k_priv *priv, u16 page) 143 { 144 u16 *cached_page = &priv->mdio_cache.page; 145 struct mii_bus *bus = priv->bus; 146 int ret; 147 148 if (page == *cached_page) 149 return 0; 150 151 ret = bus->write(bus, 0x18, 0, page); 152 if (ret < 0) { 153 dev_err_ratelimited(&bus->dev, 154 "failed to set qca8k page\n"); 155 return ret; 156 } 157 158 *cached_page = page; 159 usleep_range(1000, 2000); 160 return 0; 161 } 162 163 static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb) 164 { 165 struct qca8k_mgmt_eth_data *mgmt_eth_data; 166 struct qca8k_priv *priv = ds->priv; 167 struct qca_mgmt_ethhdr *mgmt_ethhdr; 168 u32 command; 169 u8 len, cmd; 170 int i; 171 172 mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb_mac_header(skb); 173 mgmt_eth_data = &priv->mgmt_eth_data; 174 175 command = get_unaligned_le32(&mgmt_ethhdr->command); 176 cmd = FIELD_GET(QCA_HDR_MGMT_CMD, command); 177 178 len = FIELD_GET(QCA_HDR_MGMT_LENGTH, command); 179 /* Special case for len of 15 as this is the max value for len and needs to 180 * be increased before converting it from word to dword. 181 */ 182 if (len == 15) 183 len++; 184 185 /* We can ignore odd value, we always round up them in the alloc function. */ 186 len *= sizeof(u16); 187 188 /* Make sure the seq match the requested packet */ 189 if (get_unaligned_le32(&mgmt_ethhdr->seq) == mgmt_eth_data->seq) 190 mgmt_eth_data->ack = true; 191 192 if (cmd == MDIO_READ) { 193 u32 *val = mgmt_eth_data->data; 194 195 *val = get_unaligned_le32(&mgmt_ethhdr->mdio_data); 196 197 /* Get the rest of the 12 byte of data. 198 * The read/write function will extract the requested data. 199 */ 200 if (len > QCA_HDR_MGMT_DATA1_LEN) { 201 __le32 *data2 = (__le32 *)skb->data; 202 int data_len = min_t(int, QCA_HDR_MGMT_DATA2_LEN, 203 len - QCA_HDR_MGMT_DATA1_LEN); 204 205 val++; 206 207 for (i = sizeof(u32); i <= data_len; i += sizeof(u32)) { 208 *val = get_unaligned_le32(data2); 209 val++; 210 data2++; 211 } 212 } 213 } 214 215 complete(&mgmt_eth_data->rw_done); 216 } 217 218 static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *val, 219 int priority, unsigned int len) 220 { 221 struct qca_mgmt_ethhdr *mgmt_ethhdr; 222 unsigned int real_len; 223 struct sk_buff *skb; 224 __le32 *data2; 225 u32 command; 226 u16 hdr; 227 int i; 228 229 skb = dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN); 230 if (!skb) 231 return NULL; 232 233 /* Hdr mgmt length value is in step of word size. 234 * As an example to process 4 byte of data the correct length to set is 2. 235 * To process 8 byte 4, 12 byte 6, 16 byte 8... 236 * 237 * Odd values will always return the next size on the ack packet. 238 * (length of 3 (6 byte) will always return 8 bytes of data) 239 * 240 * This means that a value of 15 (0xf) actually means reading/writing 32 bytes 241 * of data. 242 * 243 * To correctly calculate the length we devide the requested len by word and 244 * round up. 245 * On the ack function we can skip the odd check as we already handle the 246 * case here. 247 */ 248 real_len = DIV_ROUND_UP(len, sizeof(u16)); 249 250 /* We check if the result len is odd and we round up another time to 251 * the next size. (length of 3 will be increased to 4 as switch will always 252 * return 8 bytes) 253 */ 254 if (real_len % sizeof(u16) != 0) 255 real_len++; 256 257 /* Max reg value is 0xf(15) but switch will always return the next size (32 byte) */ 258 if (real_len == 16) 259 real_len--; 260 261 skb_reset_mac_header(skb); 262 skb_set_network_header(skb, skb->len); 263 264 mgmt_ethhdr = skb_push(skb, QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN); 265 266 hdr = FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION); 267 hdr |= FIELD_PREP(QCA_HDR_XMIT_PRIORITY, priority); 268 hdr |= QCA_HDR_XMIT_FROM_CPU; 269 hdr |= FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(0)); 270 hdr |= FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG); 271 272 command = FIELD_PREP(QCA_HDR_MGMT_ADDR, reg); 273 command |= FIELD_PREP(QCA_HDR_MGMT_LENGTH, real_len); 274 command |= FIELD_PREP(QCA_HDR_MGMT_CMD, cmd); 275 command |= FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE, 276 QCA_HDR_MGMT_CHECK_CODE_VAL); 277 278 put_unaligned_le32(command, &mgmt_ethhdr->command); 279 280 if (cmd == MDIO_WRITE) 281 put_unaligned_le32(*val, &mgmt_ethhdr->mdio_data); 282 283 mgmt_ethhdr->hdr = htons(hdr); 284 285 data2 = skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN); 286 if (cmd == MDIO_WRITE && len > QCA_HDR_MGMT_DATA1_LEN) { 287 int data_len = min_t(int, QCA_HDR_MGMT_DATA2_LEN, 288 len - QCA_HDR_MGMT_DATA1_LEN); 289 290 val++; 291 292 for (i = sizeof(u32); i <= data_len; i += sizeof(u32)) { 293 put_unaligned_le32(*val, data2); 294 data2++; 295 val++; 296 } 297 } 298 299 return skb; 300 } 301 302 static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_num) 303 { 304 struct qca_mgmt_ethhdr *mgmt_ethhdr; 305 u32 seq; 306 307 seq = FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num); 308 mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb->data; 309 put_unaligned_le32(seq, &mgmt_ethhdr->seq); 310 } 311 312 static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len) 313 { 314 struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data; 315 struct sk_buff *skb; 316 bool ack; 317 int ret; 318 319 skb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL, 320 QCA8K_ETHERNET_MDIO_PRIORITY, len); 321 if (!skb) 322 return -ENOMEM; 323 324 mutex_lock(&mgmt_eth_data->mutex); 325 326 /* Check mgmt_master if is operational */ 327 if (!priv->mgmt_master) { 328 kfree_skb(skb); 329 mutex_unlock(&mgmt_eth_data->mutex); 330 return -EINVAL; 331 } 332 333 skb->dev = priv->mgmt_master; 334 335 reinit_completion(&mgmt_eth_data->rw_done); 336 337 /* Increment seq_num and set it in the mdio pkt */ 338 mgmt_eth_data->seq++; 339 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); 340 mgmt_eth_data->ack = false; 341 342 dev_queue_xmit(skb); 343 344 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, 345 msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT)); 346 347 *val = mgmt_eth_data->data[0]; 348 if (len > QCA_HDR_MGMT_DATA1_LEN) 349 memcpy(val + 1, mgmt_eth_data->data + 1, len - QCA_HDR_MGMT_DATA1_LEN); 350 351 ack = mgmt_eth_data->ack; 352 353 mutex_unlock(&mgmt_eth_data->mutex); 354 355 if (ret <= 0) 356 return -ETIMEDOUT; 357 358 if (!ack) 359 return -EINVAL; 360 361 return 0; 362 } 363 364 static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len) 365 { 366 struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data; 367 struct sk_buff *skb; 368 bool ack; 369 int ret; 370 371 skb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, val, 372 QCA8K_ETHERNET_MDIO_PRIORITY, len); 373 if (!skb) 374 return -ENOMEM; 375 376 mutex_lock(&mgmt_eth_data->mutex); 377 378 /* Check mgmt_master if is operational */ 379 if (!priv->mgmt_master) { 380 kfree_skb(skb); 381 mutex_unlock(&mgmt_eth_data->mutex); 382 return -EINVAL; 383 } 384 385 skb->dev = priv->mgmt_master; 386 387 reinit_completion(&mgmt_eth_data->rw_done); 388 389 /* Increment seq_num and set it in the mdio pkt */ 390 mgmt_eth_data->seq++; 391 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); 392 mgmt_eth_data->ack = false; 393 394 dev_queue_xmit(skb); 395 396 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, 397 msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT)); 398 399 ack = mgmt_eth_data->ack; 400 401 mutex_unlock(&mgmt_eth_data->mutex); 402 403 if (ret <= 0) 404 return -ETIMEDOUT; 405 406 if (!ack) 407 return -EINVAL; 408 409 return 0; 410 } 411 412 static int 413 qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val) 414 { 415 u32 val = 0; 416 int ret; 417 418 ret = qca8k_read_eth(priv, reg, &val, sizeof(val)); 419 if (ret) 420 return ret; 421 422 val &= ~mask; 423 val |= write_val; 424 425 return qca8k_write_eth(priv, reg, &val, sizeof(val)); 426 } 427 428 static int 429 qca8k_read_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t *val) 430 { 431 struct mii_bus *bus = priv->bus; 432 u16 r1, r2, page; 433 int ret; 434 435 qca8k_split_addr(reg, &r1, &r2, &page); 436 437 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 438 439 ret = qca8k_set_page(priv, page); 440 if (ret < 0) 441 goto exit; 442 443 ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val); 444 445 exit: 446 mutex_unlock(&bus->mdio_lock); 447 return ret; 448 } 449 450 static int 451 qca8k_write_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t val) 452 { 453 struct mii_bus *bus = priv->bus; 454 u16 r1, r2, page; 455 int ret; 456 457 qca8k_split_addr(reg, &r1, &r2, &page); 458 459 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 460 461 ret = qca8k_set_page(priv, page); 462 if (ret < 0) 463 goto exit; 464 465 qca8k_mii_write32(bus, 0x10 | r2, r1, val); 466 467 exit: 468 mutex_unlock(&bus->mdio_lock); 469 return ret; 470 } 471 472 static int 473 qca8k_regmap_update_bits_mii(struct qca8k_priv *priv, uint32_t reg, 474 uint32_t mask, uint32_t write_val) 475 { 476 struct mii_bus *bus = priv->bus; 477 u16 r1, r2, page; 478 u32 val; 479 int ret; 480 481 qca8k_split_addr(reg, &r1, &r2, &page); 482 483 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 484 485 ret = qca8k_set_page(priv, page); 486 if (ret < 0) 487 goto exit; 488 489 ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val); 490 if (ret < 0) 491 goto exit; 492 493 val &= ~mask; 494 val |= write_val; 495 qca8k_mii_write32(bus, 0x10 | r2, r1, val); 496 497 exit: 498 mutex_unlock(&bus->mdio_lock); 499 500 return ret; 501 } 502 503 static int 504 qca8k_bulk_read(void *ctx, const void *reg_buf, size_t reg_len, 505 void *val_buf, size_t val_len) 506 { 507 int i, count = val_len / sizeof(u32), ret; 508 struct qca8k_priv *priv = ctx; 509 u32 reg = *(u16 *)reg_buf; 510 511 if (priv->mgmt_master && 512 !qca8k_read_eth(priv, reg, val_buf, val_len)) 513 return 0; 514 515 /* loop count times and increment reg of 4 */ 516 for (i = 0; i < count; i++, reg += sizeof(u32)) { 517 ret = qca8k_read_mii(priv, reg, val_buf + i); 518 if (ret < 0) 519 return ret; 520 } 521 522 return 0; 523 } 524 525 static int 526 qca8k_bulk_gather_write(void *ctx, const void *reg_buf, size_t reg_len, 527 const void *val_buf, size_t val_len) 528 { 529 int i, count = val_len / sizeof(u32), ret; 530 struct qca8k_priv *priv = ctx; 531 u32 reg = *(u16 *)reg_buf; 532 u32 *val = (u32 *)val_buf; 533 534 if (priv->mgmt_master && 535 !qca8k_write_eth(priv, reg, val, val_len)) 536 return 0; 537 538 /* loop count times, increment reg of 4 and increment val ptr to 539 * the next value 540 */ 541 for (i = 0; i < count; i++, reg += sizeof(u32), val++) { 542 ret = qca8k_write_mii(priv, reg, *val); 543 if (ret < 0) 544 return ret; 545 } 546 547 return 0; 548 } 549 550 static int 551 qca8k_bulk_write(void *ctx, const void *data, size_t bytes) 552 { 553 return qca8k_bulk_gather_write(ctx, data, sizeof(u16), data + sizeof(u16), 554 bytes - sizeof(u16)); 555 } 556 557 static int 558 qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val) 559 { 560 struct qca8k_priv *priv = ctx; 561 562 if (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val)) 563 return 0; 564 565 return qca8k_regmap_update_bits_mii(priv, reg, mask, write_val); 566 } 567 568 static struct regmap_config qca8k_regmap_config = { 569 .reg_bits = 16, 570 .val_bits = 32, 571 .reg_stride = 4, 572 .max_register = 0x16ac, /* end MIB - Port6 range */ 573 .read = qca8k_bulk_read, 574 .write = qca8k_bulk_write, 575 .reg_update_bits = qca8k_regmap_update_bits, 576 .rd_table = &qca8k_readable_table, 577 .disable_locking = true, /* Locking is handled by qca8k read/write */ 578 .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */ 579 .max_raw_read = 32, /* mgmt eth can read up to 8 registers at time */ 580 /* ATU regs suffer from a bug where some data are not correctly 581 * written. Disable bulk write to correctly write ATU entry. 582 */ 583 .use_single_write = true, 584 }; 585 586 static int 587 qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data, 588 struct sk_buff *read_skb, u32 *val) 589 { 590 struct sk_buff *skb = skb_copy(read_skb, GFP_KERNEL); 591 bool ack; 592 int ret; 593 594 if (!skb) 595 return -ENOMEM; 596 597 reinit_completion(&mgmt_eth_data->rw_done); 598 599 /* Increment seq_num and set it in the copy pkt */ 600 mgmt_eth_data->seq++; 601 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); 602 mgmt_eth_data->ack = false; 603 604 dev_queue_xmit(skb); 605 606 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, 607 QCA8K_ETHERNET_TIMEOUT); 608 609 ack = mgmt_eth_data->ack; 610 611 if (ret <= 0) 612 return -ETIMEDOUT; 613 614 if (!ack) 615 return -EINVAL; 616 617 *val = mgmt_eth_data->data[0]; 618 619 return 0; 620 } 621 622 static int 623 qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy, 624 int regnum, u16 data) 625 { 626 struct sk_buff *write_skb, *clear_skb, *read_skb; 627 struct qca8k_mgmt_eth_data *mgmt_eth_data; 628 u32 write_val, clear_val = 0, val; 629 struct net_device *mgmt_master; 630 int ret, ret1; 631 bool ack; 632 633 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) 634 return -EINVAL; 635 636 mgmt_eth_data = &priv->mgmt_eth_data; 637 638 write_val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | 639 QCA8K_MDIO_MASTER_PHY_ADDR(phy) | 640 QCA8K_MDIO_MASTER_REG_ADDR(regnum); 641 642 if (read) { 643 write_val |= QCA8K_MDIO_MASTER_READ; 644 } else { 645 write_val |= QCA8K_MDIO_MASTER_WRITE; 646 write_val |= QCA8K_MDIO_MASTER_DATA(data); 647 } 648 649 /* Prealloc all the needed skb before the lock */ 650 write_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &write_val, 651 QCA8K_ETHERNET_PHY_PRIORITY, sizeof(write_val)); 652 if (!write_skb) 653 return -ENOMEM; 654 655 clear_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &clear_val, 656 QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val)); 657 if (!clear_skb) { 658 ret = -ENOMEM; 659 goto err_clear_skb; 660 } 661 662 read_skb = qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, &clear_val, 663 QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val)); 664 if (!read_skb) { 665 ret = -ENOMEM; 666 goto err_read_skb; 667 } 668 669 /* It seems that accessing the switch's internal PHYs via management 670 * packets still uses the MDIO bus within the switch internally, and 671 * these accesses can conflict with external MDIO accesses to other 672 * devices on the MDIO bus. 673 * We therefore need to lock the MDIO bus onto which the switch is 674 * connected. 675 */ 676 mutex_lock(&priv->bus->mdio_lock); 677 678 /* Actually start the request: 679 * 1. Send mdio master packet 680 * 2. Busy Wait for mdio master command 681 * 3. Get the data if we are reading 682 * 4. Reset the mdio master (even with error) 683 */ 684 mutex_lock(&mgmt_eth_data->mutex); 685 686 /* Check if mgmt_master is operational */ 687 mgmt_master = priv->mgmt_master; 688 if (!mgmt_master) { 689 mutex_unlock(&mgmt_eth_data->mutex); 690 mutex_unlock(&priv->bus->mdio_lock); 691 ret = -EINVAL; 692 goto err_mgmt_master; 693 } 694 695 read_skb->dev = mgmt_master; 696 clear_skb->dev = mgmt_master; 697 write_skb->dev = mgmt_master; 698 699 reinit_completion(&mgmt_eth_data->rw_done); 700 701 /* Increment seq_num and set it in the write pkt */ 702 mgmt_eth_data->seq++; 703 qca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data->seq); 704 mgmt_eth_data->ack = false; 705 706 dev_queue_xmit(write_skb); 707 708 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, 709 QCA8K_ETHERNET_TIMEOUT); 710 711 ack = mgmt_eth_data->ack; 712 713 if (ret <= 0) { 714 ret = -ETIMEDOUT; 715 kfree_skb(read_skb); 716 goto exit; 717 } 718 719 if (!ack) { 720 ret = -EINVAL; 721 kfree_skb(read_skb); 722 goto exit; 723 } 724 725 ret = read_poll_timeout(qca8k_phy_eth_busy_wait, ret1, 726 !(val & QCA8K_MDIO_MASTER_BUSY), 0, 727 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, 728 mgmt_eth_data, read_skb, &val); 729 730 if (ret < 0 && ret1 < 0) { 731 ret = ret1; 732 goto exit; 733 } 734 735 if (read) { 736 reinit_completion(&mgmt_eth_data->rw_done); 737 738 /* Increment seq_num and set it in the read pkt */ 739 mgmt_eth_data->seq++; 740 qca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data->seq); 741 mgmt_eth_data->ack = false; 742 743 dev_queue_xmit(read_skb); 744 745 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, 746 QCA8K_ETHERNET_TIMEOUT); 747 748 ack = mgmt_eth_data->ack; 749 750 if (ret <= 0) { 751 ret = -ETIMEDOUT; 752 goto exit; 753 } 754 755 if (!ack) { 756 ret = -EINVAL; 757 goto exit; 758 } 759 760 ret = mgmt_eth_data->data[0] & QCA8K_MDIO_MASTER_DATA_MASK; 761 } else { 762 kfree_skb(read_skb); 763 } 764 exit: 765 reinit_completion(&mgmt_eth_data->rw_done); 766 767 /* Increment seq_num and set it in the clear pkt */ 768 mgmt_eth_data->seq++; 769 qca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data->seq); 770 mgmt_eth_data->ack = false; 771 772 dev_queue_xmit(clear_skb); 773 774 wait_for_completion_timeout(&mgmt_eth_data->rw_done, 775 QCA8K_ETHERNET_TIMEOUT); 776 777 mutex_unlock(&mgmt_eth_data->mutex); 778 mutex_unlock(&priv->bus->mdio_lock); 779 780 return ret; 781 782 /* Error handling before lock */ 783 err_mgmt_master: 784 kfree_skb(read_skb); 785 err_read_skb: 786 kfree_skb(clear_skb); 787 err_clear_skb: 788 kfree_skb(write_skb); 789 790 return ret; 791 } 792 793 static int 794 qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask) 795 { 796 u16 r1, r2, page; 797 u32 val; 798 int ret, ret1; 799 800 qca8k_split_addr(reg, &r1, &r2, &page); 801 802 ret = read_poll_timeout(qca8k_mii_read_hi, ret1, !(val & mask), 0, 803 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, 804 bus, 0x10 | r2, r1 + 1, &val); 805 806 /* Check if qca8k_read has failed for a different reason 807 * before returnting -ETIMEDOUT 808 */ 809 if (ret < 0 && ret1 < 0) 810 return ret1; 811 812 return ret; 813 } 814 815 static int 816 qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data) 817 { 818 struct mii_bus *bus = priv->bus; 819 u16 r1, r2, page; 820 u32 val; 821 int ret; 822 823 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) 824 return -EINVAL; 825 826 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | 827 QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | 828 QCA8K_MDIO_MASTER_REG_ADDR(regnum) | 829 QCA8K_MDIO_MASTER_DATA(data); 830 831 qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); 832 833 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 834 835 ret = qca8k_set_page(priv, page); 836 if (ret) 837 goto exit; 838 839 qca8k_mii_write32(bus, 0x10 | r2, r1, val); 840 841 ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL, 842 QCA8K_MDIO_MASTER_BUSY); 843 844 exit: 845 /* even if the busy_wait timeouts try to clear the MASTER_EN */ 846 qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0); 847 848 mutex_unlock(&bus->mdio_lock); 849 850 return ret; 851 } 852 853 static int 854 qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum) 855 { 856 struct mii_bus *bus = priv->bus; 857 u16 r1, r2, page; 858 u32 val; 859 int ret; 860 861 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) 862 return -EINVAL; 863 864 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | 865 QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | 866 QCA8K_MDIO_MASTER_REG_ADDR(regnum); 867 868 qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); 869 870 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 871 872 ret = qca8k_set_page(priv, page); 873 if (ret) 874 goto exit; 875 876 qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, val); 877 878 ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL, 879 QCA8K_MDIO_MASTER_BUSY); 880 if (ret) 881 goto exit; 882 883 ret = qca8k_mii_read_lo(bus, 0x10 | r2, r1, &val); 884 885 exit: 886 /* even if the busy_wait timeouts try to clear the MASTER_EN */ 887 qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0); 888 889 mutex_unlock(&bus->mdio_lock); 890 891 if (ret >= 0) 892 ret = val & QCA8K_MDIO_MASTER_DATA_MASK; 893 894 return ret; 895 } 896 897 static int 898 qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data) 899 { 900 struct qca8k_priv *priv = slave_bus->priv; 901 int ret; 902 903 /* Use mdio Ethernet when available, fallback to legacy one on error */ 904 ret = qca8k_phy_eth_command(priv, false, phy, regnum, data); 905 if (!ret) 906 return 0; 907 908 return qca8k_mdio_write(priv, phy, regnum, data); 909 } 910 911 static int 912 qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum) 913 { 914 struct qca8k_priv *priv = slave_bus->priv; 915 int ret; 916 917 /* Use mdio Ethernet when available, fallback to legacy one on error */ 918 ret = qca8k_phy_eth_command(priv, true, phy, regnum, 0); 919 if (ret >= 0) 920 return ret; 921 922 ret = qca8k_mdio_read(priv, phy, regnum); 923 924 if (ret < 0) 925 return 0xffff; 926 927 return ret; 928 } 929 930 static int 931 qca8k_legacy_mdio_write(struct mii_bus *slave_bus, int port, int regnum, u16 data) 932 { 933 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR; 934 935 return qca8k_internal_mdio_write(slave_bus, port, regnum, data); 936 } 937 938 static int 939 qca8k_legacy_mdio_read(struct mii_bus *slave_bus, int port, int regnum) 940 { 941 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR; 942 943 return qca8k_internal_mdio_read(slave_bus, port, regnum); 944 } 945 946 static int 947 qca8k_mdio_register(struct qca8k_priv *priv) 948 { 949 struct dsa_switch *ds = priv->ds; 950 struct device_node *mdio; 951 struct mii_bus *bus; 952 int err; 953 954 mdio = of_get_child_by_name(priv->dev->of_node, "mdio"); 955 956 bus = devm_mdiobus_alloc(ds->dev); 957 if (!bus) { 958 err = -ENOMEM; 959 goto out_put_node; 960 } 961 962 bus->priv = (void *)priv; 963 snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d.%d", 964 ds->dst->index, ds->index); 965 bus->parent = ds->dev; 966 bus->phy_mask = ~ds->phys_mii_mask; 967 ds->slave_mii_bus = bus; 968 969 /* Check if the devicetree declare the port:phy mapping */ 970 if (of_device_is_available(mdio)) { 971 bus->name = "qca8k slave mii"; 972 bus->read = qca8k_internal_mdio_read; 973 bus->write = qca8k_internal_mdio_write; 974 err = devm_of_mdiobus_register(priv->dev, bus, mdio); 975 goto out_put_node; 976 } 977 978 /* If a mapping can't be found the legacy mapping is used, 979 * using the qca8k_port_to_phy function 980 */ 981 bus->name = "qca8k-legacy slave mii"; 982 bus->read = qca8k_legacy_mdio_read; 983 bus->write = qca8k_legacy_mdio_write; 984 985 err = devm_mdiobus_register(priv->dev, bus); 986 987 out_put_node: 988 of_node_put(mdio); 989 990 return err; 991 } 992 993 static int 994 qca8k_setup_mdio_bus(struct qca8k_priv *priv) 995 { 996 u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg; 997 struct device_node *ports, *port; 998 phy_interface_t mode; 999 int err; 1000 1001 ports = of_get_child_by_name(priv->dev->of_node, "ports"); 1002 if (!ports) 1003 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports"); 1004 1005 if (!ports) 1006 return -EINVAL; 1007 1008 for_each_available_child_of_node(ports, port) { 1009 err = of_property_read_u32(port, "reg", ®); 1010 if (err) { 1011 of_node_put(port); 1012 of_node_put(ports); 1013 return err; 1014 } 1015 1016 if (!dsa_is_user_port(priv->ds, reg)) 1017 continue; 1018 1019 of_get_phy_mode(port, &mode); 1020 1021 if (of_property_read_bool(port, "phy-handle") && 1022 mode != PHY_INTERFACE_MODE_INTERNAL) 1023 external_mdio_mask |= BIT(reg); 1024 else 1025 internal_mdio_mask |= BIT(reg); 1026 } 1027 1028 of_node_put(ports); 1029 if (!external_mdio_mask && !internal_mdio_mask) { 1030 dev_err(priv->dev, "no PHYs are defined.\n"); 1031 return -EINVAL; 1032 } 1033 1034 /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through 1035 * the MDIO_MASTER register also _disconnects_ the external MDC 1036 * passthrough to the internal PHYs. It's not possible to use both 1037 * configurations at the same time! 1038 * 1039 * Because this came up during the review process: 1040 * If the external mdio-bus driver is capable magically disabling 1041 * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's 1042 * accessors for the time being, it would be possible to pull this 1043 * off. 1044 */ 1045 if (!!external_mdio_mask && !!internal_mdio_mask) { 1046 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n"); 1047 return -EINVAL; 1048 } 1049 1050 if (external_mdio_mask) { 1051 /* Make sure to disable the internal mdio bus in cases 1052 * a dt-overlay and driver reload changed the configuration 1053 */ 1054 1055 return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL, 1056 QCA8K_MDIO_MASTER_EN); 1057 } 1058 1059 return qca8k_mdio_register(priv); 1060 } 1061 1062 static int 1063 qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) 1064 { 1065 u32 mask = 0; 1066 int ret = 0; 1067 1068 /* SoC specific settings for ipq8064. 1069 * If more device require this consider adding 1070 * a dedicated binding. 1071 */ 1072 if (of_machine_is_compatible("qcom,ipq8064")) 1073 mask |= QCA8K_MAC_PWR_RGMII0_1_8V; 1074 1075 /* SoC specific settings for ipq8065 */ 1076 if (of_machine_is_compatible("qcom,ipq8065")) 1077 mask |= QCA8K_MAC_PWR_RGMII1_1_8V; 1078 1079 if (mask) { 1080 ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL, 1081 QCA8K_MAC_PWR_RGMII0_1_8V | 1082 QCA8K_MAC_PWR_RGMII1_1_8V, 1083 mask); 1084 } 1085 1086 return ret; 1087 } 1088 1089 static int qca8k_find_cpu_port(struct dsa_switch *ds) 1090 { 1091 struct qca8k_priv *priv = ds->priv; 1092 1093 /* Find the connected cpu port. Valid port are 0 or 6 */ 1094 if (dsa_is_cpu_port(ds, 0)) 1095 return 0; 1096 1097 dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6"); 1098 1099 if (dsa_is_cpu_port(ds, 6)) 1100 return 6; 1101 1102 return -EINVAL; 1103 } 1104 1105 static int 1106 qca8k_setup_of_pws_reg(struct qca8k_priv *priv) 1107 { 1108 const struct qca8k_match_data *data = priv->info; 1109 struct device_node *node = priv->dev->of_node; 1110 u32 val = 0; 1111 int ret; 1112 1113 /* QCA8327 require to set to the correct mode. 1114 * His bigger brother QCA8328 have the 172 pin layout. 1115 * Should be applied by default but we set this just to make sure. 1116 */ 1117 if (priv->switch_id == QCA8K_ID_QCA8327) { 1118 /* Set the correct package of 148 pin for QCA8327 */ 1119 if (data->reduced_package) 1120 val |= QCA8327_PWS_PACKAGE148_EN; 1121 1122 ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN, 1123 val); 1124 if (ret) 1125 return ret; 1126 } 1127 1128 if (of_property_read_bool(node, "qca,ignore-power-on-sel")) 1129 val |= QCA8K_PWS_POWER_ON_SEL; 1130 1131 if (of_property_read_bool(node, "qca,led-open-drain")) { 1132 if (!(val & QCA8K_PWS_POWER_ON_SEL)) { 1133 dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set."); 1134 return -EINVAL; 1135 } 1136 1137 val |= QCA8K_PWS_LED_OPEN_EN_CSR; 1138 } 1139 1140 return qca8k_rmw(priv, QCA8K_REG_PWS, 1141 QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL, 1142 val); 1143 } 1144 1145 static int 1146 qca8k_parse_port_config(struct qca8k_priv *priv) 1147 { 1148 int port, cpu_port_index = -1, ret; 1149 struct device_node *port_dn; 1150 phy_interface_t mode; 1151 struct dsa_port *dp; 1152 u32 delay; 1153 1154 /* We have 2 CPU port. Check them */ 1155 for (port = 0; port < QCA8K_NUM_PORTS; port++) { 1156 /* Skip every other port */ 1157 if (port != 0 && port != 6) 1158 continue; 1159 1160 dp = dsa_to_port(priv->ds, port); 1161 port_dn = dp->dn; 1162 cpu_port_index++; 1163 1164 if (!of_device_is_available(port_dn)) 1165 continue; 1166 1167 ret = of_get_phy_mode(port_dn, &mode); 1168 if (ret) 1169 continue; 1170 1171 switch (mode) { 1172 case PHY_INTERFACE_MODE_RGMII: 1173 case PHY_INTERFACE_MODE_RGMII_ID: 1174 case PHY_INTERFACE_MODE_RGMII_TXID: 1175 case PHY_INTERFACE_MODE_RGMII_RXID: 1176 case PHY_INTERFACE_MODE_SGMII: 1177 delay = 0; 1178 1179 if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay)) 1180 /* Switch regs accept value in ns, convert ps to ns */ 1181 delay = delay / 1000; 1182 else if (mode == PHY_INTERFACE_MODE_RGMII_ID || 1183 mode == PHY_INTERFACE_MODE_RGMII_TXID) 1184 delay = 1; 1185 1186 if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) { 1187 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); 1188 delay = 3; 1189 } 1190 1191 priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay; 1192 1193 delay = 0; 1194 1195 if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay)) 1196 /* Switch regs accept value in ns, convert ps to ns */ 1197 delay = delay / 1000; 1198 else if (mode == PHY_INTERFACE_MODE_RGMII_ID || 1199 mode == PHY_INTERFACE_MODE_RGMII_RXID) 1200 delay = 2; 1201 1202 if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) { 1203 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); 1204 delay = 3; 1205 } 1206 1207 priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay; 1208 1209 /* Skip sgmii parsing for rgmii* mode */ 1210 if (mode == PHY_INTERFACE_MODE_RGMII || 1211 mode == PHY_INTERFACE_MODE_RGMII_ID || 1212 mode == PHY_INTERFACE_MODE_RGMII_TXID || 1213 mode == PHY_INTERFACE_MODE_RGMII_RXID) 1214 break; 1215 1216 if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge")) 1217 priv->ports_config.sgmii_tx_clk_falling_edge = true; 1218 1219 if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge")) 1220 priv->ports_config.sgmii_rx_clk_falling_edge = true; 1221 1222 if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) { 1223 priv->ports_config.sgmii_enable_pll = true; 1224 1225 if (priv->switch_id == QCA8K_ID_QCA8327) { 1226 dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling"); 1227 priv->ports_config.sgmii_enable_pll = false; 1228 } 1229 1230 if (priv->switch_revision < 2) 1231 dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more."); 1232 } 1233 1234 break; 1235 default: 1236 continue; 1237 } 1238 } 1239 1240 return 0; 1241 } 1242 1243 static void 1244 qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index, 1245 u32 reg) 1246 { 1247 u32 delay, val = 0; 1248 int ret; 1249 1250 /* Delay can be declared in 3 different way. 1251 * Mode to rgmii and internal-delay standard binding defined 1252 * rgmii-id or rgmii-tx/rx phy mode set. 1253 * The parse logic set a delay different than 0 only when one 1254 * of the 3 different way is used. In all other case delay is 1255 * not enabled. With ID or TX/RXID delay is enabled and set 1256 * to the default and recommended value. 1257 */ 1258 if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) { 1259 delay = priv->ports_config.rgmii_tx_delay[cpu_port_index]; 1260 1261 val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) | 1262 QCA8K_PORT_PAD_RGMII_TX_DELAY_EN; 1263 } 1264 1265 if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) { 1266 delay = priv->ports_config.rgmii_rx_delay[cpu_port_index]; 1267 1268 val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) | 1269 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN; 1270 } 1271 1272 /* Set RGMII delay based on the selected values */ 1273 ret = qca8k_rmw(priv, reg, 1274 QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK | 1275 QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK | 1276 QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | 1277 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN, 1278 val); 1279 if (ret) 1280 dev_err(priv->dev, "Failed to set internal delay for CPU port%d", 1281 cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6); 1282 } 1283 1284 static struct phylink_pcs * 1285 qca8k_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 1286 phy_interface_t interface) 1287 { 1288 struct qca8k_priv *priv = ds->priv; 1289 struct phylink_pcs *pcs = NULL; 1290 1291 switch (interface) { 1292 case PHY_INTERFACE_MODE_SGMII: 1293 case PHY_INTERFACE_MODE_1000BASEX: 1294 switch (port) { 1295 case 0: 1296 pcs = &priv->pcs_port_0.pcs; 1297 break; 1298 1299 case 6: 1300 pcs = &priv->pcs_port_6.pcs; 1301 break; 1302 } 1303 break; 1304 1305 default: 1306 break; 1307 } 1308 1309 return pcs; 1310 } 1311 1312 static void 1313 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 1314 const struct phylink_link_state *state) 1315 { 1316 struct qca8k_priv *priv = ds->priv; 1317 int cpu_port_index; 1318 u32 reg; 1319 1320 switch (port) { 1321 case 0: /* 1st CPU port */ 1322 if (state->interface != PHY_INTERFACE_MODE_RGMII && 1323 state->interface != PHY_INTERFACE_MODE_RGMII_ID && 1324 state->interface != PHY_INTERFACE_MODE_RGMII_TXID && 1325 state->interface != PHY_INTERFACE_MODE_RGMII_RXID && 1326 state->interface != PHY_INTERFACE_MODE_SGMII) 1327 return; 1328 1329 reg = QCA8K_REG_PORT0_PAD_CTRL; 1330 cpu_port_index = QCA8K_CPU_PORT0; 1331 break; 1332 case 1: 1333 case 2: 1334 case 3: 1335 case 4: 1336 case 5: 1337 /* Internal PHY, nothing to do */ 1338 return; 1339 case 6: /* 2nd CPU port / external PHY */ 1340 if (state->interface != PHY_INTERFACE_MODE_RGMII && 1341 state->interface != PHY_INTERFACE_MODE_RGMII_ID && 1342 state->interface != PHY_INTERFACE_MODE_RGMII_TXID && 1343 state->interface != PHY_INTERFACE_MODE_RGMII_RXID && 1344 state->interface != PHY_INTERFACE_MODE_SGMII && 1345 state->interface != PHY_INTERFACE_MODE_1000BASEX) 1346 return; 1347 1348 reg = QCA8K_REG_PORT6_PAD_CTRL; 1349 cpu_port_index = QCA8K_CPU_PORT6; 1350 break; 1351 default: 1352 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); 1353 return; 1354 } 1355 1356 if (port != 6 && phylink_autoneg_inband(mode)) { 1357 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 1358 __func__); 1359 return; 1360 } 1361 1362 switch (state->interface) { 1363 case PHY_INTERFACE_MODE_RGMII: 1364 case PHY_INTERFACE_MODE_RGMII_ID: 1365 case PHY_INTERFACE_MODE_RGMII_TXID: 1366 case PHY_INTERFACE_MODE_RGMII_RXID: 1367 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN); 1368 1369 /* Configure rgmii delay */ 1370 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg); 1371 1372 /* QCA8337 requires to set rgmii rx delay for all ports. 1373 * This is enabled through PORT5_PAD_CTRL for all ports, 1374 * rather than individual port registers. 1375 */ 1376 if (priv->switch_id == QCA8K_ID_QCA8337) 1377 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, 1378 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); 1379 break; 1380 case PHY_INTERFACE_MODE_SGMII: 1381 case PHY_INTERFACE_MODE_1000BASEX: 1382 /* Enable SGMII on the port */ 1383 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN); 1384 break; 1385 default: 1386 dev_err(ds->dev, "xMII mode %s not supported for port %d\n", 1387 phy_modes(state->interface), port); 1388 return; 1389 } 1390 } 1391 1392 static void qca8k_phylink_get_caps(struct dsa_switch *ds, int port, 1393 struct phylink_config *config) 1394 { 1395 switch (port) { 1396 case 0: /* 1st CPU port */ 1397 phy_interface_set_rgmii(config->supported_interfaces); 1398 __set_bit(PHY_INTERFACE_MODE_SGMII, 1399 config->supported_interfaces); 1400 break; 1401 1402 case 1: 1403 case 2: 1404 case 3: 1405 case 4: 1406 case 5: 1407 /* Internal PHY */ 1408 __set_bit(PHY_INTERFACE_MODE_GMII, 1409 config->supported_interfaces); 1410 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1411 config->supported_interfaces); 1412 break; 1413 1414 case 6: /* 2nd CPU port / external PHY */ 1415 phy_interface_set_rgmii(config->supported_interfaces); 1416 __set_bit(PHY_INTERFACE_MODE_SGMII, 1417 config->supported_interfaces); 1418 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 1419 config->supported_interfaces); 1420 break; 1421 } 1422 1423 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1424 MAC_10 | MAC_100 | MAC_1000FD; 1425 } 1426 1427 static void 1428 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, 1429 phy_interface_t interface) 1430 { 1431 struct qca8k_priv *priv = ds->priv; 1432 1433 qca8k_port_set_status(priv, port, 0); 1434 } 1435 1436 static void 1437 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode, 1438 phy_interface_t interface, struct phy_device *phydev, 1439 int speed, int duplex, bool tx_pause, bool rx_pause) 1440 { 1441 struct qca8k_priv *priv = ds->priv; 1442 u32 reg; 1443 1444 if (phylink_autoneg_inband(mode)) { 1445 reg = QCA8K_PORT_STATUS_LINK_AUTO; 1446 } else { 1447 switch (speed) { 1448 case SPEED_10: 1449 reg = QCA8K_PORT_STATUS_SPEED_10; 1450 break; 1451 case SPEED_100: 1452 reg = QCA8K_PORT_STATUS_SPEED_100; 1453 break; 1454 case SPEED_1000: 1455 reg = QCA8K_PORT_STATUS_SPEED_1000; 1456 break; 1457 default: 1458 reg = QCA8K_PORT_STATUS_LINK_AUTO; 1459 break; 1460 } 1461 1462 if (duplex == DUPLEX_FULL) 1463 reg |= QCA8K_PORT_STATUS_DUPLEX; 1464 1465 if (rx_pause || dsa_is_cpu_port(ds, port)) 1466 reg |= QCA8K_PORT_STATUS_RXFLOW; 1467 1468 if (tx_pause || dsa_is_cpu_port(ds, port)) 1469 reg |= QCA8K_PORT_STATUS_TXFLOW; 1470 } 1471 1472 reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC; 1473 1474 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg); 1475 } 1476 1477 static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs) 1478 { 1479 return container_of(pcs, struct qca8k_pcs, pcs); 1480 } 1481 1482 static void qca8k_pcs_get_state(struct phylink_pcs *pcs, 1483 struct phylink_link_state *state) 1484 { 1485 struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv; 1486 int port = pcs_to_qca8k_pcs(pcs)->port; 1487 u32 reg; 1488 int ret; 1489 1490 ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), ®); 1491 if (ret < 0) { 1492 state->link = false; 1493 return; 1494 } 1495 1496 state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP); 1497 state->an_complete = state->link; 1498 state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL : 1499 DUPLEX_HALF; 1500 1501 switch (reg & QCA8K_PORT_STATUS_SPEED) { 1502 case QCA8K_PORT_STATUS_SPEED_10: 1503 state->speed = SPEED_10; 1504 break; 1505 case QCA8K_PORT_STATUS_SPEED_100: 1506 state->speed = SPEED_100; 1507 break; 1508 case QCA8K_PORT_STATUS_SPEED_1000: 1509 state->speed = SPEED_1000; 1510 break; 1511 default: 1512 state->speed = SPEED_UNKNOWN; 1513 break; 1514 } 1515 1516 if (reg & QCA8K_PORT_STATUS_RXFLOW) 1517 state->pause |= MLO_PAUSE_RX; 1518 if (reg & QCA8K_PORT_STATUS_TXFLOW) 1519 state->pause |= MLO_PAUSE_TX; 1520 } 1521 1522 static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 1523 phy_interface_t interface, 1524 const unsigned long *advertising, 1525 bool permit_pause_to_mac) 1526 { 1527 struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv; 1528 int cpu_port_index, ret, port; 1529 u32 reg, val; 1530 1531 port = pcs_to_qca8k_pcs(pcs)->port; 1532 switch (port) { 1533 case 0: 1534 reg = QCA8K_REG_PORT0_PAD_CTRL; 1535 cpu_port_index = QCA8K_CPU_PORT0; 1536 break; 1537 1538 case 6: 1539 reg = QCA8K_REG_PORT6_PAD_CTRL; 1540 cpu_port_index = QCA8K_CPU_PORT6; 1541 break; 1542 1543 default: 1544 WARN_ON(1); 1545 return -EINVAL; 1546 } 1547 1548 /* Enable/disable SerDes auto-negotiation as necessary */ 1549 val = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? 1550 0 : QCA8K_PWS_SERDES_AEN_DIS; 1551 1552 ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8K_PWS_SERDES_AEN_DIS, val); 1553 if (ret) 1554 return ret; 1555 1556 /* Configure the SGMII parameters */ 1557 ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val); 1558 if (ret) 1559 return ret; 1560 1561 val |= QCA8K_SGMII_EN_SD; 1562 1563 if (priv->ports_config.sgmii_enable_pll) 1564 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | 1565 QCA8K_SGMII_EN_TX; 1566 1567 if (dsa_is_cpu_port(priv->ds, port)) { 1568 /* CPU port, we're talking to the CPU MAC, be a PHY */ 1569 val &= ~QCA8K_SGMII_MODE_CTRL_MASK; 1570 val |= QCA8K_SGMII_MODE_CTRL_PHY; 1571 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1572 val &= ~QCA8K_SGMII_MODE_CTRL_MASK; 1573 val |= QCA8K_SGMII_MODE_CTRL_MAC; 1574 } else if (interface == PHY_INTERFACE_MODE_1000BASEX) { 1575 val &= ~QCA8K_SGMII_MODE_CTRL_MASK; 1576 val |= QCA8K_SGMII_MODE_CTRL_BASEX; 1577 } 1578 1579 qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val); 1580 1581 /* From original code is reported port instability as SGMII also 1582 * require delay set. Apply advised values here or take them from DT. 1583 */ 1584 if (interface == PHY_INTERFACE_MODE_SGMII) 1585 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg); 1586 /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and 1587 * falling edge is set writing in the PORT0 PAD reg 1588 */ 1589 if (priv->switch_id == QCA8K_ID_QCA8327 || 1590 priv->switch_id == QCA8K_ID_QCA8337) 1591 reg = QCA8K_REG_PORT0_PAD_CTRL; 1592 1593 val = 0; 1594 1595 /* SGMII Clock phase configuration */ 1596 if (priv->ports_config.sgmii_rx_clk_falling_edge) 1597 val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE; 1598 1599 if (priv->ports_config.sgmii_tx_clk_falling_edge) 1600 val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE; 1601 1602 if (val) 1603 ret = qca8k_rmw(priv, reg, 1604 QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE | 1605 QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE, 1606 val); 1607 1608 return 0; 1609 } 1610 1611 static void qca8k_pcs_an_restart(struct phylink_pcs *pcs) 1612 { 1613 } 1614 1615 static const struct phylink_pcs_ops qca8k_pcs_ops = { 1616 .pcs_get_state = qca8k_pcs_get_state, 1617 .pcs_config = qca8k_pcs_config, 1618 .pcs_an_restart = qca8k_pcs_an_restart, 1619 }; 1620 1621 static void qca8k_setup_pcs(struct qca8k_priv *priv, struct qca8k_pcs *qpcs, 1622 int port) 1623 { 1624 qpcs->pcs.ops = &qca8k_pcs_ops; 1625 qpcs->pcs.neg_mode = true; 1626 1627 /* We don't have interrupts for link changes, so we need to poll */ 1628 qpcs->pcs.poll = true; 1629 qpcs->priv = priv; 1630 qpcs->port = port; 1631 } 1632 1633 static void qca8k_mib_autocast_handler(struct dsa_switch *ds, struct sk_buff *skb) 1634 { 1635 struct qca8k_mib_eth_data *mib_eth_data; 1636 struct qca8k_priv *priv = ds->priv; 1637 const struct qca8k_mib_desc *mib; 1638 struct mib_ethhdr *mib_ethhdr; 1639 __le32 *data2; 1640 u8 port; 1641 int i; 1642 1643 mib_ethhdr = (struct mib_ethhdr *)skb_mac_header(skb); 1644 mib_eth_data = &priv->mib_eth_data; 1645 1646 /* The switch autocast every port. Ignore other packet and 1647 * parse only the requested one. 1648 */ 1649 port = FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, ntohs(mib_ethhdr->hdr)); 1650 if (port != mib_eth_data->req_port) 1651 goto exit; 1652 1653 data2 = (__le32 *)skb->data; 1654 1655 for (i = 0; i < priv->info->mib_count; i++) { 1656 mib = &ar8327_mib[i]; 1657 1658 /* First 3 mib are present in the skb head */ 1659 if (i < 3) { 1660 mib_eth_data->data[i] = get_unaligned_le32(mib_ethhdr->data + i); 1661 continue; 1662 } 1663 1664 /* Some mib are 64 bit wide */ 1665 if (mib->size == 2) 1666 mib_eth_data->data[i] = get_unaligned_le64((__le64 *)data2); 1667 else 1668 mib_eth_data->data[i] = get_unaligned_le32(data2); 1669 1670 data2 += mib->size; 1671 } 1672 1673 exit: 1674 /* Complete on receiving all the mib packet */ 1675 if (refcount_dec_and_test(&mib_eth_data->port_parsed)) 1676 complete(&mib_eth_data->rw_done); 1677 } 1678 1679 static int 1680 qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, int port, u64 *data) 1681 { 1682 struct dsa_port *dp = dsa_to_port(ds, port); 1683 struct qca8k_mib_eth_data *mib_eth_data; 1684 struct qca8k_priv *priv = ds->priv; 1685 int ret; 1686 1687 mib_eth_data = &priv->mib_eth_data; 1688 1689 mutex_lock(&mib_eth_data->mutex); 1690 1691 reinit_completion(&mib_eth_data->rw_done); 1692 1693 mib_eth_data->req_port = dp->index; 1694 mib_eth_data->data = data; 1695 refcount_set(&mib_eth_data->port_parsed, QCA8K_NUM_PORTS); 1696 1697 mutex_lock(&priv->reg_mutex); 1698 1699 /* Send mib autocast request */ 1700 ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB, 1701 QCA8K_MIB_FUNC | QCA8K_MIB_BUSY, 1702 FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_CAST) | 1703 QCA8K_MIB_BUSY); 1704 1705 mutex_unlock(&priv->reg_mutex); 1706 1707 if (ret) 1708 goto exit; 1709 1710 ret = wait_for_completion_timeout(&mib_eth_data->rw_done, QCA8K_ETHERNET_TIMEOUT); 1711 1712 exit: 1713 mutex_unlock(&mib_eth_data->mutex); 1714 1715 return ret; 1716 } 1717 1718 static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port) 1719 { 1720 struct qca8k_priv *priv = ds->priv; 1721 1722 /* Communicate to the phy internal driver the switch revision. 1723 * Based on the switch revision different values needs to be 1724 * set to the dbg and mmd reg on the phy. 1725 * The first 2 bit are used to communicate the switch revision 1726 * to the phy driver. 1727 */ 1728 if (port > 0 && port < 6) 1729 return priv->switch_revision; 1730 1731 return 0; 1732 } 1733 1734 static enum dsa_tag_protocol 1735 qca8k_get_tag_protocol(struct dsa_switch *ds, int port, 1736 enum dsa_tag_protocol mp) 1737 { 1738 return DSA_TAG_PROTO_QCA; 1739 } 1740 1741 static void 1742 qca8k_master_change(struct dsa_switch *ds, const struct net_device *master, 1743 bool operational) 1744 { 1745 struct dsa_port *dp = master->dsa_ptr; 1746 struct qca8k_priv *priv = ds->priv; 1747 1748 /* Ethernet MIB/MDIO is only supported for CPU port 0 */ 1749 if (dp->index != 0) 1750 return; 1751 1752 mutex_lock(&priv->mgmt_eth_data.mutex); 1753 mutex_lock(&priv->mib_eth_data.mutex); 1754 1755 priv->mgmt_master = operational ? (struct net_device *)master : NULL; 1756 1757 mutex_unlock(&priv->mib_eth_data.mutex); 1758 mutex_unlock(&priv->mgmt_eth_data.mutex); 1759 } 1760 1761 static int qca8k_connect_tag_protocol(struct dsa_switch *ds, 1762 enum dsa_tag_protocol proto) 1763 { 1764 struct qca_tagger_data *tagger_data; 1765 1766 switch (proto) { 1767 case DSA_TAG_PROTO_QCA: 1768 tagger_data = ds->tagger_data; 1769 1770 tagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler; 1771 tagger_data->mib_autocast_handler = qca8k_mib_autocast_handler; 1772 1773 break; 1774 default: 1775 return -EOPNOTSUPP; 1776 } 1777 1778 return 0; 1779 } 1780 1781 static void qca8k_setup_hol_fixup(struct qca8k_priv *priv, int port) 1782 { 1783 u32 mask; 1784 1785 switch (port) { 1786 /* The 2 CPU port and port 5 requires some different 1787 * priority than any other ports. 1788 */ 1789 case 0: 1790 case 5: 1791 case 6: 1792 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | 1793 QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | 1794 QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) | 1795 QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) | 1796 QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) | 1797 QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) | 1798 QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e); 1799 break; 1800 default: 1801 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | 1802 QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | 1803 QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) | 1804 QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) | 1805 QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19); 1806 } 1807 regmap_write(priv->regmap, QCA8K_REG_PORT_HOL_CTRL0(port), mask); 1808 1809 mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) | 1810 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | 1811 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | 1812 QCA8K_PORT_HOL_CTRL1_WRED_EN; 1813 regmap_update_bits(priv->regmap, QCA8K_REG_PORT_HOL_CTRL1(port), 1814 QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK | 1815 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | 1816 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | 1817 QCA8K_PORT_HOL_CTRL1_WRED_EN, 1818 mask); 1819 } 1820 1821 static int 1822 qca8k_setup(struct dsa_switch *ds) 1823 { 1824 struct qca8k_priv *priv = ds->priv; 1825 struct dsa_port *dp; 1826 int cpu_port, ret; 1827 u32 mask; 1828 1829 cpu_port = qca8k_find_cpu_port(ds); 1830 if (cpu_port < 0) { 1831 dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6"); 1832 return cpu_port; 1833 } 1834 1835 /* Parse CPU port config to be later used in phy_link mac_config */ 1836 ret = qca8k_parse_port_config(priv); 1837 if (ret) 1838 return ret; 1839 1840 ret = qca8k_setup_mdio_bus(priv); 1841 if (ret) 1842 return ret; 1843 1844 ret = qca8k_setup_of_pws_reg(priv); 1845 if (ret) 1846 return ret; 1847 1848 ret = qca8k_setup_mac_pwr_sel(priv); 1849 if (ret) 1850 return ret; 1851 1852 ret = qca8k_setup_led_ctrl(priv); 1853 if (ret) 1854 return ret; 1855 1856 qca8k_setup_pcs(priv, &priv->pcs_port_0, 0); 1857 qca8k_setup_pcs(priv, &priv->pcs_port_6, 6); 1858 1859 /* Make sure MAC06 is disabled */ 1860 ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL, 1861 QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN); 1862 if (ret) { 1863 dev_err(priv->dev, "failed disabling MAC06 exchange"); 1864 return ret; 1865 } 1866 1867 /* Enable CPU Port */ 1868 ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, 1869 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); 1870 if (ret) { 1871 dev_err(priv->dev, "failed enabling CPU port"); 1872 return ret; 1873 } 1874 1875 /* Enable MIB counters */ 1876 ret = qca8k_mib_init(priv); 1877 if (ret) 1878 dev_warn(priv->dev, "mib init failed"); 1879 1880 /* Initial setup of all ports */ 1881 dsa_switch_for_each_port(dp, ds) { 1882 /* Disable forwarding by default on all ports */ 1883 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(dp->index), 1884 QCA8K_PORT_LOOKUP_MEMBER, 0); 1885 if (ret) 1886 return ret; 1887 } 1888 1889 /* Disable MAC by default on all user ports */ 1890 dsa_switch_for_each_user_port(dp, ds) 1891 qca8k_port_set_status(priv, dp->index, 0); 1892 1893 /* Enable QCA header mode on all cpu ports */ 1894 dsa_switch_for_each_cpu_port(dp, ds) { 1895 ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(dp->index), 1896 FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) | 1897 FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL)); 1898 if (ret) { 1899 dev_err(priv->dev, "failed enabling QCA header mode on port %d", dp->index); 1900 return ret; 1901 } 1902 } 1903 1904 /* Forward all unknown frames to CPU port for Linux processing 1905 * Notice that in multi-cpu config only one port should be set 1906 * for igmp, unknown, multicast and broadcast packet 1907 */ 1908 ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, 1909 FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) | 1910 FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) | 1911 FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) | 1912 FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port))); 1913 if (ret) 1914 return ret; 1915 1916 /* CPU port gets connected to all user ports of the switch */ 1917 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port), 1918 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); 1919 if (ret) 1920 return ret; 1921 1922 /* Setup connection between CPU port & user ports 1923 * Individual user ports get connected to CPU port only 1924 */ 1925 dsa_switch_for_each_user_port(dp, ds) { 1926 u8 port = dp->index; 1927 1928 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port), 1929 QCA8K_PORT_LOOKUP_MEMBER, 1930 BIT(cpu_port)); 1931 if (ret) 1932 return ret; 1933 1934 ret = regmap_clear_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(port), 1935 QCA8K_PORT_LOOKUP_LEARN); 1936 if (ret) 1937 return ret; 1938 1939 /* For port based vlans to work we need to set the 1940 * default egress vid 1941 */ 1942 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port), 1943 QCA8K_EGREES_VLAN_PORT_MASK(port), 1944 QCA8K_EGREES_VLAN_PORT(port, QCA8K_PORT_VID_DEF)); 1945 if (ret) 1946 return ret; 1947 1948 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port), 1949 QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | 1950 QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); 1951 if (ret) 1952 return ret; 1953 } 1954 1955 /* The port 5 of the qca8337 have some problem in flood condition. The 1956 * original legacy driver had some specific buffer and priority settings 1957 * for the different port suggested by the QCA switch team. Add this 1958 * missing settings to improve switch stability under load condition. 1959 * This problem is limited to qca8337 and other qca8k switch are not affected. 1960 */ 1961 if (priv->switch_id == QCA8K_ID_QCA8337) 1962 dsa_switch_for_each_available_port(dp, ds) 1963 qca8k_setup_hol_fixup(priv, dp->index); 1964 1965 /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */ 1966 if (priv->switch_id == QCA8K_ID_QCA8327) { 1967 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) | 1968 QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496); 1969 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH, 1970 QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK | 1971 QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, 1972 mask); 1973 } 1974 1975 /* Setup our port MTUs to match power on defaults */ 1976 ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); 1977 if (ret) 1978 dev_warn(priv->dev, "failed setting MTU settings"); 1979 1980 /* Flush the FDB table */ 1981 qca8k_fdb_flush(priv); 1982 1983 /* Set min a max ageing value supported */ 1984 ds->ageing_time_min = 7000; 1985 ds->ageing_time_max = 458745000; 1986 1987 /* Set max number of LAGs supported */ 1988 ds->num_lag_ids = QCA8K_NUM_LAGS; 1989 1990 return 0; 1991 } 1992 1993 static const struct dsa_switch_ops qca8k_switch_ops = { 1994 .get_tag_protocol = qca8k_get_tag_protocol, 1995 .setup = qca8k_setup, 1996 .get_strings = qca8k_get_strings, 1997 .get_ethtool_stats = qca8k_get_ethtool_stats, 1998 .get_sset_count = qca8k_get_sset_count, 1999 .set_ageing_time = qca8k_set_ageing_time, 2000 .get_mac_eee = qca8k_get_mac_eee, 2001 .set_mac_eee = qca8k_set_mac_eee, 2002 .port_enable = qca8k_port_enable, 2003 .port_disable = qca8k_port_disable, 2004 .port_change_mtu = qca8k_port_change_mtu, 2005 .port_max_mtu = qca8k_port_max_mtu, 2006 .port_stp_state_set = qca8k_port_stp_state_set, 2007 .port_pre_bridge_flags = qca8k_port_pre_bridge_flags, 2008 .port_bridge_flags = qca8k_port_bridge_flags, 2009 .port_bridge_join = qca8k_port_bridge_join, 2010 .port_bridge_leave = qca8k_port_bridge_leave, 2011 .port_fast_age = qca8k_port_fast_age, 2012 .port_fdb_add = qca8k_port_fdb_add, 2013 .port_fdb_del = qca8k_port_fdb_del, 2014 .port_fdb_dump = qca8k_port_fdb_dump, 2015 .port_mdb_add = qca8k_port_mdb_add, 2016 .port_mdb_del = qca8k_port_mdb_del, 2017 .port_mirror_add = qca8k_port_mirror_add, 2018 .port_mirror_del = qca8k_port_mirror_del, 2019 .port_vlan_filtering = qca8k_port_vlan_filtering, 2020 .port_vlan_add = qca8k_port_vlan_add, 2021 .port_vlan_del = qca8k_port_vlan_del, 2022 .phylink_get_caps = qca8k_phylink_get_caps, 2023 .phylink_mac_select_pcs = qca8k_phylink_mac_select_pcs, 2024 .phylink_mac_config = qca8k_phylink_mac_config, 2025 .phylink_mac_link_down = qca8k_phylink_mac_link_down, 2026 .phylink_mac_link_up = qca8k_phylink_mac_link_up, 2027 .get_phy_flags = qca8k_get_phy_flags, 2028 .port_lag_join = qca8k_port_lag_join, 2029 .port_lag_leave = qca8k_port_lag_leave, 2030 .master_state_change = qca8k_master_change, 2031 .connect_tag_protocol = qca8k_connect_tag_protocol, 2032 }; 2033 2034 static int 2035 qca8k_sw_probe(struct mdio_device *mdiodev) 2036 { 2037 struct qca8k_priv *priv; 2038 int ret; 2039 2040 /* allocate the private data struct so that we can probe the switches 2041 * ID register 2042 */ 2043 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 2044 if (!priv) 2045 return -ENOMEM; 2046 2047 priv->bus = mdiodev->bus; 2048 priv->dev = &mdiodev->dev; 2049 priv->info = of_device_get_match_data(priv->dev); 2050 2051 priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset", 2052 GPIOD_OUT_HIGH); 2053 if (IS_ERR(priv->reset_gpio)) 2054 return PTR_ERR(priv->reset_gpio); 2055 2056 if (priv->reset_gpio) { 2057 /* The active low duration must be greater than 10 ms 2058 * and checkpatch.pl wants 20 ms. 2059 */ 2060 msleep(20); 2061 gpiod_set_value_cansleep(priv->reset_gpio, 0); 2062 } 2063 2064 /* Start by setting up the register mapping */ 2065 priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv, 2066 &qca8k_regmap_config); 2067 if (IS_ERR(priv->regmap)) { 2068 dev_err(priv->dev, "regmap initialization failed"); 2069 return PTR_ERR(priv->regmap); 2070 } 2071 2072 priv->mdio_cache.page = 0xffff; 2073 2074 /* Check the detected switch id */ 2075 ret = qca8k_read_switch_id(priv); 2076 if (ret) 2077 return ret; 2078 2079 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 2080 if (!priv->ds) 2081 return -ENOMEM; 2082 2083 mutex_init(&priv->mgmt_eth_data.mutex); 2084 init_completion(&priv->mgmt_eth_data.rw_done); 2085 2086 mutex_init(&priv->mib_eth_data.mutex); 2087 init_completion(&priv->mib_eth_data.rw_done); 2088 2089 priv->ds->dev = &mdiodev->dev; 2090 priv->ds->num_ports = QCA8K_NUM_PORTS; 2091 priv->ds->priv = priv; 2092 priv->ds->ops = &qca8k_switch_ops; 2093 mutex_init(&priv->reg_mutex); 2094 dev_set_drvdata(&mdiodev->dev, priv); 2095 2096 return dsa_register_switch(priv->ds); 2097 } 2098 2099 static void 2100 qca8k_sw_remove(struct mdio_device *mdiodev) 2101 { 2102 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev); 2103 int i; 2104 2105 if (!priv) 2106 return; 2107 2108 for (i = 0; i < QCA8K_NUM_PORTS; i++) 2109 qca8k_port_set_status(priv, i, 0); 2110 2111 dsa_unregister_switch(priv->ds); 2112 } 2113 2114 static void qca8k_sw_shutdown(struct mdio_device *mdiodev) 2115 { 2116 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev); 2117 2118 if (!priv) 2119 return; 2120 2121 dsa_switch_shutdown(priv->ds); 2122 2123 dev_set_drvdata(&mdiodev->dev, NULL); 2124 } 2125 2126 #ifdef CONFIG_PM_SLEEP 2127 static void 2128 qca8k_set_pm(struct qca8k_priv *priv, int enable) 2129 { 2130 int port; 2131 2132 for (port = 0; port < QCA8K_NUM_PORTS; port++) { 2133 /* Do not enable on resume if the port was 2134 * disabled before. 2135 */ 2136 if (!(priv->port_enabled_map & BIT(port))) 2137 continue; 2138 2139 qca8k_port_set_status(priv, port, enable); 2140 } 2141 } 2142 2143 static int qca8k_suspend(struct device *dev) 2144 { 2145 struct qca8k_priv *priv = dev_get_drvdata(dev); 2146 2147 qca8k_set_pm(priv, 0); 2148 2149 return dsa_switch_suspend(priv->ds); 2150 } 2151 2152 static int qca8k_resume(struct device *dev) 2153 { 2154 struct qca8k_priv *priv = dev_get_drvdata(dev); 2155 2156 qca8k_set_pm(priv, 1); 2157 2158 return dsa_switch_resume(priv->ds); 2159 } 2160 #endif /* CONFIG_PM_SLEEP */ 2161 2162 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, 2163 qca8k_suspend, qca8k_resume); 2164 2165 static const struct qca8k_info_ops qca8xxx_ops = { 2166 .autocast_mib = qca8k_get_ethtool_stats_eth, 2167 }; 2168 2169 static const struct qca8k_match_data qca8327 = { 2170 .id = QCA8K_ID_QCA8327, 2171 .reduced_package = true, 2172 .mib_count = QCA8K_QCA832X_MIB_COUNT, 2173 .ops = &qca8xxx_ops, 2174 }; 2175 2176 static const struct qca8k_match_data qca8328 = { 2177 .id = QCA8K_ID_QCA8327, 2178 .mib_count = QCA8K_QCA832X_MIB_COUNT, 2179 .ops = &qca8xxx_ops, 2180 }; 2181 2182 static const struct qca8k_match_data qca833x = { 2183 .id = QCA8K_ID_QCA8337, 2184 .mib_count = QCA8K_QCA833X_MIB_COUNT, 2185 .ops = &qca8xxx_ops, 2186 }; 2187 2188 static const struct of_device_id qca8k_of_match[] = { 2189 { .compatible = "qca,qca8327", .data = &qca8327 }, 2190 { .compatible = "qca,qca8328", .data = &qca8328 }, 2191 { .compatible = "qca,qca8334", .data = &qca833x }, 2192 { .compatible = "qca,qca8337", .data = &qca833x }, 2193 { /* sentinel */ }, 2194 }; 2195 2196 static struct mdio_driver qca8kmdio_driver = { 2197 .probe = qca8k_sw_probe, 2198 .remove = qca8k_sw_remove, 2199 .shutdown = qca8k_sw_shutdown, 2200 .mdiodrv.driver = { 2201 .name = "qca8k", 2202 .of_match_table = qca8k_of_match, 2203 .pm = &qca8k_pm_ops, 2204 }, 2205 }; 2206 2207 mdio_module_driver(qca8kmdio_driver); 2208 2209 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>"); 2210 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family"); 2211 MODULE_LICENSE("GPL v2"); 2212 MODULE_ALIAS("platform:qca8k"); 2213