1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name> 4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> 5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2016 John Crispin <john@phrozen.org> 7 */ 8 9 #include <linux/module.h> 10 #include <linux/phy.h> 11 #include <linux/netdevice.h> 12 #include <linux/bitfield.h> 13 #include <linux/regmap.h> 14 #include <net/dsa.h> 15 #include <linux/of_net.h> 16 #include <linux/of_mdio.h> 17 #include <linux/of_platform.h> 18 #include <linux/mdio.h> 19 #include <linux/phylink.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/etherdevice.h> 22 #include <linux/dsa/tag_qca.h> 23 24 #include "qca8k.h" 25 #include "qca8k_leds.h" 26 27 static void 28 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page) 29 { 30 regaddr >>= 1; 31 *r1 = regaddr & 0x1e; 32 33 regaddr >>= 5; 34 *r2 = regaddr & 0x7; 35 36 regaddr >>= 3; 37 *page = regaddr & 0x3ff; 38 } 39 40 static int 41 qca8k_mii_write_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 val) 42 { 43 int ret; 44 u16 lo; 45 46 lo = val & 0xffff; 47 ret = bus->write(bus, phy_id, regnum, lo); 48 if (ret < 0) 49 dev_err_ratelimited(&bus->dev, 50 "failed to write qca8k 32bit lo register\n"); 51 52 return ret; 53 } 54 55 static int 56 qca8k_mii_write_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 val) 57 { 58 int ret; 59 u16 hi; 60 61 hi = (u16)(val >> 16); 62 ret = bus->write(bus, phy_id, regnum, hi); 63 if (ret < 0) 64 dev_err_ratelimited(&bus->dev, 65 "failed to write qca8k 32bit hi register\n"); 66 67 return ret; 68 } 69 70 static int 71 qca8k_mii_read_lo(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val) 72 { 73 int ret; 74 75 ret = bus->read(bus, phy_id, regnum); 76 if (ret < 0) 77 goto err; 78 79 *val = ret & 0xffff; 80 return 0; 81 82 err: 83 dev_err_ratelimited(&bus->dev, 84 "failed to read qca8k 32bit lo register\n"); 85 *val = 0; 86 87 return ret; 88 } 89 90 static int 91 qca8k_mii_read_hi(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val) 92 { 93 int ret; 94 95 ret = bus->read(bus, phy_id, regnum); 96 if (ret < 0) 97 goto err; 98 99 *val = ret << 16; 100 return 0; 101 102 err: 103 dev_err_ratelimited(&bus->dev, 104 "failed to read qca8k 32bit hi register\n"); 105 *val = 0; 106 107 return ret; 108 } 109 110 static int 111 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum, u32 *val) 112 { 113 u32 hi, lo; 114 int ret; 115 116 *val = 0; 117 118 ret = qca8k_mii_read_lo(bus, phy_id, regnum, &lo); 119 if (ret < 0) 120 goto err; 121 122 ret = qca8k_mii_read_hi(bus, phy_id, regnum + 1, &hi); 123 if (ret < 0) 124 goto err; 125 126 *val = lo | hi; 127 128 err: 129 return ret; 130 } 131 132 static void 133 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val) 134 { 135 if (qca8k_mii_write_lo(bus, phy_id, regnum, val) < 0) 136 return; 137 138 qca8k_mii_write_hi(bus, phy_id, regnum + 1, val); 139 } 140 141 static int 142 qca8k_set_page(struct qca8k_priv *priv, u16 page) 143 { 144 u16 *cached_page = &priv->mdio_cache.page; 145 struct mii_bus *bus = priv->bus; 146 int ret; 147 148 if (page == *cached_page) 149 return 0; 150 151 ret = bus->write(bus, 0x18, 0, page); 152 if (ret < 0) { 153 dev_err_ratelimited(&bus->dev, 154 "failed to set qca8k page\n"); 155 return ret; 156 } 157 158 *cached_page = page; 159 usleep_range(1000, 2000); 160 return 0; 161 } 162 163 static void qca8k_rw_reg_ack_handler(struct dsa_switch *ds, struct sk_buff *skb) 164 { 165 struct qca8k_mgmt_eth_data *mgmt_eth_data; 166 struct qca8k_priv *priv = ds->priv; 167 struct qca_mgmt_ethhdr *mgmt_ethhdr; 168 u32 command; 169 u8 len, cmd; 170 int i; 171 172 mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb_mac_header(skb); 173 mgmt_eth_data = &priv->mgmt_eth_data; 174 175 command = get_unaligned_le32(&mgmt_ethhdr->command); 176 cmd = FIELD_GET(QCA_HDR_MGMT_CMD, command); 177 178 len = FIELD_GET(QCA_HDR_MGMT_LENGTH, command); 179 /* Special case for len of 15 as this is the max value for len and needs to 180 * be increased before converting it from word to dword. 181 */ 182 if (len == 15) 183 len++; 184 185 /* We can ignore odd value, we always round up them in the alloc function. */ 186 len *= sizeof(u16); 187 188 /* Make sure the seq match the requested packet */ 189 if (get_unaligned_le32(&mgmt_ethhdr->seq) == mgmt_eth_data->seq) 190 mgmt_eth_data->ack = true; 191 192 if (cmd == MDIO_READ) { 193 u32 *val = mgmt_eth_data->data; 194 195 *val = get_unaligned_le32(&mgmt_ethhdr->mdio_data); 196 197 /* Get the rest of the 12 byte of data. 198 * The read/write function will extract the requested data. 199 */ 200 if (len > QCA_HDR_MGMT_DATA1_LEN) { 201 __le32 *data2 = (__le32 *)skb->data; 202 int data_len = min_t(int, QCA_HDR_MGMT_DATA2_LEN, 203 len - QCA_HDR_MGMT_DATA1_LEN); 204 205 val++; 206 207 for (i = sizeof(u32); i <= data_len; i += sizeof(u32)) { 208 *val = get_unaligned_le32(data2); 209 val++; 210 data2++; 211 } 212 } 213 } 214 215 complete(&mgmt_eth_data->rw_done); 216 } 217 218 static struct sk_buff *qca8k_alloc_mdio_header(enum mdio_cmd cmd, u32 reg, u32 *val, 219 int priority, unsigned int len) 220 { 221 struct qca_mgmt_ethhdr *mgmt_ethhdr; 222 unsigned int real_len; 223 struct sk_buff *skb; 224 __le32 *data2; 225 u32 command; 226 u16 hdr; 227 int i; 228 229 skb = dev_alloc_skb(QCA_HDR_MGMT_PKT_LEN); 230 if (!skb) 231 return NULL; 232 233 /* Hdr mgmt length value is in step of word size. 234 * As an example to process 4 byte of data the correct length to set is 2. 235 * To process 8 byte 4, 12 byte 6, 16 byte 8... 236 * 237 * Odd values will always return the next size on the ack packet. 238 * (length of 3 (6 byte) will always return 8 bytes of data) 239 * 240 * This means that a value of 15 (0xf) actually means reading/writing 32 bytes 241 * of data. 242 * 243 * To correctly calculate the length we devide the requested len by word and 244 * round up. 245 * On the ack function we can skip the odd check as we already handle the 246 * case here. 247 */ 248 real_len = DIV_ROUND_UP(len, sizeof(u16)); 249 250 /* We check if the result len is odd and we round up another time to 251 * the next size. (length of 3 will be increased to 4 as switch will always 252 * return 8 bytes) 253 */ 254 if (real_len % sizeof(u16) != 0) 255 real_len++; 256 257 /* Max reg value is 0xf(15) but switch will always return the next size (32 byte) */ 258 if (real_len == 16) 259 real_len--; 260 261 skb_reset_mac_header(skb); 262 skb_set_network_header(skb, skb->len); 263 264 mgmt_ethhdr = skb_push(skb, QCA_HDR_MGMT_HEADER_LEN + QCA_HDR_LEN); 265 266 hdr = FIELD_PREP(QCA_HDR_XMIT_VERSION, QCA_HDR_VERSION); 267 hdr |= FIELD_PREP(QCA_HDR_XMIT_PRIORITY, priority); 268 hdr |= QCA_HDR_XMIT_FROM_CPU; 269 hdr |= FIELD_PREP(QCA_HDR_XMIT_DP_BIT, BIT(0)); 270 hdr |= FIELD_PREP(QCA_HDR_XMIT_CONTROL, QCA_HDR_XMIT_TYPE_RW_REG); 271 272 command = FIELD_PREP(QCA_HDR_MGMT_ADDR, reg); 273 command |= FIELD_PREP(QCA_HDR_MGMT_LENGTH, real_len); 274 command |= FIELD_PREP(QCA_HDR_MGMT_CMD, cmd); 275 command |= FIELD_PREP(QCA_HDR_MGMT_CHECK_CODE, 276 QCA_HDR_MGMT_CHECK_CODE_VAL); 277 278 put_unaligned_le32(command, &mgmt_ethhdr->command); 279 280 if (cmd == MDIO_WRITE) 281 put_unaligned_le32(*val, &mgmt_ethhdr->mdio_data); 282 283 mgmt_ethhdr->hdr = htons(hdr); 284 285 data2 = skb_put_zero(skb, QCA_HDR_MGMT_DATA2_LEN + QCA_HDR_MGMT_PADDING_LEN); 286 if (cmd == MDIO_WRITE && len > QCA_HDR_MGMT_DATA1_LEN) { 287 int data_len = min_t(int, QCA_HDR_MGMT_DATA2_LEN, 288 len - QCA_HDR_MGMT_DATA1_LEN); 289 290 val++; 291 292 for (i = sizeof(u32); i <= data_len; i += sizeof(u32)) { 293 put_unaligned_le32(*val, data2); 294 data2++; 295 val++; 296 } 297 } 298 299 return skb; 300 } 301 302 static void qca8k_mdio_header_fill_seq_num(struct sk_buff *skb, u32 seq_num) 303 { 304 struct qca_mgmt_ethhdr *mgmt_ethhdr; 305 u32 seq; 306 307 seq = FIELD_PREP(QCA_HDR_MGMT_SEQ_NUM, seq_num); 308 mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb->data; 309 put_unaligned_le32(seq, &mgmt_ethhdr->seq); 310 } 311 312 static int qca8k_read_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len) 313 { 314 struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data; 315 struct sk_buff *skb; 316 bool ack; 317 int ret; 318 319 skb = qca8k_alloc_mdio_header(MDIO_READ, reg, NULL, 320 QCA8K_ETHERNET_MDIO_PRIORITY, len); 321 if (!skb) 322 return -ENOMEM; 323 324 mutex_lock(&mgmt_eth_data->mutex); 325 326 /* Check mgmt_master if is operational */ 327 if (!priv->mgmt_master) { 328 kfree_skb(skb); 329 mutex_unlock(&mgmt_eth_data->mutex); 330 return -EINVAL; 331 } 332 333 skb->dev = priv->mgmt_master; 334 335 reinit_completion(&mgmt_eth_data->rw_done); 336 337 /* Increment seq_num and set it in the mdio pkt */ 338 mgmt_eth_data->seq++; 339 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); 340 mgmt_eth_data->ack = false; 341 342 dev_queue_xmit(skb); 343 344 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, 345 msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT)); 346 347 *val = mgmt_eth_data->data[0]; 348 if (len > QCA_HDR_MGMT_DATA1_LEN) 349 memcpy(val + 1, mgmt_eth_data->data + 1, len - QCA_HDR_MGMT_DATA1_LEN); 350 351 ack = mgmt_eth_data->ack; 352 353 mutex_unlock(&mgmt_eth_data->mutex); 354 355 if (ret <= 0) 356 return -ETIMEDOUT; 357 358 if (!ack) 359 return -EINVAL; 360 361 return 0; 362 } 363 364 static int qca8k_write_eth(struct qca8k_priv *priv, u32 reg, u32 *val, int len) 365 { 366 struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data; 367 struct sk_buff *skb; 368 bool ack; 369 int ret; 370 371 skb = qca8k_alloc_mdio_header(MDIO_WRITE, reg, val, 372 QCA8K_ETHERNET_MDIO_PRIORITY, len); 373 if (!skb) 374 return -ENOMEM; 375 376 mutex_lock(&mgmt_eth_data->mutex); 377 378 /* Check mgmt_master if is operational */ 379 if (!priv->mgmt_master) { 380 kfree_skb(skb); 381 mutex_unlock(&mgmt_eth_data->mutex); 382 return -EINVAL; 383 } 384 385 skb->dev = priv->mgmt_master; 386 387 reinit_completion(&mgmt_eth_data->rw_done); 388 389 /* Increment seq_num and set it in the mdio pkt */ 390 mgmt_eth_data->seq++; 391 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); 392 mgmt_eth_data->ack = false; 393 394 dev_queue_xmit(skb); 395 396 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, 397 msecs_to_jiffies(QCA8K_ETHERNET_TIMEOUT)); 398 399 ack = mgmt_eth_data->ack; 400 401 mutex_unlock(&mgmt_eth_data->mutex); 402 403 if (ret <= 0) 404 return -ETIMEDOUT; 405 406 if (!ack) 407 return -EINVAL; 408 409 return 0; 410 } 411 412 static int 413 qca8k_regmap_update_bits_eth(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val) 414 { 415 u32 val = 0; 416 int ret; 417 418 ret = qca8k_read_eth(priv, reg, &val, sizeof(val)); 419 if (ret) 420 return ret; 421 422 val &= ~mask; 423 val |= write_val; 424 425 return qca8k_write_eth(priv, reg, &val, sizeof(val)); 426 } 427 428 static int 429 qca8k_read_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t *val) 430 { 431 struct mii_bus *bus = priv->bus; 432 u16 r1, r2, page; 433 int ret; 434 435 qca8k_split_addr(reg, &r1, &r2, &page); 436 437 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 438 439 ret = qca8k_set_page(priv, page); 440 if (ret < 0) 441 goto exit; 442 443 ret = qca8k_mii_read32(bus, 0x10 | r2, r1, val); 444 445 exit: 446 mutex_unlock(&bus->mdio_lock); 447 return ret; 448 } 449 450 static int 451 qca8k_write_mii(struct qca8k_priv *priv, uint32_t reg, uint32_t val) 452 { 453 struct mii_bus *bus = priv->bus; 454 u16 r1, r2, page; 455 int ret; 456 457 qca8k_split_addr(reg, &r1, &r2, &page); 458 459 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 460 461 ret = qca8k_set_page(priv, page); 462 if (ret < 0) 463 goto exit; 464 465 qca8k_mii_write32(bus, 0x10 | r2, r1, val); 466 467 exit: 468 mutex_unlock(&bus->mdio_lock); 469 return ret; 470 } 471 472 static int 473 qca8k_regmap_update_bits_mii(struct qca8k_priv *priv, uint32_t reg, 474 uint32_t mask, uint32_t write_val) 475 { 476 struct mii_bus *bus = priv->bus; 477 u16 r1, r2, page; 478 u32 val; 479 int ret; 480 481 qca8k_split_addr(reg, &r1, &r2, &page); 482 483 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 484 485 ret = qca8k_set_page(priv, page); 486 if (ret < 0) 487 goto exit; 488 489 ret = qca8k_mii_read32(bus, 0x10 | r2, r1, &val); 490 if (ret < 0) 491 goto exit; 492 493 val &= ~mask; 494 val |= write_val; 495 qca8k_mii_write32(bus, 0x10 | r2, r1, val); 496 497 exit: 498 mutex_unlock(&bus->mdio_lock); 499 500 return ret; 501 } 502 503 static int 504 qca8k_bulk_read(void *ctx, const void *reg_buf, size_t reg_len, 505 void *val_buf, size_t val_len) 506 { 507 int i, count = val_len / sizeof(u32), ret; 508 u32 reg = *(u32 *)reg_buf & U16_MAX; 509 struct qca8k_priv *priv = ctx; 510 511 if (priv->mgmt_master && 512 !qca8k_read_eth(priv, reg, val_buf, val_len)) 513 return 0; 514 515 /* loop count times and increment reg of 4 */ 516 for (i = 0; i < count; i++, reg += sizeof(u32)) { 517 ret = qca8k_read_mii(priv, reg, val_buf + i); 518 if (ret < 0) 519 return ret; 520 } 521 522 return 0; 523 } 524 525 static int 526 qca8k_bulk_gather_write(void *ctx, const void *reg_buf, size_t reg_len, 527 const void *val_buf, size_t val_len) 528 { 529 int i, count = val_len / sizeof(u32), ret; 530 u32 reg = *(u32 *)reg_buf & U16_MAX; 531 struct qca8k_priv *priv = ctx; 532 u32 *val = (u32 *)val_buf; 533 534 if (priv->mgmt_master && 535 !qca8k_write_eth(priv, reg, val, val_len)) 536 return 0; 537 538 /* loop count times, increment reg of 4 and increment val ptr to 539 * the next value 540 */ 541 for (i = 0; i < count; i++, reg += sizeof(u32), val++) { 542 ret = qca8k_write_mii(priv, reg, *val); 543 if (ret < 0) 544 return ret; 545 } 546 547 return 0; 548 } 549 550 static int 551 qca8k_bulk_write(void *ctx, const void *data, size_t bytes) 552 { 553 return qca8k_bulk_gather_write(ctx, data, sizeof(u16), data + sizeof(u16), 554 bytes - sizeof(u16)); 555 } 556 557 static int 558 qca8k_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask, uint32_t write_val) 559 { 560 struct qca8k_priv *priv = ctx; 561 562 if (!qca8k_regmap_update_bits_eth(priv, reg, mask, write_val)) 563 return 0; 564 565 return qca8k_regmap_update_bits_mii(priv, reg, mask, write_val); 566 } 567 568 static struct regmap_config qca8k_regmap_config = { 569 .reg_bits = 16, 570 .val_bits = 32, 571 .reg_stride = 4, 572 .max_register = 0x16ac, /* end MIB - Port6 range */ 573 .read = qca8k_bulk_read, 574 .write = qca8k_bulk_write, 575 .reg_update_bits = qca8k_regmap_update_bits, 576 .rd_table = &qca8k_readable_table, 577 .disable_locking = true, /* Locking is handled by qca8k read/write */ 578 .cache_type = REGCACHE_NONE, /* Explicitly disable CACHE */ 579 .max_raw_read = 32, /* mgmt eth can read/write up to 8 registers at time */ 580 .max_raw_write = 32, 581 }; 582 583 static int 584 qca8k_phy_eth_busy_wait(struct qca8k_mgmt_eth_data *mgmt_eth_data, 585 struct sk_buff *read_skb, u32 *val) 586 { 587 struct sk_buff *skb = skb_copy(read_skb, GFP_KERNEL); 588 bool ack; 589 int ret; 590 591 reinit_completion(&mgmt_eth_data->rw_done); 592 593 /* Increment seq_num and set it in the copy pkt */ 594 mgmt_eth_data->seq++; 595 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); 596 mgmt_eth_data->ack = false; 597 598 dev_queue_xmit(skb); 599 600 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, 601 QCA8K_ETHERNET_TIMEOUT); 602 603 ack = mgmt_eth_data->ack; 604 605 if (ret <= 0) 606 return -ETIMEDOUT; 607 608 if (!ack) 609 return -EINVAL; 610 611 *val = mgmt_eth_data->data[0]; 612 613 return 0; 614 } 615 616 static int 617 qca8k_phy_eth_command(struct qca8k_priv *priv, bool read, int phy, 618 int regnum, u16 data) 619 { 620 struct sk_buff *write_skb, *clear_skb, *read_skb; 621 struct qca8k_mgmt_eth_data *mgmt_eth_data; 622 u32 write_val, clear_val = 0, val; 623 struct net_device *mgmt_master; 624 int ret, ret1; 625 bool ack; 626 627 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) 628 return -EINVAL; 629 630 mgmt_eth_data = &priv->mgmt_eth_data; 631 632 write_val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | 633 QCA8K_MDIO_MASTER_PHY_ADDR(phy) | 634 QCA8K_MDIO_MASTER_REG_ADDR(regnum); 635 636 if (read) { 637 write_val |= QCA8K_MDIO_MASTER_READ; 638 } else { 639 write_val |= QCA8K_MDIO_MASTER_WRITE; 640 write_val |= QCA8K_MDIO_MASTER_DATA(data); 641 } 642 643 /* Prealloc all the needed skb before the lock */ 644 write_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &write_val, 645 QCA8K_ETHERNET_PHY_PRIORITY, sizeof(write_val)); 646 if (!write_skb) 647 return -ENOMEM; 648 649 clear_skb = qca8k_alloc_mdio_header(MDIO_WRITE, QCA8K_MDIO_MASTER_CTRL, &clear_val, 650 QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val)); 651 if (!clear_skb) { 652 ret = -ENOMEM; 653 goto err_clear_skb; 654 } 655 656 read_skb = qca8k_alloc_mdio_header(MDIO_READ, QCA8K_MDIO_MASTER_CTRL, &clear_val, 657 QCA8K_ETHERNET_PHY_PRIORITY, sizeof(clear_val)); 658 if (!read_skb) { 659 ret = -ENOMEM; 660 goto err_read_skb; 661 } 662 663 /* Actually start the request: 664 * 1. Send mdio master packet 665 * 2. Busy Wait for mdio master command 666 * 3. Get the data if we are reading 667 * 4. Reset the mdio master (even with error) 668 */ 669 mutex_lock(&mgmt_eth_data->mutex); 670 671 /* Check if mgmt_master is operational */ 672 mgmt_master = priv->mgmt_master; 673 if (!mgmt_master) { 674 mutex_unlock(&mgmt_eth_data->mutex); 675 ret = -EINVAL; 676 goto err_mgmt_master; 677 } 678 679 read_skb->dev = mgmt_master; 680 clear_skb->dev = mgmt_master; 681 write_skb->dev = mgmt_master; 682 683 reinit_completion(&mgmt_eth_data->rw_done); 684 685 /* Increment seq_num and set it in the write pkt */ 686 mgmt_eth_data->seq++; 687 qca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data->seq); 688 mgmt_eth_data->ack = false; 689 690 dev_queue_xmit(write_skb); 691 692 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, 693 QCA8K_ETHERNET_TIMEOUT); 694 695 ack = mgmt_eth_data->ack; 696 697 if (ret <= 0) { 698 ret = -ETIMEDOUT; 699 kfree_skb(read_skb); 700 goto exit; 701 } 702 703 if (!ack) { 704 ret = -EINVAL; 705 kfree_skb(read_skb); 706 goto exit; 707 } 708 709 ret = read_poll_timeout(qca8k_phy_eth_busy_wait, ret1, 710 !(val & QCA8K_MDIO_MASTER_BUSY), 0, 711 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, 712 mgmt_eth_data, read_skb, &val); 713 714 if (ret < 0 && ret1 < 0) { 715 ret = ret1; 716 goto exit; 717 } 718 719 if (read) { 720 reinit_completion(&mgmt_eth_data->rw_done); 721 722 /* Increment seq_num and set it in the read pkt */ 723 mgmt_eth_data->seq++; 724 qca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data->seq); 725 mgmt_eth_data->ack = false; 726 727 dev_queue_xmit(read_skb); 728 729 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, 730 QCA8K_ETHERNET_TIMEOUT); 731 732 ack = mgmt_eth_data->ack; 733 734 if (ret <= 0) { 735 ret = -ETIMEDOUT; 736 goto exit; 737 } 738 739 if (!ack) { 740 ret = -EINVAL; 741 goto exit; 742 } 743 744 ret = mgmt_eth_data->data[0] & QCA8K_MDIO_MASTER_DATA_MASK; 745 } else { 746 kfree_skb(read_skb); 747 } 748 exit: 749 reinit_completion(&mgmt_eth_data->rw_done); 750 751 /* Increment seq_num and set it in the clear pkt */ 752 mgmt_eth_data->seq++; 753 qca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data->seq); 754 mgmt_eth_data->ack = false; 755 756 dev_queue_xmit(clear_skb); 757 758 wait_for_completion_timeout(&mgmt_eth_data->rw_done, 759 QCA8K_ETHERNET_TIMEOUT); 760 761 mutex_unlock(&mgmt_eth_data->mutex); 762 763 return ret; 764 765 /* Error handling before lock */ 766 err_mgmt_master: 767 kfree_skb(read_skb); 768 err_read_skb: 769 kfree_skb(clear_skb); 770 err_clear_skb: 771 kfree_skb(write_skb); 772 773 return ret; 774 } 775 776 static int 777 qca8k_mdio_busy_wait(struct mii_bus *bus, u32 reg, u32 mask) 778 { 779 u16 r1, r2, page; 780 u32 val; 781 int ret, ret1; 782 783 qca8k_split_addr(reg, &r1, &r2, &page); 784 785 ret = read_poll_timeout(qca8k_mii_read_hi, ret1, !(val & mask), 0, 786 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC, false, 787 bus, 0x10 | r2, r1 + 1, &val); 788 789 /* Check if qca8k_read has failed for a different reason 790 * before returnting -ETIMEDOUT 791 */ 792 if (ret < 0 && ret1 < 0) 793 return ret1; 794 795 return ret; 796 } 797 798 static int 799 qca8k_mdio_write(struct qca8k_priv *priv, int phy, int regnum, u16 data) 800 { 801 struct mii_bus *bus = priv->bus; 802 u16 r1, r2, page; 803 u32 val; 804 int ret; 805 806 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) 807 return -EINVAL; 808 809 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | 810 QCA8K_MDIO_MASTER_WRITE | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | 811 QCA8K_MDIO_MASTER_REG_ADDR(regnum) | 812 QCA8K_MDIO_MASTER_DATA(data); 813 814 qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); 815 816 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 817 818 ret = qca8k_set_page(priv, page); 819 if (ret) 820 goto exit; 821 822 qca8k_mii_write32(bus, 0x10 | r2, r1, val); 823 824 ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL, 825 QCA8K_MDIO_MASTER_BUSY); 826 827 exit: 828 /* even if the busy_wait timeouts try to clear the MASTER_EN */ 829 qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0); 830 831 mutex_unlock(&bus->mdio_lock); 832 833 return ret; 834 } 835 836 static int 837 qca8k_mdio_read(struct qca8k_priv *priv, int phy, int regnum) 838 { 839 struct mii_bus *bus = priv->bus; 840 u16 r1, r2, page; 841 u32 val; 842 int ret; 843 844 if (regnum >= QCA8K_MDIO_MASTER_MAX_REG) 845 return -EINVAL; 846 847 val = QCA8K_MDIO_MASTER_BUSY | QCA8K_MDIO_MASTER_EN | 848 QCA8K_MDIO_MASTER_READ | QCA8K_MDIO_MASTER_PHY_ADDR(phy) | 849 QCA8K_MDIO_MASTER_REG_ADDR(regnum); 850 851 qca8k_split_addr(QCA8K_MDIO_MASTER_CTRL, &r1, &r2, &page); 852 853 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 854 855 ret = qca8k_set_page(priv, page); 856 if (ret) 857 goto exit; 858 859 qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, val); 860 861 ret = qca8k_mdio_busy_wait(bus, QCA8K_MDIO_MASTER_CTRL, 862 QCA8K_MDIO_MASTER_BUSY); 863 if (ret) 864 goto exit; 865 866 ret = qca8k_mii_read_lo(bus, 0x10 | r2, r1, &val); 867 868 exit: 869 /* even if the busy_wait timeouts try to clear the MASTER_EN */ 870 qca8k_mii_write_hi(bus, 0x10 | r2, r1 + 1, 0); 871 872 mutex_unlock(&bus->mdio_lock); 873 874 if (ret >= 0) 875 ret = val & QCA8K_MDIO_MASTER_DATA_MASK; 876 877 return ret; 878 } 879 880 static int 881 qca8k_internal_mdio_write(struct mii_bus *slave_bus, int phy, int regnum, u16 data) 882 { 883 struct qca8k_priv *priv = slave_bus->priv; 884 int ret; 885 886 /* Use mdio Ethernet when available, fallback to legacy one on error */ 887 ret = qca8k_phy_eth_command(priv, false, phy, regnum, data); 888 if (!ret) 889 return 0; 890 891 return qca8k_mdio_write(priv, phy, regnum, data); 892 } 893 894 static int 895 qca8k_internal_mdio_read(struct mii_bus *slave_bus, int phy, int regnum) 896 { 897 struct qca8k_priv *priv = slave_bus->priv; 898 int ret; 899 900 /* Use mdio Ethernet when available, fallback to legacy one on error */ 901 ret = qca8k_phy_eth_command(priv, true, phy, regnum, 0); 902 if (ret >= 0) 903 return ret; 904 905 ret = qca8k_mdio_read(priv, phy, regnum); 906 907 if (ret < 0) 908 return 0xffff; 909 910 return ret; 911 } 912 913 static int 914 qca8k_legacy_mdio_write(struct mii_bus *slave_bus, int port, int regnum, u16 data) 915 { 916 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR; 917 918 return qca8k_internal_mdio_write(slave_bus, port, regnum, data); 919 } 920 921 static int 922 qca8k_legacy_mdio_read(struct mii_bus *slave_bus, int port, int regnum) 923 { 924 port = qca8k_port_to_phy(port) % PHY_MAX_ADDR; 925 926 return qca8k_internal_mdio_read(slave_bus, port, regnum); 927 } 928 929 static int 930 qca8k_mdio_register(struct qca8k_priv *priv) 931 { 932 struct dsa_switch *ds = priv->ds; 933 struct device_node *mdio; 934 struct mii_bus *bus; 935 936 bus = devm_mdiobus_alloc(ds->dev); 937 if (!bus) 938 return -ENOMEM; 939 940 bus->priv = (void *)priv; 941 snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d.%d", 942 ds->dst->index, ds->index); 943 bus->parent = ds->dev; 944 bus->phy_mask = ~ds->phys_mii_mask; 945 ds->slave_mii_bus = bus; 946 947 /* Check if the devicetree declare the port:phy mapping */ 948 mdio = of_get_child_by_name(priv->dev->of_node, "mdio"); 949 if (of_device_is_available(mdio)) { 950 bus->name = "qca8k slave mii"; 951 bus->read = qca8k_internal_mdio_read; 952 bus->write = qca8k_internal_mdio_write; 953 return devm_of_mdiobus_register(priv->dev, bus, mdio); 954 } 955 956 /* If a mapping can't be found the legacy mapping is used, 957 * using the qca8k_port_to_phy function 958 */ 959 bus->name = "qca8k-legacy slave mii"; 960 bus->read = qca8k_legacy_mdio_read; 961 bus->write = qca8k_legacy_mdio_write; 962 return devm_mdiobus_register(priv->dev, bus); 963 } 964 965 static int 966 qca8k_setup_mdio_bus(struct qca8k_priv *priv) 967 { 968 u32 internal_mdio_mask = 0, external_mdio_mask = 0, reg; 969 struct device_node *ports, *port; 970 phy_interface_t mode; 971 int err; 972 973 ports = of_get_child_by_name(priv->dev->of_node, "ports"); 974 if (!ports) 975 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports"); 976 977 if (!ports) 978 return -EINVAL; 979 980 for_each_available_child_of_node(ports, port) { 981 err = of_property_read_u32(port, "reg", ®); 982 if (err) { 983 of_node_put(port); 984 of_node_put(ports); 985 return err; 986 } 987 988 if (!dsa_is_user_port(priv->ds, reg)) 989 continue; 990 991 of_get_phy_mode(port, &mode); 992 993 if (of_property_read_bool(port, "phy-handle") && 994 mode != PHY_INTERFACE_MODE_INTERNAL) 995 external_mdio_mask |= BIT(reg); 996 else 997 internal_mdio_mask |= BIT(reg); 998 } 999 1000 of_node_put(ports); 1001 if (!external_mdio_mask && !internal_mdio_mask) { 1002 dev_err(priv->dev, "no PHYs are defined.\n"); 1003 return -EINVAL; 1004 } 1005 1006 /* The QCA8K_MDIO_MASTER_EN Bit, which grants access to PHYs through 1007 * the MDIO_MASTER register also _disconnects_ the external MDC 1008 * passthrough to the internal PHYs. It's not possible to use both 1009 * configurations at the same time! 1010 * 1011 * Because this came up during the review process: 1012 * If the external mdio-bus driver is capable magically disabling 1013 * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's 1014 * accessors for the time being, it would be possible to pull this 1015 * off. 1016 */ 1017 if (!!external_mdio_mask && !!internal_mdio_mask) { 1018 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n"); 1019 return -EINVAL; 1020 } 1021 1022 if (external_mdio_mask) { 1023 /* Make sure to disable the internal mdio bus in cases 1024 * a dt-overlay and driver reload changed the configuration 1025 */ 1026 1027 return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL, 1028 QCA8K_MDIO_MASTER_EN); 1029 } 1030 1031 return qca8k_mdio_register(priv); 1032 } 1033 1034 static int 1035 qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv) 1036 { 1037 u32 mask = 0; 1038 int ret = 0; 1039 1040 /* SoC specific settings for ipq8064. 1041 * If more device require this consider adding 1042 * a dedicated binding. 1043 */ 1044 if (of_machine_is_compatible("qcom,ipq8064")) 1045 mask |= QCA8K_MAC_PWR_RGMII0_1_8V; 1046 1047 /* SoC specific settings for ipq8065 */ 1048 if (of_machine_is_compatible("qcom,ipq8065")) 1049 mask |= QCA8K_MAC_PWR_RGMII1_1_8V; 1050 1051 if (mask) { 1052 ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL, 1053 QCA8K_MAC_PWR_RGMII0_1_8V | 1054 QCA8K_MAC_PWR_RGMII1_1_8V, 1055 mask); 1056 } 1057 1058 return ret; 1059 } 1060 1061 static int qca8k_find_cpu_port(struct dsa_switch *ds) 1062 { 1063 struct qca8k_priv *priv = ds->priv; 1064 1065 /* Find the connected cpu port. Valid port are 0 or 6 */ 1066 if (dsa_is_cpu_port(ds, 0)) 1067 return 0; 1068 1069 dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6"); 1070 1071 if (dsa_is_cpu_port(ds, 6)) 1072 return 6; 1073 1074 return -EINVAL; 1075 } 1076 1077 static int 1078 qca8k_setup_of_pws_reg(struct qca8k_priv *priv) 1079 { 1080 const struct qca8k_match_data *data = priv->info; 1081 struct device_node *node = priv->dev->of_node; 1082 u32 val = 0; 1083 int ret; 1084 1085 /* QCA8327 require to set to the correct mode. 1086 * His bigger brother QCA8328 have the 172 pin layout. 1087 * Should be applied by default but we set this just to make sure. 1088 */ 1089 if (priv->switch_id == QCA8K_ID_QCA8327) { 1090 /* Set the correct package of 148 pin for QCA8327 */ 1091 if (data->reduced_package) 1092 val |= QCA8327_PWS_PACKAGE148_EN; 1093 1094 ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN, 1095 val); 1096 if (ret) 1097 return ret; 1098 } 1099 1100 if (of_property_read_bool(node, "qca,ignore-power-on-sel")) 1101 val |= QCA8K_PWS_POWER_ON_SEL; 1102 1103 if (of_property_read_bool(node, "qca,led-open-drain")) { 1104 if (!(val & QCA8K_PWS_POWER_ON_SEL)) { 1105 dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set."); 1106 return -EINVAL; 1107 } 1108 1109 val |= QCA8K_PWS_LED_OPEN_EN_CSR; 1110 } 1111 1112 return qca8k_rmw(priv, QCA8K_REG_PWS, 1113 QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL, 1114 val); 1115 } 1116 1117 static int 1118 qca8k_parse_port_config(struct qca8k_priv *priv) 1119 { 1120 int port, cpu_port_index = -1, ret; 1121 struct device_node *port_dn; 1122 phy_interface_t mode; 1123 struct dsa_port *dp; 1124 u32 delay; 1125 1126 /* We have 2 CPU port. Check them */ 1127 for (port = 0; port < QCA8K_NUM_PORTS; port++) { 1128 /* Skip every other port */ 1129 if (port != 0 && port != 6) 1130 continue; 1131 1132 dp = dsa_to_port(priv->ds, port); 1133 port_dn = dp->dn; 1134 cpu_port_index++; 1135 1136 if (!of_device_is_available(port_dn)) 1137 continue; 1138 1139 ret = of_get_phy_mode(port_dn, &mode); 1140 if (ret) 1141 continue; 1142 1143 switch (mode) { 1144 case PHY_INTERFACE_MODE_RGMII: 1145 case PHY_INTERFACE_MODE_RGMII_ID: 1146 case PHY_INTERFACE_MODE_RGMII_TXID: 1147 case PHY_INTERFACE_MODE_RGMII_RXID: 1148 case PHY_INTERFACE_MODE_SGMII: 1149 delay = 0; 1150 1151 if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay)) 1152 /* Switch regs accept value in ns, convert ps to ns */ 1153 delay = delay / 1000; 1154 else if (mode == PHY_INTERFACE_MODE_RGMII_ID || 1155 mode == PHY_INTERFACE_MODE_RGMII_TXID) 1156 delay = 1; 1157 1158 if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) { 1159 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); 1160 delay = 3; 1161 } 1162 1163 priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay; 1164 1165 delay = 0; 1166 1167 if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay)) 1168 /* Switch regs accept value in ns, convert ps to ns */ 1169 delay = delay / 1000; 1170 else if (mode == PHY_INTERFACE_MODE_RGMII_ID || 1171 mode == PHY_INTERFACE_MODE_RGMII_RXID) 1172 delay = 2; 1173 1174 if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) { 1175 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); 1176 delay = 3; 1177 } 1178 1179 priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay; 1180 1181 /* Skip sgmii parsing for rgmii* mode */ 1182 if (mode == PHY_INTERFACE_MODE_RGMII || 1183 mode == PHY_INTERFACE_MODE_RGMII_ID || 1184 mode == PHY_INTERFACE_MODE_RGMII_TXID || 1185 mode == PHY_INTERFACE_MODE_RGMII_RXID) 1186 break; 1187 1188 if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge")) 1189 priv->ports_config.sgmii_tx_clk_falling_edge = true; 1190 1191 if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge")) 1192 priv->ports_config.sgmii_rx_clk_falling_edge = true; 1193 1194 if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) { 1195 priv->ports_config.sgmii_enable_pll = true; 1196 1197 if (priv->switch_id == QCA8K_ID_QCA8327) { 1198 dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling"); 1199 priv->ports_config.sgmii_enable_pll = false; 1200 } 1201 1202 if (priv->switch_revision < 2) 1203 dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more."); 1204 } 1205 1206 break; 1207 default: 1208 continue; 1209 } 1210 } 1211 1212 return 0; 1213 } 1214 1215 static void 1216 qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_index, 1217 u32 reg) 1218 { 1219 u32 delay, val = 0; 1220 int ret; 1221 1222 /* Delay can be declared in 3 different way. 1223 * Mode to rgmii and internal-delay standard binding defined 1224 * rgmii-id or rgmii-tx/rx phy mode set. 1225 * The parse logic set a delay different than 0 only when one 1226 * of the 3 different way is used. In all other case delay is 1227 * not enabled. With ID or TX/RXID delay is enabled and set 1228 * to the default and recommended value. 1229 */ 1230 if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) { 1231 delay = priv->ports_config.rgmii_tx_delay[cpu_port_index]; 1232 1233 val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) | 1234 QCA8K_PORT_PAD_RGMII_TX_DELAY_EN; 1235 } 1236 1237 if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) { 1238 delay = priv->ports_config.rgmii_rx_delay[cpu_port_index]; 1239 1240 val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) | 1241 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN; 1242 } 1243 1244 /* Set RGMII delay based on the selected values */ 1245 ret = qca8k_rmw(priv, reg, 1246 QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK | 1247 QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK | 1248 QCA8K_PORT_PAD_RGMII_TX_DELAY_EN | 1249 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN, 1250 val); 1251 if (ret) 1252 dev_err(priv->dev, "Failed to set internal delay for CPU port%d", 1253 cpu_port_index == QCA8K_CPU_PORT0 ? 0 : 6); 1254 } 1255 1256 static struct phylink_pcs * 1257 qca8k_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 1258 phy_interface_t interface) 1259 { 1260 struct qca8k_priv *priv = ds->priv; 1261 struct phylink_pcs *pcs = NULL; 1262 1263 switch (interface) { 1264 case PHY_INTERFACE_MODE_SGMII: 1265 case PHY_INTERFACE_MODE_1000BASEX: 1266 switch (port) { 1267 case 0: 1268 pcs = &priv->pcs_port_0.pcs; 1269 break; 1270 1271 case 6: 1272 pcs = &priv->pcs_port_6.pcs; 1273 break; 1274 } 1275 break; 1276 1277 default: 1278 break; 1279 } 1280 1281 return pcs; 1282 } 1283 1284 static void 1285 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 1286 const struct phylink_link_state *state) 1287 { 1288 struct qca8k_priv *priv = ds->priv; 1289 int cpu_port_index; 1290 u32 reg; 1291 1292 switch (port) { 1293 case 0: /* 1st CPU port */ 1294 if (state->interface != PHY_INTERFACE_MODE_RGMII && 1295 state->interface != PHY_INTERFACE_MODE_RGMII_ID && 1296 state->interface != PHY_INTERFACE_MODE_RGMII_TXID && 1297 state->interface != PHY_INTERFACE_MODE_RGMII_RXID && 1298 state->interface != PHY_INTERFACE_MODE_SGMII) 1299 return; 1300 1301 reg = QCA8K_REG_PORT0_PAD_CTRL; 1302 cpu_port_index = QCA8K_CPU_PORT0; 1303 break; 1304 case 1: 1305 case 2: 1306 case 3: 1307 case 4: 1308 case 5: 1309 /* Internal PHY, nothing to do */ 1310 return; 1311 case 6: /* 2nd CPU port / external PHY */ 1312 if (state->interface != PHY_INTERFACE_MODE_RGMII && 1313 state->interface != PHY_INTERFACE_MODE_RGMII_ID && 1314 state->interface != PHY_INTERFACE_MODE_RGMII_TXID && 1315 state->interface != PHY_INTERFACE_MODE_RGMII_RXID && 1316 state->interface != PHY_INTERFACE_MODE_SGMII && 1317 state->interface != PHY_INTERFACE_MODE_1000BASEX) 1318 return; 1319 1320 reg = QCA8K_REG_PORT6_PAD_CTRL; 1321 cpu_port_index = QCA8K_CPU_PORT6; 1322 break; 1323 default: 1324 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); 1325 return; 1326 } 1327 1328 if (port != 6 && phylink_autoneg_inband(mode)) { 1329 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 1330 __func__); 1331 return; 1332 } 1333 1334 switch (state->interface) { 1335 case PHY_INTERFACE_MODE_RGMII: 1336 case PHY_INTERFACE_MODE_RGMII_ID: 1337 case PHY_INTERFACE_MODE_RGMII_TXID: 1338 case PHY_INTERFACE_MODE_RGMII_RXID: 1339 qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN); 1340 1341 /* Configure rgmii delay */ 1342 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg); 1343 1344 /* QCA8337 requires to set rgmii rx delay for all ports. 1345 * This is enabled through PORT5_PAD_CTRL for all ports, 1346 * rather than individual port registers. 1347 */ 1348 if (priv->switch_id == QCA8K_ID_QCA8337) 1349 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL, 1350 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN); 1351 break; 1352 case PHY_INTERFACE_MODE_SGMII: 1353 case PHY_INTERFACE_MODE_1000BASEX: 1354 /* Enable SGMII on the port */ 1355 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN); 1356 break; 1357 default: 1358 dev_err(ds->dev, "xMII mode %s not supported for port %d\n", 1359 phy_modes(state->interface), port); 1360 return; 1361 } 1362 } 1363 1364 static void qca8k_phylink_get_caps(struct dsa_switch *ds, int port, 1365 struct phylink_config *config) 1366 { 1367 switch (port) { 1368 case 0: /* 1st CPU port */ 1369 phy_interface_set_rgmii(config->supported_interfaces); 1370 __set_bit(PHY_INTERFACE_MODE_SGMII, 1371 config->supported_interfaces); 1372 break; 1373 1374 case 1: 1375 case 2: 1376 case 3: 1377 case 4: 1378 case 5: 1379 /* Internal PHY */ 1380 __set_bit(PHY_INTERFACE_MODE_GMII, 1381 config->supported_interfaces); 1382 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1383 config->supported_interfaces); 1384 break; 1385 1386 case 6: /* 2nd CPU port / external PHY */ 1387 phy_interface_set_rgmii(config->supported_interfaces); 1388 __set_bit(PHY_INTERFACE_MODE_SGMII, 1389 config->supported_interfaces); 1390 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 1391 config->supported_interfaces); 1392 break; 1393 } 1394 1395 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1396 MAC_10 | MAC_100 | MAC_1000FD; 1397 1398 config->legacy_pre_march2020 = false; 1399 } 1400 1401 static void 1402 qca8k_phylink_mac_link_down(struct dsa_switch *ds, int port, unsigned int mode, 1403 phy_interface_t interface) 1404 { 1405 struct qca8k_priv *priv = ds->priv; 1406 1407 qca8k_port_set_status(priv, port, 0); 1408 } 1409 1410 static void 1411 qca8k_phylink_mac_link_up(struct dsa_switch *ds, int port, unsigned int mode, 1412 phy_interface_t interface, struct phy_device *phydev, 1413 int speed, int duplex, bool tx_pause, bool rx_pause) 1414 { 1415 struct qca8k_priv *priv = ds->priv; 1416 u32 reg; 1417 1418 if (phylink_autoneg_inband(mode)) { 1419 reg = QCA8K_PORT_STATUS_LINK_AUTO; 1420 } else { 1421 switch (speed) { 1422 case SPEED_10: 1423 reg = QCA8K_PORT_STATUS_SPEED_10; 1424 break; 1425 case SPEED_100: 1426 reg = QCA8K_PORT_STATUS_SPEED_100; 1427 break; 1428 case SPEED_1000: 1429 reg = QCA8K_PORT_STATUS_SPEED_1000; 1430 break; 1431 default: 1432 reg = QCA8K_PORT_STATUS_LINK_AUTO; 1433 break; 1434 } 1435 1436 if (duplex == DUPLEX_FULL) 1437 reg |= QCA8K_PORT_STATUS_DUPLEX; 1438 1439 if (rx_pause || dsa_is_cpu_port(ds, port)) 1440 reg |= QCA8K_PORT_STATUS_RXFLOW; 1441 1442 if (tx_pause || dsa_is_cpu_port(ds, port)) 1443 reg |= QCA8K_PORT_STATUS_TXFLOW; 1444 } 1445 1446 reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC; 1447 1448 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg); 1449 } 1450 1451 static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs) 1452 { 1453 return container_of(pcs, struct qca8k_pcs, pcs); 1454 } 1455 1456 static void qca8k_pcs_get_state(struct phylink_pcs *pcs, 1457 struct phylink_link_state *state) 1458 { 1459 struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv; 1460 int port = pcs_to_qca8k_pcs(pcs)->port; 1461 u32 reg; 1462 int ret; 1463 1464 ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), ®); 1465 if (ret < 0) { 1466 state->link = false; 1467 return; 1468 } 1469 1470 state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP); 1471 state->an_complete = state->link; 1472 state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL : 1473 DUPLEX_HALF; 1474 1475 switch (reg & QCA8K_PORT_STATUS_SPEED) { 1476 case QCA8K_PORT_STATUS_SPEED_10: 1477 state->speed = SPEED_10; 1478 break; 1479 case QCA8K_PORT_STATUS_SPEED_100: 1480 state->speed = SPEED_100; 1481 break; 1482 case QCA8K_PORT_STATUS_SPEED_1000: 1483 state->speed = SPEED_1000; 1484 break; 1485 default: 1486 state->speed = SPEED_UNKNOWN; 1487 break; 1488 } 1489 1490 if (reg & QCA8K_PORT_STATUS_RXFLOW) 1491 state->pause |= MLO_PAUSE_RX; 1492 if (reg & QCA8K_PORT_STATUS_TXFLOW) 1493 state->pause |= MLO_PAUSE_TX; 1494 } 1495 1496 static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 1497 phy_interface_t interface, 1498 const unsigned long *advertising, 1499 bool permit_pause_to_mac) 1500 { 1501 struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv; 1502 int cpu_port_index, ret, port; 1503 u32 reg, val; 1504 1505 port = pcs_to_qca8k_pcs(pcs)->port; 1506 switch (port) { 1507 case 0: 1508 reg = QCA8K_REG_PORT0_PAD_CTRL; 1509 cpu_port_index = QCA8K_CPU_PORT0; 1510 break; 1511 1512 case 6: 1513 reg = QCA8K_REG_PORT6_PAD_CTRL; 1514 cpu_port_index = QCA8K_CPU_PORT6; 1515 break; 1516 1517 default: 1518 WARN_ON(1); 1519 return -EINVAL; 1520 } 1521 1522 /* Enable/disable SerDes auto-negotiation as necessary */ 1523 ret = qca8k_read(priv, QCA8K_REG_PWS, &val); 1524 if (ret) 1525 return ret; 1526 if (phylink_autoneg_inband(mode)) 1527 val &= ~QCA8K_PWS_SERDES_AEN_DIS; 1528 else 1529 val |= QCA8K_PWS_SERDES_AEN_DIS; 1530 qca8k_write(priv, QCA8K_REG_PWS, val); 1531 1532 /* Configure the SGMII parameters */ 1533 ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val); 1534 if (ret) 1535 return ret; 1536 1537 val |= QCA8K_SGMII_EN_SD; 1538 1539 if (priv->ports_config.sgmii_enable_pll) 1540 val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX | 1541 QCA8K_SGMII_EN_TX; 1542 1543 if (dsa_is_cpu_port(priv->ds, port)) { 1544 /* CPU port, we're talking to the CPU MAC, be a PHY */ 1545 val &= ~QCA8K_SGMII_MODE_CTRL_MASK; 1546 val |= QCA8K_SGMII_MODE_CTRL_PHY; 1547 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1548 val &= ~QCA8K_SGMII_MODE_CTRL_MASK; 1549 val |= QCA8K_SGMII_MODE_CTRL_MAC; 1550 } else if (interface == PHY_INTERFACE_MODE_1000BASEX) { 1551 val &= ~QCA8K_SGMII_MODE_CTRL_MASK; 1552 val |= QCA8K_SGMII_MODE_CTRL_BASEX; 1553 } 1554 1555 qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val); 1556 1557 /* From original code is reported port instability as SGMII also 1558 * require delay set. Apply advised values here or take them from DT. 1559 */ 1560 if (interface == PHY_INTERFACE_MODE_SGMII) 1561 qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg); 1562 /* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and 1563 * falling edge is set writing in the PORT0 PAD reg 1564 */ 1565 if (priv->switch_id == QCA8K_ID_QCA8327 || 1566 priv->switch_id == QCA8K_ID_QCA8337) 1567 reg = QCA8K_REG_PORT0_PAD_CTRL; 1568 1569 val = 0; 1570 1571 /* SGMII Clock phase configuration */ 1572 if (priv->ports_config.sgmii_rx_clk_falling_edge) 1573 val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE; 1574 1575 if (priv->ports_config.sgmii_tx_clk_falling_edge) 1576 val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE; 1577 1578 if (val) 1579 ret = qca8k_rmw(priv, reg, 1580 QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE | 1581 QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE, 1582 val); 1583 1584 return 0; 1585 } 1586 1587 static void qca8k_pcs_an_restart(struct phylink_pcs *pcs) 1588 { 1589 } 1590 1591 static const struct phylink_pcs_ops qca8k_pcs_ops = { 1592 .pcs_get_state = qca8k_pcs_get_state, 1593 .pcs_config = qca8k_pcs_config, 1594 .pcs_an_restart = qca8k_pcs_an_restart, 1595 }; 1596 1597 static void qca8k_setup_pcs(struct qca8k_priv *priv, struct qca8k_pcs *qpcs, 1598 int port) 1599 { 1600 qpcs->pcs.ops = &qca8k_pcs_ops; 1601 1602 /* We don't have interrupts for link changes, so we need to poll */ 1603 qpcs->pcs.poll = true; 1604 qpcs->priv = priv; 1605 qpcs->port = port; 1606 } 1607 1608 static void qca8k_mib_autocast_handler(struct dsa_switch *ds, struct sk_buff *skb) 1609 { 1610 struct qca8k_mib_eth_data *mib_eth_data; 1611 struct qca8k_priv *priv = ds->priv; 1612 const struct qca8k_mib_desc *mib; 1613 struct mib_ethhdr *mib_ethhdr; 1614 __le32 *data2; 1615 u8 port; 1616 int i; 1617 1618 mib_ethhdr = (struct mib_ethhdr *)skb_mac_header(skb); 1619 mib_eth_data = &priv->mib_eth_data; 1620 1621 /* The switch autocast every port. Ignore other packet and 1622 * parse only the requested one. 1623 */ 1624 port = FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, ntohs(mib_ethhdr->hdr)); 1625 if (port != mib_eth_data->req_port) 1626 goto exit; 1627 1628 data2 = (__le32 *)skb->data; 1629 1630 for (i = 0; i < priv->info->mib_count; i++) { 1631 mib = &ar8327_mib[i]; 1632 1633 /* First 3 mib are present in the skb head */ 1634 if (i < 3) { 1635 mib_eth_data->data[i] = get_unaligned_le32(mib_ethhdr->data + i); 1636 continue; 1637 } 1638 1639 /* Some mib are 64 bit wide */ 1640 if (mib->size == 2) 1641 mib_eth_data->data[i] = get_unaligned_le64((__le64 *)data2); 1642 else 1643 mib_eth_data->data[i] = get_unaligned_le32(data2); 1644 1645 data2 += mib->size; 1646 } 1647 1648 exit: 1649 /* Complete on receiving all the mib packet */ 1650 if (refcount_dec_and_test(&mib_eth_data->port_parsed)) 1651 complete(&mib_eth_data->rw_done); 1652 } 1653 1654 static int 1655 qca8k_get_ethtool_stats_eth(struct dsa_switch *ds, int port, u64 *data) 1656 { 1657 struct dsa_port *dp = dsa_to_port(ds, port); 1658 struct qca8k_mib_eth_data *mib_eth_data; 1659 struct qca8k_priv *priv = ds->priv; 1660 int ret; 1661 1662 mib_eth_data = &priv->mib_eth_data; 1663 1664 mutex_lock(&mib_eth_data->mutex); 1665 1666 reinit_completion(&mib_eth_data->rw_done); 1667 1668 mib_eth_data->req_port = dp->index; 1669 mib_eth_data->data = data; 1670 refcount_set(&mib_eth_data->port_parsed, QCA8K_NUM_PORTS); 1671 1672 mutex_lock(&priv->reg_mutex); 1673 1674 /* Send mib autocast request */ 1675 ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB, 1676 QCA8K_MIB_FUNC | QCA8K_MIB_BUSY, 1677 FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_CAST) | 1678 QCA8K_MIB_BUSY); 1679 1680 mutex_unlock(&priv->reg_mutex); 1681 1682 if (ret) 1683 goto exit; 1684 1685 ret = wait_for_completion_timeout(&mib_eth_data->rw_done, QCA8K_ETHERNET_TIMEOUT); 1686 1687 exit: 1688 mutex_unlock(&mib_eth_data->mutex); 1689 1690 return ret; 1691 } 1692 1693 static u32 qca8k_get_phy_flags(struct dsa_switch *ds, int port) 1694 { 1695 struct qca8k_priv *priv = ds->priv; 1696 1697 /* Communicate to the phy internal driver the switch revision. 1698 * Based on the switch revision different values needs to be 1699 * set to the dbg and mmd reg on the phy. 1700 * The first 2 bit are used to communicate the switch revision 1701 * to the phy driver. 1702 */ 1703 if (port > 0 && port < 6) 1704 return priv->switch_revision; 1705 1706 return 0; 1707 } 1708 1709 static enum dsa_tag_protocol 1710 qca8k_get_tag_protocol(struct dsa_switch *ds, int port, 1711 enum dsa_tag_protocol mp) 1712 { 1713 return DSA_TAG_PROTO_QCA; 1714 } 1715 1716 static void 1717 qca8k_master_change(struct dsa_switch *ds, const struct net_device *master, 1718 bool operational) 1719 { 1720 struct dsa_port *dp = master->dsa_ptr; 1721 struct qca8k_priv *priv = ds->priv; 1722 1723 /* Ethernet MIB/MDIO is only supported for CPU port 0 */ 1724 if (dp->index != 0) 1725 return; 1726 1727 mutex_lock(&priv->mgmt_eth_data.mutex); 1728 mutex_lock(&priv->mib_eth_data.mutex); 1729 1730 priv->mgmt_master = operational ? (struct net_device *)master : NULL; 1731 1732 mutex_unlock(&priv->mib_eth_data.mutex); 1733 mutex_unlock(&priv->mgmt_eth_data.mutex); 1734 } 1735 1736 static int qca8k_connect_tag_protocol(struct dsa_switch *ds, 1737 enum dsa_tag_protocol proto) 1738 { 1739 struct qca_tagger_data *tagger_data; 1740 1741 switch (proto) { 1742 case DSA_TAG_PROTO_QCA: 1743 tagger_data = ds->tagger_data; 1744 1745 tagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler; 1746 tagger_data->mib_autocast_handler = qca8k_mib_autocast_handler; 1747 1748 break; 1749 default: 1750 return -EOPNOTSUPP; 1751 } 1752 1753 return 0; 1754 } 1755 1756 static int 1757 qca8k_setup(struct dsa_switch *ds) 1758 { 1759 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv; 1760 int cpu_port, ret, i; 1761 u32 mask; 1762 1763 cpu_port = qca8k_find_cpu_port(ds); 1764 if (cpu_port < 0) { 1765 dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6"); 1766 return cpu_port; 1767 } 1768 1769 /* Parse CPU port config to be later used in phy_link mac_config */ 1770 ret = qca8k_parse_port_config(priv); 1771 if (ret) 1772 return ret; 1773 1774 ret = qca8k_setup_mdio_bus(priv); 1775 if (ret) 1776 return ret; 1777 1778 ret = qca8k_setup_of_pws_reg(priv); 1779 if (ret) 1780 return ret; 1781 1782 ret = qca8k_setup_mac_pwr_sel(priv); 1783 if (ret) 1784 return ret; 1785 1786 ret = qca8k_setup_led_ctrl(priv); 1787 if (ret) 1788 return ret; 1789 1790 qca8k_setup_pcs(priv, &priv->pcs_port_0, 0); 1791 qca8k_setup_pcs(priv, &priv->pcs_port_6, 6); 1792 1793 /* Make sure MAC06 is disabled */ 1794 ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL, 1795 QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN); 1796 if (ret) { 1797 dev_err(priv->dev, "failed disabling MAC06 exchange"); 1798 return ret; 1799 } 1800 1801 /* Enable CPU Port */ 1802 ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, 1803 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN); 1804 if (ret) { 1805 dev_err(priv->dev, "failed enabling CPU port"); 1806 return ret; 1807 } 1808 1809 /* Enable MIB counters */ 1810 ret = qca8k_mib_init(priv); 1811 if (ret) 1812 dev_warn(priv->dev, "mib init failed"); 1813 1814 /* Initial setup of all ports */ 1815 for (i = 0; i < QCA8K_NUM_PORTS; i++) { 1816 /* Disable forwarding by default on all ports */ 1817 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), 1818 QCA8K_PORT_LOOKUP_MEMBER, 0); 1819 if (ret) 1820 return ret; 1821 1822 /* Enable QCA header mode on all cpu ports */ 1823 if (dsa_is_cpu_port(ds, i)) { 1824 ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i), 1825 FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) | 1826 FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL)); 1827 if (ret) { 1828 dev_err(priv->dev, "failed enabling QCA header mode"); 1829 return ret; 1830 } 1831 } 1832 1833 /* Disable MAC by default on all user ports */ 1834 if (dsa_is_user_port(ds, i)) 1835 qca8k_port_set_status(priv, i, 0); 1836 } 1837 1838 /* Forward all unknown frames to CPU port for Linux processing 1839 * Notice that in multi-cpu config only one port should be set 1840 * for igmp, unknown, multicast and broadcast packet 1841 */ 1842 ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1, 1843 FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) | 1844 FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) | 1845 FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) | 1846 FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port))); 1847 if (ret) 1848 return ret; 1849 1850 /* Setup connection between CPU port & user ports 1851 * Configure specific switch configuration for ports 1852 */ 1853 for (i = 0; i < QCA8K_NUM_PORTS; i++) { 1854 /* CPU port gets connected to all user ports of the switch */ 1855 if (dsa_is_cpu_port(ds, i)) { 1856 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), 1857 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds)); 1858 if (ret) 1859 return ret; 1860 } 1861 1862 /* Individual user ports get connected to CPU port only */ 1863 if (dsa_is_user_port(ds, i)) { 1864 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i), 1865 QCA8K_PORT_LOOKUP_MEMBER, 1866 BIT(cpu_port)); 1867 if (ret) 1868 return ret; 1869 1870 /* Enable ARP Auto-learning by default */ 1871 ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(i), 1872 QCA8K_PORT_LOOKUP_LEARN); 1873 if (ret) 1874 return ret; 1875 1876 /* For port based vlans to work we need to set the 1877 * default egress vid 1878 */ 1879 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i), 1880 QCA8K_EGREES_VLAN_PORT_MASK(i), 1881 QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF)); 1882 if (ret) 1883 return ret; 1884 1885 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i), 1886 QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) | 1887 QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF)); 1888 if (ret) 1889 return ret; 1890 } 1891 1892 /* The port 5 of the qca8337 have some problem in flood condition. The 1893 * original legacy driver had some specific buffer and priority settings 1894 * for the different port suggested by the QCA switch team. Add this 1895 * missing settings to improve switch stability under load condition. 1896 * This problem is limited to qca8337 and other qca8k switch are not affected. 1897 */ 1898 if (priv->switch_id == QCA8K_ID_QCA8337) { 1899 switch (i) { 1900 /* The 2 CPU port and port 5 requires some different 1901 * priority than any other ports. 1902 */ 1903 case 0: 1904 case 5: 1905 case 6: 1906 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | 1907 QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | 1908 QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) | 1909 QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) | 1910 QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) | 1911 QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) | 1912 QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e); 1913 break; 1914 default: 1915 mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) | 1916 QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) | 1917 QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) | 1918 QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) | 1919 QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19); 1920 } 1921 qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask); 1922 1923 mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) | 1924 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | 1925 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | 1926 QCA8K_PORT_HOL_CTRL1_WRED_EN; 1927 qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i), 1928 QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK | 1929 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN | 1930 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN | 1931 QCA8K_PORT_HOL_CTRL1_WRED_EN, 1932 mask); 1933 } 1934 } 1935 1936 /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */ 1937 if (priv->switch_id == QCA8K_ID_QCA8327) { 1938 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) | 1939 QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496); 1940 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH, 1941 QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK | 1942 QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, 1943 mask); 1944 } 1945 1946 /* Setup our port MTUs to match power on defaults */ 1947 ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN); 1948 if (ret) 1949 dev_warn(priv->dev, "failed setting MTU settings"); 1950 1951 /* Flush the FDB table */ 1952 qca8k_fdb_flush(priv); 1953 1954 /* Set min a max ageing value supported */ 1955 ds->ageing_time_min = 7000; 1956 ds->ageing_time_max = 458745000; 1957 1958 /* Set max number of LAGs supported */ 1959 ds->num_lag_ids = QCA8K_NUM_LAGS; 1960 1961 return 0; 1962 } 1963 1964 static const struct dsa_switch_ops qca8k_switch_ops = { 1965 .get_tag_protocol = qca8k_get_tag_protocol, 1966 .setup = qca8k_setup, 1967 .get_strings = qca8k_get_strings, 1968 .get_ethtool_stats = qca8k_get_ethtool_stats, 1969 .get_sset_count = qca8k_get_sset_count, 1970 .set_ageing_time = qca8k_set_ageing_time, 1971 .get_mac_eee = qca8k_get_mac_eee, 1972 .set_mac_eee = qca8k_set_mac_eee, 1973 .port_enable = qca8k_port_enable, 1974 .port_disable = qca8k_port_disable, 1975 .port_change_mtu = qca8k_port_change_mtu, 1976 .port_max_mtu = qca8k_port_max_mtu, 1977 .port_stp_state_set = qca8k_port_stp_state_set, 1978 .port_bridge_join = qca8k_port_bridge_join, 1979 .port_bridge_leave = qca8k_port_bridge_leave, 1980 .port_fast_age = qca8k_port_fast_age, 1981 .port_fdb_add = qca8k_port_fdb_add, 1982 .port_fdb_del = qca8k_port_fdb_del, 1983 .port_fdb_dump = qca8k_port_fdb_dump, 1984 .port_mdb_add = qca8k_port_mdb_add, 1985 .port_mdb_del = qca8k_port_mdb_del, 1986 .port_mirror_add = qca8k_port_mirror_add, 1987 .port_mirror_del = qca8k_port_mirror_del, 1988 .port_vlan_filtering = qca8k_port_vlan_filtering, 1989 .port_vlan_add = qca8k_port_vlan_add, 1990 .port_vlan_del = qca8k_port_vlan_del, 1991 .phylink_get_caps = qca8k_phylink_get_caps, 1992 .phylink_mac_select_pcs = qca8k_phylink_mac_select_pcs, 1993 .phylink_mac_config = qca8k_phylink_mac_config, 1994 .phylink_mac_link_down = qca8k_phylink_mac_link_down, 1995 .phylink_mac_link_up = qca8k_phylink_mac_link_up, 1996 .get_phy_flags = qca8k_get_phy_flags, 1997 .port_lag_join = qca8k_port_lag_join, 1998 .port_lag_leave = qca8k_port_lag_leave, 1999 .master_state_change = qca8k_master_change, 2000 .connect_tag_protocol = qca8k_connect_tag_protocol, 2001 }; 2002 2003 static int 2004 qca8k_sw_probe(struct mdio_device *mdiodev) 2005 { 2006 struct qca8k_priv *priv; 2007 int ret; 2008 2009 /* allocate the private data struct so that we can probe the switches 2010 * ID register 2011 */ 2012 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 2013 if (!priv) 2014 return -ENOMEM; 2015 2016 priv->bus = mdiodev->bus; 2017 priv->dev = &mdiodev->dev; 2018 priv->info = of_device_get_match_data(priv->dev); 2019 2020 priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset", 2021 GPIOD_ASIS); 2022 if (IS_ERR(priv->reset_gpio)) 2023 return PTR_ERR(priv->reset_gpio); 2024 2025 if (priv->reset_gpio) { 2026 gpiod_set_value_cansleep(priv->reset_gpio, 1); 2027 /* The active low duration must be greater than 10 ms 2028 * and checkpatch.pl wants 20 ms. 2029 */ 2030 msleep(20); 2031 gpiod_set_value_cansleep(priv->reset_gpio, 0); 2032 } 2033 2034 /* Start by setting up the register mapping */ 2035 priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv, 2036 &qca8k_regmap_config); 2037 if (IS_ERR(priv->regmap)) { 2038 dev_err(priv->dev, "regmap initialization failed"); 2039 return PTR_ERR(priv->regmap); 2040 } 2041 2042 priv->mdio_cache.page = 0xffff; 2043 2044 /* Check the detected switch id */ 2045 ret = qca8k_read_switch_id(priv); 2046 if (ret) 2047 return ret; 2048 2049 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 2050 if (!priv->ds) 2051 return -ENOMEM; 2052 2053 mutex_init(&priv->mgmt_eth_data.mutex); 2054 init_completion(&priv->mgmt_eth_data.rw_done); 2055 2056 mutex_init(&priv->mib_eth_data.mutex); 2057 init_completion(&priv->mib_eth_data.rw_done); 2058 2059 priv->ds->dev = &mdiodev->dev; 2060 priv->ds->num_ports = QCA8K_NUM_PORTS; 2061 priv->ds->priv = priv; 2062 priv->ds->ops = &qca8k_switch_ops; 2063 mutex_init(&priv->reg_mutex); 2064 dev_set_drvdata(&mdiodev->dev, priv); 2065 2066 return dsa_register_switch(priv->ds); 2067 } 2068 2069 static void 2070 qca8k_sw_remove(struct mdio_device *mdiodev) 2071 { 2072 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev); 2073 int i; 2074 2075 if (!priv) 2076 return; 2077 2078 for (i = 0; i < QCA8K_NUM_PORTS; i++) 2079 qca8k_port_set_status(priv, i, 0); 2080 2081 dsa_unregister_switch(priv->ds); 2082 } 2083 2084 static void qca8k_sw_shutdown(struct mdio_device *mdiodev) 2085 { 2086 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev); 2087 2088 if (!priv) 2089 return; 2090 2091 dsa_switch_shutdown(priv->ds); 2092 2093 dev_set_drvdata(&mdiodev->dev, NULL); 2094 } 2095 2096 #ifdef CONFIG_PM_SLEEP 2097 static void 2098 qca8k_set_pm(struct qca8k_priv *priv, int enable) 2099 { 2100 int port; 2101 2102 for (port = 0; port < QCA8K_NUM_PORTS; port++) { 2103 /* Do not enable on resume if the port was 2104 * disabled before. 2105 */ 2106 if (!(priv->port_enabled_map & BIT(port))) 2107 continue; 2108 2109 qca8k_port_set_status(priv, port, enable); 2110 } 2111 } 2112 2113 static int qca8k_suspend(struct device *dev) 2114 { 2115 struct qca8k_priv *priv = dev_get_drvdata(dev); 2116 2117 qca8k_set_pm(priv, 0); 2118 2119 return dsa_switch_suspend(priv->ds); 2120 } 2121 2122 static int qca8k_resume(struct device *dev) 2123 { 2124 struct qca8k_priv *priv = dev_get_drvdata(dev); 2125 2126 qca8k_set_pm(priv, 1); 2127 2128 return dsa_switch_resume(priv->ds); 2129 } 2130 #endif /* CONFIG_PM_SLEEP */ 2131 2132 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops, 2133 qca8k_suspend, qca8k_resume); 2134 2135 static const struct qca8k_info_ops qca8xxx_ops = { 2136 .autocast_mib = qca8k_get_ethtool_stats_eth, 2137 }; 2138 2139 static const struct qca8k_match_data qca8327 = { 2140 .id = QCA8K_ID_QCA8327, 2141 .reduced_package = true, 2142 .mib_count = QCA8K_QCA832X_MIB_COUNT, 2143 .ops = &qca8xxx_ops, 2144 }; 2145 2146 static const struct qca8k_match_data qca8328 = { 2147 .id = QCA8K_ID_QCA8327, 2148 .mib_count = QCA8K_QCA832X_MIB_COUNT, 2149 .ops = &qca8xxx_ops, 2150 }; 2151 2152 static const struct qca8k_match_data qca833x = { 2153 .id = QCA8K_ID_QCA8337, 2154 .mib_count = QCA8K_QCA833X_MIB_COUNT, 2155 .ops = &qca8xxx_ops, 2156 }; 2157 2158 static const struct of_device_id qca8k_of_match[] = { 2159 { .compatible = "qca,qca8327", .data = &qca8327 }, 2160 { .compatible = "qca,qca8328", .data = &qca8328 }, 2161 { .compatible = "qca,qca8334", .data = &qca833x }, 2162 { .compatible = "qca,qca8337", .data = &qca833x }, 2163 { /* sentinel */ }, 2164 }; 2165 2166 static struct mdio_driver qca8kmdio_driver = { 2167 .probe = qca8k_sw_probe, 2168 .remove = qca8k_sw_remove, 2169 .shutdown = qca8k_sw_shutdown, 2170 .mdiodrv.driver = { 2171 .name = "qca8k", 2172 .of_match_table = qca8k_of_match, 2173 .pm = &qca8k_pm_ops, 2174 }, 2175 }; 2176 2177 mdio_module_driver(qca8kmdio_driver); 2178 2179 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>"); 2180 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family"); 2181 MODULE_LICENSE("GPL v2"); 2182 MODULE_ALIAS("platform:qca8k"); 2183