1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2019 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> 3 /* 4 * +----------------------+ 5 * GMAC1----RGMII----|--MAC0 | 6 * \---MDIO1----|--REGs |----MDIO3----\ 7 * | | | +------+ 8 * | | +--| | 9 * | MAC1-|----RMII--M-----| PHY0 |-o P0 10 * | | | | +------+ 11 * | | | +--| | 12 * | MAC2-|----RMII--------| PHY1 |-o P1 13 * | | | | +------+ 14 * | | | +--| | 15 * | MAC3-|----RMII--------| PHY2 |-o P2 16 * | | | | +------+ 17 * | | | +--| | 18 * | MAC4-|----RMII--------| PHY3 |-o P3 19 * | | | | +------+ 20 * | | | +--| | 21 * | MAC5-|--+-RMII--M-----|-PHY4-|-o P4 22 * | | | | +------+ 23 * +----------------------+ | \--CFG_SW_PHY_SWAP 24 * GMAC0---------------RMII--------------------/ \-CFG_SW_PHY_ADDR_SWAP 25 * \---MDIO0--NC 26 * 27 * GMAC0 and MAC5 are connected together and use same PHY. Depending on 28 * configuration it can be PHY4 (default) or PHY0. Only GMAC0 or MAC5 can be 29 * used at same time. If GMAC0 is used (default) then MAC5 should be disabled. 30 * 31 * CFG_SW_PHY_SWAP - swap connections of PHY0 and PHY4. If this bit is not set 32 * PHY4 is connected to GMAC0/MAC5 bundle and PHY0 is connected to MAC1. If this 33 * bit is set, PHY4 is connected to MAC1 and PHY0 is connected to GMAC0/MAC5 34 * bundle. 35 * 36 * CFG_SW_PHY_ADDR_SWAP - swap addresses of PHY0 and PHY4 37 * 38 * CFG_SW_PHY_SWAP and CFG_SW_PHY_ADDR_SWAP are part of SoC specific register 39 * set and not related to switch internal registers. 40 */ 41 42 #include <linux/bitfield.h> 43 #include <linux/module.h> 44 #include <linux/of_irq.h> 45 #include <linux/of_mdio.h> 46 #include <linux/regmap.h> 47 #include <linux/reset.h> 48 #include <net/dsa.h> 49 50 #define AR9331_SW_NAME "ar9331_switch" 51 #define AR9331_SW_PORTS 6 52 53 /* dummy reg to change page */ 54 #define AR9331_SW_REG_PAGE 0x40000 55 56 /* Global Interrupt */ 57 #define AR9331_SW_REG_GINT 0x10 58 #define AR9331_SW_REG_GINT_MASK 0x14 59 #define AR9331_SW_GINT_PHY_INT BIT(2) 60 61 #define AR9331_SW_REG_FLOOD_MASK 0x2c 62 #define AR9331_SW_FLOOD_MASK_BROAD_TO_CPU BIT(26) 63 64 #define AR9331_SW_REG_GLOBAL_CTRL 0x30 65 #define AR9331_SW_GLOBAL_CTRL_MFS_M GENMASK(13, 0) 66 67 #define AR9331_SW_REG_MDIO_CTRL 0x98 68 #define AR9331_SW_MDIO_CTRL_BUSY BIT(31) 69 #define AR9331_SW_MDIO_CTRL_MASTER_EN BIT(30) 70 #define AR9331_SW_MDIO_CTRL_CMD_READ BIT(27) 71 #define AR9331_SW_MDIO_CTRL_PHY_ADDR_M GENMASK(25, 21) 72 #define AR9331_SW_MDIO_CTRL_REG_ADDR_M GENMASK(20, 16) 73 #define AR9331_SW_MDIO_CTRL_DATA_M GENMASK(16, 0) 74 75 #define AR9331_SW_REG_PORT_STATUS(_port) (0x100 + (_port) * 0x100) 76 77 /* FLOW_LINK_EN - enable mac flow control config auto-neg with phy. 78 * If not set, mac can be config by software. 79 */ 80 #define AR9331_SW_PORT_STATUS_FLOW_LINK_EN BIT(12) 81 82 /* LINK_EN - If set, MAC is configured from PHY link status. 83 * If not set, MAC should be configured by software. 84 */ 85 #define AR9331_SW_PORT_STATUS_LINK_EN BIT(9) 86 #define AR9331_SW_PORT_STATUS_DUPLEX_MODE BIT(6) 87 #define AR9331_SW_PORT_STATUS_RX_FLOW_EN BIT(5) 88 #define AR9331_SW_PORT_STATUS_TX_FLOW_EN BIT(4) 89 #define AR9331_SW_PORT_STATUS_RXMAC BIT(3) 90 #define AR9331_SW_PORT_STATUS_TXMAC BIT(2) 91 #define AR9331_SW_PORT_STATUS_SPEED_M GENMASK(1, 0) 92 #define AR9331_SW_PORT_STATUS_SPEED_1000 2 93 #define AR9331_SW_PORT_STATUS_SPEED_100 1 94 #define AR9331_SW_PORT_STATUS_SPEED_10 0 95 96 #define AR9331_SW_PORT_STATUS_MAC_MASK \ 97 (AR9331_SW_PORT_STATUS_TXMAC | AR9331_SW_PORT_STATUS_RXMAC) 98 99 #define AR9331_SW_PORT_STATUS_LINK_MASK \ 100 (AR9331_SW_PORT_STATUS_LINK_EN | AR9331_SW_PORT_STATUS_FLOW_LINK_EN | \ 101 AR9331_SW_PORT_STATUS_DUPLEX_MODE | \ 102 AR9331_SW_PORT_STATUS_RX_FLOW_EN | AR9331_SW_PORT_STATUS_TX_FLOW_EN | \ 103 AR9331_SW_PORT_STATUS_SPEED_M) 104 105 /* Phy bypass mode 106 * ------------------------------------------------------------------------ 107 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 | 108 * 109 * real | start | OP | PhyAddr | Reg Addr | TA | 110 * atheros| start | OP | 2'b00 |PhyAdd[2:0]| Reg Addr[4:0] | TA | 111 * 112 * 113 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 | 114 * real | Data | 115 * atheros| Data | 116 * 117 * ------------------------------------------------------------------------ 118 * Page address mode 119 * ------------------------------------------------------------------------ 120 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 | 121 * real | start | OP | PhyAddr | Reg Addr | TA | 122 * atheros| start | OP | 2'b11 | 8'b0 | TA | 123 * 124 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 | 125 * real | Data | 126 * atheros| | Page [9:0] | 127 */ 128 /* In case of Page Address mode, Bit[18:9] of 32 bit register address should be 129 * written to bits[9:0] of mdio data register. 130 */ 131 #define AR9331_SW_ADDR_PAGE GENMASK(18, 9) 132 133 /* ------------------------------------------------------------------------ 134 * Normal register access mode 135 * ------------------------------------------------------------------------ 136 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 | 137 * real | start | OP | PhyAddr | Reg Addr | TA | 138 * atheros| start | OP | 2'b10 | low_addr[7:0] | TA | 139 * 140 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 | 141 * real | Data | 142 * atheros| Data | 143 * ------------------------------------------------------------------------ 144 */ 145 #define AR9331_SW_LOW_ADDR_PHY GENMASK(8, 6) 146 #define AR9331_SW_LOW_ADDR_REG GENMASK(5, 1) 147 148 #define AR9331_SW_MDIO_PHY_MODE_M GENMASK(4, 3) 149 #define AR9331_SW_MDIO_PHY_MODE_PAGE 3 150 #define AR9331_SW_MDIO_PHY_MODE_REG 2 151 #define AR9331_SW_MDIO_PHY_MODE_BYPASS 0 152 #define AR9331_SW_MDIO_PHY_ADDR_M GENMASK(2, 0) 153 154 /* Empirical determined values */ 155 #define AR9331_SW_MDIO_POLL_SLEEP_US 1 156 #define AR9331_SW_MDIO_POLL_TIMEOUT_US 20 157 158 struct ar9331_sw_priv { 159 struct device *dev; 160 struct dsa_switch ds; 161 struct dsa_switch_ops ops; 162 struct irq_domain *irqdomain; 163 struct mii_bus *mbus; /* mdio master */ 164 struct mii_bus *sbus; /* mdio slave */ 165 struct regmap *regmap; 166 struct reset_control *sw_reset; 167 }; 168 169 /* Warning: switch reset will reset last AR9331_SW_MDIO_PHY_MODE_PAGE request 170 * If some kind of optimization is used, the request should be repeated. 171 */ 172 static int ar9331_sw_reset(struct ar9331_sw_priv *priv) 173 { 174 int ret; 175 176 ret = reset_control_assert(priv->sw_reset); 177 if (ret) 178 goto error; 179 180 /* AR9331 doc do not provide any information about proper reset 181 * sequence. The AR8136 (the closes switch to the AR9331) doc says: 182 * reset duration should be greater than 10ms. So, let's use this value 183 * for now. 184 */ 185 usleep_range(10000, 15000); 186 ret = reset_control_deassert(priv->sw_reset); 187 if (ret) 188 goto error; 189 /* There is no information on how long should we wait after reset. 190 * AR8136 has an EEPROM and there is an Interrupt for EEPROM load 191 * status. AR9331 has no EEPROM support. 192 * For now, do not wait. In case AR8136 will be needed, the after 193 * reset delay can be added as well. 194 */ 195 196 return 0; 197 error: 198 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 199 return ret; 200 } 201 202 static int ar9331_sw_mbus_write(struct mii_bus *mbus, int port, int regnum, 203 u16 data) 204 { 205 struct ar9331_sw_priv *priv = mbus->priv; 206 struct regmap *regmap = priv->regmap; 207 u32 val; 208 int ret; 209 210 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL, 211 AR9331_SW_MDIO_CTRL_BUSY | 212 AR9331_SW_MDIO_CTRL_MASTER_EN | 213 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) | 214 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum) | 215 FIELD_PREP(AR9331_SW_MDIO_CTRL_DATA_M, data)); 216 if (ret) 217 goto error; 218 219 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val, 220 !(val & AR9331_SW_MDIO_CTRL_BUSY), 221 AR9331_SW_MDIO_POLL_SLEEP_US, 222 AR9331_SW_MDIO_POLL_TIMEOUT_US); 223 if (ret) 224 goto error; 225 226 return 0; 227 error: 228 dev_err_ratelimited(priv->dev, "PHY write error: %i\n", ret); 229 return ret; 230 } 231 232 static int ar9331_sw_mbus_read(struct mii_bus *mbus, int port, int regnum) 233 { 234 struct ar9331_sw_priv *priv = mbus->priv; 235 struct regmap *regmap = priv->regmap; 236 u32 val; 237 int ret; 238 239 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL, 240 AR9331_SW_MDIO_CTRL_BUSY | 241 AR9331_SW_MDIO_CTRL_MASTER_EN | 242 AR9331_SW_MDIO_CTRL_CMD_READ | 243 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) | 244 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum)); 245 if (ret) 246 goto error; 247 248 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val, 249 !(val & AR9331_SW_MDIO_CTRL_BUSY), 250 AR9331_SW_MDIO_POLL_SLEEP_US, 251 AR9331_SW_MDIO_POLL_TIMEOUT_US); 252 if (ret) 253 goto error; 254 255 ret = regmap_read(regmap, AR9331_SW_REG_MDIO_CTRL, &val); 256 if (ret) 257 goto error; 258 259 return FIELD_GET(AR9331_SW_MDIO_CTRL_DATA_M, val); 260 261 error: 262 dev_err_ratelimited(priv->dev, "PHY read error: %i\n", ret); 263 return ret; 264 } 265 266 static int ar9331_sw_mbus_init(struct ar9331_sw_priv *priv) 267 { 268 struct device *dev = priv->dev; 269 struct mii_bus *mbus; 270 struct device_node *np, *mnp; 271 int ret; 272 273 np = dev->of_node; 274 275 mbus = devm_mdiobus_alloc(dev); 276 if (!mbus) 277 return -ENOMEM; 278 279 mbus->name = np->full_name; 280 snprintf(mbus->id, MII_BUS_ID_SIZE, "%pOF", np); 281 282 mbus->read = ar9331_sw_mbus_read; 283 mbus->write = ar9331_sw_mbus_write; 284 mbus->priv = priv; 285 mbus->parent = dev; 286 287 mnp = of_get_child_by_name(np, "mdio"); 288 if (!mnp) 289 return -ENODEV; 290 291 ret = of_mdiobus_register(mbus, mnp); 292 of_node_put(mnp); 293 if (ret) 294 return ret; 295 296 priv->mbus = mbus; 297 298 return 0; 299 } 300 301 static int ar9331_sw_setup(struct dsa_switch *ds) 302 { 303 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; 304 struct regmap *regmap = priv->regmap; 305 int ret; 306 307 ret = ar9331_sw_reset(priv); 308 if (ret) 309 return ret; 310 311 /* Reset will set proper defaults. CPU - Port0 will be enabled and 312 * configured. All other ports (ports 1 - 5) are disabled 313 */ 314 ret = ar9331_sw_mbus_init(priv); 315 if (ret) 316 return ret; 317 318 /* Do not drop broadcast frames */ 319 ret = regmap_write_bits(regmap, AR9331_SW_REG_FLOOD_MASK, 320 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU, 321 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU); 322 if (ret) 323 goto error; 324 325 /* Set max frame size to the maximum supported value */ 326 ret = regmap_write_bits(regmap, AR9331_SW_REG_GLOBAL_CTRL, 327 AR9331_SW_GLOBAL_CTRL_MFS_M, 328 AR9331_SW_GLOBAL_CTRL_MFS_M); 329 if (ret) 330 goto error; 331 332 return 0; 333 error: 334 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 335 return ret; 336 } 337 338 static void ar9331_sw_port_disable(struct dsa_switch *ds, int port) 339 { 340 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; 341 struct regmap *regmap = priv->regmap; 342 int ret; 343 344 ret = regmap_write(regmap, AR9331_SW_REG_PORT_STATUS(port), 0); 345 if (ret) 346 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 347 } 348 349 static enum dsa_tag_protocol ar9331_sw_get_tag_protocol(struct dsa_switch *ds, 350 int port, 351 enum dsa_tag_protocol m) 352 { 353 return DSA_TAG_PROTO_AR9331; 354 } 355 356 static void ar9331_sw_phylink_validate(struct dsa_switch *ds, int port, 357 unsigned long *supported, 358 struct phylink_link_state *state) 359 { 360 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 361 362 switch (port) { 363 case 0: 364 if (state->interface != PHY_INTERFACE_MODE_GMII) 365 goto unsupported; 366 367 phylink_set(mask, 1000baseT_Full); 368 phylink_set(mask, 1000baseT_Half); 369 break; 370 case 1: 371 case 2: 372 case 3: 373 case 4: 374 case 5: 375 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) 376 goto unsupported; 377 break; 378 default: 379 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 380 dev_err(ds->dev, "Unsupported port: %i\n", port); 381 return; 382 } 383 384 phylink_set_port_modes(mask); 385 phylink_set(mask, Pause); 386 phylink_set(mask, Asym_Pause); 387 388 phylink_set(mask, 10baseT_Half); 389 phylink_set(mask, 10baseT_Full); 390 phylink_set(mask, 100baseT_Half); 391 phylink_set(mask, 100baseT_Full); 392 393 bitmap_and(supported, supported, mask, 394 __ETHTOOL_LINK_MODE_MASK_NBITS); 395 bitmap_and(state->advertising, state->advertising, mask, 396 __ETHTOOL_LINK_MODE_MASK_NBITS); 397 398 return; 399 400 unsupported: 401 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 402 dev_err(ds->dev, "Unsupported interface: %d, port: %d\n", 403 state->interface, port); 404 } 405 406 static void ar9331_sw_phylink_mac_config(struct dsa_switch *ds, int port, 407 unsigned int mode, 408 const struct phylink_link_state *state) 409 { 410 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; 411 struct regmap *regmap = priv->regmap; 412 int ret; 413 u32 val; 414 415 switch (state->speed) { 416 case SPEED_1000: 417 val = AR9331_SW_PORT_STATUS_SPEED_1000; 418 break; 419 case SPEED_100: 420 val = AR9331_SW_PORT_STATUS_SPEED_100; 421 break; 422 case SPEED_10: 423 val = AR9331_SW_PORT_STATUS_SPEED_10; 424 break; 425 default: 426 return; 427 } 428 429 if (state->duplex) 430 val |= AR9331_SW_PORT_STATUS_DUPLEX_MODE; 431 432 if (state->pause & MLO_PAUSE_TX) 433 val |= AR9331_SW_PORT_STATUS_TX_FLOW_EN; 434 435 if (state->pause & MLO_PAUSE_RX) 436 val |= AR9331_SW_PORT_STATUS_RX_FLOW_EN; 437 438 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port), 439 AR9331_SW_PORT_STATUS_LINK_MASK, val); 440 if (ret) 441 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 442 } 443 444 static void ar9331_sw_phylink_mac_link_down(struct dsa_switch *ds, int port, 445 unsigned int mode, 446 phy_interface_t interface) 447 { 448 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; 449 struct regmap *regmap = priv->regmap; 450 int ret; 451 452 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port), 453 AR9331_SW_PORT_STATUS_MAC_MASK, 0); 454 if (ret) 455 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 456 } 457 458 static void ar9331_sw_phylink_mac_link_up(struct dsa_switch *ds, int port, 459 unsigned int mode, 460 phy_interface_t interface, 461 struct phy_device *phydev) 462 { 463 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; 464 struct regmap *regmap = priv->regmap; 465 int ret; 466 467 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port), 468 AR9331_SW_PORT_STATUS_MAC_MASK, 469 AR9331_SW_PORT_STATUS_MAC_MASK); 470 if (ret) 471 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 472 } 473 474 static const struct dsa_switch_ops ar9331_sw_ops = { 475 .get_tag_protocol = ar9331_sw_get_tag_protocol, 476 .setup = ar9331_sw_setup, 477 .port_disable = ar9331_sw_port_disable, 478 .phylink_validate = ar9331_sw_phylink_validate, 479 .phylink_mac_config = ar9331_sw_phylink_mac_config, 480 .phylink_mac_link_down = ar9331_sw_phylink_mac_link_down, 481 .phylink_mac_link_up = ar9331_sw_phylink_mac_link_up, 482 }; 483 484 static irqreturn_t ar9331_sw_irq(int irq, void *data) 485 { 486 struct ar9331_sw_priv *priv = data; 487 struct regmap *regmap = priv->regmap; 488 u32 stat; 489 int ret; 490 491 ret = regmap_read(regmap, AR9331_SW_REG_GINT, &stat); 492 if (ret) { 493 dev_err(priv->dev, "can't read interrupt status\n"); 494 return IRQ_NONE; 495 } 496 497 if (!stat) 498 return IRQ_NONE; 499 500 if (stat & AR9331_SW_GINT_PHY_INT) { 501 int child_irq; 502 503 child_irq = irq_find_mapping(priv->irqdomain, 0); 504 handle_nested_irq(child_irq); 505 } 506 507 ret = regmap_write(regmap, AR9331_SW_REG_GINT, stat); 508 if (ret) { 509 dev_err(priv->dev, "can't write interrupt status\n"); 510 return IRQ_NONE; 511 } 512 513 return IRQ_HANDLED; 514 } 515 516 static void ar9331_sw_mask_irq(struct irq_data *d) 517 { 518 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d); 519 struct regmap *regmap = priv->regmap; 520 int ret; 521 522 ret = regmap_update_bits(regmap, AR9331_SW_REG_GINT_MASK, 523 AR9331_SW_GINT_PHY_INT, 0); 524 if (ret) 525 dev_err(priv->dev, "could not mask IRQ\n"); 526 } 527 528 static void ar9331_sw_unmask_irq(struct irq_data *d) 529 { 530 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d); 531 struct regmap *regmap = priv->regmap; 532 int ret; 533 534 ret = regmap_update_bits(regmap, AR9331_SW_REG_GINT_MASK, 535 AR9331_SW_GINT_PHY_INT, 536 AR9331_SW_GINT_PHY_INT); 537 if (ret) 538 dev_err(priv->dev, "could not unmask IRQ\n"); 539 } 540 541 static struct irq_chip ar9331_sw_irq_chip = { 542 .name = AR9331_SW_NAME, 543 .irq_mask = ar9331_sw_mask_irq, 544 .irq_unmask = ar9331_sw_unmask_irq, 545 }; 546 547 static int ar9331_sw_irq_map(struct irq_domain *domain, unsigned int irq, 548 irq_hw_number_t hwirq) 549 { 550 irq_set_chip_data(irq, domain->host_data); 551 irq_set_chip_and_handler(irq, &ar9331_sw_irq_chip, handle_simple_irq); 552 irq_set_nested_thread(irq, 1); 553 irq_set_noprobe(irq); 554 555 return 0; 556 } 557 558 static void ar9331_sw_irq_unmap(struct irq_domain *d, unsigned int irq) 559 { 560 irq_set_nested_thread(irq, 0); 561 irq_set_chip_and_handler(irq, NULL, NULL); 562 irq_set_chip_data(irq, NULL); 563 } 564 565 static const struct irq_domain_ops ar9331_sw_irqdomain_ops = { 566 .map = ar9331_sw_irq_map, 567 .unmap = ar9331_sw_irq_unmap, 568 .xlate = irq_domain_xlate_onecell, 569 }; 570 571 static int ar9331_sw_irq_init(struct ar9331_sw_priv *priv) 572 { 573 struct device_node *np = priv->dev->of_node; 574 struct device *dev = priv->dev; 575 int ret, irq; 576 577 irq = of_irq_get(np, 0); 578 if (irq <= 0) { 579 dev_err(dev, "failed to get parent IRQ\n"); 580 return irq ? irq : -EINVAL; 581 } 582 583 ret = devm_request_threaded_irq(dev, irq, NULL, ar9331_sw_irq, 584 IRQF_ONESHOT, AR9331_SW_NAME, priv); 585 if (ret) { 586 dev_err(dev, "unable to request irq: %d\n", ret); 587 return ret; 588 } 589 590 priv->irqdomain = irq_domain_add_linear(np, 1, &ar9331_sw_irqdomain_ops, 591 priv); 592 if (!priv->irqdomain) { 593 dev_err(dev, "failed to create IRQ domain\n"); 594 return -EINVAL; 595 } 596 597 irq_set_parent(irq_create_mapping(priv->irqdomain, 0), irq); 598 599 return 0; 600 } 601 602 static int __ar9331_mdio_write(struct mii_bus *sbus, u8 mode, u16 reg, u16 val) 603 { 604 u8 r, p; 605 606 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, mode) | 607 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg); 608 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg); 609 610 return mdiobus_write(sbus, p, r, val); 611 } 612 613 static int __ar9331_mdio_read(struct mii_bus *sbus, u16 reg) 614 { 615 u8 r, p; 616 617 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, AR9331_SW_MDIO_PHY_MODE_REG) | 618 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg); 619 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg); 620 621 return mdiobus_read(sbus, p, r); 622 } 623 624 static int ar9331_mdio_read(void *ctx, const void *reg_buf, size_t reg_len, 625 void *val_buf, size_t val_len) 626 { 627 struct ar9331_sw_priv *priv = ctx; 628 struct mii_bus *sbus = priv->sbus; 629 u32 reg = *(u32 *)reg_buf; 630 int ret; 631 632 if (reg == AR9331_SW_REG_PAGE) { 633 /* We cannot read the page selector register from hardware and 634 * we cache its value in regmap. Return all bits set here, 635 * that regmap will always write the page on first use. 636 */ 637 *(u32 *)val_buf = GENMASK(9, 0); 638 return 0; 639 } 640 641 ret = __ar9331_mdio_read(sbus, reg); 642 if (ret < 0) 643 goto error; 644 645 *(u32 *)val_buf = ret; 646 ret = __ar9331_mdio_read(sbus, reg + 2); 647 if (ret < 0) 648 goto error; 649 650 *(u32 *)val_buf |= ret << 16; 651 652 return 0; 653 error: 654 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to read register.\n"); 655 return ret; 656 } 657 658 static int ar9331_mdio_write(void *ctx, u32 reg, u32 val) 659 { 660 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ctx; 661 struct mii_bus *sbus = priv->sbus; 662 int ret; 663 664 if (reg == AR9331_SW_REG_PAGE) { 665 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_PAGE, 666 0, val); 667 if (ret < 0) 668 goto error; 669 670 return 0; 671 } 672 673 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg, val); 674 if (ret < 0) 675 goto error; 676 677 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg + 2, 678 val >> 16); 679 if (ret < 0) 680 goto error; 681 682 return 0; 683 error: 684 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n"); 685 return ret; 686 } 687 688 static int ar9331_sw_bus_write(void *context, const void *data, size_t count) 689 { 690 u32 reg = *(u32 *)data; 691 u32 val = *((u32 *)data + 1); 692 693 return ar9331_mdio_write(context, reg, val); 694 } 695 696 static const struct regmap_range ar9331_valid_regs[] = { 697 regmap_reg_range(0x0, 0x0), 698 regmap_reg_range(0x10, 0x14), 699 regmap_reg_range(0x20, 0x24), 700 regmap_reg_range(0x2c, 0x30), 701 regmap_reg_range(0x40, 0x44), 702 regmap_reg_range(0x50, 0x78), 703 regmap_reg_range(0x80, 0x98), 704 705 regmap_reg_range(0x100, 0x120), 706 regmap_reg_range(0x200, 0x220), 707 regmap_reg_range(0x300, 0x320), 708 regmap_reg_range(0x400, 0x420), 709 regmap_reg_range(0x500, 0x520), 710 regmap_reg_range(0x600, 0x620), 711 712 regmap_reg_range(0x20000, 0x200a4), 713 regmap_reg_range(0x20100, 0x201a4), 714 regmap_reg_range(0x20200, 0x202a4), 715 regmap_reg_range(0x20300, 0x203a4), 716 regmap_reg_range(0x20400, 0x204a4), 717 regmap_reg_range(0x20500, 0x205a4), 718 719 /* dummy page selector reg */ 720 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE), 721 }; 722 723 static const struct regmap_range ar9331_nonvolatile_regs[] = { 724 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE), 725 }; 726 727 static const struct regmap_range_cfg ar9331_regmap_range[] = { 728 { 729 .selector_reg = AR9331_SW_REG_PAGE, 730 .selector_mask = GENMASK(9, 0), 731 .selector_shift = 0, 732 733 .window_start = 0, 734 .window_len = 512, 735 736 .range_min = 0, 737 .range_max = AR9331_SW_REG_PAGE - 4, 738 }, 739 }; 740 741 static const struct regmap_access_table ar9331_register_set = { 742 .yes_ranges = ar9331_valid_regs, 743 .n_yes_ranges = ARRAY_SIZE(ar9331_valid_regs), 744 }; 745 746 static const struct regmap_access_table ar9331_volatile_set = { 747 .no_ranges = ar9331_nonvolatile_regs, 748 .n_no_ranges = ARRAY_SIZE(ar9331_nonvolatile_regs), 749 }; 750 751 static const struct regmap_config ar9331_mdio_regmap_config = { 752 .reg_bits = 32, 753 .val_bits = 32, 754 .reg_stride = 4, 755 .max_register = AR9331_SW_REG_PAGE, 756 757 .ranges = ar9331_regmap_range, 758 .num_ranges = ARRAY_SIZE(ar9331_regmap_range), 759 760 .volatile_table = &ar9331_volatile_set, 761 .wr_table = &ar9331_register_set, 762 .rd_table = &ar9331_register_set, 763 764 .cache_type = REGCACHE_RBTREE, 765 }; 766 767 static struct regmap_bus ar9331_sw_bus = { 768 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, 769 .val_format_endian_default = REGMAP_ENDIAN_NATIVE, 770 .read = ar9331_mdio_read, 771 .write = ar9331_sw_bus_write, 772 .max_raw_read = 4, 773 .max_raw_write = 4, 774 }; 775 776 static int ar9331_sw_probe(struct mdio_device *mdiodev) 777 { 778 struct ar9331_sw_priv *priv; 779 struct dsa_switch *ds; 780 int ret; 781 782 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 783 if (!priv) 784 return -ENOMEM; 785 786 priv->regmap = devm_regmap_init(&mdiodev->dev, &ar9331_sw_bus, priv, 787 &ar9331_mdio_regmap_config); 788 if (IS_ERR(priv->regmap)) { 789 ret = PTR_ERR(priv->regmap); 790 dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret); 791 return ret; 792 } 793 794 priv->sw_reset = devm_reset_control_get(&mdiodev->dev, "switch"); 795 if (IS_ERR(priv->sw_reset)) { 796 dev_err(&mdiodev->dev, "missing switch reset\n"); 797 return PTR_ERR(priv->sw_reset); 798 } 799 800 priv->sbus = mdiodev->bus; 801 priv->dev = &mdiodev->dev; 802 803 ret = ar9331_sw_irq_init(priv); 804 if (ret) 805 return ret; 806 807 ds = &priv->ds; 808 ds->dev = &mdiodev->dev; 809 ds->num_ports = AR9331_SW_PORTS; 810 ds->priv = priv; 811 priv->ops = ar9331_sw_ops; 812 ds->ops = &priv->ops; 813 dev_set_drvdata(&mdiodev->dev, priv); 814 815 ret = dsa_register_switch(ds); 816 if (ret) 817 goto err_remove_irq; 818 819 return 0; 820 821 err_remove_irq: 822 irq_domain_remove(priv->irqdomain); 823 824 return ret; 825 } 826 827 static void ar9331_sw_remove(struct mdio_device *mdiodev) 828 { 829 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev); 830 831 irq_domain_remove(priv->irqdomain); 832 mdiobus_unregister(priv->mbus); 833 dsa_unregister_switch(&priv->ds); 834 835 reset_control_assert(priv->sw_reset); 836 } 837 838 static const struct of_device_id ar9331_sw_of_match[] = { 839 { .compatible = "qca,ar9331-switch" }, 840 { }, 841 }; 842 843 static struct mdio_driver ar9331_sw_mdio_driver = { 844 .probe = ar9331_sw_probe, 845 .remove = ar9331_sw_remove, 846 .mdiodrv.driver = { 847 .name = AR9331_SW_NAME, 848 .of_match_table = ar9331_sw_of_match, 849 }, 850 }; 851 852 mdio_module_driver(ar9331_sw_mdio_driver); 853 854 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>"); 855 MODULE_DESCRIPTION("Driver for Atheros AR9331 switch"); 856 MODULE_LICENSE("GPL v2"); 857