1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2019 Pengutronix, Oleksij Rempel <kernel@pengutronix.de> 3 /* 4 * +----------------------+ 5 * GMAC1----RGMII----|--MAC0 | 6 * \---MDIO1----|--REGs |----MDIO3----\ 7 * | | | +------+ 8 * | | +--| | 9 * | MAC1-|----RMII--M-----| PHY0 |-o P0 10 * | | | | +------+ 11 * | | | +--| | 12 * | MAC2-|----RMII--------| PHY1 |-o P1 13 * | | | | +------+ 14 * | | | +--| | 15 * | MAC3-|----RMII--------| PHY2 |-o P2 16 * | | | | +------+ 17 * | | | +--| | 18 * | MAC4-|----RMII--------| PHY3 |-o P3 19 * | | | | +------+ 20 * | | | +--| | 21 * | MAC5-|--+-RMII--M-----|-PHY4-|-o P4 22 * | | | | +------+ 23 * +----------------------+ | \--CFG_SW_PHY_SWAP 24 * GMAC0---------------RMII--------------------/ \-CFG_SW_PHY_ADDR_SWAP 25 * \---MDIO0--NC 26 * 27 * GMAC0 and MAC5 are connected together and use same PHY. Depending on 28 * configuration it can be PHY4 (default) or PHY0. Only GMAC0 or MAC5 can be 29 * used at same time. If GMAC0 is used (default) then MAC5 should be disabled. 30 * 31 * CFG_SW_PHY_SWAP - swap connections of PHY0 and PHY4. If this bit is not set 32 * PHY4 is connected to GMAC0/MAC5 bundle and PHY0 is connected to MAC1. If this 33 * bit is set, PHY4 is connected to MAC1 and PHY0 is connected to GMAC0/MAC5 34 * bundle. 35 * 36 * CFG_SW_PHY_ADDR_SWAP - swap addresses of PHY0 and PHY4 37 * 38 * CFG_SW_PHY_SWAP and CFG_SW_PHY_ADDR_SWAP are part of SoC specific register 39 * set and not related to switch internal registers. 40 */ 41 42 #include <linux/bitfield.h> 43 #include <linux/module.h> 44 #include <linux/of_irq.h> 45 #include <linux/of_mdio.h> 46 #include <linux/regmap.h> 47 #include <linux/reset.h> 48 #include <net/dsa.h> 49 50 #define AR9331_SW_NAME "ar9331_switch" 51 #define AR9331_SW_PORTS 6 52 53 /* dummy reg to change page */ 54 #define AR9331_SW_REG_PAGE 0x40000 55 56 /* Global Interrupt */ 57 #define AR9331_SW_REG_GINT 0x10 58 #define AR9331_SW_REG_GINT_MASK 0x14 59 #define AR9331_SW_GINT_PHY_INT BIT(2) 60 61 #define AR9331_SW_REG_FLOOD_MASK 0x2c 62 #define AR9331_SW_FLOOD_MASK_BROAD_TO_CPU BIT(26) 63 64 #define AR9331_SW_REG_GLOBAL_CTRL 0x30 65 #define AR9331_SW_GLOBAL_CTRL_MFS_M GENMASK(13, 0) 66 67 #define AR9331_SW_REG_MDIO_CTRL 0x98 68 #define AR9331_SW_MDIO_CTRL_BUSY BIT(31) 69 #define AR9331_SW_MDIO_CTRL_MASTER_EN BIT(30) 70 #define AR9331_SW_MDIO_CTRL_CMD_READ BIT(27) 71 #define AR9331_SW_MDIO_CTRL_PHY_ADDR_M GENMASK(25, 21) 72 #define AR9331_SW_MDIO_CTRL_REG_ADDR_M GENMASK(20, 16) 73 #define AR9331_SW_MDIO_CTRL_DATA_M GENMASK(16, 0) 74 75 #define AR9331_SW_REG_PORT_STATUS(_port) (0x100 + (_port) * 0x100) 76 77 /* FLOW_LINK_EN - enable mac flow control config auto-neg with phy. 78 * If not set, mac can be config by software. 79 */ 80 #define AR9331_SW_PORT_STATUS_FLOW_LINK_EN BIT(12) 81 82 /* LINK_EN - If set, MAC is configured from PHY link status. 83 * If not set, MAC should be configured by software. 84 */ 85 #define AR9331_SW_PORT_STATUS_LINK_EN BIT(9) 86 #define AR9331_SW_PORT_STATUS_DUPLEX_MODE BIT(6) 87 #define AR9331_SW_PORT_STATUS_RX_FLOW_EN BIT(5) 88 #define AR9331_SW_PORT_STATUS_TX_FLOW_EN BIT(4) 89 #define AR9331_SW_PORT_STATUS_RXMAC BIT(3) 90 #define AR9331_SW_PORT_STATUS_TXMAC BIT(2) 91 #define AR9331_SW_PORT_STATUS_SPEED_M GENMASK(1, 0) 92 #define AR9331_SW_PORT_STATUS_SPEED_1000 2 93 #define AR9331_SW_PORT_STATUS_SPEED_100 1 94 #define AR9331_SW_PORT_STATUS_SPEED_10 0 95 96 #define AR9331_SW_PORT_STATUS_MAC_MASK \ 97 (AR9331_SW_PORT_STATUS_TXMAC | AR9331_SW_PORT_STATUS_RXMAC) 98 99 #define AR9331_SW_PORT_STATUS_LINK_MASK \ 100 (AR9331_SW_PORT_STATUS_DUPLEX_MODE | \ 101 AR9331_SW_PORT_STATUS_RX_FLOW_EN | AR9331_SW_PORT_STATUS_TX_FLOW_EN | \ 102 AR9331_SW_PORT_STATUS_SPEED_M) 103 104 /* Phy bypass mode 105 * ------------------------------------------------------------------------ 106 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 | 107 * 108 * real | start | OP | PhyAddr | Reg Addr | TA | 109 * atheros| start | OP | 2'b00 |PhyAdd[2:0]| Reg Addr[4:0] | TA | 110 * 111 * 112 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 | 113 * real | Data | 114 * atheros| Data | 115 * 116 * ------------------------------------------------------------------------ 117 * Page address mode 118 * ------------------------------------------------------------------------ 119 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 | 120 * real | start | OP | PhyAddr | Reg Addr | TA | 121 * atheros| start | OP | 2'b11 | 8'b0 | TA | 122 * 123 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 | 124 * real | Data | 125 * atheros| | Page [9:0] | 126 */ 127 /* In case of Page Address mode, Bit[18:9] of 32 bit register address should be 128 * written to bits[9:0] of mdio data register. 129 */ 130 #define AR9331_SW_ADDR_PAGE GENMASK(18, 9) 131 132 /* ------------------------------------------------------------------------ 133 * Normal register access mode 134 * ------------------------------------------------------------------------ 135 * Bit: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |14 |15 | 136 * real | start | OP | PhyAddr | Reg Addr | TA | 137 * atheros| start | OP | 2'b10 | low_addr[7:0] | TA | 138 * 139 * Bit: |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |31 | 140 * real | Data | 141 * atheros| Data | 142 * ------------------------------------------------------------------------ 143 */ 144 #define AR9331_SW_LOW_ADDR_PHY GENMASK(8, 6) 145 #define AR9331_SW_LOW_ADDR_REG GENMASK(5, 1) 146 147 #define AR9331_SW_MDIO_PHY_MODE_M GENMASK(4, 3) 148 #define AR9331_SW_MDIO_PHY_MODE_PAGE 3 149 #define AR9331_SW_MDIO_PHY_MODE_REG 2 150 #define AR9331_SW_MDIO_PHY_MODE_BYPASS 0 151 #define AR9331_SW_MDIO_PHY_ADDR_M GENMASK(2, 0) 152 153 /* Empirical determined values */ 154 #define AR9331_SW_MDIO_POLL_SLEEP_US 1 155 #define AR9331_SW_MDIO_POLL_TIMEOUT_US 20 156 157 struct ar9331_sw_priv { 158 struct device *dev; 159 struct dsa_switch ds; 160 struct dsa_switch_ops ops; 161 struct irq_domain *irqdomain; 162 struct mii_bus *mbus; /* mdio master */ 163 struct mii_bus *sbus; /* mdio slave */ 164 struct regmap *regmap; 165 struct reset_control *sw_reset; 166 }; 167 168 /* Warning: switch reset will reset last AR9331_SW_MDIO_PHY_MODE_PAGE request 169 * If some kind of optimization is used, the request should be repeated. 170 */ 171 static int ar9331_sw_reset(struct ar9331_sw_priv *priv) 172 { 173 int ret; 174 175 ret = reset_control_assert(priv->sw_reset); 176 if (ret) 177 goto error; 178 179 /* AR9331 doc do not provide any information about proper reset 180 * sequence. The AR8136 (the closes switch to the AR9331) doc says: 181 * reset duration should be greater than 10ms. So, let's use this value 182 * for now. 183 */ 184 usleep_range(10000, 15000); 185 ret = reset_control_deassert(priv->sw_reset); 186 if (ret) 187 goto error; 188 /* There is no information on how long should we wait after reset. 189 * AR8136 has an EEPROM and there is an Interrupt for EEPROM load 190 * status. AR9331 has no EEPROM support. 191 * For now, do not wait. In case AR8136 will be needed, the after 192 * reset delay can be added as well. 193 */ 194 195 return 0; 196 error: 197 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 198 return ret; 199 } 200 201 static int ar9331_sw_mbus_write(struct mii_bus *mbus, int port, int regnum, 202 u16 data) 203 { 204 struct ar9331_sw_priv *priv = mbus->priv; 205 struct regmap *regmap = priv->regmap; 206 u32 val; 207 int ret; 208 209 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL, 210 AR9331_SW_MDIO_CTRL_BUSY | 211 AR9331_SW_MDIO_CTRL_MASTER_EN | 212 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) | 213 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum) | 214 FIELD_PREP(AR9331_SW_MDIO_CTRL_DATA_M, data)); 215 if (ret) 216 goto error; 217 218 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val, 219 !(val & AR9331_SW_MDIO_CTRL_BUSY), 220 AR9331_SW_MDIO_POLL_SLEEP_US, 221 AR9331_SW_MDIO_POLL_TIMEOUT_US); 222 if (ret) 223 goto error; 224 225 return 0; 226 error: 227 dev_err_ratelimited(priv->dev, "PHY write error: %i\n", ret); 228 return ret; 229 } 230 231 static int ar9331_sw_mbus_read(struct mii_bus *mbus, int port, int regnum) 232 { 233 struct ar9331_sw_priv *priv = mbus->priv; 234 struct regmap *regmap = priv->regmap; 235 u32 val; 236 int ret; 237 238 ret = regmap_write(regmap, AR9331_SW_REG_MDIO_CTRL, 239 AR9331_SW_MDIO_CTRL_BUSY | 240 AR9331_SW_MDIO_CTRL_MASTER_EN | 241 AR9331_SW_MDIO_CTRL_CMD_READ | 242 FIELD_PREP(AR9331_SW_MDIO_CTRL_PHY_ADDR_M, port) | 243 FIELD_PREP(AR9331_SW_MDIO_CTRL_REG_ADDR_M, regnum)); 244 if (ret) 245 goto error; 246 247 ret = regmap_read_poll_timeout(regmap, AR9331_SW_REG_MDIO_CTRL, val, 248 !(val & AR9331_SW_MDIO_CTRL_BUSY), 249 AR9331_SW_MDIO_POLL_SLEEP_US, 250 AR9331_SW_MDIO_POLL_TIMEOUT_US); 251 if (ret) 252 goto error; 253 254 ret = regmap_read(regmap, AR9331_SW_REG_MDIO_CTRL, &val); 255 if (ret) 256 goto error; 257 258 return FIELD_GET(AR9331_SW_MDIO_CTRL_DATA_M, val); 259 260 error: 261 dev_err_ratelimited(priv->dev, "PHY read error: %i\n", ret); 262 return ret; 263 } 264 265 static int ar9331_sw_mbus_init(struct ar9331_sw_priv *priv) 266 { 267 struct device *dev = priv->dev; 268 struct mii_bus *mbus; 269 struct device_node *np, *mnp; 270 int ret; 271 272 np = dev->of_node; 273 274 mbus = devm_mdiobus_alloc(dev); 275 if (!mbus) 276 return -ENOMEM; 277 278 mbus->name = np->full_name; 279 snprintf(mbus->id, MII_BUS_ID_SIZE, "%pOF", np); 280 281 mbus->read = ar9331_sw_mbus_read; 282 mbus->write = ar9331_sw_mbus_write; 283 mbus->priv = priv; 284 mbus->parent = dev; 285 286 mnp = of_get_child_by_name(np, "mdio"); 287 if (!mnp) 288 return -ENODEV; 289 290 ret = of_mdiobus_register(mbus, mnp); 291 of_node_put(mnp); 292 if (ret) 293 return ret; 294 295 priv->mbus = mbus; 296 297 return 0; 298 } 299 300 static int ar9331_sw_setup(struct dsa_switch *ds) 301 { 302 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; 303 struct regmap *regmap = priv->regmap; 304 int ret; 305 306 ret = ar9331_sw_reset(priv); 307 if (ret) 308 return ret; 309 310 /* Reset will set proper defaults. CPU - Port0 will be enabled and 311 * configured. All other ports (ports 1 - 5) are disabled 312 */ 313 ret = ar9331_sw_mbus_init(priv); 314 if (ret) 315 return ret; 316 317 /* Do not drop broadcast frames */ 318 ret = regmap_write_bits(regmap, AR9331_SW_REG_FLOOD_MASK, 319 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU, 320 AR9331_SW_FLOOD_MASK_BROAD_TO_CPU); 321 if (ret) 322 goto error; 323 324 /* Set max frame size to the maximum supported value */ 325 ret = regmap_write_bits(regmap, AR9331_SW_REG_GLOBAL_CTRL, 326 AR9331_SW_GLOBAL_CTRL_MFS_M, 327 AR9331_SW_GLOBAL_CTRL_MFS_M); 328 if (ret) 329 goto error; 330 331 return 0; 332 error: 333 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 334 return ret; 335 } 336 337 static void ar9331_sw_port_disable(struct dsa_switch *ds, int port) 338 { 339 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; 340 struct regmap *regmap = priv->regmap; 341 int ret; 342 343 ret = regmap_write(regmap, AR9331_SW_REG_PORT_STATUS(port), 0); 344 if (ret) 345 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 346 } 347 348 static enum dsa_tag_protocol ar9331_sw_get_tag_protocol(struct dsa_switch *ds, 349 int port, 350 enum dsa_tag_protocol m) 351 { 352 return DSA_TAG_PROTO_AR9331; 353 } 354 355 static void ar9331_sw_phylink_validate(struct dsa_switch *ds, int port, 356 unsigned long *supported, 357 struct phylink_link_state *state) 358 { 359 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 360 361 switch (port) { 362 case 0: 363 if (state->interface != PHY_INTERFACE_MODE_GMII) 364 goto unsupported; 365 366 phylink_set(mask, 1000baseT_Full); 367 phylink_set(mask, 1000baseT_Half); 368 break; 369 case 1: 370 case 2: 371 case 3: 372 case 4: 373 case 5: 374 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) 375 goto unsupported; 376 break; 377 default: 378 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 379 dev_err(ds->dev, "Unsupported port: %i\n", port); 380 return; 381 } 382 383 phylink_set_port_modes(mask); 384 phylink_set(mask, Pause); 385 phylink_set(mask, Asym_Pause); 386 387 phylink_set(mask, 10baseT_Half); 388 phylink_set(mask, 10baseT_Full); 389 phylink_set(mask, 100baseT_Half); 390 phylink_set(mask, 100baseT_Full); 391 392 bitmap_and(supported, supported, mask, 393 __ETHTOOL_LINK_MODE_MASK_NBITS); 394 bitmap_and(state->advertising, state->advertising, mask, 395 __ETHTOOL_LINK_MODE_MASK_NBITS); 396 397 return; 398 399 unsupported: 400 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 401 dev_err(ds->dev, "Unsupported interface: %d, port: %d\n", 402 state->interface, port); 403 } 404 405 static void ar9331_sw_phylink_mac_config(struct dsa_switch *ds, int port, 406 unsigned int mode, 407 const struct phylink_link_state *state) 408 { 409 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; 410 struct regmap *regmap = priv->regmap; 411 int ret; 412 413 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port), 414 AR9331_SW_PORT_STATUS_LINK_EN | 415 AR9331_SW_PORT_STATUS_FLOW_LINK_EN, 0); 416 if (ret) 417 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 418 } 419 420 static void ar9331_sw_phylink_mac_link_down(struct dsa_switch *ds, int port, 421 unsigned int mode, 422 phy_interface_t interface) 423 { 424 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; 425 struct regmap *regmap = priv->regmap; 426 int ret; 427 428 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port), 429 AR9331_SW_PORT_STATUS_MAC_MASK, 0); 430 if (ret) 431 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 432 } 433 434 static void ar9331_sw_phylink_mac_link_up(struct dsa_switch *ds, int port, 435 unsigned int mode, 436 phy_interface_t interface, 437 struct phy_device *phydev, 438 int speed, int duplex, 439 bool tx_pause, bool rx_pause) 440 { 441 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; 442 struct regmap *regmap = priv->regmap; 443 u32 val; 444 int ret; 445 446 val = AR9331_SW_PORT_STATUS_MAC_MASK; 447 switch (speed) { 448 case SPEED_1000: 449 val |= AR9331_SW_PORT_STATUS_SPEED_1000; 450 break; 451 case SPEED_100: 452 val |= AR9331_SW_PORT_STATUS_SPEED_100; 453 break; 454 case SPEED_10: 455 val |= AR9331_SW_PORT_STATUS_SPEED_10; 456 break; 457 default: 458 return; 459 } 460 461 if (duplex) 462 val |= AR9331_SW_PORT_STATUS_DUPLEX_MODE; 463 464 if (tx_pause) 465 val |= AR9331_SW_PORT_STATUS_TX_FLOW_EN; 466 467 if (rx_pause) 468 val |= AR9331_SW_PORT_STATUS_RX_FLOW_EN; 469 470 ret = regmap_update_bits(regmap, AR9331_SW_REG_PORT_STATUS(port), 471 AR9331_SW_PORT_STATUS_MAC_MASK | 472 AR9331_SW_PORT_STATUS_LINK_MASK, 473 val); 474 if (ret) 475 dev_err_ratelimited(priv->dev, "%s: %i\n", __func__, ret); 476 } 477 478 static const struct dsa_switch_ops ar9331_sw_ops = { 479 .get_tag_protocol = ar9331_sw_get_tag_protocol, 480 .setup = ar9331_sw_setup, 481 .port_disable = ar9331_sw_port_disable, 482 .phylink_validate = ar9331_sw_phylink_validate, 483 .phylink_mac_config = ar9331_sw_phylink_mac_config, 484 .phylink_mac_link_down = ar9331_sw_phylink_mac_link_down, 485 .phylink_mac_link_up = ar9331_sw_phylink_mac_link_up, 486 }; 487 488 static irqreturn_t ar9331_sw_irq(int irq, void *data) 489 { 490 struct ar9331_sw_priv *priv = data; 491 struct regmap *regmap = priv->regmap; 492 u32 stat; 493 int ret; 494 495 ret = regmap_read(regmap, AR9331_SW_REG_GINT, &stat); 496 if (ret) { 497 dev_err(priv->dev, "can't read interrupt status\n"); 498 return IRQ_NONE; 499 } 500 501 if (!stat) 502 return IRQ_NONE; 503 504 if (stat & AR9331_SW_GINT_PHY_INT) { 505 int child_irq; 506 507 child_irq = irq_find_mapping(priv->irqdomain, 0); 508 handle_nested_irq(child_irq); 509 } 510 511 ret = regmap_write(regmap, AR9331_SW_REG_GINT, stat); 512 if (ret) { 513 dev_err(priv->dev, "can't write interrupt status\n"); 514 return IRQ_NONE; 515 } 516 517 return IRQ_HANDLED; 518 } 519 520 static void ar9331_sw_mask_irq(struct irq_data *d) 521 { 522 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d); 523 struct regmap *regmap = priv->regmap; 524 int ret; 525 526 ret = regmap_update_bits(regmap, AR9331_SW_REG_GINT_MASK, 527 AR9331_SW_GINT_PHY_INT, 0); 528 if (ret) 529 dev_err(priv->dev, "could not mask IRQ\n"); 530 } 531 532 static void ar9331_sw_unmask_irq(struct irq_data *d) 533 { 534 struct ar9331_sw_priv *priv = irq_data_get_irq_chip_data(d); 535 struct regmap *regmap = priv->regmap; 536 int ret; 537 538 ret = regmap_update_bits(regmap, AR9331_SW_REG_GINT_MASK, 539 AR9331_SW_GINT_PHY_INT, 540 AR9331_SW_GINT_PHY_INT); 541 if (ret) 542 dev_err(priv->dev, "could not unmask IRQ\n"); 543 } 544 545 static struct irq_chip ar9331_sw_irq_chip = { 546 .name = AR9331_SW_NAME, 547 .irq_mask = ar9331_sw_mask_irq, 548 .irq_unmask = ar9331_sw_unmask_irq, 549 }; 550 551 static int ar9331_sw_irq_map(struct irq_domain *domain, unsigned int irq, 552 irq_hw_number_t hwirq) 553 { 554 irq_set_chip_data(irq, domain->host_data); 555 irq_set_chip_and_handler(irq, &ar9331_sw_irq_chip, handle_simple_irq); 556 irq_set_nested_thread(irq, 1); 557 irq_set_noprobe(irq); 558 559 return 0; 560 } 561 562 static void ar9331_sw_irq_unmap(struct irq_domain *d, unsigned int irq) 563 { 564 irq_set_nested_thread(irq, 0); 565 irq_set_chip_and_handler(irq, NULL, NULL); 566 irq_set_chip_data(irq, NULL); 567 } 568 569 static const struct irq_domain_ops ar9331_sw_irqdomain_ops = { 570 .map = ar9331_sw_irq_map, 571 .unmap = ar9331_sw_irq_unmap, 572 .xlate = irq_domain_xlate_onecell, 573 }; 574 575 static int ar9331_sw_irq_init(struct ar9331_sw_priv *priv) 576 { 577 struct device_node *np = priv->dev->of_node; 578 struct device *dev = priv->dev; 579 int ret, irq; 580 581 irq = of_irq_get(np, 0); 582 if (irq <= 0) { 583 dev_err(dev, "failed to get parent IRQ\n"); 584 return irq ? irq : -EINVAL; 585 } 586 587 ret = devm_request_threaded_irq(dev, irq, NULL, ar9331_sw_irq, 588 IRQF_ONESHOT, AR9331_SW_NAME, priv); 589 if (ret) { 590 dev_err(dev, "unable to request irq: %d\n", ret); 591 return ret; 592 } 593 594 priv->irqdomain = irq_domain_add_linear(np, 1, &ar9331_sw_irqdomain_ops, 595 priv); 596 if (!priv->irqdomain) { 597 dev_err(dev, "failed to create IRQ domain\n"); 598 return -EINVAL; 599 } 600 601 irq_set_parent(irq_create_mapping(priv->irqdomain, 0), irq); 602 603 return 0; 604 } 605 606 static int __ar9331_mdio_write(struct mii_bus *sbus, u8 mode, u16 reg, u16 val) 607 { 608 u8 r, p; 609 610 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, mode) | 611 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg); 612 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg); 613 614 return mdiobus_write(sbus, p, r, val); 615 } 616 617 static int __ar9331_mdio_read(struct mii_bus *sbus, u16 reg) 618 { 619 u8 r, p; 620 621 p = FIELD_PREP(AR9331_SW_MDIO_PHY_MODE_M, AR9331_SW_MDIO_PHY_MODE_REG) | 622 FIELD_GET(AR9331_SW_LOW_ADDR_PHY, reg); 623 r = FIELD_GET(AR9331_SW_LOW_ADDR_REG, reg); 624 625 return mdiobus_read(sbus, p, r); 626 } 627 628 static int ar9331_mdio_read(void *ctx, const void *reg_buf, size_t reg_len, 629 void *val_buf, size_t val_len) 630 { 631 struct ar9331_sw_priv *priv = ctx; 632 struct mii_bus *sbus = priv->sbus; 633 u32 reg = *(u32 *)reg_buf; 634 int ret; 635 636 if (reg == AR9331_SW_REG_PAGE) { 637 /* We cannot read the page selector register from hardware and 638 * we cache its value in regmap. Return all bits set here, 639 * that regmap will always write the page on first use. 640 */ 641 *(u32 *)val_buf = GENMASK(9, 0); 642 return 0; 643 } 644 645 ret = __ar9331_mdio_read(sbus, reg); 646 if (ret < 0) 647 goto error; 648 649 *(u32 *)val_buf = ret; 650 ret = __ar9331_mdio_read(sbus, reg + 2); 651 if (ret < 0) 652 goto error; 653 654 *(u32 *)val_buf |= ret << 16; 655 656 return 0; 657 error: 658 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to read register.\n"); 659 return ret; 660 } 661 662 static int ar9331_mdio_write(void *ctx, u32 reg, u32 val) 663 { 664 struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ctx; 665 struct mii_bus *sbus = priv->sbus; 666 int ret; 667 668 if (reg == AR9331_SW_REG_PAGE) { 669 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_PAGE, 670 0, val); 671 if (ret < 0) 672 goto error; 673 674 return 0; 675 } 676 677 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg, val); 678 if (ret < 0) 679 goto error; 680 681 ret = __ar9331_mdio_write(sbus, AR9331_SW_MDIO_PHY_MODE_REG, reg + 2, 682 val >> 16); 683 if (ret < 0) 684 goto error; 685 686 return 0; 687 error: 688 dev_err_ratelimited(&sbus->dev, "Bus error. Failed to write register.\n"); 689 return ret; 690 } 691 692 static int ar9331_sw_bus_write(void *context, const void *data, size_t count) 693 { 694 u32 reg = *(u32 *)data; 695 u32 val = *((u32 *)data + 1); 696 697 return ar9331_mdio_write(context, reg, val); 698 } 699 700 static const struct regmap_range ar9331_valid_regs[] = { 701 regmap_reg_range(0x0, 0x0), 702 regmap_reg_range(0x10, 0x14), 703 regmap_reg_range(0x20, 0x24), 704 regmap_reg_range(0x2c, 0x30), 705 regmap_reg_range(0x40, 0x44), 706 regmap_reg_range(0x50, 0x78), 707 regmap_reg_range(0x80, 0x98), 708 709 regmap_reg_range(0x100, 0x120), 710 regmap_reg_range(0x200, 0x220), 711 regmap_reg_range(0x300, 0x320), 712 regmap_reg_range(0x400, 0x420), 713 regmap_reg_range(0x500, 0x520), 714 regmap_reg_range(0x600, 0x620), 715 716 regmap_reg_range(0x20000, 0x200a4), 717 regmap_reg_range(0x20100, 0x201a4), 718 regmap_reg_range(0x20200, 0x202a4), 719 regmap_reg_range(0x20300, 0x203a4), 720 regmap_reg_range(0x20400, 0x204a4), 721 regmap_reg_range(0x20500, 0x205a4), 722 723 /* dummy page selector reg */ 724 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE), 725 }; 726 727 static const struct regmap_range ar9331_nonvolatile_regs[] = { 728 regmap_reg_range(AR9331_SW_REG_PAGE, AR9331_SW_REG_PAGE), 729 }; 730 731 static const struct regmap_range_cfg ar9331_regmap_range[] = { 732 { 733 .selector_reg = AR9331_SW_REG_PAGE, 734 .selector_mask = GENMASK(9, 0), 735 .selector_shift = 0, 736 737 .window_start = 0, 738 .window_len = 512, 739 740 .range_min = 0, 741 .range_max = AR9331_SW_REG_PAGE - 4, 742 }, 743 }; 744 745 static const struct regmap_access_table ar9331_register_set = { 746 .yes_ranges = ar9331_valid_regs, 747 .n_yes_ranges = ARRAY_SIZE(ar9331_valid_regs), 748 }; 749 750 static const struct regmap_access_table ar9331_volatile_set = { 751 .no_ranges = ar9331_nonvolatile_regs, 752 .n_no_ranges = ARRAY_SIZE(ar9331_nonvolatile_regs), 753 }; 754 755 static const struct regmap_config ar9331_mdio_regmap_config = { 756 .reg_bits = 32, 757 .val_bits = 32, 758 .reg_stride = 4, 759 .max_register = AR9331_SW_REG_PAGE, 760 761 .ranges = ar9331_regmap_range, 762 .num_ranges = ARRAY_SIZE(ar9331_regmap_range), 763 764 .volatile_table = &ar9331_volatile_set, 765 .wr_table = &ar9331_register_set, 766 .rd_table = &ar9331_register_set, 767 768 .cache_type = REGCACHE_RBTREE, 769 }; 770 771 static struct regmap_bus ar9331_sw_bus = { 772 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE, 773 .val_format_endian_default = REGMAP_ENDIAN_NATIVE, 774 .read = ar9331_mdio_read, 775 .write = ar9331_sw_bus_write, 776 .max_raw_read = 4, 777 .max_raw_write = 4, 778 }; 779 780 static int ar9331_sw_probe(struct mdio_device *mdiodev) 781 { 782 struct ar9331_sw_priv *priv; 783 struct dsa_switch *ds; 784 int ret; 785 786 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 787 if (!priv) 788 return -ENOMEM; 789 790 priv->regmap = devm_regmap_init(&mdiodev->dev, &ar9331_sw_bus, priv, 791 &ar9331_mdio_regmap_config); 792 if (IS_ERR(priv->regmap)) { 793 ret = PTR_ERR(priv->regmap); 794 dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret); 795 return ret; 796 } 797 798 priv->sw_reset = devm_reset_control_get(&mdiodev->dev, "switch"); 799 if (IS_ERR(priv->sw_reset)) { 800 dev_err(&mdiodev->dev, "missing switch reset\n"); 801 return PTR_ERR(priv->sw_reset); 802 } 803 804 priv->sbus = mdiodev->bus; 805 priv->dev = &mdiodev->dev; 806 807 ret = ar9331_sw_irq_init(priv); 808 if (ret) 809 return ret; 810 811 ds = &priv->ds; 812 ds->dev = &mdiodev->dev; 813 ds->num_ports = AR9331_SW_PORTS; 814 ds->priv = priv; 815 priv->ops = ar9331_sw_ops; 816 ds->ops = &priv->ops; 817 dev_set_drvdata(&mdiodev->dev, priv); 818 819 ret = dsa_register_switch(ds); 820 if (ret) 821 goto err_remove_irq; 822 823 return 0; 824 825 err_remove_irq: 826 irq_domain_remove(priv->irqdomain); 827 828 return ret; 829 } 830 831 static void ar9331_sw_remove(struct mdio_device *mdiodev) 832 { 833 struct ar9331_sw_priv *priv = dev_get_drvdata(&mdiodev->dev); 834 835 irq_domain_remove(priv->irqdomain); 836 mdiobus_unregister(priv->mbus); 837 dsa_unregister_switch(&priv->ds); 838 839 reset_control_assert(priv->sw_reset); 840 } 841 842 static const struct of_device_id ar9331_sw_of_match[] = { 843 { .compatible = "qca,ar9331-switch" }, 844 { }, 845 }; 846 847 static struct mdio_driver ar9331_sw_mdio_driver = { 848 .probe = ar9331_sw_probe, 849 .remove = ar9331_sw_remove, 850 .mdiodrv.driver = { 851 .name = AR9331_SW_NAME, 852 .of_match_table = ar9331_sw_of_match, 853 }, 854 }; 855 856 mdio_module_driver(ar9331_sw_mdio_driver); 857 858 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>"); 859 MODULE_DESCRIPTION("Driver for Atheros AR9331 switch"); 860 MODULE_LICENSE("GPL v2"); 861