1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Distributed Switch Architecture VSC9953 driver
3  * Copyright (C) 2020, Maxim Kochetkov <fido_max@inbox.ru>
4  */
5 #include <linux/types.h>
6 #include <soc/mscc/ocelot_vcap.h>
7 #include <soc/mscc/ocelot_sys.h>
8 #include <soc/mscc/ocelot.h>
9 #include <linux/mdio/mdio-mscc-miim.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_platform.h>
12 #include <linux/pcs-lynx.h>
13 #include <linux/dsa/ocelot.h>
14 #include <linux/iopoll.h>
15 #include "felix.h"
16 
17 #define VSC9953_NUM_PORTS			10
18 
19 #define VSC9953_VCAP_POLICER_BASE		11
20 #define VSC9953_VCAP_POLICER_MAX		31
21 #define VSC9953_VCAP_POLICER_BASE2		120
22 #define VSC9953_VCAP_POLICER_MAX2		161
23 
24 #define VSC9953_PORT_MODE_SERDES		(OCELOT_PORT_MODE_1000BASEX | \
25 						 OCELOT_PORT_MODE_SGMII | \
26 						 OCELOT_PORT_MODE_QSGMII)
27 
28 static const u32 vsc9953_port_modes[VSC9953_NUM_PORTS] = {
29 	VSC9953_PORT_MODE_SERDES,
30 	VSC9953_PORT_MODE_SERDES,
31 	VSC9953_PORT_MODE_SERDES,
32 	VSC9953_PORT_MODE_SERDES,
33 	VSC9953_PORT_MODE_SERDES,
34 	VSC9953_PORT_MODE_SERDES,
35 	VSC9953_PORT_MODE_SERDES,
36 	VSC9953_PORT_MODE_SERDES,
37 	OCELOT_PORT_MODE_INTERNAL,
38 	OCELOT_PORT_MODE_INTERNAL,
39 };
40 
41 static const u32 vsc9953_ana_regmap[] = {
42 	REG(ANA_ADVLEARN,			0x00b500),
43 	REG(ANA_VLANMASK,			0x00b504),
44 	REG_RESERVED(ANA_PORT_B_DOMAIN),
45 	REG(ANA_ANAGEFIL,			0x00b50c),
46 	REG(ANA_ANEVENTS,			0x00b510),
47 	REG(ANA_STORMLIMIT_BURST,		0x00b514),
48 	REG(ANA_STORMLIMIT_CFG,			0x00b518),
49 	REG(ANA_ISOLATED_PORTS,			0x00b528),
50 	REG(ANA_COMMUNITY_PORTS,		0x00b52c),
51 	REG(ANA_AUTOAGE,			0x00b530),
52 	REG(ANA_MACTOPTIONS,			0x00b534),
53 	REG(ANA_LEARNDISC,			0x00b538),
54 	REG(ANA_AGENCTRL,			0x00b53c),
55 	REG(ANA_MIRRORPORTS,			0x00b540),
56 	REG(ANA_EMIRRORPORTS,			0x00b544),
57 	REG(ANA_FLOODING,			0x00b548),
58 	REG(ANA_FLOODING_IPMC,			0x00b54c),
59 	REG(ANA_SFLOW_CFG,			0x00b550),
60 	REG(ANA_PORT_MODE,			0x00b57c),
61 	REG_RESERVED(ANA_CUT_THRU_CFG),
62 	REG(ANA_PGID_PGID,			0x00b600),
63 	REG(ANA_TABLES_ANMOVED,			0x00b4ac),
64 	REG(ANA_TABLES_MACHDATA,		0x00b4b0),
65 	REG(ANA_TABLES_MACLDATA,		0x00b4b4),
66 	REG_RESERVED(ANA_TABLES_STREAMDATA),
67 	REG(ANA_TABLES_MACACCESS,		0x00b4b8),
68 	REG(ANA_TABLES_MACTINDX,		0x00b4bc),
69 	REG(ANA_TABLES_VLANACCESS,		0x00b4c0),
70 	REG(ANA_TABLES_VLANTIDX,		0x00b4c4),
71 	REG_RESERVED(ANA_TABLES_ISDXACCESS),
72 	REG_RESERVED(ANA_TABLES_ISDXTIDX),
73 	REG(ANA_TABLES_ENTRYLIM,		0x00b480),
74 	REG_RESERVED(ANA_TABLES_PTP_ID_HIGH),
75 	REG_RESERVED(ANA_TABLES_PTP_ID_LOW),
76 	REG_RESERVED(ANA_TABLES_STREAMACCESS),
77 	REG_RESERVED(ANA_TABLES_STREAMTIDX),
78 	REG_RESERVED(ANA_TABLES_SEQ_HISTORY),
79 	REG_RESERVED(ANA_TABLES_SEQ_MASK),
80 	REG_RESERVED(ANA_TABLES_SFID_MASK),
81 	REG_RESERVED(ANA_TABLES_SFIDACCESS),
82 	REG_RESERVED(ANA_TABLES_SFIDTIDX),
83 	REG_RESERVED(ANA_MSTI_STATE),
84 	REG_RESERVED(ANA_OAM_UPM_LM_CNT),
85 	REG_RESERVED(ANA_SG_ACCESS_CTRL),
86 	REG_RESERVED(ANA_SG_CONFIG_REG_1),
87 	REG_RESERVED(ANA_SG_CONFIG_REG_2),
88 	REG_RESERVED(ANA_SG_CONFIG_REG_3),
89 	REG_RESERVED(ANA_SG_CONFIG_REG_4),
90 	REG_RESERVED(ANA_SG_CONFIG_REG_5),
91 	REG_RESERVED(ANA_SG_GCL_GS_CONFIG),
92 	REG_RESERVED(ANA_SG_GCL_TI_CONFIG),
93 	REG_RESERVED(ANA_SG_STATUS_REG_1),
94 	REG_RESERVED(ANA_SG_STATUS_REG_2),
95 	REG_RESERVED(ANA_SG_STATUS_REG_3),
96 	REG(ANA_PORT_VLAN_CFG,			0x000000),
97 	REG(ANA_PORT_DROP_CFG,			0x000004),
98 	REG(ANA_PORT_QOS_CFG,			0x000008),
99 	REG(ANA_PORT_VCAP_CFG,			0x00000c),
100 	REG(ANA_PORT_VCAP_S1_KEY_CFG,		0x000010),
101 	REG(ANA_PORT_VCAP_S2_CFG,		0x00001c),
102 	REG(ANA_PORT_PCP_DEI_MAP,		0x000020),
103 	REG(ANA_PORT_CPU_FWD_CFG,		0x000060),
104 	REG(ANA_PORT_CPU_FWD_BPDU_CFG,		0x000064),
105 	REG(ANA_PORT_CPU_FWD_GARP_CFG,		0x000068),
106 	REG(ANA_PORT_CPU_FWD_CCM_CFG,		0x00006c),
107 	REG(ANA_PORT_PORT_CFG,			0x000070),
108 	REG(ANA_PORT_POL_CFG,			0x000074),
109 	REG_RESERVED(ANA_PORT_PTP_CFG),
110 	REG_RESERVED(ANA_PORT_PTP_DLY1_CFG),
111 	REG_RESERVED(ANA_PORT_PTP_DLY2_CFG),
112 	REG_RESERVED(ANA_PORT_SFID_CFG),
113 	REG(ANA_PFC_PFC_CFG,			0x00c000),
114 	REG_RESERVED(ANA_PFC_PFC_TIMER),
115 	REG_RESERVED(ANA_IPT_OAM_MEP_CFG),
116 	REG_RESERVED(ANA_IPT_IPT),
117 	REG_RESERVED(ANA_PPT_PPT),
118 	REG_RESERVED(ANA_FID_MAP_FID_MAP),
119 	REG(ANA_AGGR_CFG,			0x00c600),
120 	REG(ANA_CPUQ_CFG,			0x00c604),
121 	REG_RESERVED(ANA_CPUQ_CFG2),
122 	REG(ANA_CPUQ_8021_CFG,			0x00c60c),
123 	REG(ANA_DSCP_CFG,			0x00c64c),
124 	REG(ANA_DSCP_REWR_CFG,			0x00c74c),
125 	REG(ANA_VCAP_RNG_TYPE_CFG,		0x00c78c),
126 	REG(ANA_VCAP_RNG_VAL_CFG,		0x00c7ac),
127 	REG_RESERVED(ANA_VRAP_CFG),
128 	REG_RESERVED(ANA_VRAP_HDR_DATA),
129 	REG_RESERVED(ANA_VRAP_HDR_MASK),
130 	REG(ANA_DISCARD_CFG,			0x00c7d8),
131 	REG(ANA_FID_CFG,			0x00c7dc),
132 	REG(ANA_POL_PIR_CFG,			0x00a000),
133 	REG(ANA_POL_CIR_CFG,			0x00a004),
134 	REG(ANA_POL_MODE_CFG,			0x00a008),
135 	REG(ANA_POL_PIR_STATE,			0x00a00c),
136 	REG(ANA_POL_CIR_STATE,			0x00a010),
137 	REG_RESERVED(ANA_POL_STATE),
138 	REG(ANA_POL_FLOWC,			0x00c280),
139 	REG(ANA_POL_HYST,			0x00c2ec),
140 	REG_RESERVED(ANA_POL_MISC_CFG),
141 };
142 
143 static const u32 vsc9953_qs_regmap[] = {
144 	REG(QS_XTR_GRP_CFG,			0x000000),
145 	REG(QS_XTR_RD,				0x000008),
146 	REG(QS_XTR_FRM_PRUNING,			0x000010),
147 	REG(QS_XTR_FLUSH,			0x000018),
148 	REG(QS_XTR_DATA_PRESENT,		0x00001c),
149 	REG(QS_XTR_CFG,				0x000020),
150 	REG(QS_INJ_GRP_CFG,			0x000024),
151 	REG(QS_INJ_WR,				0x00002c),
152 	REG(QS_INJ_CTRL,			0x000034),
153 	REG(QS_INJ_STATUS,			0x00003c),
154 	REG(QS_INJ_ERR,				0x000040),
155 	REG_RESERVED(QS_INH_DBG),
156 };
157 
158 static const u32 vsc9953_vcap_regmap[] = {
159 	/* VCAP_CORE_CFG */
160 	REG(VCAP_CORE_UPDATE_CTRL,		0x000000),
161 	REG(VCAP_CORE_MV_CFG,			0x000004),
162 	/* VCAP_CORE_CACHE */
163 	REG(VCAP_CACHE_ENTRY_DAT,		0x000008),
164 	REG(VCAP_CACHE_MASK_DAT,		0x000108),
165 	REG(VCAP_CACHE_ACTION_DAT,		0x000208),
166 	REG(VCAP_CACHE_CNT_DAT,			0x000308),
167 	REG(VCAP_CACHE_TG_DAT,			0x000388),
168 	/* VCAP_CONST */
169 	REG(VCAP_CONST_VCAP_VER,		0x000398),
170 	REG(VCAP_CONST_ENTRY_WIDTH,		0x00039c),
171 	REG(VCAP_CONST_ENTRY_CNT,		0x0003a0),
172 	REG(VCAP_CONST_ENTRY_SWCNT,		0x0003a4),
173 	REG(VCAP_CONST_ENTRY_TG_WIDTH,		0x0003a8),
174 	REG(VCAP_CONST_ACTION_DEF_CNT,		0x0003ac),
175 	REG(VCAP_CONST_ACTION_WIDTH,		0x0003b0),
176 	REG(VCAP_CONST_CNT_WIDTH,		0x0003b4),
177 	REG_RESERVED(VCAP_CONST_CORE_CNT),
178 	REG_RESERVED(VCAP_CONST_IF_CNT),
179 };
180 
181 static const u32 vsc9953_qsys_regmap[] = {
182 	REG(QSYS_PORT_MODE,			0x003600),
183 	REG(QSYS_SWITCH_PORT_MODE,		0x003630),
184 	REG(QSYS_STAT_CNT_CFG,			0x00365c),
185 	REG(QSYS_EEE_CFG,			0x003660),
186 	REG(QSYS_EEE_THRES,			0x003688),
187 	REG(QSYS_IGR_NO_SHARING,		0x00368c),
188 	REG(QSYS_EGR_NO_SHARING,		0x003690),
189 	REG(QSYS_SW_STATUS,			0x003694),
190 	REG(QSYS_EXT_CPU_CFG,			0x0036c0),
191 	REG_RESERVED(QSYS_PAD_CFG),
192 	REG(QSYS_CPU_GROUP_MAP,			0x0036c8),
193 	REG_RESERVED(QSYS_QMAP),
194 	REG_RESERVED(QSYS_ISDX_SGRP),
195 	REG_RESERVED(QSYS_TIMED_FRAME_ENTRY),
196 	REG_RESERVED(QSYS_TFRM_MISC),
197 	REG_RESERVED(QSYS_TFRM_PORT_DLY),
198 	REG_RESERVED(QSYS_TFRM_TIMER_CFG_1),
199 	REG_RESERVED(QSYS_TFRM_TIMER_CFG_2),
200 	REG_RESERVED(QSYS_TFRM_TIMER_CFG_3),
201 	REG_RESERVED(QSYS_TFRM_TIMER_CFG_4),
202 	REG_RESERVED(QSYS_TFRM_TIMER_CFG_5),
203 	REG_RESERVED(QSYS_TFRM_TIMER_CFG_6),
204 	REG_RESERVED(QSYS_TFRM_TIMER_CFG_7),
205 	REG_RESERVED(QSYS_TFRM_TIMER_CFG_8),
206 	REG(QSYS_RED_PROFILE,			0x003724),
207 	REG(QSYS_RES_QOS_MODE,			0x003764),
208 	REG(QSYS_RES_CFG,			0x004000),
209 	REG(QSYS_RES_STAT,			0x004004),
210 	REG(QSYS_EGR_DROP_MODE,			0x003768),
211 	REG(QSYS_EQ_CTRL,			0x00376c),
212 	REG_RESERVED(QSYS_EVENTS_CORE),
213 	REG_RESERVED(QSYS_QMAXSDU_CFG_0),
214 	REG_RESERVED(QSYS_QMAXSDU_CFG_1),
215 	REG_RESERVED(QSYS_QMAXSDU_CFG_2),
216 	REG_RESERVED(QSYS_QMAXSDU_CFG_3),
217 	REG_RESERVED(QSYS_QMAXSDU_CFG_4),
218 	REG_RESERVED(QSYS_QMAXSDU_CFG_5),
219 	REG_RESERVED(QSYS_QMAXSDU_CFG_6),
220 	REG_RESERVED(QSYS_QMAXSDU_CFG_7),
221 	REG_RESERVED(QSYS_PREEMPTION_CFG),
222 	REG(QSYS_CIR_CFG,			0x000000),
223 	REG_RESERVED(QSYS_EIR_CFG),
224 	REG(QSYS_SE_CFG,			0x000008),
225 	REG(QSYS_SE_DWRR_CFG,			0x00000c),
226 	REG_RESERVED(QSYS_SE_CONNECT),
227 	REG_RESERVED(QSYS_SE_DLB_SENSE),
228 	REG(QSYS_CIR_STATE,			0x000044),
229 	REG_RESERVED(QSYS_EIR_STATE),
230 	REG_RESERVED(QSYS_SE_STATE),
231 	REG(QSYS_HSCH_MISC_CFG,			0x003774),
232 	REG_RESERVED(QSYS_TAG_CONFIG),
233 	REG_RESERVED(QSYS_TAS_PARAM_CFG_CTRL),
234 	REG_RESERVED(QSYS_PORT_MAX_SDU),
235 	REG_RESERVED(QSYS_PARAM_CFG_REG_1),
236 	REG_RESERVED(QSYS_PARAM_CFG_REG_2),
237 	REG_RESERVED(QSYS_PARAM_CFG_REG_3),
238 	REG_RESERVED(QSYS_PARAM_CFG_REG_4),
239 	REG_RESERVED(QSYS_PARAM_CFG_REG_5),
240 	REG_RESERVED(QSYS_GCL_CFG_REG_1),
241 	REG_RESERVED(QSYS_GCL_CFG_REG_2),
242 	REG_RESERVED(QSYS_PARAM_STATUS_REG_1),
243 	REG_RESERVED(QSYS_PARAM_STATUS_REG_2),
244 	REG_RESERVED(QSYS_PARAM_STATUS_REG_3),
245 	REG_RESERVED(QSYS_PARAM_STATUS_REG_4),
246 	REG_RESERVED(QSYS_PARAM_STATUS_REG_5),
247 	REG_RESERVED(QSYS_PARAM_STATUS_REG_6),
248 	REG_RESERVED(QSYS_PARAM_STATUS_REG_7),
249 	REG_RESERVED(QSYS_PARAM_STATUS_REG_8),
250 	REG_RESERVED(QSYS_PARAM_STATUS_REG_9),
251 	REG_RESERVED(QSYS_GCL_STATUS_REG_1),
252 	REG_RESERVED(QSYS_GCL_STATUS_REG_2),
253 };
254 
255 static const u32 vsc9953_rew_regmap[] = {
256 	REG(REW_PORT_VLAN_CFG,			0x000000),
257 	REG(REW_TAG_CFG,			0x000004),
258 	REG(REW_PORT_CFG,			0x000008),
259 	REG(REW_DSCP_CFG,			0x00000c),
260 	REG(REW_PCP_DEI_QOS_MAP_CFG,		0x000010),
261 	REG_RESERVED(REW_PTP_CFG),
262 	REG_RESERVED(REW_PTP_DLY1_CFG),
263 	REG_RESERVED(REW_RED_TAG_CFG),
264 	REG(REW_DSCP_REMAP_DP1_CFG,		0x000610),
265 	REG(REW_DSCP_REMAP_CFG,			0x000710),
266 	REG_RESERVED(REW_STAT_CFG),
267 	REG_RESERVED(REW_REW_STICKY),
268 	REG_RESERVED(REW_PPT),
269 };
270 
271 static const u32 vsc9953_sys_regmap[] = {
272 	REG(SYS_COUNT_RX_OCTETS,		0x000000),
273 	REG(SYS_COUNT_RX_UNICAST,		0x000004),
274 	REG(SYS_COUNT_RX_MULTICAST,		0x000008),
275 	REG(SYS_COUNT_RX_BROADCAST,		0x00000c),
276 	REG(SYS_COUNT_RX_SHORTS,		0x000010),
277 	REG(SYS_COUNT_RX_FRAGMENTS,		0x000014),
278 	REG(SYS_COUNT_RX_JABBERS,		0x000018),
279 	REG(SYS_COUNT_RX_CRC_ALIGN_ERRS,	0x00001c),
280 	REG(SYS_COUNT_RX_SYM_ERRS,		0x000020),
281 	REG(SYS_COUNT_RX_64,			0x000024),
282 	REG(SYS_COUNT_RX_65_127,		0x000028),
283 	REG(SYS_COUNT_RX_128_255,		0x00002c),
284 	REG(SYS_COUNT_RX_256_511,		0x000030),
285 	REG(SYS_COUNT_RX_512_1023,		0x000034),
286 	REG(SYS_COUNT_RX_1024_1526,		0x000038),
287 	REG(SYS_COUNT_RX_1527_MAX,		0x00003c),
288 	REG(SYS_COUNT_RX_PAUSE,			0x000040),
289 	REG(SYS_COUNT_RX_CONTROL,		0x000044),
290 	REG(SYS_COUNT_RX_LONGS,			0x000048),
291 	REG(SYS_COUNT_RX_CLASSIFIED_DROPS,	0x00004c),
292 	REG(SYS_COUNT_RX_RED_PRIO_0,		0x000050),
293 	REG(SYS_COUNT_RX_RED_PRIO_1,		0x000054),
294 	REG(SYS_COUNT_RX_RED_PRIO_2,		0x000058),
295 	REG(SYS_COUNT_RX_RED_PRIO_3,		0x00005c),
296 	REG(SYS_COUNT_RX_RED_PRIO_4,		0x000060),
297 	REG(SYS_COUNT_RX_RED_PRIO_5,		0x000064),
298 	REG(SYS_COUNT_RX_RED_PRIO_6,		0x000068),
299 	REG(SYS_COUNT_RX_RED_PRIO_7,		0x00006c),
300 	REG(SYS_COUNT_RX_YELLOW_PRIO_0,		0x000070),
301 	REG(SYS_COUNT_RX_YELLOW_PRIO_1,		0x000074),
302 	REG(SYS_COUNT_RX_YELLOW_PRIO_2,		0x000078),
303 	REG(SYS_COUNT_RX_YELLOW_PRIO_3,		0x00007c),
304 	REG(SYS_COUNT_RX_YELLOW_PRIO_4,		0x000080),
305 	REG(SYS_COUNT_RX_YELLOW_PRIO_5,		0x000084),
306 	REG(SYS_COUNT_RX_YELLOW_PRIO_6,		0x000088),
307 	REG(SYS_COUNT_RX_YELLOW_PRIO_7,		0x00008c),
308 	REG(SYS_COUNT_RX_GREEN_PRIO_0,		0x000090),
309 	REG(SYS_COUNT_RX_GREEN_PRIO_1,		0x000094),
310 	REG(SYS_COUNT_RX_GREEN_PRIO_2,		0x000098),
311 	REG(SYS_COUNT_RX_GREEN_PRIO_3,		0x00009c),
312 	REG(SYS_COUNT_RX_GREEN_PRIO_4,		0x0000a0),
313 	REG(SYS_COUNT_RX_GREEN_PRIO_5,		0x0000a4),
314 	REG(SYS_COUNT_RX_GREEN_PRIO_6,		0x0000a8),
315 	REG(SYS_COUNT_RX_GREEN_PRIO_7,		0x0000ac),
316 	REG(SYS_COUNT_TX_OCTETS,		0x000100),
317 	REG(SYS_COUNT_TX_UNICAST,		0x000104),
318 	REG(SYS_COUNT_TX_MULTICAST,		0x000108),
319 	REG(SYS_COUNT_TX_BROADCAST,		0x00010c),
320 	REG(SYS_COUNT_TX_COLLISION,		0x000110),
321 	REG(SYS_COUNT_TX_DROPS,			0x000114),
322 	REG(SYS_COUNT_TX_PAUSE,			0x000118),
323 	REG(SYS_COUNT_TX_64,			0x00011c),
324 	REG(SYS_COUNT_TX_65_127,		0x000120),
325 	REG(SYS_COUNT_TX_128_255,		0x000124),
326 	REG(SYS_COUNT_TX_256_511,		0x000128),
327 	REG(SYS_COUNT_TX_512_1023,		0x00012c),
328 	REG(SYS_COUNT_TX_1024_1526,		0x000130),
329 	REG(SYS_COUNT_TX_1527_MAX,		0x000134),
330 	REG(SYS_COUNT_TX_YELLOW_PRIO_0,		0x000138),
331 	REG(SYS_COUNT_TX_YELLOW_PRIO_1,		0x00013c),
332 	REG(SYS_COUNT_TX_YELLOW_PRIO_2,		0x000140),
333 	REG(SYS_COUNT_TX_YELLOW_PRIO_3,		0x000144),
334 	REG(SYS_COUNT_TX_YELLOW_PRIO_4,		0x000148),
335 	REG(SYS_COUNT_TX_YELLOW_PRIO_5,		0x00014c),
336 	REG(SYS_COUNT_TX_YELLOW_PRIO_6,		0x000150),
337 	REG(SYS_COUNT_TX_YELLOW_PRIO_7,		0x000154),
338 	REG(SYS_COUNT_TX_GREEN_PRIO_0,		0x000158),
339 	REG(SYS_COUNT_TX_GREEN_PRIO_1,		0x00015c),
340 	REG(SYS_COUNT_TX_GREEN_PRIO_2,		0x000160),
341 	REG(SYS_COUNT_TX_GREEN_PRIO_3,		0x000164),
342 	REG(SYS_COUNT_TX_GREEN_PRIO_4,		0x000168),
343 	REG(SYS_COUNT_TX_GREEN_PRIO_5,		0x00016c),
344 	REG(SYS_COUNT_TX_GREEN_PRIO_6,		0x000170),
345 	REG(SYS_COUNT_TX_GREEN_PRIO_7,		0x000174),
346 	REG(SYS_COUNT_TX_AGED,			0x000178),
347 	REG(SYS_COUNT_DROP_LOCAL,		0x000200),
348 	REG(SYS_COUNT_DROP_TAIL,		0x000204),
349 	REG(SYS_COUNT_DROP_YELLOW_PRIO_0,	0x000208),
350 	REG(SYS_COUNT_DROP_YELLOW_PRIO_1,	0x00020c),
351 	REG(SYS_COUNT_DROP_YELLOW_PRIO_2,	0x000210),
352 	REG(SYS_COUNT_DROP_YELLOW_PRIO_3,	0x000214),
353 	REG(SYS_COUNT_DROP_YELLOW_PRIO_4,	0x000218),
354 	REG(SYS_COUNT_DROP_YELLOW_PRIO_5,	0x00021c),
355 	REG(SYS_COUNT_DROP_YELLOW_PRIO_6,	0x000220),
356 	REG(SYS_COUNT_DROP_YELLOW_PRIO_7,	0x000224),
357 	REG(SYS_COUNT_DROP_GREEN_PRIO_0,	0x000228),
358 	REG(SYS_COUNT_DROP_GREEN_PRIO_1,	0x00022c),
359 	REG(SYS_COUNT_DROP_GREEN_PRIO_2,	0x000230),
360 	REG(SYS_COUNT_DROP_GREEN_PRIO_3,	0x000234),
361 	REG(SYS_COUNT_DROP_GREEN_PRIO_4,	0x000238),
362 	REG(SYS_COUNT_DROP_GREEN_PRIO_5,	0x00023c),
363 	REG(SYS_COUNT_DROP_GREEN_PRIO_6,	0x000240),
364 	REG(SYS_COUNT_DROP_GREEN_PRIO_7,	0x000244),
365 	REG(SYS_RESET_CFG,			0x000318),
366 	REG_RESERVED(SYS_SR_ETYPE_CFG),
367 	REG(SYS_VLAN_ETYPE_CFG,			0x000320),
368 	REG(SYS_PORT_MODE,			0x000324),
369 	REG(SYS_FRONT_PORT_MODE,		0x000354),
370 	REG(SYS_FRM_AGING,			0x00037c),
371 	REG(SYS_STAT_CFG,			0x000380),
372 	REG_RESERVED(SYS_SW_STATUS),
373 	REG_RESERVED(SYS_MISC_CFG),
374 	REG_RESERVED(SYS_REW_MAC_HIGH_CFG),
375 	REG_RESERVED(SYS_REW_MAC_LOW_CFG),
376 	REG_RESERVED(SYS_TIMESTAMP_OFFSET),
377 	REG(SYS_PAUSE_CFG,			0x00044c),
378 	REG(SYS_PAUSE_TOT_CFG,			0x000478),
379 	REG(SYS_ATOP,				0x00047c),
380 	REG(SYS_ATOP_TOT_CFG,			0x0004a8),
381 	REG(SYS_MAC_FC_CFG,			0x0004ac),
382 	REG(SYS_MMGT,				0x0004d4),
383 	REG_RESERVED(SYS_MMGT_FAST),
384 	REG_RESERVED(SYS_EVENTS_DIF),
385 	REG_RESERVED(SYS_EVENTS_CORE),
386 	REG_RESERVED(SYS_PTP_STATUS),
387 	REG_RESERVED(SYS_PTP_TXSTAMP),
388 	REG_RESERVED(SYS_PTP_NXT),
389 	REG_RESERVED(SYS_PTP_CFG),
390 	REG_RESERVED(SYS_RAM_INIT),
391 	REG_RESERVED(SYS_CM_ADDR),
392 	REG_RESERVED(SYS_CM_DATA_WR),
393 	REG_RESERVED(SYS_CM_DATA_RD),
394 	REG_RESERVED(SYS_CM_OP),
395 	REG_RESERVED(SYS_CM_DATA),
396 };
397 
398 static const u32 vsc9953_gcb_regmap[] = {
399 	REG(GCB_SOFT_RST,			0x000008),
400 	REG(GCB_MIIM_MII_STATUS,		0x0000ac),
401 	REG(GCB_MIIM_MII_CMD,			0x0000b4),
402 	REG(GCB_MIIM_MII_DATA,			0x0000b8),
403 };
404 
405 static const u32 vsc9953_dev_gmii_regmap[] = {
406 	REG(DEV_CLOCK_CFG,			0x0),
407 	REG(DEV_PORT_MISC,			0x4),
408 	REG_RESERVED(DEV_EVENTS),
409 	REG(DEV_EEE_CFG,			0xc),
410 	REG_RESERVED(DEV_RX_PATH_DELAY),
411 	REG_RESERVED(DEV_TX_PATH_DELAY),
412 	REG_RESERVED(DEV_PTP_PREDICT_CFG),
413 	REG(DEV_MAC_ENA_CFG,			0x10),
414 	REG(DEV_MAC_MODE_CFG,			0x14),
415 	REG(DEV_MAC_MAXLEN_CFG,			0x18),
416 	REG(DEV_MAC_TAGS_CFG,			0x1c),
417 	REG(DEV_MAC_ADV_CHK_CFG,		0x20),
418 	REG(DEV_MAC_IFG_CFG,			0x24),
419 	REG(DEV_MAC_HDX_CFG,			0x28),
420 	REG_RESERVED(DEV_MAC_DBG_CFG),
421 	REG(DEV_MAC_FC_MAC_LOW_CFG,		0x30),
422 	REG(DEV_MAC_FC_MAC_HIGH_CFG,		0x34),
423 	REG(DEV_MAC_STICKY,			0x38),
424 	REG_RESERVED(PCS1G_CFG),
425 	REG_RESERVED(PCS1G_MODE_CFG),
426 	REG_RESERVED(PCS1G_SD_CFG),
427 	REG_RESERVED(PCS1G_ANEG_CFG),
428 	REG_RESERVED(PCS1G_ANEG_NP_CFG),
429 	REG_RESERVED(PCS1G_LB_CFG),
430 	REG_RESERVED(PCS1G_DBG_CFG),
431 	REG_RESERVED(PCS1G_CDET_CFG),
432 	REG_RESERVED(PCS1G_ANEG_STATUS),
433 	REG_RESERVED(PCS1G_ANEG_NP_STATUS),
434 	REG_RESERVED(PCS1G_LINK_STATUS),
435 	REG_RESERVED(PCS1G_LINK_DOWN_CNT),
436 	REG_RESERVED(PCS1G_STICKY),
437 	REG_RESERVED(PCS1G_DEBUG_STATUS),
438 	REG_RESERVED(PCS1G_LPI_CFG),
439 	REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT),
440 	REG_RESERVED(PCS1G_LPI_STATUS),
441 	REG_RESERVED(PCS1G_TSTPAT_MODE_CFG),
442 	REG_RESERVED(PCS1G_TSTPAT_STATUS),
443 	REG_RESERVED(DEV_PCS_FX100_CFG),
444 	REG_RESERVED(DEV_PCS_FX100_STATUS),
445 };
446 
447 static const u32 *vsc9953_regmap[TARGET_MAX] = {
448 	[ANA]		= vsc9953_ana_regmap,
449 	[QS]		= vsc9953_qs_regmap,
450 	[QSYS]		= vsc9953_qsys_regmap,
451 	[REW]		= vsc9953_rew_regmap,
452 	[SYS]		= vsc9953_sys_regmap,
453 	[S0]		= vsc9953_vcap_regmap,
454 	[S1]		= vsc9953_vcap_regmap,
455 	[S2]		= vsc9953_vcap_regmap,
456 	[GCB]		= vsc9953_gcb_regmap,
457 	[DEV_GMII]	= vsc9953_dev_gmii_regmap,
458 };
459 
460 /* Addresses are relative to the device's base address */
461 static const struct resource vsc9953_resources[] = {
462 	DEFINE_RES_MEM_NAMED(0x0010000, 0x0010000, "sys"),
463 	DEFINE_RES_MEM_NAMED(0x0030000, 0x0010000, "rew"),
464 	DEFINE_RES_MEM_NAMED(0x0040000, 0x0000400, "s0"),
465 	DEFINE_RES_MEM_NAMED(0x0050000, 0x0000400, "s1"),
466 	DEFINE_RES_MEM_NAMED(0x0060000, 0x0000400, "s2"),
467 	DEFINE_RES_MEM_NAMED(0x0070000, 0x0000200, "devcpu_gcb"),
468 	DEFINE_RES_MEM_NAMED(0x0080000, 0x0000100, "qs"),
469 	DEFINE_RES_MEM_NAMED(0x0090000, 0x00000cc, "ptp"),
470 	DEFINE_RES_MEM_NAMED(0x0100000, 0x0010000, "port0"),
471 	DEFINE_RES_MEM_NAMED(0x0110000, 0x0010000, "port1"),
472 	DEFINE_RES_MEM_NAMED(0x0120000, 0x0010000, "port2"),
473 	DEFINE_RES_MEM_NAMED(0x0130000, 0x0010000, "port3"),
474 	DEFINE_RES_MEM_NAMED(0x0140000, 0x0010000, "port4"),
475 	DEFINE_RES_MEM_NAMED(0x0150000, 0x0010000, "port5"),
476 	DEFINE_RES_MEM_NAMED(0x0160000, 0x0010000, "port6"),
477 	DEFINE_RES_MEM_NAMED(0x0170000, 0x0010000, "port7"),
478 	DEFINE_RES_MEM_NAMED(0x0180000, 0x0010000, "port8"),
479 	DEFINE_RES_MEM_NAMED(0x0190000, 0x0010000, "port9"),
480 	DEFINE_RES_MEM_NAMED(0x0200000, 0x0020000, "qsys"),
481 	DEFINE_RES_MEM_NAMED(0x0280000, 0x0010000, "ana"),
482 };
483 
484 static const char * const vsc9953_resource_names[TARGET_MAX] = {
485 	[SYS] = "sys",
486 	[REW] = "rew",
487 	[S0] = "s0",
488 	[S1] = "s1",
489 	[S2] = "s2",
490 	[GCB] = "devcpu_gcb",
491 	[QS] = "qs",
492 	[PTP] = "ptp",
493 	[QSYS] = "qsys",
494 	[ANA] = "ana",
495 };
496 
497 static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = {
498 	[ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 10, 10),
499 	[ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 9),
500 	[ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24),
501 	[ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22),
502 	[ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21),
503 	[ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20),
504 	[ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19),
505 	[ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18),
506 	[ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17),
507 	[ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16),
508 	[ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15),
509 	[ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13),
510 	[ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12),
511 	[ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11),
512 	[ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10),
513 	[ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9),
514 	[ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8),
515 	[ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7),
516 	[ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6),
517 	[ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5),
518 	[ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4),
519 	[ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3),
520 	[ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2),
521 	[ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1),
522 	[ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0),
523 	[ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16),
524 	[ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12),
525 	[ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),
526 	[SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 7, 7),
527 	[SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 6, 6),
528 	[SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 5, 5),
529 	[GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),
530 	[GCB_MIIM_MII_STATUS_PENDING] = REG_FIELD(GCB_MIIM_MII_STATUS, 2, 2),
531 	[GCB_MIIM_MII_STATUS_BUSY] = REG_FIELD(GCB_MIIM_MII_STATUS, 3, 3),
532 	/* Replicated per number of ports (11), register size 4 per port */
533 	[QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 13, 13, 11, 4),
534 	[QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 11, 4),
535 	[QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 11, 4),
536 	[QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 11, 4),
537 	[QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 11, 4),
538 	[SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 4, 5, 11, 4),
539 	[SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 2, 3, 11, 4),
540 	[SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 11, 4),
541 	[SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 11, 20, 11, 4),
542 	[SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 10, 11, 4),
543 	[SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 11, 4),
544 };
545 
546 static const struct vcap_field vsc9953_vcap_es0_keys[] = {
547 	[VCAP_ES0_EGR_PORT]			= {  0,  4},
548 	[VCAP_ES0_IGR_PORT]			= {  4,  4},
549 	[VCAP_ES0_RSV]				= {  8,  2},
550 	[VCAP_ES0_L2_MC]			= { 10,  1},
551 	[VCAP_ES0_L2_BC]			= { 11,  1},
552 	[VCAP_ES0_VID]				= { 12, 12},
553 	[VCAP_ES0_DP]				= { 24,  1},
554 	[VCAP_ES0_PCP]				= { 25,  3},
555 };
556 
557 static const struct vcap_field vsc9953_vcap_es0_actions[] = {
558 	[VCAP_ES0_ACT_PUSH_OUTER_TAG]		= {  0,  2},
559 	[VCAP_ES0_ACT_PUSH_INNER_TAG]		= {  2,  1},
560 	[VCAP_ES0_ACT_TAG_A_TPID_SEL]		= {  3,  2},
561 	[VCAP_ES0_ACT_TAG_A_VID_SEL]		= {  5,  1},
562 	[VCAP_ES0_ACT_TAG_A_PCP_SEL]		= {  6,  2},
563 	[VCAP_ES0_ACT_TAG_A_DEI_SEL]		= {  8,  2},
564 	[VCAP_ES0_ACT_TAG_B_TPID_SEL]		= { 10,  2},
565 	[VCAP_ES0_ACT_TAG_B_VID_SEL]		= { 12,  1},
566 	[VCAP_ES0_ACT_TAG_B_PCP_SEL]		= { 13,  2},
567 	[VCAP_ES0_ACT_TAG_B_DEI_SEL]		= { 15,  2},
568 	[VCAP_ES0_ACT_VID_A_VAL]		= { 17, 12},
569 	[VCAP_ES0_ACT_PCP_A_VAL]		= { 29,  3},
570 	[VCAP_ES0_ACT_DEI_A_VAL]		= { 32,  1},
571 	[VCAP_ES0_ACT_VID_B_VAL]		= { 33, 12},
572 	[VCAP_ES0_ACT_PCP_B_VAL]		= { 45,  3},
573 	[VCAP_ES0_ACT_DEI_B_VAL]		= { 48,  1},
574 	[VCAP_ES0_ACT_RSV]			= { 49, 24},
575 	[VCAP_ES0_ACT_HIT_STICKY]		= { 73,  1},
576 };
577 
578 static const struct vcap_field vsc9953_vcap_is1_keys[] = {
579 	[VCAP_IS1_HK_TYPE]			= {  0,   1},
580 	[VCAP_IS1_HK_LOOKUP]			= {  1,   2},
581 	[VCAP_IS1_HK_IGR_PORT_MASK]		= {  3,  11},
582 	[VCAP_IS1_HK_RSV]			= { 14,  10},
583 	/* VCAP_IS1_HK_OAM_Y1731 not supported */
584 	[VCAP_IS1_HK_L2_MC]			= { 24,   1},
585 	[VCAP_IS1_HK_L2_BC]			= { 25,   1},
586 	[VCAP_IS1_HK_IP_MC]			= { 26,   1},
587 	[VCAP_IS1_HK_VLAN_TAGGED]		= { 27,   1},
588 	[VCAP_IS1_HK_VLAN_DBL_TAGGED]		= { 28,   1},
589 	[VCAP_IS1_HK_TPID]			= { 29,   1},
590 	[VCAP_IS1_HK_VID]			= { 30,  12},
591 	[VCAP_IS1_HK_DEI]			= { 42,   1},
592 	[VCAP_IS1_HK_PCP]			= { 43,   3},
593 	/* Specific Fields for IS1 Half Key S1_NORMAL */
594 	[VCAP_IS1_HK_L2_SMAC]			= { 46,  48},
595 	[VCAP_IS1_HK_ETYPE_LEN]			= { 94,   1},
596 	[VCAP_IS1_HK_ETYPE]			= { 95,  16},
597 	[VCAP_IS1_HK_IP_SNAP]			= {111,   1},
598 	[VCAP_IS1_HK_IP4]			= {112,   1},
599 	/* Layer-3 Information */
600 	[VCAP_IS1_HK_L3_FRAGMENT]		= {113,   1},
601 	[VCAP_IS1_HK_L3_FRAG_OFS_GT0]		= {114,   1},
602 	[VCAP_IS1_HK_L3_OPTIONS]		= {115,   1},
603 	[VCAP_IS1_HK_L3_DSCP]			= {116,   6},
604 	[VCAP_IS1_HK_L3_IP4_SIP]		= {122,  32},
605 	/* Layer-4 Information */
606 	[VCAP_IS1_HK_TCP_UDP]			= {154,   1},
607 	[VCAP_IS1_HK_TCP]			= {155,   1},
608 	[VCAP_IS1_HK_L4_SPORT]			= {156,  16},
609 	[VCAP_IS1_HK_L4_RNG]			= {172,   8},
610 	/* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
611 	[VCAP_IS1_HK_IP4_INNER_TPID]            = { 46,   1},
612 	[VCAP_IS1_HK_IP4_INNER_VID]		= { 47,  12},
613 	[VCAP_IS1_HK_IP4_INNER_DEI]		= { 59,   1},
614 	[VCAP_IS1_HK_IP4_INNER_PCP]		= { 60,   3},
615 	[VCAP_IS1_HK_IP4_IP4]			= { 63,   1},
616 	[VCAP_IS1_HK_IP4_L3_FRAGMENT]		= { 64,   1},
617 	[VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0]	= { 65,   1},
618 	[VCAP_IS1_HK_IP4_L3_OPTIONS]		= { 66,   1},
619 	[VCAP_IS1_HK_IP4_L3_DSCP]		= { 67,   6},
620 	[VCAP_IS1_HK_IP4_L3_IP4_DIP]		= { 73,  32},
621 	[VCAP_IS1_HK_IP4_L3_IP4_SIP]		= {105,  32},
622 	[VCAP_IS1_HK_IP4_L3_PROTO]		= {137,   8},
623 	[VCAP_IS1_HK_IP4_TCP_UDP]		= {145,   1},
624 	[VCAP_IS1_HK_IP4_TCP]			= {146,   1},
625 	[VCAP_IS1_HK_IP4_L4_RNG]		= {147,   8},
626 	[VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE]	= {155,  32},
627 };
628 
629 static const struct vcap_field vsc9953_vcap_is1_actions[] = {
630 	[VCAP_IS1_ACT_DSCP_ENA]			= {  0,  1},
631 	[VCAP_IS1_ACT_DSCP_VAL]			= {  1,  6},
632 	[VCAP_IS1_ACT_QOS_ENA]			= {  7,  1},
633 	[VCAP_IS1_ACT_QOS_VAL]			= {  8,  3},
634 	[VCAP_IS1_ACT_DP_ENA]			= { 11,  1},
635 	[VCAP_IS1_ACT_DP_VAL]			= { 12,  1},
636 	[VCAP_IS1_ACT_PAG_OVERRIDE_MASK]	= { 13,  8},
637 	[VCAP_IS1_ACT_PAG_VAL]			= { 21,  8},
638 	[VCAP_IS1_ACT_RSV]			= { 29, 11},
639 	[VCAP_IS1_ACT_VID_REPLACE_ENA]		= { 40,  1},
640 	[VCAP_IS1_ACT_VID_ADD_VAL]		= { 41, 12},
641 	[VCAP_IS1_ACT_FID_SEL]			= { 53,  2},
642 	[VCAP_IS1_ACT_FID_VAL]			= { 55, 13},
643 	[VCAP_IS1_ACT_PCP_DEI_ENA]		= { 68,  1},
644 	[VCAP_IS1_ACT_PCP_VAL]			= { 69,  3},
645 	[VCAP_IS1_ACT_DEI_VAL]			= { 72,  1},
646 	[VCAP_IS1_ACT_VLAN_POP_CNT_ENA]		= { 73,  1},
647 	[VCAP_IS1_ACT_VLAN_POP_CNT]		= { 74,  2},
648 	[VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA]	= { 76,  4},
649 	[VCAP_IS1_ACT_HIT_STICKY]		= { 80,  1},
650 };
651 
652 static struct vcap_field vsc9953_vcap_is2_keys[] = {
653 	/* Common: 41 bits */
654 	[VCAP_IS2_TYPE]				= {  0,   4},
655 	[VCAP_IS2_HK_FIRST]			= {  4,   1},
656 	[VCAP_IS2_HK_PAG]			= {  5,   8},
657 	[VCAP_IS2_HK_IGR_PORT_MASK]		= { 13,  11},
658 	[VCAP_IS2_HK_RSV2]			= { 24,   1},
659 	[VCAP_IS2_HK_HOST_MATCH]		= { 25,   1},
660 	[VCAP_IS2_HK_L2_MC]			= { 26,   1},
661 	[VCAP_IS2_HK_L2_BC]			= { 27,   1},
662 	[VCAP_IS2_HK_VLAN_TAGGED]		= { 28,   1},
663 	[VCAP_IS2_HK_VID]			= { 29,  12},
664 	[VCAP_IS2_HK_DEI]			= { 41,   1},
665 	[VCAP_IS2_HK_PCP]			= { 42,   3},
666 	/* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
667 	[VCAP_IS2_HK_L2_DMAC]			= { 45,  48},
668 	[VCAP_IS2_HK_L2_SMAC]			= { 93,  48},
669 	/* MAC_ETYPE (TYPE=000) */
670 	[VCAP_IS2_HK_MAC_ETYPE_ETYPE]		= {141,  16},
671 	[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0]	= {157,  16},
672 	[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1]	= {173,   8},
673 	[VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2]	= {181,   3},
674 	/* MAC_LLC (TYPE=001) */
675 	[VCAP_IS2_HK_MAC_LLC_L2_LLC]		= {141,  40},
676 	/* MAC_SNAP (TYPE=010) */
677 	[VCAP_IS2_HK_MAC_SNAP_L2_SNAP]		= {141,  40},
678 	/* MAC_ARP (TYPE=011) */
679 	[VCAP_IS2_HK_MAC_ARP_SMAC]		= { 45,  48},
680 	[VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK]	= { 93,   1},
681 	[VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK]	= { 94,   1},
682 	[VCAP_IS2_HK_MAC_ARP_LEN_OK]		= { 95,   1},
683 	[VCAP_IS2_HK_MAC_ARP_TARGET_MATCH]	= { 96,   1},
684 	[VCAP_IS2_HK_MAC_ARP_SENDER_MATCH]	= { 97,   1},
685 	[VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN]	= { 98,   1},
686 	[VCAP_IS2_HK_MAC_ARP_OPCODE]		= { 99,   2},
687 	[VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP]	= {101,  32},
688 	[VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP]	= {133,  32},
689 	[VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP]	= {165,   1},
690 	/* IP4_TCP_UDP / IP4_OTHER common */
691 	[VCAP_IS2_HK_IP4]			= { 45,   1},
692 	[VCAP_IS2_HK_L3_FRAGMENT]		= { 46,   1},
693 	[VCAP_IS2_HK_L3_FRAG_OFS_GT0]		= { 47,   1},
694 	[VCAP_IS2_HK_L3_OPTIONS]		= { 48,   1},
695 	[VCAP_IS2_HK_IP4_L3_TTL_GT0]		= { 49,   1},
696 	[VCAP_IS2_HK_L3_TOS]			= { 50,   8},
697 	[VCAP_IS2_HK_L3_IP4_DIP]		= { 58,  32},
698 	[VCAP_IS2_HK_L3_IP4_SIP]		= { 90,  32},
699 	[VCAP_IS2_HK_DIP_EQ_SIP]		= {122,   1},
700 	/* IP4_TCP_UDP (TYPE=100) */
701 	[VCAP_IS2_HK_TCP]			= {123,   1},
702 	[VCAP_IS2_HK_L4_DPORT]			= {124,  16},
703 	[VCAP_IS2_HK_L4_SPORT]			= {140,  16},
704 	[VCAP_IS2_HK_L4_RNG]			= {156,   8},
705 	[VCAP_IS2_HK_L4_SPORT_EQ_DPORT]		= {164,   1},
706 	[VCAP_IS2_HK_L4_SEQUENCE_EQ0]		= {165,   1},
707 	[VCAP_IS2_HK_L4_FIN]			= {166,   1},
708 	[VCAP_IS2_HK_L4_SYN]			= {167,   1},
709 	[VCAP_IS2_HK_L4_RST]			= {168,   1},
710 	[VCAP_IS2_HK_L4_PSH]			= {169,   1},
711 	[VCAP_IS2_HK_L4_ACK]			= {170,   1},
712 	[VCAP_IS2_HK_L4_URG]			= {171,   1},
713 	/* IP4_OTHER (TYPE=101) */
714 	[VCAP_IS2_HK_IP4_L3_PROTO]		= {123,   8},
715 	[VCAP_IS2_HK_L3_PAYLOAD]		= {131,  56},
716 	/* IP6_STD (TYPE=110) */
717 	[VCAP_IS2_HK_IP6_L3_TTL_GT0]		= { 45,   1},
718 	[VCAP_IS2_HK_L3_IP6_SIP]		= { 46, 128},
719 	[VCAP_IS2_HK_IP6_L3_PROTO]		= {174,   8},
720 };
721 
722 static struct vcap_field vsc9953_vcap_is2_actions[] = {
723 	[VCAP_IS2_ACT_HIT_ME_ONCE]		= {  0,  1},
724 	[VCAP_IS2_ACT_CPU_COPY_ENA]		= {  1,  1},
725 	[VCAP_IS2_ACT_CPU_QU_NUM]		= {  2,  3},
726 	[VCAP_IS2_ACT_MASK_MODE]		= {  5,  2},
727 	[VCAP_IS2_ACT_MIRROR_ENA]		= {  7,  1},
728 	[VCAP_IS2_ACT_LRN_DIS]			= {  8,  1},
729 	[VCAP_IS2_ACT_POLICE_ENA]		= {  9,  1},
730 	[VCAP_IS2_ACT_POLICE_IDX]		= { 10,  8},
731 	[VCAP_IS2_ACT_POLICE_VCAP_ONLY]		= { 21,  1},
732 	[VCAP_IS2_ACT_PORT_MASK]		= { 22, 10},
733 	[VCAP_IS2_ACT_ACL_ID]			= { 44,  6},
734 	[VCAP_IS2_ACT_HIT_CNT]			= { 50, 32},
735 };
736 
737 static struct vcap_props vsc9953_vcap_props[] = {
738 	[VCAP_ES0] = {
739 		.action_type_width = 0,
740 		.action_table = {
741 			[ES0_ACTION_TYPE_NORMAL] = {
742 				.width = 73, /* HIT_STICKY not included */
743 				.count = 1,
744 			},
745 		},
746 		.target = S0,
747 		.keys = vsc9953_vcap_es0_keys,
748 		.actions = vsc9953_vcap_es0_actions,
749 	},
750 	[VCAP_IS1] = {
751 		.action_type_width = 0,
752 		.action_table = {
753 			[IS1_ACTION_TYPE_NORMAL] = {
754 				.width = 80, /* HIT_STICKY not included */
755 				.count = 4,
756 			},
757 		},
758 		.target = S1,
759 		.keys = vsc9953_vcap_is1_keys,
760 		.actions = vsc9953_vcap_is1_actions,
761 	},
762 	[VCAP_IS2] = {
763 		.action_type_width = 1,
764 		.action_table = {
765 			[IS2_ACTION_TYPE_NORMAL] = {
766 				.width = 50, /* HIT_CNT not included */
767 				.count = 2
768 			},
769 			[IS2_ACTION_TYPE_SMAC_SIP] = {
770 				.width = 6,
771 				.count = 4
772 			},
773 		},
774 		.target = S2,
775 		.keys = vsc9953_vcap_is2_keys,
776 		.actions = vsc9953_vcap_is2_actions,
777 	},
778 };
779 
780 #define VSC9953_INIT_TIMEOUT			50000
781 #define VSC9953_GCB_RST_SLEEP			100
782 #define VSC9953_SYS_RAMINIT_SLEEP		80
783 
784 static int vsc9953_gcb_soft_rst_status(struct ocelot *ocelot)
785 {
786 	int val;
787 
788 	ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val);
789 
790 	return val;
791 }
792 
793 static int vsc9953_sys_ram_init_status(struct ocelot *ocelot)
794 {
795 	int val;
796 
797 	ocelot_field_read(ocelot, SYS_RESET_CFG_MEM_INIT, &val);
798 
799 	return val;
800 }
801 
802 
803 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG
804  * MEM_INIT is in SYS:SYSTEM:RESET_CFG
805  * MEM_ENA is in SYS:SYSTEM:RESET_CFG
806  */
807 static int vsc9953_reset(struct ocelot *ocelot)
808 {
809 	int val, err;
810 
811 	/* soft-reset the switch core */
812 	ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1);
813 
814 	err = readx_poll_timeout(vsc9953_gcb_soft_rst_status, ocelot, val, !val,
815 				 VSC9953_GCB_RST_SLEEP, VSC9953_INIT_TIMEOUT);
816 	if (err) {
817 		dev_err(ocelot->dev, "timeout: switch core reset\n");
818 		return err;
819 	}
820 
821 	/* initialize switch mem ~40us */
822 	ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_ENA, 1);
823 	ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_INIT, 1);
824 
825 	err = readx_poll_timeout(vsc9953_sys_ram_init_status, ocelot, val, !val,
826 				 VSC9953_SYS_RAMINIT_SLEEP,
827 				 VSC9953_INIT_TIMEOUT);
828 	if (err) {
829 		dev_err(ocelot->dev, "timeout: switch sram init\n");
830 		return err;
831 	}
832 
833 	/* enable switch core */
834 	ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1);
835 
836 	return 0;
837 }
838 
839 /* Watermark encode
840  * Bit 9:   Unit; 0:1, 1:16
841  * Bit 8-0: Value to be multiplied with unit
842  */
843 static u16 vsc9953_wm_enc(u16 value)
844 {
845 	WARN_ON(value >= 16 * BIT(9));
846 
847 	if (value >= BIT(9))
848 		return BIT(9) | (value / 16);
849 
850 	return value;
851 }
852 
853 static u16 vsc9953_wm_dec(u16 wm)
854 {
855 	WARN_ON(wm & ~GENMASK(9, 0));
856 
857 	if (wm & BIT(9))
858 		return (wm & GENMASK(8, 0)) * 16;
859 
860 	return wm;
861 }
862 
863 static void vsc9953_wm_stat(u32 val, u32 *inuse, u32 *maxuse)
864 {
865 	*inuse = (val & GENMASK(25, 13)) >> 13;
866 	*maxuse = val & GENMASK(12, 0);
867 }
868 
869 static const struct ocelot_ops vsc9953_ops = {
870 	.reset			= vsc9953_reset,
871 	.wm_enc			= vsc9953_wm_enc,
872 	.wm_dec			= vsc9953_wm_dec,
873 	.wm_stat		= vsc9953_wm_stat,
874 	.port_to_netdev		= felix_port_to_netdev,
875 	.netdev_to_port		= felix_netdev_to_port,
876 };
877 
878 static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot)
879 {
880 	struct felix *felix = ocelot_to_felix(ocelot);
881 	struct device *dev = ocelot->dev;
882 	struct mii_bus *bus;
883 	int port;
884 	int rc;
885 
886 	felix->pcs = devm_kcalloc(dev, felix->info->num_ports,
887 				  sizeof(struct phylink_pcs *),
888 				  GFP_KERNEL);
889 	if (!felix->pcs) {
890 		dev_err(dev, "failed to allocate array for PCS PHYs\n");
891 		return -ENOMEM;
892 	}
893 
894 	rc = mscc_miim_setup(dev, &bus, "VSC9953 internal MDIO bus",
895 			     ocelot->targets[GCB],
896 			     ocelot->map[GCB][GCB_MIIM_MII_STATUS & REG_MASK],
897 			     true);
898 	if (rc) {
899 		dev_err(dev, "failed to setup MDIO bus\n");
900 		return rc;
901 	}
902 
903 	/* Needed in order to initialize the bus mutex lock */
904 	rc = devm_of_mdiobus_register(dev, bus, NULL);
905 	if (rc < 0) {
906 		dev_err(dev, "failed to register MDIO bus\n");
907 		return rc;
908 	}
909 
910 	felix->imdio = bus;
911 
912 	for (port = 0; port < felix->info->num_ports; port++) {
913 		struct ocelot_port *ocelot_port = ocelot->ports[port];
914 		struct phylink_pcs *phylink_pcs;
915 		int addr = port + 4;
916 
917 		if (dsa_is_unused_port(felix->ds, port))
918 			continue;
919 
920 		if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)
921 			continue;
922 
923 		phylink_pcs = lynx_pcs_create_mdiodev(felix->imdio, addr);
924 		if (IS_ERR(phylink_pcs))
925 			continue;
926 
927 		felix->pcs[port] = phylink_pcs;
928 
929 		dev_info(dev, "Found PCS at internal MDIO address %d\n", addr);
930 	}
931 
932 	return 0;
933 }
934 
935 static void vsc9953_mdio_bus_free(struct ocelot *ocelot)
936 {
937 	struct felix *felix = ocelot_to_felix(ocelot);
938 	int port;
939 
940 	for (port = 0; port < ocelot->num_phys_ports; port++) {
941 		struct phylink_pcs *phylink_pcs = felix->pcs[port];
942 
943 		if (phylink_pcs)
944 			lynx_pcs_destroy(phylink_pcs);
945 	}
946 
947 	/* mdiobus_unregister and mdiobus_free handled by devres */
948 }
949 
950 static const struct felix_info seville_info_vsc9953 = {
951 	.resources		= vsc9953_resources,
952 	.num_resources		= ARRAY_SIZE(vsc9953_resources),
953 	.resource_names		= vsc9953_resource_names,
954 	.regfields		= vsc9953_regfields,
955 	.map			= vsc9953_regmap,
956 	.ops			= &vsc9953_ops,
957 	.vcap			= vsc9953_vcap_props,
958 	.vcap_pol_base		= VSC9953_VCAP_POLICER_BASE,
959 	.vcap_pol_max		= VSC9953_VCAP_POLICER_MAX,
960 	.vcap_pol_base2		= VSC9953_VCAP_POLICER_BASE2,
961 	.vcap_pol_max2		= VSC9953_VCAP_POLICER_MAX2,
962 	.quirks			= FELIX_MAC_QUIRKS,
963 	.num_mact_rows		= 2048,
964 	.num_ports		= VSC9953_NUM_PORTS,
965 	.num_tx_queues		= OCELOT_NUM_TC,
966 	.mdio_bus_alloc		= vsc9953_mdio_bus_alloc,
967 	.mdio_bus_free		= vsc9953_mdio_bus_free,
968 	.port_modes		= vsc9953_port_modes,
969 };
970 
971 static int seville_probe(struct platform_device *pdev)
972 {
973 	struct dsa_switch *ds;
974 	struct ocelot *ocelot;
975 	struct resource *res;
976 	struct felix *felix;
977 	int err;
978 
979 	felix = kzalloc(sizeof(struct felix), GFP_KERNEL);
980 	if (!felix) {
981 		err = -ENOMEM;
982 		dev_err(&pdev->dev, "Failed to allocate driver memory\n");
983 		goto err_alloc_felix;
984 	}
985 
986 	platform_set_drvdata(pdev, felix);
987 
988 	ocelot = &felix->ocelot;
989 	ocelot->dev = &pdev->dev;
990 	ocelot->num_flooding_pgids = 1;
991 	felix->info = &seville_info_vsc9953;
992 
993 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
994 	if (!res) {
995 		err = -EINVAL;
996 		dev_err(&pdev->dev, "Invalid resource\n");
997 		goto err_alloc_felix;
998 	}
999 	felix->switch_base = res->start;
1000 
1001 	ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL);
1002 	if (!ds) {
1003 		err = -ENOMEM;
1004 		dev_err(&pdev->dev, "Failed to allocate DSA switch\n");
1005 		goto err_alloc_ds;
1006 	}
1007 
1008 	ds->dev = &pdev->dev;
1009 	ds->num_ports = felix->info->num_ports;
1010 	ds->ops = &felix_switch_ops;
1011 	ds->priv = ocelot;
1012 	felix->ds = ds;
1013 	felix->tag_proto = DSA_TAG_PROTO_SEVILLE;
1014 
1015 	err = dsa_register_switch(ds);
1016 	if (err) {
1017 		dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err);
1018 		goto err_register_ds;
1019 	}
1020 
1021 	return 0;
1022 
1023 err_register_ds:
1024 	kfree(ds);
1025 err_alloc_ds:
1026 err_alloc_felix:
1027 	kfree(felix);
1028 	return err;
1029 }
1030 
1031 static int seville_remove(struct platform_device *pdev)
1032 {
1033 	struct felix *felix = platform_get_drvdata(pdev);
1034 
1035 	if (!felix)
1036 		return 0;
1037 
1038 	dsa_unregister_switch(felix->ds);
1039 
1040 	kfree(felix->ds);
1041 	kfree(felix);
1042 
1043 	return 0;
1044 }
1045 
1046 static void seville_shutdown(struct platform_device *pdev)
1047 {
1048 	struct felix *felix = platform_get_drvdata(pdev);
1049 
1050 	if (!felix)
1051 		return;
1052 
1053 	dsa_switch_shutdown(felix->ds);
1054 
1055 	platform_set_drvdata(pdev, NULL);
1056 }
1057 
1058 static const struct of_device_id seville_of_match[] = {
1059 	{ .compatible = "mscc,vsc9953-switch" },
1060 	{ },
1061 };
1062 MODULE_DEVICE_TABLE(of, seville_of_match);
1063 
1064 static struct platform_driver seville_vsc9953_driver = {
1065 	.probe		= seville_probe,
1066 	.remove		= seville_remove,
1067 	.shutdown	= seville_shutdown,
1068 	.driver = {
1069 		.name		= "mscc_seville",
1070 		.of_match_table	= seville_of_match,
1071 	},
1072 };
1073 module_platform_driver(seville_vsc9953_driver);
1074 
1075 MODULE_DESCRIPTION("Seville Switch driver");
1076 MODULE_LICENSE("GPL v2");
1077