1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* Distributed Switch Architecture VSC9953 driver 3 * Copyright (C) 2020, Maxim Kochetkov <fido_max@inbox.ru> 4 */ 5 #include <linux/types.h> 6 #include <soc/mscc/ocelot_vcap.h> 7 #include <soc/mscc/ocelot_sys.h> 8 #include <soc/mscc/ocelot.h> 9 #include <linux/mdio/mdio-mscc-miim.h> 10 #include <linux/of_mdio.h> 11 #include <linux/of_platform.h> 12 #include <linux/pcs-lynx.h> 13 #include <linux/dsa/ocelot.h> 14 #include <linux/iopoll.h> 15 #include "felix.h" 16 17 #define VSC9953_NUM_PORTS 10 18 19 #define VSC9953_VCAP_POLICER_BASE 11 20 #define VSC9953_VCAP_POLICER_MAX 31 21 #define VSC9953_VCAP_POLICER_BASE2 120 22 #define VSC9953_VCAP_POLICER_MAX2 161 23 24 #define VSC9953_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \ 25 OCELOT_PORT_MODE_QSGMII) 26 27 static const u32 vsc9953_port_modes[VSC9953_NUM_PORTS] = { 28 VSC9953_PORT_MODE_SERDES, 29 VSC9953_PORT_MODE_SERDES, 30 VSC9953_PORT_MODE_SERDES, 31 VSC9953_PORT_MODE_SERDES, 32 VSC9953_PORT_MODE_SERDES, 33 VSC9953_PORT_MODE_SERDES, 34 VSC9953_PORT_MODE_SERDES, 35 VSC9953_PORT_MODE_SERDES, 36 OCELOT_PORT_MODE_INTERNAL, 37 OCELOT_PORT_MODE_INTERNAL, 38 }; 39 40 static const u32 vsc9953_ana_regmap[] = { 41 REG(ANA_ADVLEARN, 0x00b500), 42 REG(ANA_VLANMASK, 0x00b504), 43 REG_RESERVED(ANA_PORT_B_DOMAIN), 44 REG(ANA_ANAGEFIL, 0x00b50c), 45 REG(ANA_ANEVENTS, 0x00b510), 46 REG(ANA_STORMLIMIT_BURST, 0x00b514), 47 REG(ANA_STORMLIMIT_CFG, 0x00b518), 48 REG(ANA_ISOLATED_PORTS, 0x00b528), 49 REG(ANA_COMMUNITY_PORTS, 0x00b52c), 50 REG(ANA_AUTOAGE, 0x00b530), 51 REG(ANA_MACTOPTIONS, 0x00b534), 52 REG(ANA_LEARNDISC, 0x00b538), 53 REG(ANA_AGENCTRL, 0x00b53c), 54 REG(ANA_MIRRORPORTS, 0x00b540), 55 REG(ANA_EMIRRORPORTS, 0x00b544), 56 REG(ANA_FLOODING, 0x00b548), 57 REG(ANA_FLOODING_IPMC, 0x00b54c), 58 REG(ANA_SFLOW_CFG, 0x00b550), 59 REG(ANA_PORT_MODE, 0x00b57c), 60 REG_RESERVED(ANA_CUT_THRU_CFG), 61 REG(ANA_PGID_PGID, 0x00b600), 62 REG(ANA_TABLES_ANMOVED, 0x00b4ac), 63 REG(ANA_TABLES_MACHDATA, 0x00b4b0), 64 REG(ANA_TABLES_MACLDATA, 0x00b4b4), 65 REG_RESERVED(ANA_TABLES_STREAMDATA), 66 REG(ANA_TABLES_MACACCESS, 0x00b4b8), 67 REG(ANA_TABLES_MACTINDX, 0x00b4bc), 68 REG(ANA_TABLES_VLANACCESS, 0x00b4c0), 69 REG(ANA_TABLES_VLANTIDX, 0x00b4c4), 70 REG_RESERVED(ANA_TABLES_ISDXACCESS), 71 REG_RESERVED(ANA_TABLES_ISDXTIDX), 72 REG(ANA_TABLES_ENTRYLIM, 0x00b480), 73 REG_RESERVED(ANA_TABLES_PTP_ID_HIGH), 74 REG_RESERVED(ANA_TABLES_PTP_ID_LOW), 75 REG_RESERVED(ANA_TABLES_STREAMACCESS), 76 REG_RESERVED(ANA_TABLES_STREAMTIDX), 77 REG_RESERVED(ANA_TABLES_SEQ_HISTORY), 78 REG_RESERVED(ANA_TABLES_SEQ_MASK), 79 REG_RESERVED(ANA_TABLES_SFID_MASK), 80 REG_RESERVED(ANA_TABLES_SFIDACCESS), 81 REG_RESERVED(ANA_TABLES_SFIDTIDX), 82 REG_RESERVED(ANA_MSTI_STATE), 83 REG_RESERVED(ANA_OAM_UPM_LM_CNT), 84 REG_RESERVED(ANA_SG_ACCESS_CTRL), 85 REG_RESERVED(ANA_SG_CONFIG_REG_1), 86 REG_RESERVED(ANA_SG_CONFIG_REG_2), 87 REG_RESERVED(ANA_SG_CONFIG_REG_3), 88 REG_RESERVED(ANA_SG_CONFIG_REG_4), 89 REG_RESERVED(ANA_SG_CONFIG_REG_5), 90 REG_RESERVED(ANA_SG_GCL_GS_CONFIG), 91 REG_RESERVED(ANA_SG_GCL_TI_CONFIG), 92 REG_RESERVED(ANA_SG_STATUS_REG_1), 93 REG_RESERVED(ANA_SG_STATUS_REG_2), 94 REG_RESERVED(ANA_SG_STATUS_REG_3), 95 REG(ANA_PORT_VLAN_CFG, 0x000000), 96 REG(ANA_PORT_DROP_CFG, 0x000004), 97 REG(ANA_PORT_QOS_CFG, 0x000008), 98 REG(ANA_PORT_VCAP_CFG, 0x00000c), 99 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x000010), 100 REG(ANA_PORT_VCAP_S2_CFG, 0x00001c), 101 REG(ANA_PORT_PCP_DEI_MAP, 0x000020), 102 REG(ANA_PORT_CPU_FWD_CFG, 0x000060), 103 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x000064), 104 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x000068), 105 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00006c), 106 REG(ANA_PORT_PORT_CFG, 0x000070), 107 REG(ANA_PORT_POL_CFG, 0x000074), 108 REG_RESERVED(ANA_PORT_PTP_CFG), 109 REG_RESERVED(ANA_PORT_PTP_DLY1_CFG), 110 REG_RESERVED(ANA_PORT_PTP_DLY2_CFG), 111 REG_RESERVED(ANA_PORT_SFID_CFG), 112 REG(ANA_PFC_PFC_CFG, 0x00c000), 113 REG_RESERVED(ANA_PFC_PFC_TIMER), 114 REG_RESERVED(ANA_IPT_OAM_MEP_CFG), 115 REG_RESERVED(ANA_IPT_IPT), 116 REG_RESERVED(ANA_PPT_PPT), 117 REG_RESERVED(ANA_FID_MAP_FID_MAP), 118 REG(ANA_AGGR_CFG, 0x00c600), 119 REG(ANA_CPUQ_CFG, 0x00c604), 120 REG_RESERVED(ANA_CPUQ_CFG2), 121 REG(ANA_CPUQ_8021_CFG, 0x00c60c), 122 REG(ANA_DSCP_CFG, 0x00c64c), 123 REG(ANA_DSCP_REWR_CFG, 0x00c74c), 124 REG(ANA_VCAP_RNG_TYPE_CFG, 0x00c78c), 125 REG(ANA_VCAP_RNG_VAL_CFG, 0x00c7ac), 126 REG_RESERVED(ANA_VRAP_CFG), 127 REG_RESERVED(ANA_VRAP_HDR_DATA), 128 REG_RESERVED(ANA_VRAP_HDR_MASK), 129 REG(ANA_DISCARD_CFG, 0x00c7d8), 130 REG(ANA_FID_CFG, 0x00c7dc), 131 REG(ANA_POL_PIR_CFG, 0x00a000), 132 REG(ANA_POL_CIR_CFG, 0x00a004), 133 REG(ANA_POL_MODE_CFG, 0x00a008), 134 REG(ANA_POL_PIR_STATE, 0x00a00c), 135 REG(ANA_POL_CIR_STATE, 0x00a010), 136 REG_RESERVED(ANA_POL_STATE), 137 REG(ANA_POL_FLOWC, 0x00c280), 138 REG(ANA_POL_HYST, 0x00c2ec), 139 REG_RESERVED(ANA_POL_MISC_CFG), 140 }; 141 142 static const u32 vsc9953_qs_regmap[] = { 143 REG(QS_XTR_GRP_CFG, 0x000000), 144 REG(QS_XTR_RD, 0x000008), 145 REG(QS_XTR_FRM_PRUNING, 0x000010), 146 REG(QS_XTR_FLUSH, 0x000018), 147 REG(QS_XTR_DATA_PRESENT, 0x00001c), 148 REG(QS_XTR_CFG, 0x000020), 149 REG(QS_INJ_GRP_CFG, 0x000024), 150 REG(QS_INJ_WR, 0x00002c), 151 REG(QS_INJ_CTRL, 0x000034), 152 REG(QS_INJ_STATUS, 0x00003c), 153 REG(QS_INJ_ERR, 0x000040), 154 REG_RESERVED(QS_INH_DBG), 155 }; 156 157 static const u32 vsc9953_vcap_regmap[] = { 158 /* VCAP_CORE_CFG */ 159 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 160 REG(VCAP_CORE_MV_CFG, 0x000004), 161 /* VCAP_CORE_CACHE */ 162 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 163 REG(VCAP_CACHE_MASK_DAT, 0x000108), 164 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 165 REG(VCAP_CACHE_CNT_DAT, 0x000308), 166 REG(VCAP_CACHE_TG_DAT, 0x000388), 167 /* VCAP_CONST */ 168 REG(VCAP_CONST_VCAP_VER, 0x000398), 169 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 170 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 171 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 172 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 173 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 174 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 175 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 176 REG_RESERVED(VCAP_CONST_CORE_CNT), 177 REG_RESERVED(VCAP_CONST_IF_CNT), 178 }; 179 180 static const u32 vsc9953_qsys_regmap[] = { 181 REG(QSYS_PORT_MODE, 0x003600), 182 REG(QSYS_SWITCH_PORT_MODE, 0x003630), 183 REG(QSYS_STAT_CNT_CFG, 0x00365c), 184 REG(QSYS_EEE_CFG, 0x003660), 185 REG(QSYS_EEE_THRES, 0x003688), 186 REG(QSYS_IGR_NO_SHARING, 0x00368c), 187 REG(QSYS_EGR_NO_SHARING, 0x003690), 188 REG(QSYS_SW_STATUS, 0x003694), 189 REG(QSYS_EXT_CPU_CFG, 0x0036c0), 190 REG_RESERVED(QSYS_PAD_CFG), 191 REG(QSYS_CPU_GROUP_MAP, 0x0036c8), 192 REG_RESERVED(QSYS_QMAP), 193 REG_RESERVED(QSYS_ISDX_SGRP), 194 REG_RESERVED(QSYS_TIMED_FRAME_ENTRY), 195 REG_RESERVED(QSYS_TFRM_MISC), 196 REG_RESERVED(QSYS_TFRM_PORT_DLY), 197 REG_RESERVED(QSYS_TFRM_TIMER_CFG_1), 198 REG_RESERVED(QSYS_TFRM_TIMER_CFG_2), 199 REG_RESERVED(QSYS_TFRM_TIMER_CFG_3), 200 REG_RESERVED(QSYS_TFRM_TIMER_CFG_4), 201 REG_RESERVED(QSYS_TFRM_TIMER_CFG_5), 202 REG_RESERVED(QSYS_TFRM_TIMER_CFG_6), 203 REG_RESERVED(QSYS_TFRM_TIMER_CFG_7), 204 REG_RESERVED(QSYS_TFRM_TIMER_CFG_8), 205 REG(QSYS_RED_PROFILE, 0x003724), 206 REG(QSYS_RES_QOS_MODE, 0x003764), 207 REG(QSYS_RES_CFG, 0x004000), 208 REG(QSYS_RES_STAT, 0x004004), 209 REG(QSYS_EGR_DROP_MODE, 0x003768), 210 REG(QSYS_EQ_CTRL, 0x00376c), 211 REG_RESERVED(QSYS_EVENTS_CORE), 212 REG_RESERVED(QSYS_QMAXSDU_CFG_0), 213 REG_RESERVED(QSYS_QMAXSDU_CFG_1), 214 REG_RESERVED(QSYS_QMAXSDU_CFG_2), 215 REG_RESERVED(QSYS_QMAXSDU_CFG_3), 216 REG_RESERVED(QSYS_QMAXSDU_CFG_4), 217 REG_RESERVED(QSYS_QMAXSDU_CFG_5), 218 REG_RESERVED(QSYS_QMAXSDU_CFG_6), 219 REG_RESERVED(QSYS_QMAXSDU_CFG_7), 220 REG_RESERVED(QSYS_PREEMPTION_CFG), 221 REG(QSYS_CIR_CFG, 0x000000), 222 REG_RESERVED(QSYS_EIR_CFG), 223 REG(QSYS_SE_CFG, 0x000008), 224 REG(QSYS_SE_DWRR_CFG, 0x00000c), 225 REG_RESERVED(QSYS_SE_CONNECT), 226 REG_RESERVED(QSYS_SE_DLB_SENSE), 227 REG(QSYS_CIR_STATE, 0x000044), 228 REG_RESERVED(QSYS_EIR_STATE), 229 REG_RESERVED(QSYS_SE_STATE), 230 REG(QSYS_HSCH_MISC_CFG, 0x003774), 231 REG_RESERVED(QSYS_TAG_CONFIG), 232 REG_RESERVED(QSYS_TAS_PARAM_CFG_CTRL), 233 REG_RESERVED(QSYS_PORT_MAX_SDU), 234 REG_RESERVED(QSYS_PARAM_CFG_REG_1), 235 REG_RESERVED(QSYS_PARAM_CFG_REG_2), 236 REG_RESERVED(QSYS_PARAM_CFG_REG_3), 237 REG_RESERVED(QSYS_PARAM_CFG_REG_4), 238 REG_RESERVED(QSYS_PARAM_CFG_REG_5), 239 REG_RESERVED(QSYS_GCL_CFG_REG_1), 240 REG_RESERVED(QSYS_GCL_CFG_REG_2), 241 REG_RESERVED(QSYS_PARAM_STATUS_REG_1), 242 REG_RESERVED(QSYS_PARAM_STATUS_REG_2), 243 REG_RESERVED(QSYS_PARAM_STATUS_REG_3), 244 REG_RESERVED(QSYS_PARAM_STATUS_REG_4), 245 REG_RESERVED(QSYS_PARAM_STATUS_REG_5), 246 REG_RESERVED(QSYS_PARAM_STATUS_REG_6), 247 REG_RESERVED(QSYS_PARAM_STATUS_REG_7), 248 REG_RESERVED(QSYS_PARAM_STATUS_REG_8), 249 REG_RESERVED(QSYS_PARAM_STATUS_REG_9), 250 REG_RESERVED(QSYS_GCL_STATUS_REG_1), 251 REG_RESERVED(QSYS_GCL_STATUS_REG_2), 252 }; 253 254 static const u32 vsc9953_rew_regmap[] = { 255 REG(REW_PORT_VLAN_CFG, 0x000000), 256 REG(REW_TAG_CFG, 0x000004), 257 REG(REW_PORT_CFG, 0x000008), 258 REG(REW_DSCP_CFG, 0x00000c), 259 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 260 REG_RESERVED(REW_PTP_CFG), 261 REG_RESERVED(REW_PTP_DLY1_CFG), 262 REG_RESERVED(REW_RED_TAG_CFG), 263 REG(REW_DSCP_REMAP_DP1_CFG, 0x000610), 264 REG(REW_DSCP_REMAP_CFG, 0x000710), 265 REG_RESERVED(REW_STAT_CFG), 266 REG_RESERVED(REW_REW_STICKY), 267 REG_RESERVED(REW_PPT), 268 }; 269 270 static const u32 vsc9953_sys_regmap[] = { 271 REG(SYS_COUNT_RX_OCTETS, 0x000000), 272 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 273 REG(SYS_COUNT_RX_SHORTS, 0x000010), 274 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 275 REG(SYS_COUNT_RX_JABBERS, 0x000018), 276 REG(SYS_COUNT_RX_64, 0x000024), 277 REG(SYS_COUNT_RX_65_127, 0x000028), 278 REG(SYS_COUNT_RX_128_255, 0x00002c), 279 REG(SYS_COUNT_RX_256_1023, 0x000030), 280 REG(SYS_COUNT_RX_1024_1526, 0x000034), 281 REG(SYS_COUNT_RX_1527_MAX, 0x000038), 282 REG(SYS_COUNT_RX_LONGS, 0x000048), 283 REG(SYS_COUNT_TX_OCTETS, 0x000100), 284 REG(SYS_COUNT_TX_COLLISION, 0x000110), 285 REG(SYS_COUNT_TX_DROPS, 0x000114), 286 REG(SYS_COUNT_TX_64, 0x00011c), 287 REG(SYS_COUNT_TX_65_127, 0x000120), 288 REG(SYS_COUNT_TX_128_511, 0x000124), 289 REG(SYS_COUNT_TX_512_1023, 0x000128), 290 REG(SYS_COUNT_TX_1024_1526, 0x00012c), 291 REG(SYS_COUNT_TX_1527_MAX, 0x000130), 292 REG(SYS_COUNT_TX_AGING, 0x000178), 293 REG(SYS_RESET_CFG, 0x000318), 294 REG_RESERVED(SYS_SR_ETYPE_CFG), 295 REG(SYS_VLAN_ETYPE_CFG, 0x000320), 296 REG(SYS_PORT_MODE, 0x000324), 297 REG(SYS_FRONT_PORT_MODE, 0x000354), 298 REG(SYS_FRM_AGING, 0x00037c), 299 REG(SYS_STAT_CFG, 0x000380), 300 REG_RESERVED(SYS_SW_STATUS), 301 REG_RESERVED(SYS_MISC_CFG), 302 REG_RESERVED(SYS_REW_MAC_HIGH_CFG), 303 REG_RESERVED(SYS_REW_MAC_LOW_CFG), 304 REG_RESERVED(SYS_TIMESTAMP_OFFSET), 305 REG(SYS_PAUSE_CFG, 0x00044c), 306 REG(SYS_PAUSE_TOT_CFG, 0x000478), 307 REG(SYS_ATOP, 0x00047c), 308 REG(SYS_ATOP_TOT_CFG, 0x0004a8), 309 REG(SYS_MAC_FC_CFG, 0x0004ac), 310 REG(SYS_MMGT, 0x0004d4), 311 REG_RESERVED(SYS_MMGT_FAST), 312 REG_RESERVED(SYS_EVENTS_DIF), 313 REG_RESERVED(SYS_EVENTS_CORE), 314 REG_RESERVED(SYS_CNT), 315 REG_RESERVED(SYS_PTP_STATUS), 316 REG_RESERVED(SYS_PTP_TXSTAMP), 317 REG_RESERVED(SYS_PTP_NXT), 318 REG_RESERVED(SYS_PTP_CFG), 319 REG_RESERVED(SYS_RAM_INIT), 320 REG_RESERVED(SYS_CM_ADDR), 321 REG_RESERVED(SYS_CM_DATA_WR), 322 REG_RESERVED(SYS_CM_DATA_RD), 323 REG_RESERVED(SYS_CM_OP), 324 REG_RESERVED(SYS_CM_DATA), 325 }; 326 327 static const u32 vsc9953_gcb_regmap[] = { 328 REG(GCB_SOFT_RST, 0x000008), 329 REG(GCB_MIIM_MII_STATUS, 0x0000ac), 330 REG(GCB_MIIM_MII_CMD, 0x0000b4), 331 REG(GCB_MIIM_MII_DATA, 0x0000b8), 332 }; 333 334 static const u32 vsc9953_dev_gmii_regmap[] = { 335 REG(DEV_CLOCK_CFG, 0x0), 336 REG(DEV_PORT_MISC, 0x4), 337 REG_RESERVED(DEV_EVENTS), 338 REG(DEV_EEE_CFG, 0xc), 339 REG_RESERVED(DEV_RX_PATH_DELAY), 340 REG_RESERVED(DEV_TX_PATH_DELAY), 341 REG_RESERVED(DEV_PTP_PREDICT_CFG), 342 REG(DEV_MAC_ENA_CFG, 0x10), 343 REG(DEV_MAC_MODE_CFG, 0x14), 344 REG(DEV_MAC_MAXLEN_CFG, 0x18), 345 REG(DEV_MAC_TAGS_CFG, 0x1c), 346 REG(DEV_MAC_ADV_CHK_CFG, 0x20), 347 REG(DEV_MAC_IFG_CFG, 0x24), 348 REG(DEV_MAC_HDX_CFG, 0x28), 349 REG_RESERVED(DEV_MAC_DBG_CFG), 350 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x30), 351 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x34), 352 REG(DEV_MAC_STICKY, 0x38), 353 REG_RESERVED(PCS1G_CFG), 354 REG_RESERVED(PCS1G_MODE_CFG), 355 REG_RESERVED(PCS1G_SD_CFG), 356 REG_RESERVED(PCS1G_ANEG_CFG), 357 REG_RESERVED(PCS1G_ANEG_NP_CFG), 358 REG_RESERVED(PCS1G_LB_CFG), 359 REG_RESERVED(PCS1G_DBG_CFG), 360 REG_RESERVED(PCS1G_CDET_CFG), 361 REG_RESERVED(PCS1G_ANEG_STATUS), 362 REG_RESERVED(PCS1G_ANEG_NP_STATUS), 363 REG_RESERVED(PCS1G_LINK_STATUS), 364 REG_RESERVED(PCS1G_LINK_DOWN_CNT), 365 REG_RESERVED(PCS1G_STICKY), 366 REG_RESERVED(PCS1G_DEBUG_STATUS), 367 REG_RESERVED(PCS1G_LPI_CFG), 368 REG_RESERVED(PCS1G_LPI_WAKE_ERROR_CNT), 369 REG_RESERVED(PCS1G_LPI_STATUS), 370 REG_RESERVED(PCS1G_TSTPAT_MODE_CFG), 371 REG_RESERVED(PCS1G_TSTPAT_STATUS), 372 REG_RESERVED(DEV_PCS_FX100_CFG), 373 REG_RESERVED(DEV_PCS_FX100_STATUS), 374 }; 375 376 static const u32 *vsc9953_regmap[TARGET_MAX] = { 377 [ANA] = vsc9953_ana_regmap, 378 [QS] = vsc9953_qs_regmap, 379 [QSYS] = vsc9953_qsys_regmap, 380 [REW] = vsc9953_rew_regmap, 381 [SYS] = vsc9953_sys_regmap, 382 [S0] = vsc9953_vcap_regmap, 383 [S1] = vsc9953_vcap_regmap, 384 [S2] = vsc9953_vcap_regmap, 385 [GCB] = vsc9953_gcb_regmap, 386 [DEV_GMII] = vsc9953_dev_gmii_regmap, 387 }; 388 389 /* Addresses are relative to the device's base address */ 390 static const struct resource vsc9953_target_io_res[TARGET_MAX] = { 391 [ANA] = { 392 .start = 0x0280000, 393 .end = 0x028ffff, 394 .name = "ana", 395 }, 396 [QS] = { 397 .start = 0x0080000, 398 .end = 0x00800ff, 399 .name = "qs", 400 }, 401 [QSYS] = { 402 .start = 0x0200000, 403 .end = 0x021ffff, 404 .name = "qsys", 405 }, 406 [REW] = { 407 .start = 0x0030000, 408 .end = 0x003ffff, 409 .name = "rew", 410 }, 411 [SYS] = { 412 .start = 0x0010000, 413 .end = 0x001ffff, 414 .name = "sys", 415 }, 416 [S0] = { 417 .start = 0x0040000, 418 .end = 0x00403ff, 419 .name = "s0", 420 }, 421 [S1] = { 422 .start = 0x0050000, 423 .end = 0x00503ff, 424 .name = "s1", 425 }, 426 [S2] = { 427 .start = 0x0060000, 428 .end = 0x00603ff, 429 .name = "s2", 430 }, 431 [PTP] = { 432 .start = 0x0090000, 433 .end = 0x00900cb, 434 .name = "ptp", 435 }, 436 [GCB] = { 437 .start = 0x0070000, 438 .end = 0x00701ff, 439 .name = "devcpu_gcb", 440 }, 441 }; 442 443 static const struct resource vsc9953_port_io_res[] = { 444 { 445 .start = 0x0100000, 446 .end = 0x010ffff, 447 .name = "port0", 448 }, 449 { 450 .start = 0x0110000, 451 .end = 0x011ffff, 452 .name = "port1", 453 }, 454 { 455 .start = 0x0120000, 456 .end = 0x012ffff, 457 .name = "port2", 458 }, 459 { 460 .start = 0x0130000, 461 .end = 0x013ffff, 462 .name = "port3", 463 }, 464 { 465 .start = 0x0140000, 466 .end = 0x014ffff, 467 .name = "port4", 468 }, 469 { 470 .start = 0x0150000, 471 .end = 0x015ffff, 472 .name = "port5", 473 }, 474 { 475 .start = 0x0160000, 476 .end = 0x016ffff, 477 .name = "port6", 478 }, 479 { 480 .start = 0x0170000, 481 .end = 0x017ffff, 482 .name = "port7", 483 }, 484 { 485 .start = 0x0180000, 486 .end = 0x018ffff, 487 .name = "port8", 488 }, 489 { 490 .start = 0x0190000, 491 .end = 0x019ffff, 492 .name = "port9", 493 }, 494 }; 495 496 static const struct reg_field vsc9953_regfields[REGFIELD_MAX] = { 497 [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 10, 10), 498 [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 9), 499 [ANA_ANEVENTS_AUTOAGE] = REG_FIELD(ANA_ANEVENTS, 24, 24), 500 [ANA_ANEVENTS_STORM_DROP] = REG_FIELD(ANA_ANEVENTS, 22, 22), 501 [ANA_ANEVENTS_LEARN_DROP] = REG_FIELD(ANA_ANEVENTS, 21, 21), 502 [ANA_ANEVENTS_AGED_ENTRY] = REG_FIELD(ANA_ANEVENTS, 20, 20), 503 [ANA_ANEVENTS_CPU_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 19, 19), 504 [ANA_ANEVENTS_AUTO_LEARN_FAILED] = REG_FIELD(ANA_ANEVENTS, 18, 18), 505 [ANA_ANEVENTS_LEARN_REMOVE] = REG_FIELD(ANA_ANEVENTS, 17, 17), 506 [ANA_ANEVENTS_AUTO_LEARNED] = REG_FIELD(ANA_ANEVENTS, 16, 16), 507 [ANA_ANEVENTS_AUTO_MOVED] = REG_FIELD(ANA_ANEVENTS, 15, 15), 508 [ANA_ANEVENTS_CLASSIFIED_DROP] = REG_FIELD(ANA_ANEVENTS, 13, 13), 509 [ANA_ANEVENTS_CLASSIFIED_COPY] = REG_FIELD(ANA_ANEVENTS, 12, 12), 510 [ANA_ANEVENTS_VLAN_DISCARD] = REG_FIELD(ANA_ANEVENTS, 11, 11), 511 [ANA_ANEVENTS_FWD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 10, 10), 512 [ANA_ANEVENTS_MULTICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 9, 9), 513 [ANA_ANEVENTS_UNICAST_FLOOD] = REG_FIELD(ANA_ANEVENTS, 8, 8), 514 [ANA_ANEVENTS_DEST_KNOWN] = REG_FIELD(ANA_ANEVENTS, 7, 7), 515 [ANA_ANEVENTS_BUCKET3_MATCH] = REG_FIELD(ANA_ANEVENTS, 6, 6), 516 [ANA_ANEVENTS_BUCKET2_MATCH] = REG_FIELD(ANA_ANEVENTS, 5, 5), 517 [ANA_ANEVENTS_BUCKET1_MATCH] = REG_FIELD(ANA_ANEVENTS, 4, 4), 518 [ANA_ANEVENTS_BUCKET0_MATCH] = REG_FIELD(ANA_ANEVENTS, 3, 3), 519 [ANA_ANEVENTS_CPU_OPERATION] = REG_FIELD(ANA_ANEVENTS, 2, 2), 520 [ANA_ANEVENTS_DMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 1, 1), 521 [ANA_ANEVENTS_SMAC_LOOKUP] = REG_FIELD(ANA_ANEVENTS, 0, 0), 522 [ANA_TABLES_MACACCESS_B_DOM] = REG_FIELD(ANA_TABLES_MACACCESS, 16, 16), 523 [ANA_TABLES_MACTINDX_BUCKET] = REG_FIELD(ANA_TABLES_MACTINDX, 11, 12), 524 [ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10), 525 [SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 7, 7), 526 [SYS_RESET_CFG_MEM_ENA] = REG_FIELD(SYS_RESET_CFG, 6, 6), 527 [SYS_RESET_CFG_MEM_INIT] = REG_FIELD(SYS_RESET_CFG, 5, 5), 528 [GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0), 529 [GCB_MIIM_MII_STATUS_PENDING] = REG_FIELD(GCB_MIIM_MII_STATUS, 2, 2), 530 [GCB_MIIM_MII_STATUS_BUSY] = REG_FIELD(GCB_MIIM_MII_STATUS, 3, 3), 531 /* Replicated per number of ports (11), register size 4 per port */ 532 [QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 13, 13, 11, 4), 533 [QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 11, 4), 534 [QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 11, 4), 535 [QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 11, 4), 536 [QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 11, 4), 537 [SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 4, 5, 11, 4), 538 [SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 2, 3, 11, 4), 539 [SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 11, 4), 540 [SYS_PAUSE_CFG_PAUSE_START] = REG_FIELD_ID(SYS_PAUSE_CFG, 11, 20, 11, 4), 541 [SYS_PAUSE_CFG_PAUSE_STOP] = REG_FIELD_ID(SYS_PAUSE_CFG, 1, 10, 11, 4), 542 [SYS_PAUSE_CFG_PAUSE_ENA] = REG_FIELD_ID(SYS_PAUSE_CFG, 0, 1, 11, 4), 543 }; 544 545 static const struct ocelot_stat_layout vsc9953_stats_layout[] = { 546 { .offset = 0x00, .name = "rx_octets", }, 547 { .offset = 0x01, .name = "rx_unicast", }, 548 { .offset = 0x02, .name = "rx_multicast", }, 549 { .offset = 0x03, .name = "rx_broadcast", }, 550 { .offset = 0x04, .name = "rx_shorts", }, 551 { .offset = 0x05, .name = "rx_fragments", }, 552 { .offset = 0x06, .name = "rx_jabbers", }, 553 { .offset = 0x07, .name = "rx_crc_align_errs", }, 554 { .offset = 0x08, .name = "rx_sym_errs", }, 555 { .offset = 0x09, .name = "rx_frames_below_65_octets", }, 556 { .offset = 0x0A, .name = "rx_frames_65_to_127_octets", }, 557 { .offset = 0x0B, .name = "rx_frames_128_to_255_octets", }, 558 { .offset = 0x0C, .name = "rx_frames_256_to_511_octets", }, 559 { .offset = 0x0D, .name = "rx_frames_512_to_1023_octets", }, 560 { .offset = 0x0E, .name = "rx_frames_1024_to_1526_octets", }, 561 { .offset = 0x0F, .name = "rx_frames_over_1526_octets", }, 562 { .offset = 0x10, .name = "rx_pause", }, 563 { .offset = 0x11, .name = "rx_control", }, 564 { .offset = 0x12, .name = "rx_longs", }, 565 { .offset = 0x13, .name = "rx_classified_drops", }, 566 { .offset = 0x14, .name = "rx_red_prio_0", }, 567 { .offset = 0x15, .name = "rx_red_prio_1", }, 568 { .offset = 0x16, .name = "rx_red_prio_2", }, 569 { .offset = 0x17, .name = "rx_red_prio_3", }, 570 { .offset = 0x18, .name = "rx_red_prio_4", }, 571 { .offset = 0x19, .name = "rx_red_prio_5", }, 572 { .offset = 0x1A, .name = "rx_red_prio_6", }, 573 { .offset = 0x1B, .name = "rx_red_prio_7", }, 574 { .offset = 0x1C, .name = "rx_yellow_prio_0", }, 575 { .offset = 0x1D, .name = "rx_yellow_prio_1", }, 576 { .offset = 0x1E, .name = "rx_yellow_prio_2", }, 577 { .offset = 0x1F, .name = "rx_yellow_prio_3", }, 578 { .offset = 0x20, .name = "rx_yellow_prio_4", }, 579 { .offset = 0x21, .name = "rx_yellow_prio_5", }, 580 { .offset = 0x22, .name = "rx_yellow_prio_6", }, 581 { .offset = 0x23, .name = "rx_yellow_prio_7", }, 582 { .offset = 0x24, .name = "rx_green_prio_0", }, 583 { .offset = 0x25, .name = "rx_green_prio_1", }, 584 { .offset = 0x26, .name = "rx_green_prio_2", }, 585 { .offset = 0x27, .name = "rx_green_prio_3", }, 586 { .offset = 0x28, .name = "rx_green_prio_4", }, 587 { .offset = 0x29, .name = "rx_green_prio_5", }, 588 { .offset = 0x2A, .name = "rx_green_prio_6", }, 589 { .offset = 0x2B, .name = "rx_green_prio_7", }, 590 { .offset = 0x40, .name = "tx_octets", }, 591 { .offset = 0x41, .name = "tx_unicast", }, 592 { .offset = 0x42, .name = "tx_multicast", }, 593 { .offset = 0x43, .name = "tx_broadcast", }, 594 { .offset = 0x44, .name = "tx_collision", }, 595 { .offset = 0x45, .name = "tx_drops", }, 596 { .offset = 0x46, .name = "tx_pause", }, 597 { .offset = 0x47, .name = "tx_frames_below_65_octets", }, 598 { .offset = 0x48, .name = "tx_frames_65_to_127_octets", }, 599 { .offset = 0x49, .name = "tx_frames_128_255_octets", }, 600 { .offset = 0x4A, .name = "tx_frames_256_511_octets", }, 601 { .offset = 0x4B, .name = "tx_frames_512_1023_octets", }, 602 { .offset = 0x4C, .name = "tx_frames_1024_1526_octets", }, 603 { .offset = 0x4D, .name = "tx_frames_over_1526_octets", }, 604 { .offset = 0x4E, .name = "tx_yellow_prio_0", }, 605 { .offset = 0x4F, .name = "tx_yellow_prio_1", }, 606 { .offset = 0x50, .name = "tx_yellow_prio_2", }, 607 { .offset = 0x51, .name = "tx_yellow_prio_3", }, 608 { .offset = 0x52, .name = "tx_yellow_prio_4", }, 609 { .offset = 0x53, .name = "tx_yellow_prio_5", }, 610 { .offset = 0x54, .name = "tx_yellow_prio_6", }, 611 { .offset = 0x55, .name = "tx_yellow_prio_7", }, 612 { .offset = 0x56, .name = "tx_green_prio_0", }, 613 { .offset = 0x57, .name = "tx_green_prio_1", }, 614 { .offset = 0x58, .name = "tx_green_prio_2", }, 615 { .offset = 0x59, .name = "tx_green_prio_3", }, 616 { .offset = 0x5A, .name = "tx_green_prio_4", }, 617 { .offset = 0x5B, .name = "tx_green_prio_5", }, 618 { .offset = 0x5C, .name = "tx_green_prio_6", }, 619 { .offset = 0x5D, .name = "tx_green_prio_7", }, 620 { .offset = 0x5E, .name = "tx_aged", }, 621 { .offset = 0x80, .name = "drop_local", }, 622 { .offset = 0x81, .name = "drop_tail", }, 623 { .offset = 0x82, .name = "drop_yellow_prio_0", }, 624 { .offset = 0x83, .name = "drop_yellow_prio_1", }, 625 { .offset = 0x84, .name = "drop_yellow_prio_2", }, 626 { .offset = 0x85, .name = "drop_yellow_prio_3", }, 627 { .offset = 0x86, .name = "drop_yellow_prio_4", }, 628 { .offset = 0x87, .name = "drop_yellow_prio_5", }, 629 { .offset = 0x88, .name = "drop_yellow_prio_6", }, 630 { .offset = 0x89, .name = "drop_yellow_prio_7", }, 631 { .offset = 0x8A, .name = "drop_green_prio_0", }, 632 { .offset = 0x8B, .name = "drop_green_prio_1", }, 633 { .offset = 0x8C, .name = "drop_green_prio_2", }, 634 { .offset = 0x8D, .name = "drop_green_prio_3", }, 635 { .offset = 0x8E, .name = "drop_green_prio_4", }, 636 { .offset = 0x8F, .name = "drop_green_prio_5", }, 637 { .offset = 0x90, .name = "drop_green_prio_6", }, 638 { .offset = 0x91, .name = "drop_green_prio_7", }, 639 }; 640 641 static const struct vcap_field vsc9953_vcap_es0_keys[] = { 642 [VCAP_ES0_EGR_PORT] = { 0, 4}, 643 [VCAP_ES0_IGR_PORT] = { 4, 4}, 644 [VCAP_ES0_RSV] = { 8, 2}, 645 [VCAP_ES0_L2_MC] = { 10, 1}, 646 [VCAP_ES0_L2_BC] = { 11, 1}, 647 [VCAP_ES0_VID] = { 12, 12}, 648 [VCAP_ES0_DP] = { 24, 1}, 649 [VCAP_ES0_PCP] = { 25, 3}, 650 }; 651 652 static const struct vcap_field vsc9953_vcap_es0_actions[] = { 653 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2}, 654 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1}, 655 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2}, 656 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1}, 657 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2}, 658 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2}, 659 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2}, 660 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1}, 661 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2}, 662 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2}, 663 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12}, 664 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3}, 665 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1}, 666 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12}, 667 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3}, 668 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1}, 669 [VCAP_ES0_ACT_RSV] = { 49, 24}, 670 [VCAP_ES0_ACT_HIT_STICKY] = { 73, 1}, 671 }; 672 673 static const struct vcap_field vsc9953_vcap_is1_keys[] = { 674 [VCAP_IS1_HK_TYPE] = { 0, 1}, 675 [VCAP_IS1_HK_LOOKUP] = { 1, 2}, 676 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 11}, 677 [VCAP_IS1_HK_RSV] = { 14, 10}, 678 /* VCAP_IS1_HK_OAM_Y1731 not supported */ 679 [VCAP_IS1_HK_L2_MC] = { 24, 1}, 680 [VCAP_IS1_HK_L2_BC] = { 25, 1}, 681 [VCAP_IS1_HK_IP_MC] = { 26, 1}, 682 [VCAP_IS1_HK_VLAN_TAGGED] = { 27, 1}, 683 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 28, 1}, 684 [VCAP_IS1_HK_TPID] = { 29, 1}, 685 [VCAP_IS1_HK_VID] = { 30, 12}, 686 [VCAP_IS1_HK_DEI] = { 42, 1}, 687 [VCAP_IS1_HK_PCP] = { 43, 3}, 688 /* Specific Fields for IS1 Half Key S1_NORMAL */ 689 [VCAP_IS1_HK_L2_SMAC] = { 46, 48}, 690 [VCAP_IS1_HK_ETYPE_LEN] = { 94, 1}, 691 [VCAP_IS1_HK_ETYPE] = { 95, 16}, 692 [VCAP_IS1_HK_IP_SNAP] = {111, 1}, 693 [VCAP_IS1_HK_IP4] = {112, 1}, 694 /* Layer-3 Information */ 695 [VCAP_IS1_HK_L3_FRAGMENT] = {113, 1}, 696 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = {114, 1}, 697 [VCAP_IS1_HK_L3_OPTIONS] = {115, 1}, 698 [VCAP_IS1_HK_L3_DSCP] = {116, 6}, 699 [VCAP_IS1_HK_L3_IP4_SIP] = {122, 32}, 700 /* Layer-4 Information */ 701 [VCAP_IS1_HK_TCP_UDP] = {154, 1}, 702 [VCAP_IS1_HK_TCP] = {155, 1}, 703 [VCAP_IS1_HK_L4_SPORT] = {156, 16}, 704 [VCAP_IS1_HK_L4_RNG] = {172, 8}, 705 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 706 [VCAP_IS1_HK_IP4_INNER_TPID] = { 46, 1}, 707 [VCAP_IS1_HK_IP4_INNER_VID] = { 47, 12}, 708 [VCAP_IS1_HK_IP4_INNER_DEI] = { 59, 1}, 709 [VCAP_IS1_HK_IP4_INNER_PCP] = { 60, 3}, 710 [VCAP_IS1_HK_IP4_IP4] = { 63, 1}, 711 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 64, 1}, 712 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 65, 1}, 713 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 66, 1}, 714 [VCAP_IS1_HK_IP4_L3_DSCP] = { 67, 6}, 715 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 73, 32}, 716 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = {105, 32}, 717 [VCAP_IS1_HK_IP4_L3_PROTO] = {137, 8}, 718 [VCAP_IS1_HK_IP4_TCP_UDP] = {145, 1}, 719 [VCAP_IS1_HK_IP4_TCP] = {146, 1}, 720 [VCAP_IS1_HK_IP4_L4_RNG] = {147, 8}, 721 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = {155, 32}, 722 }; 723 724 static const struct vcap_field vsc9953_vcap_is1_actions[] = { 725 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1}, 726 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6}, 727 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1}, 728 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3}, 729 [VCAP_IS1_ACT_DP_ENA] = { 11, 1}, 730 [VCAP_IS1_ACT_DP_VAL] = { 12, 1}, 731 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8}, 732 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8}, 733 [VCAP_IS1_ACT_RSV] = { 29, 11}, 734 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 40, 1}, 735 [VCAP_IS1_ACT_VID_ADD_VAL] = { 41, 12}, 736 [VCAP_IS1_ACT_FID_SEL] = { 53, 2}, 737 [VCAP_IS1_ACT_FID_VAL] = { 55, 13}, 738 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 68, 1}, 739 [VCAP_IS1_ACT_PCP_VAL] = { 69, 3}, 740 [VCAP_IS1_ACT_DEI_VAL] = { 72, 1}, 741 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 73, 1}, 742 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 74, 2}, 743 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 76, 4}, 744 [VCAP_IS1_ACT_HIT_STICKY] = { 80, 1}, 745 }; 746 747 static struct vcap_field vsc9953_vcap_is2_keys[] = { 748 /* Common: 41 bits */ 749 [VCAP_IS2_TYPE] = { 0, 4}, 750 [VCAP_IS2_HK_FIRST] = { 4, 1}, 751 [VCAP_IS2_HK_PAG] = { 5, 8}, 752 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 11}, 753 [VCAP_IS2_HK_RSV2] = { 24, 1}, 754 [VCAP_IS2_HK_HOST_MATCH] = { 25, 1}, 755 [VCAP_IS2_HK_L2_MC] = { 26, 1}, 756 [VCAP_IS2_HK_L2_BC] = { 27, 1}, 757 [VCAP_IS2_HK_VLAN_TAGGED] = { 28, 1}, 758 [VCAP_IS2_HK_VID] = { 29, 12}, 759 [VCAP_IS2_HK_DEI] = { 41, 1}, 760 [VCAP_IS2_HK_PCP] = { 42, 3}, 761 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 762 [VCAP_IS2_HK_L2_DMAC] = { 45, 48}, 763 [VCAP_IS2_HK_L2_SMAC] = { 93, 48}, 764 /* MAC_ETYPE (TYPE=000) */ 765 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = {141, 16}, 766 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = {157, 16}, 767 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = {173, 8}, 768 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = {181, 3}, 769 /* MAC_LLC (TYPE=001) */ 770 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = {141, 40}, 771 /* MAC_SNAP (TYPE=010) */ 772 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = {141, 40}, 773 /* MAC_ARP (TYPE=011) */ 774 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 45, 48}, 775 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 93, 1}, 776 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 94, 1}, 777 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 95, 1}, 778 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 96, 1}, 779 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 97, 1}, 780 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 98, 1}, 781 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 99, 2}, 782 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = {101, 32}, 783 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = {133, 32}, 784 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = {165, 1}, 785 /* IP4_TCP_UDP / IP4_OTHER common */ 786 [VCAP_IS2_HK_IP4] = { 45, 1}, 787 [VCAP_IS2_HK_L3_FRAGMENT] = { 46, 1}, 788 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 47, 1}, 789 [VCAP_IS2_HK_L3_OPTIONS] = { 48, 1}, 790 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 49, 1}, 791 [VCAP_IS2_HK_L3_TOS] = { 50, 8}, 792 [VCAP_IS2_HK_L3_IP4_DIP] = { 58, 32}, 793 [VCAP_IS2_HK_L3_IP4_SIP] = { 90, 32}, 794 [VCAP_IS2_HK_DIP_EQ_SIP] = {122, 1}, 795 /* IP4_TCP_UDP (TYPE=100) */ 796 [VCAP_IS2_HK_TCP] = {123, 1}, 797 [VCAP_IS2_HK_L4_DPORT] = {124, 16}, 798 [VCAP_IS2_HK_L4_SPORT] = {140, 16}, 799 [VCAP_IS2_HK_L4_RNG] = {156, 8}, 800 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = {164, 1}, 801 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = {165, 1}, 802 [VCAP_IS2_HK_L4_FIN] = {166, 1}, 803 [VCAP_IS2_HK_L4_SYN] = {167, 1}, 804 [VCAP_IS2_HK_L4_RST] = {168, 1}, 805 [VCAP_IS2_HK_L4_PSH] = {169, 1}, 806 [VCAP_IS2_HK_L4_ACK] = {170, 1}, 807 [VCAP_IS2_HK_L4_URG] = {171, 1}, 808 /* IP4_OTHER (TYPE=101) */ 809 [VCAP_IS2_HK_IP4_L3_PROTO] = {123, 8}, 810 [VCAP_IS2_HK_L3_PAYLOAD] = {131, 56}, 811 /* IP6_STD (TYPE=110) */ 812 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 45, 1}, 813 [VCAP_IS2_HK_L3_IP6_SIP] = { 46, 128}, 814 [VCAP_IS2_HK_IP6_L3_PROTO] = {174, 8}, 815 }; 816 817 static struct vcap_field vsc9953_vcap_is2_actions[] = { 818 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1}, 819 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1}, 820 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3}, 821 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2}, 822 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1}, 823 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1}, 824 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1}, 825 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 8}, 826 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 21, 1}, 827 [VCAP_IS2_ACT_PORT_MASK] = { 22, 10}, 828 [VCAP_IS2_ACT_ACL_ID] = { 44, 6}, 829 [VCAP_IS2_ACT_HIT_CNT] = { 50, 32}, 830 }; 831 832 static struct vcap_props vsc9953_vcap_props[] = { 833 [VCAP_ES0] = { 834 .action_type_width = 0, 835 .action_table = { 836 [ES0_ACTION_TYPE_NORMAL] = { 837 .width = 73, /* HIT_STICKY not included */ 838 .count = 1, 839 }, 840 }, 841 .target = S0, 842 .keys = vsc9953_vcap_es0_keys, 843 .actions = vsc9953_vcap_es0_actions, 844 }, 845 [VCAP_IS1] = { 846 .action_type_width = 0, 847 .action_table = { 848 [IS1_ACTION_TYPE_NORMAL] = { 849 .width = 80, /* HIT_STICKY not included */ 850 .count = 4, 851 }, 852 }, 853 .target = S1, 854 .keys = vsc9953_vcap_is1_keys, 855 .actions = vsc9953_vcap_is1_actions, 856 }, 857 [VCAP_IS2] = { 858 .action_type_width = 1, 859 .action_table = { 860 [IS2_ACTION_TYPE_NORMAL] = { 861 .width = 50, /* HIT_CNT not included */ 862 .count = 2 863 }, 864 [IS2_ACTION_TYPE_SMAC_SIP] = { 865 .width = 6, 866 .count = 4 867 }, 868 }, 869 .target = S2, 870 .keys = vsc9953_vcap_is2_keys, 871 .actions = vsc9953_vcap_is2_actions, 872 }, 873 }; 874 875 #define VSC9953_INIT_TIMEOUT 50000 876 #define VSC9953_GCB_RST_SLEEP 100 877 #define VSC9953_SYS_RAMINIT_SLEEP 80 878 879 static int vsc9953_gcb_soft_rst_status(struct ocelot *ocelot) 880 { 881 int val; 882 883 ocelot_field_read(ocelot, GCB_SOFT_RST_SWC_RST, &val); 884 885 return val; 886 } 887 888 static int vsc9953_sys_ram_init_status(struct ocelot *ocelot) 889 { 890 int val; 891 892 ocelot_field_read(ocelot, SYS_RESET_CFG_MEM_INIT, &val); 893 894 return val; 895 } 896 897 898 /* CORE_ENA is in SYS:SYSTEM:RESET_CFG 899 * MEM_INIT is in SYS:SYSTEM:RESET_CFG 900 * MEM_ENA is in SYS:SYSTEM:RESET_CFG 901 */ 902 static int vsc9953_reset(struct ocelot *ocelot) 903 { 904 int val, err; 905 906 /* soft-reset the switch core */ 907 ocelot_field_write(ocelot, GCB_SOFT_RST_SWC_RST, 1); 908 909 err = readx_poll_timeout(vsc9953_gcb_soft_rst_status, ocelot, val, !val, 910 VSC9953_GCB_RST_SLEEP, VSC9953_INIT_TIMEOUT); 911 if (err) { 912 dev_err(ocelot->dev, "timeout: switch core reset\n"); 913 return err; 914 } 915 916 /* initialize switch mem ~40us */ 917 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_ENA, 1); 918 ocelot_field_write(ocelot, SYS_RESET_CFG_MEM_INIT, 1); 919 920 err = readx_poll_timeout(vsc9953_sys_ram_init_status, ocelot, val, !val, 921 VSC9953_SYS_RAMINIT_SLEEP, 922 VSC9953_INIT_TIMEOUT); 923 if (err) { 924 dev_err(ocelot->dev, "timeout: switch sram init\n"); 925 return err; 926 } 927 928 /* enable switch core */ 929 ocelot_field_write(ocelot, SYS_RESET_CFG_CORE_ENA, 1); 930 931 return 0; 932 } 933 934 static void vsc9953_phylink_validate(struct ocelot *ocelot, int port, 935 unsigned long *supported, 936 struct phylink_link_state *state) 937 { 938 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 939 940 phylink_set_port_modes(mask); 941 phylink_set(mask, Autoneg); 942 phylink_set(mask, Pause); 943 phylink_set(mask, Asym_Pause); 944 phylink_set(mask, 10baseT_Full); 945 phylink_set(mask, 10baseT_Half); 946 phylink_set(mask, 100baseT_Full); 947 phylink_set(mask, 100baseT_Half); 948 phylink_set(mask, 1000baseT_Full); 949 950 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) { 951 phylink_set(mask, 2500baseT_Full); 952 phylink_set(mask, 2500baseX_Full); 953 } 954 955 linkmode_and(supported, supported, mask); 956 linkmode_and(state->advertising, state->advertising, mask); 957 } 958 959 /* Watermark encode 960 * Bit 9: Unit; 0:1, 1:16 961 * Bit 8-0: Value to be multiplied with unit 962 */ 963 static u16 vsc9953_wm_enc(u16 value) 964 { 965 WARN_ON(value >= 16 * BIT(9)); 966 967 if (value >= BIT(9)) 968 return BIT(9) | (value / 16); 969 970 return value; 971 } 972 973 static u16 vsc9953_wm_dec(u16 wm) 974 { 975 WARN_ON(wm & ~GENMASK(9, 0)); 976 977 if (wm & BIT(9)) 978 return (wm & GENMASK(8, 0)) * 16; 979 980 return wm; 981 } 982 983 static void vsc9953_wm_stat(u32 val, u32 *inuse, u32 *maxuse) 984 { 985 *inuse = (val & GENMASK(25, 13)) >> 13; 986 *maxuse = val & GENMASK(12, 0); 987 } 988 989 static const struct ocelot_ops vsc9953_ops = { 990 .reset = vsc9953_reset, 991 .wm_enc = vsc9953_wm_enc, 992 .wm_dec = vsc9953_wm_dec, 993 .wm_stat = vsc9953_wm_stat, 994 .port_to_netdev = felix_port_to_netdev, 995 .netdev_to_port = felix_netdev_to_port, 996 }; 997 998 static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot) 999 { 1000 struct felix *felix = ocelot_to_felix(ocelot); 1001 struct device *dev = ocelot->dev; 1002 struct mii_bus *bus; 1003 int port; 1004 int rc; 1005 1006 felix->pcs = devm_kcalloc(dev, felix->info->num_ports, 1007 sizeof(struct phylink_pcs *), 1008 GFP_KERNEL); 1009 if (!felix->pcs) { 1010 dev_err(dev, "failed to allocate array for PCS PHYs\n"); 1011 return -ENOMEM; 1012 } 1013 1014 rc = mscc_miim_setup(dev, &bus, "VSC9953 internal MDIO bus", 1015 ocelot->targets[GCB], 1016 ocelot->map[GCB][GCB_MIIM_MII_STATUS & REG_MASK]); 1017 1018 if (rc) { 1019 dev_err(dev, "failed to setup MDIO bus\n"); 1020 return rc; 1021 } 1022 1023 /* Needed in order to initialize the bus mutex lock */ 1024 rc = devm_of_mdiobus_register(dev, bus, NULL); 1025 if (rc < 0) { 1026 dev_err(dev, "failed to register MDIO bus\n"); 1027 return rc; 1028 } 1029 1030 felix->imdio = bus; 1031 1032 for (port = 0; port < felix->info->num_ports; port++) { 1033 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1034 struct phylink_pcs *phylink_pcs; 1035 struct mdio_device *mdio_device; 1036 int addr = port + 4; 1037 1038 if (dsa_is_unused_port(felix->ds, port)) 1039 continue; 1040 1041 if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL) 1042 continue; 1043 1044 mdio_device = mdio_device_create(felix->imdio, addr); 1045 if (IS_ERR(mdio_device)) 1046 continue; 1047 1048 phylink_pcs = lynx_pcs_create(mdio_device); 1049 if (!phylink_pcs) { 1050 mdio_device_free(mdio_device); 1051 continue; 1052 } 1053 1054 felix->pcs[port] = phylink_pcs; 1055 1056 dev_info(dev, "Found PCS at internal MDIO address %d\n", addr); 1057 } 1058 1059 return 0; 1060 } 1061 1062 static void vsc9953_mdio_bus_free(struct ocelot *ocelot) 1063 { 1064 struct felix *felix = ocelot_to_felix(ocelot); 1065 int port; 1066 1067 for (port = 0; port < ocelot->num_phys_ports; port++) { 1068 struct phylink_pcs *phylink_pcs = felix->pcs[port]; 1069 struct mdio_device *mdio_device; 1070 1071 if (!phylink_pcs) 1072 continue; 1073 1074 mdio_device = lynx_get_mdio_device(phylink_pcs); 1075 mdio_device_free(mdio_device); 1076 lynx_pcs_destroy(phylink_pcs); 1077 } 1078 1079 /* mdiobus_unregister and mdiobus_free handled by devres */ 1080 } 1081 1082 static const struct felix_info seville_info_vsc9953 = { 1083 .target_io_res = vsc9953_target_io_res, 1084 .port_io_res = vsc9953_port_io_res, 1085 .regfields = vsc9953_regfields, 1086 .map = vsc9953_regmap, 1087 .ops = &vsc9953_ops, 1088 .stats_layout = vsc9953_stats_layout, 1089 .num_stats = ARRAY_SIZE(vsc9953_stats_layout), 1090 .vcap = vsc9953_vcap_props, 1091 .vcap_pol_base = VSC9953_VCAP_POLICER_BASE, 1092 .vcap_pol_max = VSC9953_VCAP_POLICER_MAX, 1093 .vcap_pol_base2 = VSC9953_VCAP_POLICER_BASE2, 1094 .vcap_pol_max2 = VSC9953_VCAP_POLICER_MAX2, 1095 .num_mact_rows = 2048, 1096 .num_ports = VSC9953_NUM_PORTS, 1097 .num_tx_queues = OCELOT_NUM_TC, 1098 .mdio_bus_alloc = vsc9953_mdio_bus_alloc, 1099 .mdio_bus_free = vsc9953_mdio_bus_free, 1100 .phylink_validate = vsc9953_phylink_validate, 1101 .port_modes = vsc9953_port_modes, 1102 .init_regmap = ocelot_regmap_init, 1103 }; 1104 1105 static int seville_probe(struct platform_device *pdev) 1106 { 1107 struct dsa_switch *ds; 1108 struct ocelot *ocelot; 1109 struct resource *res; 1110 struct felix *felix; 1111 int err; 1112 1113 felix = kzalloc(sizeof(struct felix), GFP_KERNEL); 1114 if (!felix) { 1115 err = -ENOMEM; 1116 dev_err(&pdev->dev, "Failed to allocate driver memory\n"); 1117 goto err_alloc_felix; 1118 } 1119 1120 platform_set_drvdata(pdev, felix); 1121 1122 ocelot = &felix->ocelot; 1123 ocelot->dev = &pdev->dev; 1124 ocelot->num_flooding_pgids = 1; 1125 felix->info = &seville_info_vsc9953; 1126 1127 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1128 if (!res) { 1129 err = -EINVAL; 1130 dev_err(&pdev->dev, "Invalid resource\n"); 1131 goto err_alloc_felix; 1132 } 1133 felix->switch_base = res->start; 1134 1135 ds = kzalloc(sizeof(struct dsa_switch), GFP_KERNEL); 1136 if (!ds) { 1137 err = -ENOMEM; 1138 dev_err(&pdev->dev, "Failed to allocate DSA switch\n"); 1139 goto err_alloc_ds; 1140 } 1141 1142 ds->dev = &pdev->dev; 1143 ds->num_ports = felix->info->num_ports; 1144 ds->ops = &felix_switch_ops; 1145 ds->priv = ocelot; 1146 felix->ds = ds; 1147 felix->tag_proto = DSA_TAG_PROTO_SEVILLE; 1148 1149 err = dsa_register_switch(ds); 1150 if (err) { 1151 dev_err(&pdev->dev, "Failed to register DSA switch: %d\n", err); 1152 goto err_register_ds; 1153 } 1154 1155 return 0; 1156 1157 err_register_ds: 1158 kfree(ds); 1159 err_alloc_ds: 1160 err_alloc_felix: 1161 kfree(felix); 1162 return err; 1163 } 1164 1165 static int seville_remove(struct platform_device *pdev) 1166 { 1167 struct felix *felix = platform_get_drvdata(pdev); 1168 1169 if (!felix) 1170 return 0; 1171 1172 dsa_unregister_switch(felix->ds); 1173 1174 kfree(felix->ds); 1175 kfree(felix); 1176 1177 platform_set_drvdata(pdev, NULL); 1178 1179 return 0; 1180 } 1181 1182 static void seville_shutdown(struct platform_device *pdev) 1183 { 1184 struct felix *felix = platform_get_drvdata(pdev); 1185 1186 if (!felix) 1187 return; 1188 1189 dsa_switch_shutdown(felix->ds); 1190 1191 platform_set_drvdata(pdev, NULL); 1192 } 1193 1194 static const struct of_device_id seville_of_match[] = { 1195 { .compatible = "mscc,vsc9953-switch" }, 1196 { }, 1197 }; 1198 MODULE_DEVICE_TABLE(of, seville_of_match); 1199 1200 static struct platform_driver seville_vsc9953_driver = { 1201 .probe = seville_probe, 1202 .remove = seville_remove, 1203 .shutdown = seville_shutdown, 1204 .driver = { 1205 .name = "mscc_seville", 1206 .of_match_table = of_match_ptr(seville_of_match), 1207 }, 1208 }; 1209 module_platform_driver(seville_vsc9953_driver); 1210 1211 MODULE_DESCRIPTION("Seville Switch driver"); 1212 MODULE_LICENSE("GPL v2"); 1213